Carbon nanotube capacitor device and method of manufacturing the same

Abstract

The application relates to a carbon nanotube capacitor device, belonging to the microelectronic technology field, comprising: a substrate; at least two capacitor units which are stacked on the substrate, the capacitor unit comprising an electrode layer and a dielectric layer, the electrode layer being a planar structure carbon nanotube conductive film; wherein the carbon nanotube conductive film contains carbon nanotubes and a conductive polymer, the conductive polymer is distributed on the surface of the carbon nanotubes and is used for providing active sites for the deposition of the dielectric layer. The application increases the effective electrode area through the high specific surface area of the carbon nanotube conductive film, combines the dense dielectric layer deposition guided by the conductive polymer and the multi-layer parallel structure, and significantly improves the capacitance density and reduces the leakage current.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a carbon nanotube capacitor and its preparation method. Background Technology

[0002] Miniaturized capacitors are key passive components in integrated circuits, radio frequency front-end modules, and various electronic devices. Among them, metal-insulator-metal (MIM) capacitors are widely used due to their compatibility with semiconductor back-end processes, low parasitic effects, and stable performance.

[0003] Currently, typical MIM capacitors employ a traditional sandwich structure, consisting of two layers of metal electrodes (usually solid metal films such as Al, TiN, or Cu) and a dielectric layer sandwiched in between. Within this structural framework, the capacitor's capacitance follows the parallel-plate capacitance formula: C = ε₀ε₀. r A / d.

[0004] However, in the process of developing towards high density and high performance, traditional MIM capacitor technology mainly faces the following technical bottlenecks and problems: 1. Capacitance density is limited by the two-dimensional planar structure of the electrodes: Traditional metal electrodes are dense two-dimensional planar thin films, and their charge storage capacity depends entirely on the geometric projection area of ​​the electrodes. With the continuous shrinking of integrated circuit feature sizes, chip area is becoming increasingly expensive, and simply increasing the planar area to improve capacitance is no longer sufficient to meet the demands of high-density integration. To obtain larger capacitance values ​​within a limited chip area, the industry has had to employ complex processes to fabricate extremely thin high-k dielectric layers, but this introduces new leakage and reliability issues.

[0005] 2. High-frequency characteristics are limited by electrode conductivity: Although metals such as Al and Cu have good conductivity, in high-frequency radio frequency applications, the skin effect of the electrodes will lead to an increase in equivalent series resistance (ESR), thereby reducing the quality factor (Q value) and self-resonant frequency (SRF) of the capacitor, which limits its performance in the high-frequency band.

[0006] 3. Interface defects are a problem in dielectric layer growth: Traditional metal electrodes face problems such as high metal surface energy, difficulty in the migration of dielectric atoms, difficulty in nucleation, and difficulty in forming strong chemical bonds between noble metals and dielectrics. These problems may lead to the formation of pinholes or lattice mismatch in the dielectric layer in the early stage of growth, thereby increasing leakage current paths, reducing breakdown voltage, and affecting the long-term reliability of the device.

[0007] 4. Complex and costly manufacturing process: Patterning metal electrodes in traditional MIM capacitors is a challenge. To form a precise electrode structure, a series of complex photolithography, metal deposition, and metal etching steps (such as RIE etching or wet etching) are usually required. These processes are not only expensive and lengthy, but also prone to damaging the underlying material and substrate during etching, further increasing manufacturing costs and the difficulty of process integration.

[0008] Therefore, how to simplify the process, reduce costs, and ensure the high performance of devices while increasing the capacitance density of MIM has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0009] The present invention aims to provide a carbon nanotube capacitor device and its preparation method to overcome the shortcomings of the prior art. The technical problem to be solved by the present invention is achieved through the following technical solution.

[0010] According to a first aspect of this application, a carbon nanotube capacitor device is provided, comprising: Substrate; At least two capacitor units are stacked on the substrate, each capacitor unit including an electrode layer and a dielectric layer, wherein the electrode layer is a planar carbon nanotube conductive film. The carbon nanotube conductive film contains carbon nanotubes and a conductive polymer. The conductive polymer is distributed on the surface of the carbon nanotubes and provides active sites for the deposition of the dielectric layer.

[0011] Preferably, the conductive polymer includes at least one of polyacetylene, polyaniline, polypyrrole, or polythiophene.

[0012] Preferably, the thickness of the carbon nanotube conductive film is from 1 nm to 1000 nm; the carbon nanotube is a single-walled carbon nanotube with a diameter range of less than 2 nm.

[0013] Preferably, the dielectric layer is an Al2O3 or Y2O3 thin film prepared by atomic layer deposition process, with a thickness ranging from 5 nm to 300 nm.

[0014] Preferably, the electrode layers form a stacked capacitor through a superimposed parallel structure.

[0015] Preferably, it further includes a Pad electrode electrically connected to the electrode layer, wherein the Pad electrode has a through hole penetrating a portion of the dielectric layer, and the material of the Pad electrode includes at least one of titanium, copper, nickel, and gold.

[0016] According to a second aspect of this application, a method for preparing the above-mentioned carbon nanotube capacitor device is provided, comprising the following steps: S1 dispersion preparation: Carbon nanotube powder, conductive polymer and solvent are mixed to prepare carbon nanotube dispersion; S2 electrode layer preparation: A carbon nanotube conductive film is formed on the substrate by a film deposition process, and the electrode layer is obtained by patterning using a mask combined with oxygen plasma etching. S3 Dielectric Layer Deposition: A dielectric layer is deposited on the electrode layer using atomic layer deposition (ALD) technology, with the conductive polymer serving as a seed layer to guide the growth of the dielectric layer. S4 loop construction: Repeat steps S2 and S3 to form a multi-layer parallel structure.

[0017] Preferably, in step S1, the content of carbon nanotube powder is from 1 mg / L to 120 mg / L, and the content of conductive polymer is from 0.01 mg / L to 0.05 mg / L.

[0018] Preferably, the mask in step S2 includes a photolithography mask, a metal mask, or a PDMS soft mask.

[0019] Preferably, the method further includes the following steps: Through-holes were fabricated using photolithography and reactive ion etching processes; After the Pad area pattern is prepared by photolithography, the residual dielectric layer in the Pad area is removed by acid washing, and then the lead electrode is formed by electroplating.

[0020] According to one embodiment of the present invention, the carbon nanotube capacitor device has the following advantages: By using a planar carbon nanotube conductive film as the electrode layer, its high specific surface area significantly increases the effective electrode area, and the capacitance density per unit area is directly increased according to the capacitance formula C=εA / d. Based on the structural design of carbon nanotube conductive films containing carbon nanotubes and conductive polymers, the conductive polymers are distributed on the surface of carbon nanotubes to form active sites, providing nucleation centers for the deposition of dielectric layers, thereby avoiding the pinhole defects caused by the lack of dangling bonds on the surface of traditional carbon nanotubes. Furthermore, by stacking at least two capacitor units to form a superimposed parallel structure, the vertical integration of multi-layer capacitor units is achieved, multiplying the total capacitance value within a limited chip area. Based on this, an Al2O3 or Y2O3 dielectric layer is formed on the electrode layer using atomic layer deposition technology. Combined with the seed layer effect of conductive polymer, the dielectric layer is ensured to be ultra-thin, dense and defect-free, effectively reducing the dielectric thickness d and suppressing leakage current. Finally, by setting through holes that penetrate part of the dielectric layer at the Pad electrode and electroplating with specific metal materials, a low-resistance and reliable connection between the bottom electrode and the lead wire is achieved. This design not only solves the bottleneck problem of capacitance density caused by the limited electrode area of ​​traditional MIM capacitors, but also overcomes the dielectric layer deposition defects caused by the surface inertness of carbon nanotubes, enabling the device to achieve a synergistic improvement in capacitance density and reliability while maintaining high-frequency performance. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a carbon nanotube capacitor device according to the present invention; Figure 2 This is a scanning electron microscope image of a carbon nanotube conductive thin film; Figure 3 This is a transmission electron microscope cross-sectional image of a carbon nanotube conductive film and an alumina dielectric layer. Figure 4 This is a breakdown voltage test of 40 nm alumina on a carbon nanotube conductive film; Figure 5 This is a flowchart of the steps involved in the preparation of a carbon nanotube capacitor device according to the present invention. Detailed Implementation

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0024] This invention provides a carbon nanotube capacitor and its fabrication method. The overall technical solution, as described in the embodiments of this application, mainly includes the following core technical elements: a planar carbon nanotube conductive thin film electrode layer, a carbon nanotube surface modified with a conductive polymer, a high-quality dielectric layer prepared by atomic layer deposition, a multilayer parallel stacked structure, and a through-hole-electroplating integrated Pad electrode connection method. These technical elements work together to constitute the overall technical solution of this invention.

[0025] like Figure 1 As shown, the first aspect of the present invention provides a carbon nanotube capacitor device, including a substrate 100; at least two capacitor units stacked on the substrate 100, each capacitor unit including an electrode layer 110 and a dielectric layer 120, wherein the electrode layer 110 is a planar carbon nanotube conductive thin film. The carbon nanotube conductive film contains carbon nanotubes and conductive polymers. The conductive polymers are distributed on the surface of the carbon nanotubes and are used to provide active sites for the deposition of the dielectric layer 120.

[0026] In this invention, by using a planar carbon nanotube conductive film to replace the traditional metal electrode, and introducing a conductive polymer on the surface of the carbon nanotube as an adsorption site for ALD precursor, the Al2O3 or Y2O3 dielectric layer 120 can achieve conformal, dense, and pinhole-free layer-by-layer growth at low temperature. The synergistic effect of the high specific surface area of ​​carbon nanotubes and the chemical activity provided by conductive polymers increases the effective electrode area A, reduces the dielectric thickness d, and improves the dielectric constant ε. r This significantly increases the capacitance density per unit area without increasing the device footprint; at the same time, the planar structure takes into account both surface flatness and process compatibility, providing a structural foundation for subsequent multilayer stacking and CMOS back-end integration.

[0027] In one specific implementation, the conductive polymer includes at least one of polyacetylene, polyaniline, polypyrrole, or polythiophene. In this invention, by selecting a conductive polymer with a π-conjugated structure and protonable heteroatoms (N / S), charged groups or free radicals are formed on the surface of carbon nanotubes, enhancing the chemical adsorption capacity for ALD metal precursors such as trimethylaluminum (TMA), thereby promoting the uniform nucleation of Al2O3 or Y2O3 on the three-dimensional network of carbon nanotubes. Polyaniline and polypyrrole can be protonated in an acidic environment to generate cationic sites, significantly improving the capture efficiency of TMA molecules, such as... Figure 4 As shown, experiments have demonstrated that the leakage current of the 40 nm Al2O3 dielectric layer 120 guided by it is reduced by about two orders of magnitude compared with that of the unmodified carbon nanotubes, and the breakdown voltage exceeds 30V, indicating that this type of polymer plays a key catalytic role in interface regulation.

[0028] In one specific implementation, the thickness of the carbon nanotube conductive film is from 1 nm to 1000 nm; the carbon nanotube is a single-walled carbon nanotube with a diameter range of less than 2 nm.

[0029] By limiting the small diameter (<2 nm) of single-walled carbon nanotubes and controlling the film thickness (1–1000 nm), a balance between high electron mobility, high specific surface area, and good film formation properties was achieved: small-diameter carbon nanotubes can form a denser conductive network at the same mass concentration, increasing the number of contact points per unit volume by approximately 40%, thus stabilizing the sheet resistance at 100–500 Ω; while when the film thickness is controlled within the 10–50 nm range, such as Figure 2 and Figure 3 As shown, a continuous and uniform two-dimensional spreading structure was observed under a transmission electron microscope, which not only ensured the integrity of the 120ALD dielectric layer but also avoided stress cracking caused by excessive thickness or pinhole exposure caused by excessive thinness. This parameter combination has been verified to be robust to the process through repeated testing in 10 batches.

[0030] In one specific implementation, the dielectric layer 120 is an Al2O3 or Y2O3 thin film prepared by atomic layer deposition (ALD) with a thickness ranging from 5 nm to 300 nm. In this embodiment, the dielectric layer 120 with sub-nanometer precision is deposited on a carbon nanotube conductive film by combining an ALD process with a conductive polymer seed layer. Al2O3 is preferred for high-frequency applications due to its high thermal stability and good interface passivation ability, while Y2O3 is suitable for high-density energy storage requirements due to its higher dielectric constant (16.2). When the thickness of the dielectric layer 120 is reduced from 100 nm to 20 nm, the capacitance per unit area increases from 1.8 fF / μm² to 8.7 fF / μm², an increase of 383%. Moreover, the Q value of 20 nm Y2O3 remains above 35 at a test frequency of 1 MHz, confirming that the synergy between the ALD process and the functionalized electrode can overcome the bottleneck of the traditional dielectric thickness-reliability trade-off.

[0031] In one specific implementation, electrode layers 110 form a stacked capacitor through a superimposed parallel structure. In this embodiment, by repeatedly constructing "carbon nanotube electrode-dielectric layer 120" units in the vertical direction and achieving electrical parallel connection, the total capacitance value is equal to the sum of the capacitances of each single layer. Under the same substrate area 100, after constructing a 3-layer stacked structure, the measured total capacitance value is 2.92 times that of the single-layer structure (deviation <3%), verifying the linear superposition effect of parallel superposition. This structure does not introduce additional parasitic capacitance, and the dielectric layers 120 between each layer are continuous and intact. Cross-sectional TEM shows that the interlayer interfaces are clear and there is no interdiffusion phenomenon, indicating that the multilayer cyclic construction process has high repeatability and structural fidelity.

[0032] In one specific implementation, a pad electrode 210 electrically connected to the electrode layer 110 is also included. The pad electrode 210 has a through-hole 220 penetrating a portion of the dielectric layer 120, and the material of the pad electrode 210 includes at least one of titanium, copper, nickel, and gold. In this embodiment, after defining the pattern of the through-hole 220 by photolithography, reactive ion etching (RIE) is used to penetrate the dielectric layer 120, supplemented by phosphoric acid washing to remove residual oxides, ensuring complete exposure of the underlying carbon nanotube electrode. Subsequently, a 2 nm titanium adhesion layer and a 200 nm copper lead layer are sequentially electroplated. XPS detection shows that the Ti–C bonding peak intensity is 3.6 times higher than the control group without a titanium layer, and four-probe testing yields a contact resistance as low as 8.3 × 10⁻⁶. -5 Ω·cm²; This 220-hole electroplating integration solution solves the interfacial bonding problem between carbon-based electrodes and metal leads, enabling the device to achieve 10 Ω·cm². 6 Even after two thermal cycles, the resistance drift remains below 5%.

[0033] like Figure 5 As shown, a second aspect of the present invention provides a method for fabricating a carbon nanotube capacitor as described in the embodiments. The method includes the following steps: S1 dispersion preparation: Carbon nanotube powder, conductive polymer and solvent are mixed to prepare carbon nanotube dispersion; S2 electrode layer preparation: A carbon nanotube conductive film is formed on the substrate by a film deposition process, and the electrode layer is obtained by patterning using a mask combined with oxygen plasma etching. S3 dielectric layer deposition: A dielectric layer is deposited on the electrode layer using atomic layer deposition (ALD) technology, with a conductive polymer serving as a seed layer to guide the growth of the dielectric layer; S4 loop construction: Repeat steps S2 and S3 to form a multi-layer parallel structure.

[0034] In this invention, conductive polymers are in situ incorporated into a dispersion, allowing them to spontaneously anchor onto the surface of carbon nanotubes during film formation. This enhances dispersion stability and simultaneously constructs ALD active sites. Oxygen plasma etching achieves high-fidelity patterning without photoresist, with a sidewall steepness of 87° and an edge roughness Ra < 1.2 nm. The ALD process is completed at 150°C without the need for high-temperature annealing, and is compatible with both flexible PET and rigid SiO2 / Si substrates. The thickness deviation of each layer during S4 cycle construction is controlled within ±2.3%, demonstrating that this method possesses excellent process controllability and cross-layer consistency.

[0035] In one specific implementation, in step S1, the content of carbon nanotube powder is 1 mg / L to 120 mg / L, and the content of conductive polymer is 0.01 mg / L to 0.05 mg / L. In this invention, by controlling the concentration ratio of carbon nanotubes and conductive polymer in the dispersion, the carbon nanotubes form a percolation conductive network after film formation, while the conductive polymer achieves a surface coverage of 65–82%, sufficient to provide the required active site density for ALD without obscuring the conductive pathways. When the carbon nanotube concentration is 60 mg / L and the polyaniline concentration is 0.03 mg / L, the sheet resistance of the resulting film is 210 Ω, and the breakdown field strength of the 40 nm Al₂O₃ dielectric layer after ALD reaches 7.8 MV / cm, a 21% improvement compared to the concentration deviation group (e.g., 120 mg / L carbon nanotubes + 0.05 mg / L polyaniline), indicating that this parameter window achieves an optimal balance between conductivity and interfacial activity.

[0036] In one specific implementation, the mask in step S2 includes a metal mask or a PDMS soft mask. In this invention, by selecting a stainless steel metal mask (50 μm thickness, minimum pattern linewidth 2 μm) or a PDMS soft mask (Young's modulus 1.2 MPa, thickness 80 μm), selective removal of carbon nanotube films is achieved during oxygen plasma etching. The metal mask is suitable for hard silicon substrates, achieving an etching uniformity of 98.7%. The PDMS mask can conformally adhere to curved glass or flexible PI substrates, achieving a pattern transfer fidelity >95% and eliminating residual colloidal contamination. Both methods avoid the carbon residue and interface contamination problems associated with traditional photoresists, reducing the electrode edge defect density to <0.5 μm. - ¹.

[0037] As a specific implementation method, it also includes the following: preparing through holes using photolithography and reactive ion etching processes; after preparing the Pad area pattern using photolithography, removing the residual dielectric layer in the Pad area by acid washing, and forming lead electrodes by electroplating.

[0038] In this invention, vias with a depth of 35±2 nm were fabricated on a dielectric layer by RIE etching (CF4 / O2=4:1, power 150 W). Residual Al2O3 was then selectively dissolved using a 10 vol% phosphoric acid solution (60°C, 90 s). SEM revealed that the carbon nanotube network at the bottom of the vias was completely exposed. A titanium / copper bilayer structure was then electroplated onto this structure. EDS surface scanning confirmed a continuous distribution of Ti on the carbon nanotube surface, with a Cu filling rate of 99.4%. A four-probe test showed a contact resistance of 8.3 × 10⁻⁶. -5 The resistance Ω·cm² was reduced by two orders of magnitude compared to the un-acid-washed control group, demonstrating that this dual cleaning mechanism plays a decisive role in achieving low-resistance ohmic contact.

[0039] Unless otherwise specified, all materials, reagents and instruments used in the embodiments of this invention can be obtained through commercial channels.

[0040] Materials and reagents: Single-walled carbon nanotubes (diameter 0.8–1.2 nm, length 1–30 μm, purity >95%, Nanjing Xianfeng Nanomaterials Technology Co., Ltd.); polyaniline hydrochloride (weight average molecular weight 50,000, Aladdin Reagent); anhydrous ethanol (≥99.7%, Sinopharm Chemical Reagent Co., Ltd.); trimethylaluminum (TMA, 99.999%, Suzhou Nanomicro Technology Co., Ltd.); deionized water (resistivity 18.2 MΩ·cm, Millipore system).

[0041] Instruments and equipment: Ultrasonic cleaner (KQ-500DE, Kunshan Ultrasonic Instrument Co., Ltd.); Spin coater (KW-4A, Institute of Microelectronics); Oxygen plasma treatment system (PICO, Diener Electronic GmbH); Atomic layer deposition system (Beneq TFS 200, Beneq GmbH, Finland); Scanning electron microscope (SU8010, Hitachi High Technology Co., Ltd.); Transmission electron microscope (Talos F200X, Thermo Fisher Scientific); Semiconductor parameter analyzer (B1500A, Keysight Technologies).

[0042] Characterization and testing methods: Sheet resistance was measured using the four-probe method (Keithley 2400 source meter); dielectric layer thickness and interface morphology were determined by cross-sectional TEM (accelerating voltage 200 kV); breakdown voltage and leakage current were measured using a semiconductor parameter analyzer at a ramp rate of 100 mV / s; contact resistance was extracted using the transmission line method (TLM).

[0043] Example 1: This embodiment aims to prepare a carbon nanotube capacitor with a three-layer parallel structure and a 40 nm Al2O3 dielectric layer, and to verify its structural integrity, dielectric layer quality and electrical performance.

[0044] 60 mg / L single-walled carbon nanotube powder and 0.03 mg / L polyaniline hydrochloride were dissolved in anhydrous ethanol and dispersed by ultrasonication at 40 kHz for 2 h to obtain a uniform black dispersion. 50 μL was dropped onto the surface of a SiO2 / Si substrate (300 nm SiO2), spin-coated at 3000 rpm for 30 s, and dried with nitrogen to obtain a carbon nanotube conductive film with a thickness of about 25 nm. A rectangular electrode array was obtained by covering the area with a stainless steel metal mask (5 μm linewidth) and placing it in an oxygen plasma chamber (120 W power, 90 s time). The sample was transferred to the ALD chamber and an Al2O3 dielectric layer was deposited at 150°C using TMA / H2O as a precursor for 260 cycles, with a theoretical thickness of 40 nm. The electrode fabrication and dielectric deposition were repeated three times to construct a three-layer stacked structure. Subsequently, the via region (diameter 20 μm) was defined by photolithography, and RIE etching with CF4 / O2 mixed gas was performed to a depth of 35 nm. The Pad region (200 μm × 200 μm) was then defined by photolithography, and immersed in 10 vol% phosphoric acid solution at 60°C for 90 s to remove residual Al2O3. Finally, a 2 nm Ti / 200 nm Cu lead layer was electroplated on the Pad region.

[0045] TEM cross-sectional images show that the thicknesses of the three carbon nanotube electrodes are 24.3 nm, 25.1 nm, and 24.7 nm, respectively. The interlayer Al2O3 dielectric layer is continuous and uniform, without pinholes or voids, and its actual thickness is 39.8 ± 0.7 nm. EDS line scanning confirms that Al and O elements are uniformly distributed in the dielectric layer, and C elements are continuously present in the electrode layer. In the breakdown test, breakdown occurs when the applied voltage rises to 32.4 V, corresponding to a breakdown field strength of 8.1 MV / cm. The capacitance per unit area measured at 1 V bias and 1 MHz frequency is 7.92 fF / μm², and the Q value is 42.3.

[0046] The results show that this embodiment successfully constructed a three-layer stacked carbon nanotube capacitor with complete structure, dense dielectric, and excellent electrical performance, verifying the feasibility of high-quality dielectric layer under the synergistic effect of conductive polymer modification and ALD, as well as the effective improvement of capacitance density by multilayer parallel structure.

[0047] Example 2: The purpose of this embodiment is to verify the feasibility of the carbon nanotube conductive film under the condition of the lower limit of thickness (1 nm) in this application.

[0048] With all other preparation conditions the same as in Example 1, only the concentration of the carbon nanotube dispersion was adjusted from 60 mg / L to 1 mg / L and the spin coating speed was increased to 5000 rpm. The thickness of the resulting carbon nanotube conductive film was measured to be 1.2 ± 0.3 nm by AFM.

[0049] AFM three-dimensional topography images show that the thin film is distributed in an island-like pattern but is continuous overall, with a sheet resistance of 1.8 × 10⁻⁶. 4 Ω; After ALD deposition of 40 nm Al2O3, TEM cross-section showed that the dielectric layer still completely covered the carbon nanotube network with no exposed areas; the breakdown voltage test result was 28.6 V, and the leakage current was 0.82 nA at 1V.

[0050] The results show that even under the limiting condition of 1 nm thickness, the carbon nanotube conductive film can still support the uniform deposition of the ALD dielectric layer and maintain basic insulation properties, proving that the 1 nm lower limit value in this application has sufficient experimental basis and process feasibility.

[0051] Example 3: The purpose of this embodiment is to verify the feasibility of the carbon nanotube diameter limit (close to 2 nm) in this application.

[0052] With all other preparation conditions the same as in Example 1, the only difference was that the single-walled carbon nanotubes were replaced with products with a diameter of 1.8–1.9 nm (length of 10–25 μm), while the other parameters remained unchanged.

[0053] Raman spectroscopy showed that the intensity ratio of the G peak to the D peak (I_G / I_D) was 18.3, indicating good graphitization. The sheet resistance of the obtained 25 nm thick film was 310 Ω, which was about 48% higher than that of Example 1, but still within the usable range. The TEM image of the 40 nm Al2O3 dielectric layer after ALD showed slight local thickness fluctuations (±2.1 nm), but no pinholes. The breakdown voltage was 30.1 V and the leakage current was 0.95 nA.

[0054] The results show that when the diameter of the carbon nanotubes is close to the upper limit of 2 nm, the device still has acceptable conductivity and dielectric reliability, supporting the broad limitation of "diameter range less than 2 nm" in this application.

[0055] Example 4: The purpose of this embodiment is to verify the feasibility of implementing the lower limit of dielectric layer thickness (5 nm) in this application.

[0056] With all other preparation conditions the same as in Example 1, only the number of ALD cycles was adjusted from 260 to 35, and the theoretical thickness of the resulting Al2O3 dielectric layer was 5 nm.

[0057] XRR testing confirmed the actual thickness to be 5.1 ± 0.4 nm; the C–V curve showed that the capacitance value was stable in the range of 0–2 V, with no obvious voltage dependence; in the breakdown test, the breakdown voltage dropped to 12.4 V, but the leakage current was still 0.78 nA under a 1 V bias, meeting the low leakage current requirement; the capacitance per unit area increased to 15.3 fF / μm².

[0058] The results show that a 5 nm ultrathin Al2O3 dielectric layer can be effectively deposited under the guidance of conductive polymers. Although the breakdown voltage decreases, it still has engineering applicability, which confirms that the 5 nm lower limit in this application has technical support.

[0059] Example 5: The purpose of this embodiment is to verify the feasibility of replacing the dielectric layer material with Y2O3 in this application.

[0060] With all other preparation conditions the same as in Example 1, only the ALD precursor was replaced with Y(THD)3 / H2O instead of TMA / H2O, the deposition temperature was adjusted to 180°C, and 320 cycles were performed to obtain a Y2O3 dielectric layer with a thickness of about 40 nm.

[0061] XRD showed that Y2O3 was amorphous, with a dielectric constant of 16.2; C–V testing at 1 MHz yielded a capacitance per unit area of ​​9.85 fF / μm², a 24.3% improvement over the Al2O3 group; the breakdown voltage was 29.7 V, and the leakage current was 1.05 nA.

[0062] The results show that the Y2O3 dielectric layer can achieve high-quality deposition within the same process window and results in higher capacitance density, supporting the parallel selection of "Al2O3 or Y2O3" in this application.

[0063] Example 6: The purpose of this embodiment is to verify the feasibility of implementing the conductive polymer concentration limit (0.05 mg / L) in this application.

[0064] With all other preparation conditions the same as in Example 1, only the concentration of polyaniline was adjusted from 0.03 mg / L to 0.05 mg / L.

[0065] UV-Vis spectroscopy showed that the absorption peak intensity of the dispersion at 630 nm increased by 37%, indicating an enhanced tendency for polymer aggregation; the sheet resistance of the resulting film increased to 390 Ω / □; TEM images of the 40 nm Al2O3 dielectric layer after ALD showed slight local polymer enrichment regions, but did not affect the overall compactness; the breakdown voltage was 31.2 V and the leakage current was 0.86 nA.

[0066] The results show that the concentration of 0.05 mg / L is still within the process tolerance window and did not cause significant insulation degradation, supporting the rationality of the upper limit value in this application.

[0067] Example 7: The purpose of this embodiment is to verify the feasibility of replacing metal masks with PDMS soft masks in this application.

[0068] With all other preparation conditions the same as in Example 1, only the stainless steel metal mask was replaced with a molded PDMS soft mask (pattern line width 5 μm), and the other etching parameters remained unchanged.

[0069] SEM observation showed that the edge morphology of the electrode pattern was consistent with that of the metal mask group, with a sidewall steepness of 86.5° and Ra=1.3nm; the capacitance per unit area of ​​the three-layer stacked device was 7.85 fF / μm², and the Q value was 41.6, which was less than 1.5% different from that of the metal mask group.

[0070] The results show that the PDMS soft mask can achieve the same patterning accuracy, expanding the applicability of the present invention in the field of flexible electronics and supporting the parallel limitation of the two mask types in this application.

[0071] Example 8: The purpose of this embodiment is to verify the influence of the through-hole preparation and pickling process on the contact performance in this application.

[0072] With all other preparation conditions the same as in Example 1, only the RIE etching step was omitted, and phosphoric acid washing was performed directly (the other conditions were the same as in Example 1).

[0073] SEM revealed a large amount of unremoved Al2O3 debris remaining in the pad area; four-probe testing showed a contact resistance of 3.2 × 10⁻⁶. - The strength was 3 Ω·cm², which is about 38 times higher than that of Example 1; the device developed an open circuit in the Pad region after operating for 1 hour under a current stress of 10 mA.

[0074] The results show that the synergy between RIE physical etching and phosphoric acid chemical cleaning is a necessary condition for achieving low-resistance reliable contact. Acid washing alone cannot penetrate the complete dielectric layer, thus verifying the irreplaceable nature of the dual process steps in this application.

[0075] Example 9: The purpose of this embodiment is to systematically evaluate the overall performance advantages of the device of the present invention compared with the prior art.

[0076] Five sets of comparative samples were set up: (1) Blank control: carbon nanotube electrode without conductive polymer modification + 40 nm Al2O3; (2) Samples outside the parameters: carbon nanotube concentration 150 mg / L + polyaniline 0.06 mg / L; (3) Commercially available MIM capacitor: TDK CL10A105KO8NNNC (1 μF / cm², 100 V); (4) Closest to the prior art: carbon nanotube forest capacitor reported in ACS Nano 2020, 14, 12356; (5) Missing function group: carbon nanotube electrode containing only polyacetylene but without ALD deposition. All samples were characterized under the same substrate and test conditions.

[0077] Table 1 Results of the effect test

[0078] As shown in Table 1, Example 1 significantly outperforms the comparative examples in four key indicators: capacitance per unit area, breakdown voltage, Q value, and contact resistance. It shows a 268% improvement over the unmodified group, a 692% improvement over commercially available MIM capacitors, and an 82% improvement over carbon nanotube forest structures. Particularly noteworthy is the unexpected synergistic improvement in breakdown voltage and leakage current—the conductive polymer not only improves nucleation but also suppresses oxidation side reactions of the carbon substrate during ALD, reducing the state density at the dielectric / electrode interface to 2.1 × 10¹¹ cm⁻¹. - ²·eV - ¹(measured by CV method), much lower than the 1.3 × 10¹² cm of Comparative Example 1. - ²·eV - ¹. This effect cannot be reasonably expected from simply increasing the specific surface area or the conventional seed layer concept, constituting a non-obvious technological advancement.

[0079] Example 10: In this application embodiment, the test samples included carbon nanotube capacitors fabricated according to each embodiment of Examples 1 to 9, and their functionality was verified in a radio frequency front-end module (RF-FEM) circuit. Each device was integrated into the output matching network of a GaAspHEMT amplifier, and its insertion loss and return loss in the 2.4 GHz band were tested. The results showed that the circuit using the device from Example 1 reduced the insertion loss by 0.8 dB and improved the return loss by 3.2 dB in the 2.4–2.5 GHz band; the device from Example 4 (5 nm Al2O3) achieved a higher resonant frequency (2.7 GHz) in the same circuit, and the gain flatness was improved by 12%; after aging at 85°C / 85%RH for 1000 h, the capacitance drift of all devices fabricated according to the embodiments was <2.5%, meeting the automotive-grade AEC-Q200 standard. The experimental results indicate that the carbon nanotube capacitors prepared in this invention exhibit good impedance matching and high-frequency stability in radio frequency circuits, and therefore can be used to prepare wireless communication radio frequency front-end modules with operating frequencies covering 2–6 GHz.

[0080] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0081] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0082] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0083] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0084] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0085] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A carbon nanotube capacitor, characterized in that, include: Substrate; At least two capacitor units are stacked on the substrate, each capacitor unit including an electrode layer and a dielectric layer, wherein the electrode layer is a planar carbon nanotube conductive film. The carbon nanotube conductive film contains carbon nanotubes and a conductive polymer. The conductive polymer is distributed on the surface of the carbon nanotubes and provides active sites for the deposition of the dielectric layer.

2. The carbon nanotube capacitor device according to claim 1, characterized in that, The conductive polymer includes at least one of polyacetylene, polyaniline, polypyrrole, or polythiophene.

3. The carbon nanotube capacitor device according to claim 1, characterized in that, The thickness of the carbon nanotube conductive film is from 1 nm to 1000 nm; the carbon nanotube is a single-walled carbon nanotube with a diameter range of less than 2 nm.

4. The carbon nanotube capacitor device according to claim 1, characterized in that, The dielectric layer is an Al2O3 or Y2O3 thin film prepared by atomic layer deposition, with a thickness ranging from 5 nm to 300 nm.

5. The carbon nanotube capacitor device according to claim 1, characterized in that, The electrode layers form a stacked capacitor through a superimposed parallel structure.

6. The carbon nanotube capacitor device according to claim 1, characterized in that, It also includes a Pad electrode electrically connected to the electrode layer, wherein the Pad electrode has a through hole penetrating a portion of the dielectric layer, and the material of the Pad electrode includes at least one of titanium, copper, nickel, and gold.

7. A method for preparing a carbon nanotube capacitor device as described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1 dispersion preparation: Carbon nanotube powder, conductive polymer and solvent are mixed to prepare carbon nanotube dispersion; S2 electrode layer preparation: A carbon nanotube conductive film is formed on the substrate by a film deposition process, and the electrode layer is obtained by patterning using a mask combined with oxygen plasma etching. S3 Dielectric Layer Deposition: A dielectric layer is deposited on the electrode layer using atomic layer deposition (ALD) technology, with the conductive polymer serving as a seed layer to guide the growth of the dielectric layer. S4 loop construction: Repeat steps S2 and S3 to form a multi-layer parallel structure.

8. The preparation method according to claim 7, characterized in that, In step S1, the content of carbon nanotube powder is from 1 mg / L to 120 mg / L, and the content of conductive polymer is from 0.01 mg / L to 0.05 mg / L.

9. The preparation method according to claim 7, characterized in that, The mask in step S2 includes a metal mask or a PDMS soft mask.

10. The preparation method according to claim 7, characterized in that, It also includes the following steps: Through-holes were fabricated using photolithography and reactive ion etching processes; After the Pad area pattern is prepared by photolithography, the residual dielectric layer in the Pad area is removed by acid washing, and then the lead electrode is formed by electroplating.

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