Electronic device, chip and negative voltage clamping circuit for chip

Abstract

This application relates to the field of power electronics technology, and discloses an electronic device, a chip, and a negative voltage clamping circuit for the chip. The chip includes a power switch transistor adapted to control the chip to disconnect power supply to a load. The negative voltage clamping circuit includes: a negative voltage detection module configured to generate a negative voltage detection signal when the output pin voltage of the chip is detected to be less than a preset negative voltage threshold; and a clamping control module configured to generate a clamping control signal based on the negative voltage detection signal. The clamping control signal is used to control the power switch transistor to turn on, thereby clamping the output pin voltage of the chip with negative voltage. This application clamps the output pin voltage of the chip by utilizing the large current capability of the power switch transistor to quickly clamp the output pin voltage of the chip near a set threshold, shortening the time of negative voltage occurrence at the output pin to a sufficiently short duration, thereby greatly reducing the risk of latch-up.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a negative voltage clamping circuit for a chip, a chip, and an electronic device. Background Technology

[0002] Currently, efuse chips are widely used in mobile terminals, servers, communication equipment, and other fields to achieve power management, load control, and current limiting protection. Furthermore, efuse chips are typically used in high-side driving applications. When an overcurrent or output short circuit is detected, a rapid response is required to shut down the power MOSFET for protection. However, when the output load has parasitic inductance and the load is heavy, the parasitic inductance freewheeling current after the power MOSFET is turned off can pull the chip's OUT pin to a negative voltage, leading to latch-up problems and even burning out the chip.

[0003] In related technologies, in order to minimize the impact of negative voltage on the OUT pin on the chip, an isolation ring is usually added during layout to increase the distance between the relevant circuits at the OUT pin and other voltage domain circuits around it, thereby reducing parasitic effects; or a Schottky diode is added outside the chip for negative voltage clamping to reduce the risk of latch-up.

[0004] However, the wire bonding inductance of the OUT pin inside the chip also generates parasitic effects, resulting in a less than ideal clamping effect and wasting a significant amount of layout area, increasing application costs. Therefore, the negative voltage clamping schemes in related technologies cannot fundamentally eliminate negative voltage and still carry the risk of latch-up. Summary of the Invention

[0005] The purpose of this application is to provide a negative voltage clamping circuit for a chip, a chip having the negative voltage clamping circuit, and an electronic device. By clamping the negative voltage at the output pin of the chip, the large current capability of the power switching transistor itself is used to quickly clamp the output pin voltage of the chip to near a set threshold, reducing the time of negative voltage occurrence at the output pin to a sufficiently short time, thereby greatly reducing the risk of latch-up of the chip, and also reducing the requirements for layout without increasing the application cost.

[0006] To achieve the above objectives, the main technical solutions adopted in this application include:

[0007] In a first aspect, embodiments of this application provide a negative voltage clamping circuit for a chip, wherein the chip includes a power switch transistor adapted to control the chip to disconnect the power supply to a load, and the negative voltage clamping circuit includes: a negative voltage detection module configured to generate a negative voltage detection signal when the output pin voltage of the chip is detected to be less than a preset negative voltage threshold; and a clamping control module configured to generate a clamping control signal based on the negative voltage detection signal, the clamping control signal being used to control the power switch transistor to turn on, so as to perform negative voltage clamping on the output pin voltage of the chip.

[0008] According to the negative voltage clamping circuit for chips provided in the embodiments of this application, the output pin voltage of the chip is detected by a negative voltage detection module. When the output pin voltage of the chip is detected to be less than a preset negative voltage threshold, a negative voltage detection signal is generated. The clamping control module generates a clamping control signal based on the negative voltage detection signal to control the power switch to turn on. By utilizing the large current capability of the power switch itself, the output pin voltage of the chip is quickly clamped to near the set threshold. This can shorten the time when the output pin negative voltage occurs to a sufficiently short time, thereby greatly reducing the risk of latch-up of the chip. It can also reduce the requirements for layout and eliminate the need for additional application costs.

[0009] Optionally, in some embodiments of this application, the negative pressure detection module includes: a threshold providing unit configured to provide the preset negative pressure threshold; and a signal generation unit configured to generate the negative pressure detection signal when the output pin voltage of the chip is less than the preset negative pressure threshold.

[0010] Specifically, in some embodiments of this application, the threshold providing unit includes: a first current source, the positive terminal of which is adapted to be connected to a first reference voltage; a first resistor, one end of which is connected to the negative terminal of the first current source; a first transistor, the gate of which is connected to one end of the first resistor, the drain of which is connected to the other end of the first resistor, and the source of which is grounded.

[0011] Optionally, in some embodiments of this application, the signal generation unit includes: a second transistor, the gate of which is connected to the drain of the first transistor; a third transistor, the gate of which is adapted to be connected to the first reference voltage, the source of which is connected to the source of the second transistor, and the drain of which is adapted to be connected to the output pin of the chip; and a second current source, the positive terminal of which is adapted to be connected to the first reference voltage, the negative terminal of which is connected to the drain of the second transistor, and having a first node, the first node being used to output the negative voltage detection signal.

[0012] Optionally, in some embodiments of this application, the clamping control module includes: a fourth transistor, the gate of which is connected to the output terminal of the negative voltage detection module, and the source of which is adapted to be connected to a first reference voltage; and a first diode, the anode of which is connected to the drain of the fourth transistor, and the cathode of which is adapted to be connected to the control terminal of the power switch.

[0013] Optionally, in some embodiments of this application, the negative pressure clamping circuit for the chip further includes: a pull-down control module, which is configured to generate a negative pressure control signal based on the negative pressure detection signal, and control the pull-down module of the chip to close based on the negative pressure control signal.

[0014] Optionally, in some embodiments of this application, the pull-down control module includes: a fifth transistor, the gate of which is connected to the output terminal of the negative voltage detection module, and the source of which is adapted to be connected to a first reference voltage; a third current source, the positive terminal of which is connected to the drain of the fifth transistor and has a second node, the negative terminal of which is grounded, wherein the second node is used to output the negative voltage control signal.

[0015] Optionally, in some embodiments of this application, the pull-down module is configured to control the power switch to turn off upon receiving a load shutdown enable signal triggered by the chip, so that the chip disconnects the power supply to the load.

[0016] Optionally, in some embodiments of this application, the pull-down module includes: an OR gate, the first input of which is connected to the output of the pull-down control module, and the second input of which is adapted to receive the load shutdown enable signal; a level converter, the input of which is connected to the output of the OR gate; a fourth current source, the positive terminal of which is adapted to be connected to a second reference voltage; a sixth transistor, the gate of which is connected to the output of the level converter, and the source of which is connected to the negative terminal of the fourth current source; a second resistor, one end of which is connected to the drain of the sixth transistor, and the other end of which is adapted to be connected to the output pin of the chip; and a seventh transistor, the gate of which is connected to the drain of the sixth transistor, the source of which is connected to the other end of the second resistor, and the drain of which is adapted to be connected to the control terminal of the power switch.

[0017] Optionally, in some embodiments of this application, the negative voltage clamping circuit for the chip described above further includes: a first capacitor, one end of which is adapted to be connected to the first reference voltage; and a third resistor, one end of which is connected to the other end of the first capacitor, and the other end of which is connected to the gate of the fourth transistor.

[0018] Optionally, in some other embodiments of this application, the negative pressure detection module includes: a first comparator, the positive input terminal of the first comparator being adapted to connect to the preset negative pressure threshold, and the negative input terminal of the first comparator being adapted to connect to the output pin of the chip; a second comparator, the positive input terminal of the second comparator being adapted to connect to the output pin of the chip, and the negative input terminal of the second comparator being adapted to connect to a clamping reference voltage; and a trigger, the setting terminal of the trigger being connected to the output terminal of the first comparator, the reset terminal of the trigger being connected to the output terminal of the second comparator, and the trigger being configured to output the negative pressure detection signal.

[0019] Optionally, in some other embodiments of this application, the clamping control module includes: an inverter, the input terminal of which is connected to the output terminal of the flip-flop; an eighth transistor, the gate of which is connected to the output terminal of the inverter, and the drain of which is adapted to be connected to the control terminal of the power switch; and a fifth current source, the positive terminal of which is adapted to be connected to a third reference voltage, and the negative terminal of which is connected to the source of the eighth transistor.

[0020] Secondly, embodiments of this application provide a chip, including: an input pin and an output pin; a power switch disposed between the input pin and the output pin, the power switch being adapted to control the disconnection between the input pin and the output pin, so that the chip disconnects the power supply to the load; and a negative voltage clamping circuit for the chip described in the above embodiments, the negative voltage clamping circuit being configured to control the power switch to turn on when the output pin voltage of the chip is less than a preset negative voltage threshold, so as to perform negative voltage clamping on the output pin voltage of the chip.

[0021] According to the chip provided in the embodiments of this application, when the power switch controls the disconnection between the input pin and the output pin to disconnect the power supply to the load, based on the above-mentioned negative voltage clamping circuit, the power switch can be turned on when the output pin voltage of the chip is less than a preset negative voltage threshold. By utilizing the large current capability of the power switch itself, the output pin voltage can be quickly clamped to near the set threshold, which can shorten the time of negative voltage on the output pin to a sufficiently short time, thereby greatly reducing the risk of latch-up of the chip, and also reducing the requirements for layout without increasing the application cost.

[0022] Thirdly, embodiments of this application also provide an electronic device, including: a negative pressure clamping circuit for a chip as described in the above embodiments; or a chip as described in the above embodiments.

[0023] According to the electronic device provided in the embodiments of this application, when the power switch of the chip disconnects between the control input pin and the output pin to disconnect the chip from the load, based on the above-mentioned negative voltage clamping circuit, the power switch can be turned on when the output pin voltage of the chip is less than a preset negative voltage threshold. By utilizing the large current capability of the power switch itself, the output pin voltage of the chip can be quickly clamped to near the set threshold, which can shorten the time of the output pin negative voltage to a sufficiently short time, thereby greatly reducing the risk of chip latch-up, and also reducing the requirements for layout without increasing the application cost. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 A block diagram illustrating a chip according to one embodiment of this application;

[0026] Figure 2 A circuit diagram of a negative pressure clamping circuit for a chip provided in one embodiment of this application;

[0027] Figure 3 A circuit diagram of a negative pressure clamping circuit for a chip provided for another embodiment of this application;

[0028] Figure 4 A block diagram of a negative pressure clamping circuit for a chip provided in another embodiment of this application;

[0029] Figure 5 A block diagram of an electronic device provided in one embodiment of this application;

[0030] Figure 6 A block diagram of an electronic device provided in another embodiment of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] In related technologies, in order to minimize the impact of negative voltage on the OUT pin on the chip, one approach is to add an isolation ring during layout to increase the distance between the relevant circuits at the OUT pin and other voltage domain circuits around it, thereby reducing parasitic effects. Another approach is to add a Schottky diode outside the chip for negative voltage clamping to reduce the risk of latch-up.

[0033] However, since the wire bonding inductance between the OUT pin and the source of the power MOSFET inside the chip also generates parasitic effects, the clamping effect is not ideal whether an isolation ring is added to reduce the parasitic effect or a Schottky diode is added outside the chip for negative voltage clamping. Furthermore, adding an isolation ring during layout will waste a large amount of layout area, and adding a Schottky diode outside the chip will increase the chip application cost.

[0034] To address this, embodiments of this application provide a negative voltage clamping circuit for a chip, a chip having the negative voltage clamping circuit, and an electronic device. By clamping the negative voltage at the chip's output pin, the large current capability of the power switching transistor itself is used to quickly clamp the chip's output pin voltage near a set threshold, reducing the time for the negative voltage to appear at the output pin to a sufficiently short duration. This greatly reduces the risk of latch-up in the chip and also reduces the requirements for layout, without incurring additional application costs.

[0035] The following description, with reference to the accompanying drawings, details the negative pressure clamping circuit for a chip, the chip having the negative pressure clamping circuit, and the electronic device provided in the embodiments of this application.

[0036] refer to Figure 1 The diagram shown is a block illustration of a chip according to an embodiment of this application. Figure 1 As shown, the chip 100 may include a power switch M0, an input pin VIN, and an output pin VOUT. The power switch M0 is located between the input pin VIN and the output pin VOUT and is adapted to control the chip 100 to disconnect the power supply to the load. For example, after the chip triggers protection, by turning off the power switch M0, the chip 100 disconnects the power supply to the load. Here, IL is the parasitic inductance current output externally to the chip, and ILOAD is the load current. Furthermore, as... Figure 1 As shown, the negative pressure clamping circuit 10 includes a negative pressure detection module 11 and a clamping control module 12.

[0037] The negative voltage detection module 11 is configured to generate a negative voltage detection signal when the output pin voltage of the chip 100 is detected to be less than a preset negative voltage threshold. The clamping control module 12 is connected to the negative voltage detection module 11 and is configured to generate a clamping control signal based on the negative voltage detection signal. The clamping control signal is used to control the power switch M0 to turn on, so as to clamp the output pin voltage of the chip 100 under negative voltage.

[0038] Therefore, this application determines whether the negative voltage of the output pin of chip 100 is less than a preset negative voltage threshold by detecting the output pin voltage of chip 100. When the negative voltage of the output pin of chip 100 is less than the preset negative voltage threshold, the power switch M0 is turned on. By utilizing the large current capability of the power switch M0 itself, the output pin voltage of chip 100 is quickly clamped to near the set threshold, which can shorten the time of the negative voltage at the output pin to a sufficiently short time, thereby greatly reducing the risk of latch-up of the chip.

[0039] Optionally, in one embodiment of this application, such as Figure 2As shown, the negative pressure detection module 11 includes a threshold providing unit 111 and a signal generating unit 112. The threshold providing unit 111 is configured to provide a preset negative pressure threshold, and the signal generating unit 112 is configured to generate a negative pressure detection signal when the output pin voltage of the chip 100 is less than the preset negative pressure threshold.

[0040] In other words, the threshold providing unit 111 can configure a preset negative voltage threshold based on the reference power supply and provide the configured preset negative voltage threshold to the signal generation unit 112. In this way, the signal generation unit 112 generates a negative voltage detection signal based on the output pin voltage of the chip 100 and the preset negative voltage threshold, and provides it to the clamping control module 12. The clamping control module 12 then controls the power switch M0 to turn on, thereby clamping the output pin voltage of the chip 100 with negative voltage and clamping the negative voltage of the chip 100 near the preset negative voltage threshold, ensuring that the chip 100 will not experience latch-up problems.

[0041] Specifically, in some embodiments of this application, such as Figure 2 As shown, the threshold providing unit 111 includes a first current source I1, a first resistor R1, and a first transistor M1. The positive terminal of the first current source I1 is adapted to be connected to a first reference voltage VA. One end of the first resistor R1 is connected to the negative terminal of the first current source I1. The gate of the first transistor M1 is connected to one end of the first resistor R1, the drain of the first transistor M1 is connected to the other end of the first resistor R1, and the source of the first transistor M1 is grounded.

[0042] Furthermore, such as Figure 2 As shown, the signal generation unit 112 includes a second transistor M2, a third transistor M3, and a second current source I2. The gate of the second transistor M2 is connected to the drain of the first transistor M1. The gate of the third transistor M3 is adapted to be connected to a first reference voltage VA. The source of the third transistor M3 is connected to the source of the second transistor M2. The drain of the third transistor M3 is adapted to be connected to the output pin VOUT of the chip 100. The positive terminal of the second current source I2 is adapted to be connected to the first reference voltage VA. The negative terminal of the second current source I2 is connected to the drain of the second transistor M2 and has a first node, which is used to output a negative voltage detection signal.

[0043] In this embodiment, as Figure 2As shown, the preset negative voltage threshold can be configured based on -I1*R1. Generally, I1*R1 can be set between 100mV and 400mV to ensure it is less than the diode's forward voltage, preventing the parasitic diode between PSUB and the output pin VOUT inside the chip from conducting and causing a latch-up problem. Furthermore, when the chip is working normally, the output pin voltage of chip 100 is positive. At this time, the VGS voltage of the second transistor M2 = VGS_M1 - I1*RV OUT When the voltage at the output pin of chip 100 is less than the threshold voltage Vth, transistor M2 is turned off, so the first node will not output a negative voltage detection signal. Here, VGS_M1 is the VGS voltage of the first transistor. When the output pin voltage of chip 100 is less than -I1*R1, the second transistor M2 is turned on, pulling down the first node, so the first node outputs a negative voltage detection signal. The third transistor M3 can be turned on continuously, and it isolates the high voltage at the output pin of chip 100 from the second transistor M2.

[0044] Optionally, in some embodiments of this application, such as Figure 2 As shown, the clamping control module 12 includes a fourth transistor M4 and a first diode D1. The gate of the fourth transistor M4 is connected to the output terminal of the negative voltage detection module 11, the source of the fourth transistor M4 is adapted to be connected to a first reference voltage VA, the anode of the first diode D1 is connected to the drain of the fourth transistor M4, and the cathode of the first diode D1 is adapted to be connected to the control terminal of the power switch M0. For example, if the power switch M0 is an NMOS transistor, the cathode of the first diode D1 is connected to the gate of the NMOS transistor.

[0045] Specifically, when the second transistor M2 is turned on to pull down the first node, thereby outputting a negative voltage detection signal through the first node, the gate signal of the fourth transistor M4 is pulled down, thus turning on the fourth transistor M4. The first reference voltage VA starts to pull up the gate signal of the power switch M0 through the first diode D1, thus turning on the power switch M0. When the power switch current and the output load current ILOAD are balanced, the output pin voltage of chip 100 can be stabilized at -I1*R1, thereby achieving negative voltage clamping of the output pin voltage of chip 100 and ensuring that chip 100 will not have a latch-up problem.

[0046] Furthermore, when the chip is working normally, the output pin voltage of chip 100 is positive. At this time, the second transistor M2 is turned off, so the first node will not output a negative voltage detection signal. The gate signal of the fourth transistor M4 is pulled up to the first reference voltage VA by the second current I2. The fourth transistor M4 is turned off, and the clamping control module 12 does not function.

[0047] The first diode D1 serves to isolate the gate signal of the power switch M0 from the fourth transistor M4.

[0048] Optionally, in some embodiments of this application, such as Figure 2 As shown, the negative pressure clamping circuit for the chip described above also includes a pull-down control module 13. The pull-down control module 13 is configured to generate a negative pressure control signal VOUT_NEG based on the negative pressure detection signal, and control the pull-down module 20 of the chip 100 to turn off based on the negative pressure control signal VOUT_NEG.

[0049] Specifically, such as Figure 2 As shown, the pull-down control module 13 includes a fifth transistor M5 and a third current source I3. The gate of the fifth transistor M5 is connected to the output terminal of the negative voltage detection module 11. The source of the fifth transistor M5 is adapted to be connected to the first reference voltage VA. The positive terminal of the third current source I3 is connected to the drain of the fifth transistor M5 and has a second node. The negative terminal of the third current source I3 is grounded. The second node is used to output the negative voltage control signal VOUT_NEG.

[0050] In this embodiment, when the second transistor M2 is turned on to pull down the first node and output a negative voltage detection signal through the first node, the gate signal of the fifth transistor M5 is pulled down, thereby turning on the fifth transistor M5. In this way, the second node is pulled up to the first reference voltage VA, outputting a high-level negative voltage control signal VOUT_NEG, and turning off the pull-down module 20.

[0051] Optionally, in some embodiments of this application, the pull-down module 20 is configured to control the power switch M0 to turn off upon receiving a chip-triggered load shutdown enable signal EN, so that the chip 100 disconnects the power supply to the load.

[0052] For example, after the chip triggers protection, it outputs a load shutdown enable signal EN to the pull-down module 20, which then shuts down the power switch M0, disconnecting the power supply to the load.

[0053] In some embodiments of the application, such as Figure 2As shown, the pull-down module 20 includes an OR gate 21, a level shifter (LVSFT) 22, a fourth current source I4, a sixth transistor M6, a second resistor R2, and a seventh transistor M7. The first input of the OR gate 21 is connected to the output of the pull-down control module 13, and the second input of the OR gate 21 is adapted to receive the load turn-off enable signal EN. The input of the level shifter 22 is connected to the output of the OR gate 21. The positive terminal of the fourth current source I4 is adapted to connect to the second reference voltage CP. The gate of the sixth transistor M6 is connected to the output of the level shifter 22, and the source of the sixth transistor M6 is connected to the negative terminal of the fourth current source I4. One end of the second resistor R2 is connected to the drain of the sixth transistor M6, and the other end of the second resistor R2 is adapted to connect to the output pin VOUT of the chip 100. The gate of the seventh transistor M7 is connected to the drain of the sixth transistor M6, and the source of the seventh transistor M7 is connected to the other end of the second resistor R2. The drain of the seventh transistor M7 is adapted to connect to the control terminal of the power switch M0.

[0054] In the embodiments of this application, such as Figure 2 As shown, when chip 100 is working normally, the output pin VOUT of chip 100 is positive. At this time, the voltage VGS of the second transistor M2 is VGS_M1-I1*RV. OUTWhen the voltage is less than the threshold voltage Vth, the second transistor M2 turns off, and the gate signal of the fifth transistor M5 is pulled up to the first reference voltage VA by the second current I2, turning off the fifth transistor M5. This results in a low-level output signal from the second node. If the chip triggers protection, it outputs a low-level load shutdown enable signal EN to the pull-down module 20. The OR gate 21 receives two low-level signals and outputs a low-level signal. At this time, the sixth transistor M6 turns on, and the gate signal of the seventh transistor M7 is pulled up to the second reference voltage CP, thus turning on the seventh transistor M7 and turning off the power switch M0. This disconnects the input pin VIN and output pin VOUT of chip 100, cutting off the power supply to the load. After the power switch M0 turns off, due to the parasitic inductance of the output load, the inductor current IL generated by the parasitic inductor's freewheeling current will pull the output pin VOUT of chip 100 to a negative voltage. When the output pin voltage of chip 100 is less than -I1*R1, the second transistor M2 turns on, pulling down the first node, so that the first node outputs a negative voltage detection signal. At this time, the gate signal of the fifth transistor M5 is pulled down, so the fifth transistor M5 turns on. In this way, the second node is pulled up to the first reference voltage VA, and outputs a high-level negative voltage control signal VOUT_NEG. When OR gate 21 receives the high-level signal, it outputs a high-level signal. At this time, the sixth transistor M6 turns off, and the gate signal of the seventh transistor M7 is no longer pulled up to the second reference voltage CP, so the seventh transistor M7 turns off. Simultaneously, the second transistor M2 turns on, pulling down the first node. When the first node outputs a negative voltage detection signal, the gate signal of the fourth transistor M4 is pulled down, thus turning on the fourth transistor M4. The first reference voltage VA starts to pull up the gate signal of the power switch M0 through the first diode D1, thereby turning on the power switch M0. When the power switch current and the output load current ILOAD are balanced, the output pin voltage of chip 100 can be stabilized at -I1*R1, realizing negative voltage clamping of the output pin voltage of chip 100 and ensuring that chip 100 will not have a latch-up problem.

[0055] Therefore, in the negative voltage clamping circuit for the chip in this embodiment, after detecting that the output pin voltage of chip 100 is lower than the preset negative voltage threshold (usually less than the diode's forward voltage), the clamping loop will immediately turn on the power switch M0 and simultaneously pull down and disconnect the VGS of the power switch M0. The output pin will be freewheeled through the powerful current capability of the power switch M0 itself, thereby clamping the output pin voltage near the set negative voltage threshold. As the output parasitic inductance freewheeling gradually decreases, the output pin voltage of chip 100 slowly returns to 0V, which can significantly improve the chip's latch-up problem.

[0056] Furthermore, after the output pin voltage of chip 100 returns to 0V, if the chip needs to continue working, the gate signal of power switch M0 is pulled up through other circuits to drive power switch M0 to turn on and achieve normal power supply output.

[0057] Optionally, in some embodiments of this application, such as Figure 3 As shown, the negative voltage clamping circuit for the chip described above also includes a third resistor R3 and a first capacitor C1. One end of the first capacitor C1 is adapted to be connected to a first reference voltage VA, one end of the third resistor R3 is connected to the other end of the first capacitor C1, and the other end of the third resistor R3 is connected to the gate of the fourth transistor M4.

[0058] In this embodiment, the RC circuit composed of the first capacitor C1 and the third resistor R3 plays a compensating role for the clamping loop, enabling the clamping control module 12 to quickly clamp the negative voltage of the output pin, shortening the time of the negative voltage of the output pin to a sufficiently short time, and ensuring that the chip 100 will not have a latch-up problem.

[0059] Alternatively, in another embodiment of this application, such as Figure 4 As shown, the negative pressure detection module 11 includes a first comparator 101, a second comparator 102, and a trigger 103. The positive input terminal of the first comparator 101 is adapted to connect to a preset negative pressure threshold, such as -300mV. The negative input terminal of the first comparator 101 is adapted to connect to the output pin VOUT of the chip 100. The positive input terminal of the second comparator 102 is adapted to connect to the output pin VOUT of the chip 100. The negative input terminal of the second comparator 102 is adapted to connect to a clamping reference voltage, such as -20mV. The setting terminal of the trigger 103 is connected to the output terminal of the first comparator 101, and the reset terminal of the trigger 103 is connected to the output terminal of the second comparator 102. The trigger 103 is configured to output a negative pressure detection signal.

[0060] Specifically, such as Figure 4 As shown, by setting a comparator in the negative voltage detection module 11 for comparison and judgment, it is possible to quickly detect whether the output pin voltage of chip 100 is less than a preset negative voltage threshold, such as -300mV. When the output pin voltage V is detected... OUT When the voltage is less than -300mV, the output VOLT of the first comparator 101 flips to a high level, and the negative voltage detection signal is output through the trigger 103. At this time, the negative voltage detection signal is at a high level.

[0061] Furthermore, such as Figure 4As shown, the clamping control module 12 includes an inverter 121, an eighth transistor M8, and a fifth current source I5. The input terminal of the inverter 121 is connected to the output terminal of the flip-flop 103. The gate of the eighth transistor M8 is connected to the output terminal of the inverter 121. The drain of the eighth transistor M8 is adapted to be connected to the control terminal of the power switch M0. The positive terminal of the fifth current source I5 is adapted to be connected to the third reference voltage VC. The negative terminal of the fifth current source I5 is connected to the source of the eighth transistor M8.

[0062] When trigger 103 outputs a high-level negative voltage detection signal, the high-level negative voltage detection signal is flipped to a low-level signal by inverter 121, turning on the eighth transistor M8. The third reference voltage VC pulls up the gate signal of power switch M0, forcibly turning on power switch M0. Power switch M0 then provides freewheeling to the output pin, preventing the output pin voltage V from increasing. OUT It decreases further; when the output pin voltage V OUT When the voltage gradually rises to a level greater than the clamping reference voltage, for example -20mV, the output VOHT of the second comparator 102 flips to a high level, the trigger 103 is reset, and the output low-level signal is generated. After being flipped by the inverter 103, it becomes a high-level signal, the eighth transistor M8 is turned off, the pull-up current of the fifth current source I5 is turned off, and the power switch M0 can resume its own pull-down module control and be turned off.

[0063] Therefore, the negative voltage clamping circuit in this embodiment can control the output pin voltage of chip 100 between -20mV and -300mV through two comparators until the output parasitic inductor freewheeling is complete, and the output pin voltage V OUT When the voltage returns to 0V, the power switch M0 turns off naturally, completing the negative voltage clamping operation.

[0064] According to the negative voltage clamping circuit for chips provided in the embodiments of this application, the output pin voltage of the chip is detected by a negative voltage detection module. When the output pin voltage of the chip is detected to be less than a preset negative voltage threshold, a negative voltage detection signal is generated. The clamping control module generates a clamping control signal based on the negative voltage detection signal to control the power switch to turn on. By utilizing the large current capability of the power switch itself, the output pin voltage of the chip is quickly clamped to near the set threshold. This can shorten the time when the output pin negative voltage occurs to a sufficiently short time, thereby greatly reducing the risk of latch-up of the chip. It can also reduce the requirements for layout and eliminate the need for additional application costs.

[0065] Optionally, in some embodiments of this application, such as Figure 1As shown, chip 100 includes an input pin VIN and an output pin VOUT, a power switch M0 disposed between the input pin VIN and the output pin VOUT, and a negative voltage clamping circuit 10 for the chip described in the above embodiment. The power switch M0 is adapted to control the disconnection between the input pin VIN and the output pin VOUT, so that the chip disconnects the power supply to the load. The negative voltage clamping circuit 10 is configured to control the power switch M0 to turn on when the output pin voltage of chip 100 is less than a preset negative voltage threshold, so as to perform negative voltage clamping on the output pin voltage of chip 100.

[0066] In other words, the negative pressure clamping circuit 10 described in the above embodiments can be integrated and packaged in the chip 100.

[0067] According to the chip 100 provided in the embodiments of this application, when the power switch M0 controls the disconnection between the input pin VIN and the output pin VOUT to disconnect the power supply to the load, based on the above-mentioned negative voltage clamping circuit 10, the power switch M0 can be turned on when the output pin voltage of the chip 100 is less than the preset negative voltage threshold. By utilizing the large current capability of the power switch M0 itself, the output pin voltage can be quickly clamped to near the set threshold, which can shorten the time of the output pin negative voltage to a sufficiently short time, thereby greatly reducing the risk of chip latch-up, and also reducing the requirements for layout without increasing the application cost.

[0068] like Figure 5 As shown, in some embodiments of this application, an electronic device 1 is also provided, which includes the negative pressure clamping circuit 10 for a chip described in the above embodiments.

[0069] And, as Figure 6 As shown, in some other embodiments of this application, an electronic device 1 is also provided, which includes the chip 100 described in the above embodiments.

[0070] Optionally, electronic device 1 may be a mobile terminal device, a server, a communication device, etc.

[0071] According to the electronic device 1 provided in the embodiments of this application, when the power switch of chip 100 disconnects between the control input pin and the output pin to disconnect the power supply to the load, based on the above-mentioned negative voltage clamping circuit, the power switch can be turned on when the output pin voltage of the chip is less than a preset negative voltage threshold. By utilizing the large current capability of the power switch itself, the output pin voltage of the chip can be quickly clamped to near the set threshold, which can shorten the time of negative voltage at the output pin to a sufficiently short time, thereby greatly reducing the risk of latch-up of the chip, and also reducing the requirements for layout without increasing the application cost.

[0072] In the description of this specification, the terms "one embodiment," "some embodiments," "embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0073] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make modifications, alterations, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A negative voltage clamping circuit for a chip, characterized in that, The chip includes a power switch transistor adapted to control the chip to disconnect the power supply to the load, and the negative voltage clamping circuit includes: A negative pressure detection module is configured to generate a negative pressure detection signal when the output pin voltage of the chip is detected to be less than a preset negative pressure threshold. A clamping control module is configured to generate a clamping control signal based on the negative voltage detection signal. The clamping control signal is used to control the power switch to turn on, so as to perform negative voltage clamping on the output pin voltage of the chip.

2. The negative voltage clamping circuit for a chip according to claim 1, characterized in that, The negative pressure detection module includes: A threshold providing unit, configured to provide the preset negative pressure threshold; A signal generation unit is configured to generate the negative voltage detection signal when the output pin voltage of the chip is less than the preset negative voltage threshold.

3. The negative voltage clamping circuit for a chip according to claim 2, characterized in that, The threshold providing unit includes: A first current source, wherein the positive terminal of the first current source is adapted to be connected to a first reference voltage; The first resistor, one end of which is connected to the negative terminal of the first current source; The first transistor has its gate connected to one end of the first resistor, its drain connected to the other end of the first resistor, and its source grounded.

4. The negative voltage clamping circuit for a chip according to claim 3, characterized in that, The signal generation unit includes: The second transistor has its gate connected to the drain of the first transistor; The third transistor has a gate adapted to be connected to the first reference voltage, a source connected to the source of the second transistor, and a drain adapted to be connected to the output pin of the chip. A second current source, the positive terminal of which is adapted to be connected to the first reference voltage, the negative terminal of which is connected to the drain of the second transistor, and having a first node, the first node being used to output the negative voltage detection signal.

5. The negative voltage clamping circuit for a chip according to any one of claims 1-4, characterized in that, The clamping control module includes: The fourth transistor has its gate connected to the output terminal of the negative voltage detection module, and its source is adapted to be connected to the first reference voltage. A first diode, the anode of which is connected to the drain of the fourth transistor, and the cathode of which is adapted to be connected to the control terminal of the power switch.

6. The negative voltage clamping circuit for a chip according to any one of claims 1-4, characterized in that, Also includes: A pull-down control module is configured to generate a negative pressure control signal based on the negative pressure detection signal, and to control the pull-down module of the chip to close based on the negative pressure control signal.

7. The negative voltage clamping circuit for a chip according to claim 6, characterized in that, The drop-down control module includes: The fifth transistor has its gate connected to the output terminal of the negative voltage detection module, and its source is adapted to be connected to the first reference voltage. A third current source, the positive terminal of which is connected to the drain of the fifth transistor and has a second node, the negative terminal of which is grounded, wherein the second node is used to output the negative voltage control signal.

8. The negative voltage clamping circuit for a chip according to claim 6, characterized in that, The pull-down module is configured to control the power switch to turn off upon receiving a load shutdown enable signal triggered by the chip, thereby causing the chip to disconnect the power supply to the load.

9. The negative voltage clamping circuit for a chip according to claim 8, characterized in that, The drop-down module includes: An OR gate, wherein the first input terminal of the OR gate is connected to the output terminal of the pull-down control module, and the second input terminal of the OR gate is adapted to receive the load shutdown enable signal; A level converter, wherein the input terminal of the level converter is connected to the output terminal of the OR gate; A fourth current source, wherein the positive terminal of the fourth current source is adapted to be connected to a second reference voltage; The sixth transistor has its gate connected to the output terminal of the level converter and its source connected to the negative terminal of the fourth current source. A second resistor, one end of which is connected to the drain of the sixth transistor, and the other end of which is adapted to be connected to the output pin of the chip; The seventh transistor has its gate connected to the drain of the sixth transistor, its source connected to the other end of the second resistor, and its drain adapted to be connected to the control terminal of the power switch.

10. The negative voltage clamping circuit for a chip according to claim 5, characterized in that, Also includes: A first capacitor, one end of which is adapted to be connected to the first reference voltage; A third resistor, one end of which is connected to the other end of the first capacitor, and the other end of which is connected to the gate of the fourth transistor.

11. The negative voltage clamping circuit for a chip according to claim 1, characterized in that, The negative pressure detection module includes: A first comparator, wherein the positive input terminal of the first comparator is adapted to be connected to the preset negative voltage threshold, and the negative input terminal of the first comparator is adapted to be connected to the output pin of the chip; A second comparator, wherein the positive input terminal of the second comparator is adapted to be connected to the output pin of the chip, and the negative input terminal of the second comparator is adapted to be connected to the clamping reference voltage; The trigger is configured to output the negative pressure detection signal. The setting terminal of the trigger is connected to the output terminal of the first comparator, and the reset terminal of the trigger is connected to the output terminal of the second comparator.

12. The negative voltage clamping circuit for a chip according to claim 11, characterized in that, The clamping control module includes: An inverter, wherein the input terminal of the inverter is connected to the output terminal of the flip-flop; The eighth transistor has its gate connected to the output of the inverter and its drain adapted to be connected to the control terminal of the power switch. A fifth current source, the positive terminal of which is adapted to be connected to a third reference voltage, and the negative terminal of which is connected to the source of the eighth transistor.

13. A chip, characterized in that, include: Input pins and output pins; A power switch is disposed between the input pin and the output pin, the power switch being adapted to control the disconnection between the input pin and the output pin, so that the chip disconnects the power supply to the load; According to any one of claims 1-12, the negative voltage clamping circuit for a chip is configured to control the power switch to turn on when the output pin voltage of the chip is less than a preset negative voltage threshold, so as to perform negative voltage clamping on the output pin voltage of the chip.

14. An electronic device, characterized in that, include: Negative voltage clamping circuit for a chip according to any one of claims 1-12; or The chip according to claim 13.

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