High frequency device and multiplexer

Abstract

The present application provides a high-frequency device and a multiplexer capable of suppressing generation of unnecessary loss in a high-frequency signal. The high-frequency device includes a substrate having a first surface and a second surface, and a chip component mounted to the first surface of the substrate. The substrate has a signal electrode, a signal line, a lead-out line, a reference potential electrode, and an inductor. The signal electrode is provided on the second surface and is connected to a functional element of the chip component via the signal line. The lead-out line has one end and the other end. One end of the inductor is connected to the other end of the lead-out line, and the other end of the inductor is connected to the reference potential electrode. The one end of the lead-out line is connected to the signal electrode or the signal line at a position closer to the second surface than the one end of the inductor.

Description

Technical Field

[0001] This invention relates to high-frequency equipment and multiplexers. Background Technology

[0002] Conventionally, high-frequency devices equipped with filters and inductors are known as high-frequency devices installed in mobile communication devices, etc. Patent Document 1 discloses a high-frequency device that includes a chip component mounted on a substrate and an inductor formed within the substrate. In this high-frequency device, a high-frequency signal input to the substrate is fed to the filter of the chip component via lines within the substrate.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-9583 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] In previous high-frequency devices, there was a problem where large currents flowed in the circuitry within the substrate, resulting in unnecessary losses in high-frequency signals.

[0008] The present invention was made to solve the above-mentioned problems and provides a high-frequency device that can suppress unnecessary losses in high-frequency signals.

[0009] Methods for solving problems

[0010] To achieve the above objectives, a high-frequency device according to one aspect of the present invention comprises: a substrate having a first surface and a second surface; and a chip component mounted on the first surface of the substrate, the substrate having a signal electrode, a signal line, a lead-out line, a reference potential electrode, and an inductor, the signal electrode being disposed on the second surface and connected to a functional element of the chip component via the signal line, the lead-out line having one end and the other end serving as two ends of the lead-out line, one end of the inductor being connected to the other end of the lead-out line, the other end of the inductor being connected to the reference potential electrode, and one end of the lead-out line being connected to the signal electrode or the signal line at a position closer to the second surface than one end of the inductor.

[0011] One aspect of the present invention relates to a multiplexer including the aforementioned high-frequency device.

[0012] Invention Effects

[0013] The high-frequency devices and the like of the present invention can suppress unnecessary losses in high-frequency signals. Attached Figure Description

[0014] Figure 1 This is a schematic diagram showing a cross-section of a comparative example high-frequency device.

[0015] Figure 2 This is a circuit diagram of the high-frequency device involved in the implementation method.

[0016] Figure 3 This is a schematic diagram showing a cross-section of the high-frequency device involved in the embodiment.

[0017] Figure 4 This is a diagram showing the circuit patterns formed on the substrate sheets of each layer of the high-frequency device involved in the embodiment.

[0018] Figure 5 This is a diagram showing the insertion loss of the high-frequency device according to the embodiments and comparative examples.

[0019] Figure 6 This is a circuit diagram of the high-frequency device involved in the modified example 1 of the implementation method.

[0020] Figure 7 This is a schematic diagram showing a cross-section of the high-frequency device involved in a variation of embodiment 1.

[0021] Figure 8 This is a diagram showing the insertion loss of the high-frequency device of the modified example 1 and the comparative example of the embodiment.

[0022] Figure 9 This is a schematic diagram showing a cross-section of the high-frequency device involved in a variation of the embodiment, Example 2.

[0023] Figure 10 This is a schematic diagram showing a cross-section of the high-frequency device involved in variation 3 of the embodiment.

[0024] Figure 11 This is a schematic diagram showing a cross-section of the high-frequency device involved in variation 4 of the embodiment.

[0025] Figure 12 This is a schematic diagram showing a cross-section of the high-frequency device involved in variation 5 of the embodiment.

[0026] Explanation of reference numerals in the attached figures

[0027] 1. 1A, 1B, 1C, 1D, 1E High-frequency equipment;

[0028] 10, 10E chip components;

[0029] 11. First Opposite Plane;

[0030] 14. Substrate;

[0031] 15. Conductor section;

[0032] 13, 13a Functional elements;

[0033] 16, 16a Functional electrodes;

[0034] 17. Wiring electrodes;

[0035] 18 terminal electrodes;

[0036] 19. Resin;

[0037] 30 substrate;

[0038] 31 First page;

[0039] 32. Second page;

[0040] 33. Signal electrode;

[0041] 33E External Terminal;

[0042] 34. Route 1;

[0043] 34a signal line;

[0044] 34b Lead-out line;

[0045] 35. Reference potential electrode;

[0046] 35E External Terminals;

[0047] 36. Second Route;

[0048] 38. Pad electrodes;

[0049] 39. Back side;

[0050] 40 Inductors;

[0051] 41. One end;

[0052] 42. The other end;

[0053] 50 bump electrode;

[0054] 90 multi-tasking machines;

[0055] 91, 92, 92a Input / output terminals;

[0056] 97 Antenna components;

[0057] 98 Power Amplifier;

[0058] Connection point between c1 and c2;

[0059] e1 is one end of the lead-out line;

[0060] e2 leads out the other end of the line;

[0061] Nodes n1 and n2;

[0062] p, p12 conductor patterns;

[0063] p1 First conductor pattern;

[0064] p2 Second conductor pattern;

[0065] pg grounding pattern;

[0066] Paths r1, r2, r12;

[0067] v, vi, vs, vd, vg are conductor vias. Detailed Implementation

[0068] (The process of realizing this invention)

[0069] Reference Figure 1 The process of implementing this invention will be described.

[0070] Figure 1 This is a schematic cross-sectional view of the comparative example high-frequency device 101.

[0071] The comparative example high-frequency device 101 includes a substrate 130 and a chip component 10 mounted on the substrate 130. The chip component 10 is surrounded by resin 19.

[0072] The chip component 10 has a functional element 13 formed by a substrate 14 and functional electrodes 16, and a functional element 13a formed by a substrate 14 and functional electrodes 16a. Additionally, the chip component 10 has a conductor portion 15 and terminal electrodes 18. The conductor portion 15 is composed of functional electrodes 16 and 16a and wiring electrodes 17 formed on the main surface of the substrate 14. The conductor portion 15 is disposed on the first opposing surface 11 of the chip component 10. The conductor portion 15 is electrically connected to the internal conductor of the substrate 130 via bump electrodes 50.

[0073] The substrate 130 has a signal electrode 133, a first line 134 connected to the signal electrode 133, a ground electrode 135, a second line 136 connected to the ground electrode 135, and an inductor 140. The first line 134 has a signal line 134a and a lead-out line 134b.

[0074] Signal electrode 133 is connected to functional elements 13, 13a of chip component 10 via signal line 134a. One end 141 of inductor 140 is connected to signal electrode 133 via lead line 134b and a portion of signal line 134a. The other end 142 of inductor 140 is connected to ground electrode 135 via second line 136.

[0075] In the comparative example, lead-out line 134b extends from one end 141 of inductor 140 to the front side and connects to signal line 134a at the same height as end 141. Therefore, the distance from the point where signal line 134a connects to signal electrode 133 (connection point c1) to the point where lead-out line 134b connects to signal line 134a (connection point c2) becomes longer. Consequently, a large current flows in signal line 134a from connection point c1 to connection point c2, resulting in unnecessary losses in high-frequency signals.

[0076] In contrast, the high-frequency device of this embodiment has a structure that suppresses the flow of large currents in the signal lines within the substrate. This allows for the suppression of unnecessary losses in high-frequency signals.

[0077] Hereinafter, embodiments of the present invention will be described in detail using the accompanying drawings. Furthermore, the embodiments described below represent inclusive or specific examples. The numerical values, shapes, materials, constituent elements, arrangements of constituent elements, and connection methods shown in the following embodiments are examples and are not intended to limit the present invention. Additionally, in the figures, substantially identical structures are labeled with the same reference numerals, and sometimes repeated descriptions are omitted or simplified. Furthermore, in the following embodiments, "connection" includes not only direct connections but also electrical connections via other elements.

[0078] (Implementation Method)

[0079] [Structure of high-frequency equipment]

[0080] Reference Figures 2-5 The structure of the high-frequency device involved in the implementation method will be described.

[0081] Figure 2 This is a circuit structure diagram of the high-frequency device 1 involved in the implementation method.

[0082] like Figure 2 As shown, the high-frequency device 1 includes functional elements 13 and 13a and an inductor 40. The figure also shows an antenna element 97 and input / output terminals 91, 92, and 92a for inputting and outputting high-frequency signals.

[0083] Functional elements 13 and 13a are, for example, receiving filters. Furthermore, functional elements 13 and 13a can be either receiving filters or transmitting filters. Figure 2 The diagram shows two functional elements, but there can be one or more functional elements. Multiple functional elements can also be a quad-interface that uses Band1 and Band3 as passbands.

[0084] Functional elements 13 and 13a each have one or more elastic wave resonators. These elastic wave resonators include, for example, at least one of SAW (Surface Acoustic Wave) resonators, BAW (Bulk Acoustic Wave) resonators, and XBAR (Laterally Excited Thin Film Bulk Acoustic Resonator). Furthermore, SAW resonators include not only surface waves but also boundary waves. The SAW resonator is composed of a piezoelectric substrate (a piezoelectric film, a low-velocity film, a high-velocity film, or a high-velocity support substrate) and an IDT electrode, serving as the functional electrode 16, formed on the piezoelectric substrate. The BAW resonator is composed of a support substrate such as silicon and an electrode, i.e., the functional electrode 16, sandwiching the piezoelectric film.

[0085] Functional element 13 is disposed on path r1 connecting input / output terminal 91 and input / output terminal 92. Functional element 13a is disposed on path r2 connecting input / output terminal 91 and input / output terminal 92a. Antenna element 97 is connected to input / output terminal 91. In addition, one end of functional element 13 and one end of functional element 13a are connected to input / output terminal 91.

[0086] The other end of functional element 13 is connected to input / output terminal 92. The other end of functional element 13a is connected to input / output terminal 92a. Furthermore, when functional elements 13 and 13a are receiving filters, an LNA (Low Noise Amplifier) ​​and a signal processing circuit are connected sequentially to input / output terminal 92, and an LNA and a signal processing circuit are connected sequentially to input / output terminal 92a. When multiple functional elements are quadrupoles using Band 1 and Band 3 as passbands, all input / output terminals 92 and 92a become four. Two of the four input / output terminals are connected sequentially to an LNA and a signal processing circuit, respectively, and the other two are connected sequentially to a power amplifier and a signal processing circuit, respectively.

[0087] The high-frequency device 1 can also be a structure included within the multiplexer 90. That is, the high-frequency device 1 can also be a structure in which the input / output terminals 91, 92, and 92a of multiple functional elements 13, 13a are directly or indirectly connected to the common terminal of the antenna. For example, the multiplexer 90 is a duplexer when there are two multiple functional elements, a triplexer when there are three multiple functional elements, and a quadruplexer when there are four multiple functional elements. In addition, there can be five or more multiple functional elements.

[0088] An inductor 40 is connected to a portion of the path r12 between the input / output terminal 91 and functional elements 13 and 13a. One end 41 of the inductor 40 is connected to a first node n1, which is part of the path r12, and the other end 42 of the inductor 40 is connected to ground.

[0089] In the high-frequency device 1 of this embodiment, functional elements 13 and 13a are disposed on the chip component 10, and inductor 40 is disposed on the substrate 30.

[0090] Figure 3 This is a schematic diagram showing a cross-section of the high-frequency device 1.

[0091] like Figure 3 As shown, the high-frequency device 1 includes a substrate 30 having a first surface 31 and a second surface 32, and a chip component 10 mounted on the substrate 30. The chip component 10 is surrounded by a resin 19. The resin 19 is formed to cover the first surface 31 of the substrate 30 and the top and side surfaces of the chip component 10. Alternatively, the chip component 10 may not necessarily be covered by the resin 19.

[0092] exist Figure 3 In this embodiment, the direction perpendicular to the substrate 30 is defined as the Z-direction. Furthermore, the direction perpendicular to the substrate 30 is the same as the thickness direction of the substrate 30. Additionally, the direction perpendicular to the substrate 30 is also perpendicular to the two main surfaces of the substrate 30, namely the first surface 31 and the second surface 32. Furthermore, in this embodiment, the direction of the arrow in the Z-direction is sometimes referred to as the upper side, and the direction opposite to the arrow is sometimes referred to as the lower side.

[0093] The chip component 10 is mounted on the first surface 31 of the substrate 30 using bump electrodes 50.

[0094] The chip component 10 is positioned closer to the first surface 31 than the second surface 32 of the substrate 30. The chip component 10 is cuboid in shape and has a first opposing surface 11 that faces the first surface 31 of the substrate 30. The first opposing surface 11 faces the first surface 31 across the space between the substrate 30 and the chip component 10.

[0095] The chip component 10 has a functional element 13 formed by a substrate 14 and functional electrodes 16, and a functional element 13a formed by the substrate 14 and functional electrodes 16a. Additionally, the chip component 10 has a conductor portion 15 and terminal electrodes 18. The conductor portion 15 is composed of functional electrodes 16 and 16a and wiring electrodes 17 formed on the main surface of the substrate 14. The conductor portion 15 is disposed on the first opposing surface 11 of the chip component 10.

[0096] Figure 3 The conductor portion 15 shown is composed of functional electrodes 16, 16a and wiring electrodes 17, but the conductor portion 15 may include at least one of the functional electrodes 16, 16a and wiring electrodes 17. Figure 3 In this process, the wiring electrode 17, which is part of the conductor portion 15, is disposed within the functional elements 13 and 13a, but the wiring electrode 17 may also be formed outside the functional elements 13 and 13a.

[0097] The conductor portion 15 is exposed in the space between the substrate 30 and the chip component 10. Furthermore, a protective film (e.g., SiO2) may be formed on the surface of the conductor portion 15. Alternatively, the conductor portion 15 may be disposed not only on the first opposing surface 11 but also inside the chip component 10. For example, functional elements 13, 13a may also be disposed in the hollow region inside the chip component 10.

[0098] Wiring electrode 17 is led out from functional elements 13 and 13a and connected to bump electrode 50 via terminal electrode 18, which is part of wiring electrode 17. That is, conductor portion 15 is electrically connected to internal conductor of substrate 30 via bump electrode 50.

[0099] The substrate 30 is rectangular in shape. For example, the substrate 30 is a multilayer substrate formed by stacking multiple substrate sheets. The substrate 30 can be a circuit substrate containing ceramic material or a flexible circuit substrate containing resin material. Furthermore, in Figure 3 The image also shows the boundary surfaces between the stacked substrate sheets.

[0100] The two main surfaces of the substrate 30, namely the first surface 31 and the second surface 32, are parallel to each other. The first surface 31 is located on the surface of the substrate 30, and the second surface 32 is located on the back side of the substrate 30 opposite to the back surface. The first surface 31 is the surface on which the chip component 10 is mounted. The second surface 32 is the surface facing the printed circuit board when the high-frequency device 1 is mounted on other printed circuit boards.

[0101] The substrate 30 has a signal electrode 33, a first line 34 connected to the signal electrode 33, a reference potential electrode 35, a second line 36 connected to the reference potential electrode 35, and an inductor 40. The signal electrode 33, the first line 34, the reference potential electrode 35, the second line 36, and the inductor 40 are formed, for example, of a metallic material with copper as the main component.

[0102] One end 41 of the inductor 40 is connected to the signal electrode 33 via the first line 34. Specifically, one end 41 of the inductor 40 is connected to the other end e2 of the lead-out line 34b, which is part of the first line 34. The other end 42 of the inductor 40 is electrically connected to the reference potential electrode 35. Specifically, the other end 42 of the inductor 40 is connected to the reference potential electrode 35 via the second line 36.

[0103] Inductor 40 consists of multiple conductor patterns p and conductor vias vi connecting the conductor patterns p to each other (see reference). Figure 4 The structure consists of a conductor pattern p formed on a substrate sheet of each layer, parallel to the first surface 31. The inductor 40 is formed such that the coil axis of the inductor 40 is perpendicular to the substrate 30.

[0104] Figure 3 The inductor 40 shown has three layers of conductor patterns p. The inductor 40 has a first conductor pattern p1 closest to the first surface 31, a second conductor pattern p2 closest to the second surface 32, and other conductor patterns p12 located between the first conductor pattern p1 and the second conductor pattern p2. Furthermore, more than two conductor patterns may be provided between the first conductor pattern p1 and the second conductor pattern p2, or no conductor pattern may be provided at all.

[0105] The first conductor pattern p1 is connected to the signal electrode 33 via the first line 34. The second conductor pattern p2 is connected to the reference potential electrode 35 via the second line 36.

[0106] A reference potential electrode 35 is disposed on the second surface 32 of the substrate 30. The reference potential electrode 35 is, for example, an external terminal for grounding, and is set to a reference potential (e.g., ground potential). In this example, the reference potential electrode 35 is equivalent to... Figure 2 Grounding in the circuit structure diagram.

[0107] The second line 36 is a different line from the first line 34 and is disposed inside the substrate 30. The second line 36 is formed by the circuit pattern and conductor vias vg within the substrate 30 (see reference). Figure 4 The second line 36 is configured such that one end is connected to the other end 42 of the inductor 40, and the other end of the second line 36 is connected to the reference potential electrode 35.

[0108] Signal electrode 33 is disposed on the second surface 32 of substrate 30. Signal electrode 33 is, for example, an external terminal for signal input, for high-frequency signal input to antenna element 97. Signal electrode 33 is connected to functional elements 13, 13a of chip component 10 via signal line 34a, which is part of first line 34, and bump electrode 50.

[0109] The first line 34 is disposed inside the substrate 30 and on the first surface 31. The first line 34 consists of multiple line patterns, conductor vias vs and conductor vias vd formed on the substrate 30 (see reference). Figure 4 It is composed of a first surface 31 and a pad electrode 38, which is part of a first circuit 34. The first circuit 34 has a signal line 34a and a lead-out line 34b.

[0110] Signal line 34a is a line that electrically connects signal electrode 33 to bump electrode 50. One end of signal line 34a is connected to signal electrode 33 on the second surface 32 of substrate 30. The other end of signal line 34a, namely pad electrode 38, is exposed on the first surface 31 of substrate 30 and connected to bump electrode 50. That is, signal line 34a is formed from the second surface 32 to the first surface 31 and is electrically connected to functional elements 13, 13a of chip component 10. In this figure, signal line 34a is formed as a straight line through a line perpendicular to the second surface 32, but it is not limited to this. For example, signal line 34a can also be formed in a stepped manner through lines perpendicular to the second surface 32, lines parallel to the first surface 31, and lines perpendicular to the first surface 31.

[0111] Lead-out line 34b is a line used to connect signal electrode 33 to inductor 40. Lead-out line 34b extends from the end of the first conductor pattern p1, which is closest to the first surface 31, among a plurality of conductor patterns p, and is connected to signal electrode 33. Lead-out line 34b has one end e1 and the other end e2 as its two ends. One end e1 of lead-out line 34b is connected to signal electrode 33, and the other end e2 of lead-out line 34b is connected to one end 41 of inductor 40.

[0112] In this embodiment, one end e1 of the lead-out line 34b is directly connected to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40. Furthermore, one end e1 of the lead-out line 34b is connected to the signal electrode 33 in a different region than the signal line 34a. The signal electrode 33, which becomes the connection destination of one end e1 of the lead-out line 34b, is equivalent to... Figure 2 The circuit structure diagram shows the input / output terminals 91 and the first node n1.

[0113] Here, the circuit patterns of the substrate wafer having each layer forming the inductor 40, the first line 34, the signal electrode 33, the second line 36, and the reference potential electrode 35 will be described in detail. Here, the circuit pattern corresponding to a quadcopter with Band 1 and Band 3 as passbands will be used as an example for explanation.

[0114] Figure 4 This is a diagram showing the circuit patterns formed on the substrate sheets of each layer in the high-frequency device 1. Figure 4 The circuit patterns of layers one through six from the top are shown in the diagram. The conductor vias vs, vg, vi, and vd shown below are conductors extending along the depth direction of the paper to penetrate the substrate.

[0115] The circuit pattern of the first layer includes pad electrodes 38 and conductor vias as part of signal lines 34a, and ground pattern pg and conductor vias vg located on the outer periphery of the substrate. The pad electrodes 38 are connected to the signal lines 34a of the second layer via the conductor vias vs. The ground pattern pg of the first layer is connected to the ground pattern pg of the second layer via the conductor vias vg.

[0116] The circuit pattern of the second layer includes a first conductor pattern p1 with 7 / 8 turns, a conductor via vi of the inductor 40, a circuit pattern and conductor via vs as part of signal line 34a, a circuit pattern and conductor via vd as part of lead line 34b, and a ground pattern pg and conductor via vg located on the outer periphery of the substrate. The first conductor pattern p1 is connected to the conductor pattern p12 of the third layer via conductor via vi. A part of signal line 34a is connected to the conductor via vs of the third layer via conductor via vs. A part of lead line 34b is connected to the conductor via vd of the third layer via conductor via vd. The ground pattern pg of the second layer is connected to the ground pattern pg of the third layer via conductor via vg.

[0117] The circuit pattern of the third layer includes a conductor pattern p12 with approximately 7 / 8 turns, a conductor via vi of the inductor 40, a conductor via vs as part of signal line 34a, a conductor via vd as part of lead line 34b, and a ground pattern pg and conductor via vg located on the outer periphery of the substrate. Conductor pattern p12 is connected to the second conductor pattern p2 of the fourth layer via conductor via vi. The conductor via vs of the third layer is connected to the conductor via vs of the fourth layer as part of signal line 34a. The conductor via vd of the third layer is connected to the conductor via vd of the fourth layer as part of lead line 34b. The ground pattern pg of the third layer is connected to the ground pattern pg of the fourth layer via conductor via vg.

[0118] The circuit pattern of the fourth layer includes a second conductor pattern p2 with 3 / 4 turns, a portion of the second line 36, a conductor via vs as part of the signal line 34a, a conductor via vd as part of the lead-out line 34b, and a ground pattern pg and conductor via vg located on the outer periphery of the substrate. The second conductor pattern p2 is connected to the ground pattern pg via the second line 36. The conductor via vs of the fourth layer is connected to the conductor via vs of the fifth layer as part of the signal line 34a. The conductor via vd of the fourth layer is connected to the conductor via vd of the fifth layer as part of the lead-out line 34b. The ground pattern pg of the fourth layer is connected to the ground pattern pg of the fifth layer via the conductor via vg.

[0119] The circuit pattern of the fifth layer includes a conductor via vs as part of signal line 34a, a conductor via vd as part of lead-out line 34b, and a ground pattern pg and conductor via vg located on the outer periphery of the substrate. The conductor via vs of the fifth layer is connected to the signal electrode 33 of the sixth layer. The conductor via vd of the fifth layer is also connected to the signal electrode 33 of the sixth layer. The ground pattern pg of the fifth layer is connected to the reference potential electrode 35 of the sixth layer via the conductor via vg.

[0120] The circuit pattern of the sixth layer includes a signal electrode 33 and a reference potential electrode 35. The signal electrode 33 and the reference potential electrode 35 are respectively disposed on the outer peripheral end of the substrate sheet. The signal electrode 33 is connected to the signal line 34a of the upper layer via the aforementioned conductive vias vs, and is connected to the lead-out line 34b of the upper layer via the aforementioned conductive vias vd, etc. The conductive vias vs and vd are adjacent to each other when viewed from a direction perpendicular to the first surface 31 of the substrate 30, and are connected to different areas on the signal electrode 33.

[0121] A reference potential electrode 35 is formed from the outer peripheral end of the substrate sheet to the central region. The reference potential electrode 35 is connected to the ground pattern pg of the upper layer via the aforementioned conductive vias vg, etc. Furthermore, the ground patterns pg of each substrate sheet disposed in the first to fifth layers are interconnected via conductive vias vg formed in each substrate sheet.

[0122] In addition, the circuit pattern on the sixth layer also includes terminals for B1R, B1T, B3R, and B3T. These terminals are equivalent to... Figure 2 The input / output terminals 92 and 92a are shown in the circuit diagram. Each terminal is connected to the terminal electrodes of B1R, B1T, B3R and B3T of the chip component 10 via conductor vias and bump electrodes provided on each layer (illustration omitted).

[0123] For example, in Figure 3In the high-frequency device 1 shown, when input / output terminals 92 and 92a are formed on the second surface 32 of the substrate 30, the other end of the functional elements 13 and 13a of the chip component 10 can also be connected to the input / output terminals 92 and 92a via bump electrodes and conductor vias in the substrate 30 (illustration omitted).

[0124] In the high-frequency device 1 of this embodiment, the signal electrode 33 disposed on the second surface 32 of the substrate 30 is connected to the functional elements 13, 13a of the chip component 10 via the signal line 34a. Furthermore, the other end e2 of the lead-out line 34b is connected to one end 41 of the inductor 40, and one end e1 of the lead-out line 34b is connected to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40. According to this structure, the high-frequency signal input to the signal electrode 33 is split at the signal electrode 33 as a branch point and transmitted via the signal line 34a and the lead-out line 34b. Therefore, it is possible to suppress the flow of large current in the signal line 34a. Thus, it is possible to suppress unnecessary losses in the high-frequency signal.

[0125] Furthermore, the example shown above illustrates the connection between the lead-out line 34b and the signal electrode 33, but the method is not limited thereto. For example, the lead-out line 34b may also be led out from one end 41 of the inductor 40 and connected to the signal line 34a at a position closer to the second surface 32 than that end 41.

[0126] [Effects, etc.]

[0127] Reference Figure 5 The effects of the high-frequency device 1 involved in the implementation method will be explained.

[0128] Figure 5 (a) and (b) are graphs showing the insertion loss of the high-frequency devices of the embodiments and comparative examples, respectively.

[0129] exist Figure 5 The diagram shows the insertion loss of the high-frequency signal input from input / output terminal 91 to high-frequency device 1 or 101. Figure 5 In (a), the insertion loss of the receiver filter with Band 66 as the passband is shown, and in (b), the insertion loss of the receiver filter with Band 3 as the passband is shown.

[0130] like Figure 5 As shown, compared to the comparative example, the insertion loss in the passband of the embodiment is reduced. According to the high-frequency device 1 of the embodiment, compared to the high-frequency device 101 of the comparative example, the generation of insertion loss in the passband can be suppressed.

[0131] [Modification of the implementation method 1]

[0132] Reference Figure 6 and Figure 7 The structure of the high-frequency device 1A according to Modification 1 of the embodiment will be described. In Modification 1, the case where the functional element 13 of the high-frequency device 1A is a transmitting filter will be used as an example for explanation.

[0133] Figure 6 This is a circuit diagram of the high-frequency device 1A according to a variation of the implementation method 1.

[0134] like Figure 6 As shown, the high-frequency device 1A includes a functional element 13 and an inductor 40. The figure also shows a power amplifier 98 and input / output terminals 91 and 92 for high-frequency signal input and output.

[0135] Functional element 13 has one or more elastic wave resonators. These elastic wave resonators include, for example, at least one of SAW resonators, BAW resonators, and XBARs. Furthermore, SAW resonators include not only surface waves but also boundary waves. In this modified example, functional element 13 is, for example, a transmitting filter.

[0136] Functional element 13 is disposed on path r1 connecting input / output terminal 91 and input / output terminal 92. One end of functional element 13 is connected to input / output terminal 91. The other end of functional element 13 is connected to input / output terminal 92. In the case that functional element 13 is a transmit filter, power amplifier 98 and signal processing circuit are sequentially connected to input / output terminal 92.

[0137] An inductor 40 is connected to a portion of the path r1 between the functional element 13 and the input / output terminal 92. One end 41 of the inductor 40 is connected to a second node n2, which is part of the path r1, and the other end 42 of the inductor 40 is connected to ground.

[0138] In the high-frequency device 1A of Modified Example 1, the functional element 13 is disposed on the chip component 10, and the inductor 40 is disposed on the substrate 30.

[0139] Figure 7 This is a schematic diagram showing a cross-section of the high-frequency device 1A.

[0140] like Figure 7 As shown, the high-frequency device 1A includes a substrate 30 having a first surface 31 and a second surface 32, and a chip component 10 mounted on the substrate 30. The structure of the chip component 10 in Modified Example 1 is substantially the same as that in the Embodiment 1. The structure of the substrate 30 in Modified Example 1 is substantially the same as that in the Embodiment 1.

[0141] The substrate 30 has a signal electrode 33, a first line 34 connected to the signal electrode 33, a reference potential electrode 35, a second line 36 connected to the reference potential electrode 35, and an inductor 40.

[0142] The reference potential electrode 35 is, for example, an external terminal for grounding, and is set to a reference potential (e.g., ground potential). In this example, the reference potential electrode 35 is equivalent to... Figure 6 Grounding in the circuit structure diagram.

[0143] One end of the second line 36 is connected to the other end 42 of the inductor 40, and the other end of the second line 36 is connected to the reference potential electrode 35.

[0144] Signal electrode 33 is, for example, an external terminal for signal input, into which a high-frequency signal output from power amplifier 98 is input. Signal electrode 33 is connected to functional element 13 of chip component 10 via signal line 34a, which is part of first line 34, and bump electrode 50.

[0145] The first line 34 has a signal line 34a and a lead-out line 34b.

[0146] Signal line 34a is a line that electrically connects signal electrode 33 to bump electrode 50. One end of signal line 34a is connected to signal electrode 33 on the second surface 32 of substrate 30. The other end of signal line 34a, pad electrode 38, is exposed on the first surface 31 of substrate 30 and connected to bump electrode 50. That is, signal line 34a is formed from the second surface 32 to the first surface 31 and is electrically connected to functional element 13 of chip component 10.

[0147] Lead-out line 34b is used to connect signal electrode 33 to inductor 40. Lead-out line 34b extends from the end of the first conductor pattern p1, which is closest to the first surface 31, among a plurality of conductor patterns p, and is connected to signal electrode 33. One end e1 of lead-out line 34b is connected to signal electrode 33, and the other end e2 of lead-out line 34b is connected to one end 41 of inductor 40.

[0148] In this modified example, one end e1 of the lead-out line 34b is directly connected to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40. Furthermore, one end e1 of the lead-out line 34b is connected to the signal electrode 33 in a different region than the signal line 34a. The signal electrode 33, which becomes the connection destination of one end e1 of the lead-out line 34b, is equivalent to... Figure 6 The input / output terminals 92 and the second node n2 in the circuit structure diagram.

[0149] In the high-frequency device 1A of Modified Example 1, the signal electrode 33 disposed on the second surface 32 of the substrate 30 is connected to the functional element 13 of the chip component 10 via the signal line 34a. Furthermore, the other end e2 of the lead-out line 34b is connected to one end 41 of the inductor 40, and one end e1 of the lead-out line 34b is connected to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40. According to this structure, the high-frequency signal input to the signal electrode 33 is split at the signal electrode 33 as a branch point, and transmitted via the signal line 34a and the lead-out line 34b. Therefore, it is possible to suppress the flow of large current in the signal line 34a. Thus, it is possible to suppress unnecessary losses in the high-frequency signal.

[0150] [Effects, etc.]

[0151] Reference Figure 8 The effects of the high-frequency device 1A involved in Modification Example 1 will be explained.

[0152] Figure 8 This is a diagram showing the insertion loss of the high-frequency device of the modified example 1 and the comparative example of the embodiment.

[0153] exist Figure 8 The diagram shows the insertion loss of the high-frequency signal input from input / output terminal 92 to high-frequency device 1A or 101. Figure 8 The diagram shows the insertion loss of the transmit filter with Band1 as the passband.

[0154] like Figure 8 As shown, compared to the comparative example, the insertion loss in the passband of Modified Example 1 is reduced. According to the high-frequency device 1A of Modified Example 1, compared to the high-frequency device 101 of the comparative example, the insertion loss generated in the passband can be suppressed.

[0155] [Modification 2 of the implementation method]

[0156] Reference Figure 9 The structure of the high-frequency device 1B according to Modification 2 of the embodiment will be described. In Modification 2, an example in which one end e1 of the lead-out line 34b is connected to the signal line 34a will be described.

[0157] Figure 9 This is a schematic diagram showing a cross-section of the high-frequency device 1B.

[0158] like Figure 9 As shown, the high-frequency device 1B includes a substrate 30 having a first surface 31 and a second surface 32, and a chip component 10 mounted on the substrate 30. The structure of the chip component 10 in Modified Example 2 is the same as that in the embodiment.

[0159] The substrate 30 has a signal electrode 33, a first line 34 connected to the signal electrode 33, a reference potential electrode 35, a second line 36 connected to the reference potential electrode 35, and an inductor 40. The structure of the signal electrode 33, the reference potential electrode 35, the second line 36, and the inductor 40 is the same as in the embodiment.

[0160] In Modification 2, lead-out line 34b is used to connect signal electrode 33 to inductor 40, but one end e1 of lead-out line 34b is connected to a portion of signal line 34a. The connection point c2 of signal line 34a, which becomes the connection destination of end e1 of lead-out line 34b, is equivalent to... Figure 2 The first node n1 in the circuit structure diagram.

[0161] One end of the first line 34 is connected to the signal electrode 33. The other end of the first line 34 has two parts: the first part, the pad electrode 38, is connected to the bump electrode 50, and the second part is connected to one end 41 of the inductor 40.

[0162] For example, lead-out line 34b extends from the end of the first conductor pattern p1, which is closest to the first surface 31, among the plurality of conductor patterns p, and connects to signal line 34a. Specifically, one end e1 of lead-out line 34b is connected to signal line 34a at a position closer to the second surface 32 than one end 41 of inductor 40. More specifically, one end e1 of lead-out line 34b is connected to connection point c2 of signal line 34a at a position closer to the second surface 32 than the second conductor pattern p2, which is closest to the second surface 32 among the plurality of conductor patterns p.

[0163] In the high-frequency device 1B of Modified Example 2, the signal electrode 33 disposed on the second surface 32 of the substrate 30 is connected to the functional elements 13, 13a of the chip component 10 via the signal line 34a. Furthermore, the other end e2 of the lead-out line 34b is connected to one end 41 of the inductor 40, and one end e1 of the lead-out line 34b is connected to the signal line 34a at a position closer to the second surface 32 than one end 41 of the inductor 40. According to this structure, compared to the comparative example, the distance from the point where the signal line 34a connects to the signal electrode 33 (connection point c1) to the point where the lead-out line 34b connects to the signal line 34a (connection point c2) can be shortened. Therefore, the high-frequency signal input to the signal electrode 33 will be split at the connection point c2 near the signal electrode 33, and transmitted to the signal line 34a and the lead-out line 34b. This shortens the portion of the signal line 34a where a large current flows, suppressing unnecessary losses in the high-frequency signal.

[0164] [Modification 3 of the implementation method]

[0165] Reference Figure 10 The structure of the high-frequency device 1C according to Modification 3 of the embodiment will be described. In Modification 3, an example in which the inductor 40 is formed by a single layer of conductor pattern p will be described.

[0166] Figure 10 This is a schematic diagram showing a cross-section of the high-frequency device 1C.

[0167] like Figure 10 As shown, the high-frequency device 1C includes a substrate 30 having a first surface 31 and a second surface 32, and a chip component 10 mounted on the substrate 30. The structure of the chip component 10 in Modified Example 3 is the same as that in the Embodiment 1.

[0168] The substrate 30 has a signal electrode 33, a first line 34 connected to the signal electrode 33, a reference potential electrode 35, a second line 36 connected to the reference potential electrode 35, and an inductor 40. The structure of the signal electrode 33, the first line 34, the reference potential electrode 35, and the second line 36 is the same as in the embodiment.

[0169] One end 41 of the inductor 40 is connected to the signal electrode 33 via lead-out line 34b. The other end 42 of the inductor 40 is electrically connected to the reference potential electrode 35.

[0170] Specifically, the inductor 40 of Modified Example 3 is composed of a conductor pattern p with 3 / 4 turns. The conductor pattern p is formed on a substrate sheet and is parallel to the first surface 31. One end of the conductor pattern p is connected to the signal electrode 33 via the first line 34, and the other end of the conductor pattern p is connected to the reference potential electrode 35 via the second line 36.

[0171] In the high-frequency device 1C of Modified Example 3, one end e1 of the lead-out line 34b is also connected to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40. Thus, the same effect as in the embodiment can be achieved.

[0172] [Modification 4 of the implementation method]

[0173] Reference Figure 11 The structure of the high-frequency device 1D according to Modification 4 of the embodiment will be described. In Modification 4, an example in which the top and bottom of the inductor 40 are reversed will be described.

[0174] Figure 11 This is a schematic diagram showing a cross-section of the high-frequency device 1D.

[0175] like Figure 11As shown, the high-frequency device 1D includes a substrate 30 having a first surface 31 and a second surface 32, and a chip component 10 mounted on the substrate 30. The structure of the chip component 10 in Modified Example 4 is the same as that in the embodiment.

[0176] The substrate 30 has a signal electrode 33, a first line 34 connected to the signal electrode 33, a reference potential electrode 35, a second line 36 connected to the reference potential electrode 35, and an inductor 40. The structure of the signal electrode 33, the first line 34, the reference potential electrode 35, and the second line 36 is the same as in the embodiment.

[0177] In Modification 4, one end 41 of the inductor 40 is located near the second surface 32 of the substrate 30 compared to the other end 42. In other words, in Modification 4, the other end 42 of the inductor 40 is located near the first surface 31 of the substrate 30 compared to the other end 41. One end 41 of the inductor 40 is connected to the signal electrode 33 via a lead-out line 34b. The other end 42 of the inductor 40 is electrically connected to the reference potential electrode 35.

[0178] Specifically, the inductor 40 of Variation 4 has three conductor patterns p. The inductor 40 has a first conductor pattern p1 closest to the first surface 31, a second conductor pattern p2 closest to the second surface 32, and other conductor patterns p12 located between the first conductor pattern p1 and the second conductor pattern p2. The second conductor pattern p2 is connected to the signal electrode 33 via a lead-out line 34b. The first conductor pattern p1 is connected to the reference potential electrode 35 via a second line 36.

[0179] In the high-frequency device 1D of Modified Example 4, one end e1 of the lead-out line 34b is also directly connected to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40. Thus, the same effect as in the embodiment can be achieved.

[0180] In addition, in the high-frequency device 1D, the lead-out line 34b is led out from the end of the second conductor pattern p2, which is closest to the second surface 32 among the multiple conductor patterns p. Therefore, the length of the lead-out line 34b can be shortened and the resistance of the lead-out line 34b can be reduced.

[0181] Furthermore, in the high-frequency device 1D, the second conductor pattern p2 connected to the signal electrode 33 is far away from the conductor portion 15 of the chip component 10, and the first conductor pattern p1 connected to the reference potential electrode 35 is located between the second conductor pattern p2 and the conductor portion 15. Therefore, it is possible to suppress the degradation of high-frequency characteristics.

[0182] [Modification of the implementation method 5]

[0183] Reference Figure 12The structure of the high-frequency device 1E according to Variation 5 of the embodiment will be described. In Variation 5, an example of the high-frequency device 1 of the embodiment being incorporated into a module substrate will be described.

[0184] Figure 12 This is a schematic diagram showing a cross-section of the high-frequency device 1E.

[0185] like Figure 12 As shown, the high-frequency device 1E includes a substrate 30 having a first surface 31 and a second surface 32, and a chip component 10 mounted on the substrate 30. The structure of the chip component 10 in Modified Example 5 is the same as that in the embodiment.

[0186] In addition, Figure 12 The image also shows other chip components 10E mounted on the first surface 31 of the substrate 30. The chip components 10E are, for example, LNAs or power amplifiers, and are connected to the other end of the functional element 13 of the chip components 10.

[0187] The substrate 30 is, for example, a multilayer substrate formed by stacking multiple substrate sheets. The substrate 30 may be a circuit substrate containing ceramic material or a flexible circuit substrate containing resin material.

[0188] The two main surfaces of the substrate 30, namely the first surface 31 and the second surface 32, are parallel to each other. The first surface 31 is located on the surface of the substrate 30, and the second surface 32 is located inside the substrate 30. The first surface 31 is the surface on which the chip component 10 is mounted. The second surface 32 is not the back surface 39 of the substrate 30, but the boundary surface between the substrate sheet and the signal electrode 33 and the reference potential electrode 35.

[0189] The substrate 30 has a signal electrode 33, a first line 34 connected to the signal electrode 33, a reference potential electrode 35, a second line 36 connected to the reference potential electrode 35, and an inductor 40.

[0190] One end 41 of the inductor 40 is connected to the signal electrode 33 via a first line 34. The other end 42 of the inductor 40 is electrically connected to the reference potential electrode 35. Specifically, the other end 42 of the inductor 40 is connected to the reference potential electrode 35 via a second line 36.

[0191] The inductor 40 is composed of multiple conductor patterns p and conductor vias vi connecting the conductor patterns p to each other. Each conductor pattern p is formed on a substrate sheet of each layer, parallel to the first surface 31. The inductor 40 is configured such that the coil axis of the inductor 40 is perpendicular to the substrate 30.

[0192] Figure 12The inductor 40 shown has three conductor patterns p. The inductor 40 has a first conductor pattern p1 closest to the first surface 31, a second conductor pattern p2 closest to the second surface 32, and other conductor patterns p12 located between the first conductor pattern p1 and the second conductor pattern p2. The first conductor pattern p1 is connected to the signal electrode 33 via a first line 34. The second conductor pattern p2 is connected to the reference potential electrode 35 via a second line 36.

[0193] A reference potential electrode 35 is disposed on the second surface 32 of the substrate 30. The reference potential electrode 35 is, for example, an internal terminal for grounding, and is set to a reference potential (e.g., ground potential). In this example, the reference potential electrode 35 is equivalent to... Figure 2 The grounding is shown in the circuit diagram. The reference potential electrode 35 is connected to the external terminal 35E on the back side 39 of the substrate 30 via a conductor via v in the substrate 30.

[0194] The second line 36 is disposed inside the substrate 30. One end of the second line 36 is connected to the other end 42 of the inductor 40, and the other end of the second line 36 is connected to the reference potential electrode 35.

[0195] Signal electrode 33 is disposed on the second surface 32 of substrate 30. Signal electrode 33 is, for example, an internal terminal for signal input, providing a high-frequency signal input to antenna element 97. In this example, signal electrode 33 is equivalent to... Figure 2 The input / output terminal 91 is shown in the circuit diagram. The signal electrode 33 is connected to the functional elements 13, 13a of the chip component 10 via the signal line 34a, which is part of the first line 34, and the bump electrode 50. In addition, the signal electrode 33 is connected to the external terminal 33E on the back side 39 of the substrate 30 via the conductor via v in the substrate 30.

[0196] A first line 34 is disposed inside the substrate 30 and on the first surface 31. The first line 34 is composed of multiple line patterns, conductor vias vs and conductor vias vd formed on the substrate 30. A pad electrode 38, which is part of the first line 34, is formed on the first surface 31. The first line 34 has a signal line 34a and a lead-out line 34b.

[0197] Signal line 34a is a line that electrically connects signal electrode 33 to bump electrode 50. One end of signal line 34a is connected to signal electrode 33 on the second surface 32 of substrate 30. The other end of signal line 34a, pad electrode 38, is exposed on the first surface 31 of substrate 30 and connected to bump electrode 50. That is, signal line 34a is formed from the second surface 32 to the first surface 31 and is electrically connected to functional elements 13, 13a of chip component 10.

[0198] Lead-out line 34b is used to connect signal electrode 33 to inductor 40. One end e1 of lead-out line 34b is connected to signal electrode 33, and the other end e2 of lead-out line 34b is connected to one end 41 of inductor 40.

[0199] In this modified example, one end e1 of the lead-out line 34b is directly connected to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40. Furthermore, one end e1 of the lead-out line 34b is connected to the signal electrode 33 in a different region than the signal line 34a. The signal electrode 33, which becomes the connection destination of one end e1 of the lead-out line 34b, is equivalent to... Figure 2 The circuit structure diagram shows the input / output terminals 91 and the first node n1.

[0200] In the high-frequency device 1E of Modified Example 5, the signal electrode 33 disposed on the second surface 32 of the substrate 30 is connected to the functional elements 13, 13a of the chip component 10 via the signal line 34a. Furthermore, the other end e2 of the lead-out line 34b is connected to one end 41 of the inductor 40, and one end e1 of the lead-out line 34b is connected to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40. According to this structure, the high-frequency signal input to the signal electrode 33 is split at the signal electrode 33 as a branch point, and transmitted via the signal line 34a and the lead-out line 34b. Therefore, large currents flowing in the signal line 34a can be suppressed. Thus, unnecessary losses in high-frequency signals can be suppressed.

[0201] Furthermore, the example shown above illustrates the connection between the lead-out line 34b and the signal electrode 33, but the method is not limited thereto. For example, the lead-out line 34b may also be led out from one end 41 of the inductor 40 and connected to the signal line 34a at a position closer to the second surface 32 than that end 41.

[0202] (Summarize)

[0203] An example of a high-frequency device according to one aspect of the present invention will be provided.

[0204] The high-frequency device of Example 1 includes a substrate 30 having a first surface 31 and a second surface 32, and a chip component 10 mounted on the first surface 31 of the substrate 30. The substrate 30 has a signal electrode 33, a signal line 34a, a lead-out line 34b, a reference potential electrode 35, and an inductor 40. The signal electrode 33 is disposed on the second surface 32 and is connected to the functional element 13 of the chip component 10 via the signal line 34a. The lead-out line 34b has one end e1 and the other end e2 as the two ends of the lead-out line 34b. One end 41 of the inductor 40 is connected to the other end e2 of the lead-out line 34b, and the other end 42 of the inductor 40 is connected to the reference potential electrode 35. One end e1 of the lead-out line 34b is connected to the signal electrode 33 or the signal line 34a at a position closer to the second surface 32 than one end 41 of the inductor 40.

[0205] For example, by connecting one end e1 of the aforementioned lead-out line 34b to the signal electrode 33 at a position closer to the second surface 32 than one end 41 of the inductor 40, the high-frequency signal input to the signal electrode 33 is split at the signal electrode 33 as a branch point, and transmitted to the signal line 34a and the lead-out line 34b. Therefore, large currents flowing in the signal line 34a can be suppressed. This, in turn, suppresses unnecessary losses in high-frequency signals.

[0206] Alternatively, for example, one end e1 of the aforementioned lead-out line 34b can be connected to the signal line 34a at a position closer to the second surface 32 than one end 41 of the inductor 40. This allows the high-frequency signal input to the signal electrode 33 to be transmitted via a branch point, with one end e1 of the lead-out line 34b serving as a branch point, splitting into the signal line 34a and the lead-out line 34b. Therefore, the portion of the signal line 34a carrying a large current can be shortened. This, in turn, suppresses unnecessary losses in high-frequency signals.

[0207] The high-frequency device in Example 2 can also be based on the high-frequency device described in Example 1, in which one end 41 of the inductor 40 is connected to the signal electrode 33 or the signal line 34a via the lead-out line 34b, and the other end 42 of the inductor 40 is connected to the reference potential electrode 35 via a different line (e.g., a second line 36) that is different from both the signal line 34a and the lead-out line 34b.

[0208] Therefore, the high-frequency signal input to signal electrode 33 is split and transmitted through signal line 34a and lead-out line 34b. This suppresses the flow of large currents in signal line 34a. Consequently, unnecessary losses in the high-frequency signal are suppressed.

[0209] The high-frequency device in Example 3 can also be based on the high-frequency device described in Example 1 or 2, wherein the inductor 40 includes a plurality of conductor patterns p formed on the substrate 30 and conductor vias vi, and the lead-out line 34b is led out from the end of the conductor pattern p closest to the first surface 31 and connected to the signal electrode 33 or the signal line 34a.

[0210] Therefore, even when the lead-out line 34b is led out from the end of the conductor pattern close to the first surface 31, the high-frequency signal input to the signal electrode 33 will be split into the signal line 34a and the lead-out line 34b as the aforementioned signal electrode 33 or connection point c2 for transmission. Thus, large currents flowing in the signal line 34a can be suppressed. Consequently, unnecessary losses in high-frequency signals can be suppressed.

[0211] The high-frequency device in Example 4 can also be based on the high-frequency device described in Example 1 or 2, wherein the inductor 40 has a plurality of conductor patterns p and conductor vias vi formed on the substrate 30, and one end e1 of the lead-out line 34b is connected to the signal line 34a at a position closer to the second surface 32 than the conductor pattern closest to the second surface 32 among the plurality of conductor patterns p.

[0212] This shortens the distance from the point where signal line 34a connects to signal electrode 33 (connection point c1) to the point where one end e1 of lead-out line 34b connects to signal line 34a (connection point c2). Therefore, the high-frequency signal input to signal electrode 33 is split at connection point c2 (or one end e1) and transmitted to signal line 34a and lead-out line 34b. This shortens the portion of signal line 34a where a large current flows, suppressing unnecessary losses in high-frequency signals.

[0213] The high-frequency device in Example 5 can also be based on the high-frequency device described in Example 1 or 2, wherein the inductor 40 includes a plurality of conductor patterns p formed on the substrate 30 and conductor vias vi, and the lead-out line 34b is led out from the end of the conductor pattern p closest to the second surface 32 and connected to the signal electrode 33 or the signal line 34a.

[0214] This structure allows for a shorter length of the lead-out line 34b and a reduced resistance. This, in turn, helps suppress unnecessary losses in high-frequency signals.

[0215] The high-frequency device in Example 6 can also be based on the high-frequency device described in any of Examples 1 to 5, wherein the chip component 10 has a functional element 13 formed by a substrate 14 and a functional electrode 16, and the functional element 13 has one or more elastic wave resonators, the one or more elastic wave resonators including at least one of SAW resonator, BAW resonator and XBAR.

[0216] This allows for the suppression of insertion loss in the passband of high-frequency devices.

[0217] The high-frequency device in Example 7 can also be based on the high-frequency device described in any of Examples 1 to 6, wherein the signal electrode 33 is input with a high-frequency signal and the reference potential electrode 35 is set to ground potential.

[0218] Therefore, when a high-frequency signal is input to the signal electrode 33, it is possible to suppress the flow of large current in the signal line 34a. This also helps to suppress unnecessary losses in the high-frequency signal.

[0219] The high-frequency device in Example 8 can also be based on the high-frequency device described in any of Examples 1 to 7, wherein the first surface 31 is located on the surface of the substrate 30, the second surface 32 is located on the back side of the substrate 30, and the signal electrode 33 and the reference potential electrode 35 are respectively disposed on the second surface 32.

[0220] Therefore, it is possible to provide a surface-mount type high-frequency device consisting of a substrate 30 and a chip component 10.

[0221] The high-frequency device in Example 9 can also be based on the high-frequency device described in any of Examples 1 to 7, wherein the first surface 31 is located on the surface of the substrate 30, and the second surface 32 is parallel to the first surface 31 and located inside the substrate 30.

[0222] Therefore, it is possible to provide a modular high-frequency device including a substrate 30 and a chip component 10.

[0223] The multiplexer 90 in Example 10 includes the high-frequency device described in any of Examples 1 to 9.

[0224] Thus, a multiplexer 90 can be provided that can suppress unnecessary losses in high-frequency signals.

[0225] (Other implementation methods)

[0226] The high-frequency device and multiplexer of the present invention have been described above, but the present invention is not limited to each embodiment. Various modifications conceived by those skilled in the art, applied to the embodiments, and combinations of constituent elements from different embodiments, can be included within the scope of one or more embodiments of the present invention, as long as they do not depart from the spirit of the invention.

[0227] Industrial utilization

[0228] This invention, as a high-frequency device or multiplexer capable of suppressing unnecessary losses in high-frequency signals, can be widely used in communication devices such as portable telephones.

Claims

1. A high-frequency device, comprising: A substrate having a first side and a second side; and A chip component, which is mounted on the first surface of the substrate. The substrate has signal electrodes, signal lines, lead-out lines, a reference potential electrode, and an inductor. The signal electrode is disposed on the second surface and is connected to the functional elements of the chip component via the signal line. The lead-out line has one end and the other end, which serve as the two ends of the lead-out line. One end of the inductor is connected to the other end of the lead-out line, and the other end of the inductor is connected to the reference potential electrode. One end of the lead-out line is connected to the signal electrode or the signal line at a position closer to the second surface than one end of the inductor.

2. The high-frequency device according to claim 1, wherein, One end of the inductor is connected to the signal electrode or the signal line via the lead-out line. The other end of the inductor is connected to the reference potential electrode via a different line than the signal line and the lead-out line.

3. The high-frequency device according to claim 1 or 2, wherein, The inductor includes a plurality of conductor patterns and conductor vias formed on the substrate. The lead-out line extends from the end of the conductor pattern closest to the first face among the plurality of conductor patterns and is connected to the signal electrode or the signal line.

4. The high-frequency device according to claim 1 or 2, wherein, The inductor has multiple conductor patterns and conductor vias formed on the substrate. One end of the lead-out line is connected to the signal line at a position closer to the second surface than the conductor pattern closest to the second surface among the plurality of conductor patterns.

5. The high-frequency device according to claim 1 or 2, wherein, The inductor includes a plurality of conductor patterns and conductor vias formed on the substrate. The lead-out line extends from the end of the conductor pattern closest to the second face among the plurality of conductor patterns and is connected to the signal electrode or the signal line.

6. The high-frequency device according to any one of claims 1 to 5, wherein, The chip component has the functional elements formed by a substrate and functional electrodes. The functional element has one or more elastic wave resonators. The more than one elastic wave resonator includes at least one of surface acoustic wave (SAW) resonator, bulk acoustic wave (BAW) resonator, and transversely excited thin-film bulk acoustic resonator (XBAR).

7. The high-frequency device according to any one of claims 1 to 6, wherein, The signal electrode is input with a high-frequency signal. The reference potential electrode is set to ground potential.

8. The high-frequency device according to any one of claims 1 to 7, wherein, The first surface is located on the surface of the substrate. The second surface is located on the back side of the substrate. The signal electrode and the reference potential electrode are respectively disposed on the second surface.

9. The high-frequency device according to any one of claims 1 to 7, wherein, The first surface is located on the surface of the substrate. The second surface is parallel to the first surface and is located inside the substrate.

10. A multiplexer comprising the high-frequency device according to any one of claims 1 to 9.

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