Chip input / output circuit

Abstract

The application discloses a chip input and output circuit, relates to the technical field of integrated circuits, and comprises a variable impedance transmission circuit, an impedance matching detection circuit and an input and output interface. The application dynamically adjusts the impedance of a transmission path by arranging a variable resistor in the variable impedance transmission circuit and combining the real-time feedback of the impedance matching detection circuit, and does not need to additionally design a peripheral matching circuit. The design saves additional impedance matching elements and wiring on a PCB, reduces material cost and design workload, and significantly reduces the overall design complexity and implementation cost of the system.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a chip input / output circuit. Background Technology

[0002] The chip input / output interface (I / O PAD) is the core processing module of the chip pins. It is responsible for processing external signals received by the chip pins and transmitting them into the chip, while also processing signals output from the chip and sending them to the chip pins. It can handle the input and output of signals such as clock, reset, and data, control signal levels and drive current, and has detection functions. Impedance matching of the input / output interface refers to the impedance adaptation characteristics between the chip output pins and the external printed circuit board (PCB) circuit. Its matching effect directly affects the integrity of high-speed signal transmission and is crucial to the stable operation of the entire system.

[0003] Existing chip input / output interfaces typically use fixed impedance values ​​during design, which cannot be dynamically adjusted. After the chip design is completed, a dedicated PCB needs to be designed based on this fixed impedance value, and a separate impedance matching circuit needs to be added. This not only increases the design cost and complexity of the system, but also has obvious drawbacks: the fixed impedance value is difficult to adapt to impedance shifts caused by factors such as temperature drift, frequency switching, and voltage fluctuations in dynamic operating environments. This can easily lead to problems such as overshoot and undershoot in signal transmission, seriously affecting signal integrity and even potentially damaging the electronic components at the receiving end, thus reducing system reliability. Summary of the Invention

[0004] This application provides a chip input / output circuit to at least solve the problem that the impedance matching circuit of the chip input / output interface in the related art cannot be dynamically adjusted.

[0005] This application provides a chip input / output circuit, including: a variable impedance transmission circuit, an impedance matching detection circuit, and an input / output interface. The first terminal of the variable impedance transmission circuit is a data input terminal, the second terminal is a data output terminal, and the third terminal is connected to the first terminal of the input / output interface. The first terminal of the impedance matching detection circuit is connected to the first terminal of the input / output interface, and the second terminal is connected to the control terminal of the variable impedance transmission circuit. The impedance matching detection circuit compares the voltage at the first terminal of the input / output interface with a first reference voltage and a second reference voltage, and then outputs an adjustment signal to the variable impedance transmission circuit to adjust the resistance value of the variable impedance transmission circuit. The second terminal of the input / output interface is used to input or output data. The first reference voltage is related to an overshoot voltage, and the second reference voltage is related to an undershoot voltage; the first reference voltage is greater than the second reference voltage.

[0006] In existing technologies, chip input / output interfaces use fixed impedances, requiring the addition of a separate impedance matching circuit on the PCB to adapt to the external transmission line impedance, leading to increased design costs and increased complexity. This application addresses this by incorporating a variable resistor in the variable impedance transmission circuit, combined with real-time feedback from the impedance matching detection circuit, to dynamically adjust the transmission path impedance without requiring additional external matching circuitry. This design eliminates the need for additional impedance matching components and wiring on the PCB, reducing material costs and design workload, and significantly lowering the overall system design complexity and implementation cost.

[0007] Traditional fixed impedance circuits cannot handle impedance shifts caused by dynamic factors such as temperature drift, frequency switching, and voltage fluctuations, easily leading to signal overshoot, undershoot, and even damage to receiver components. In this application, the impedance matching detection circuit uses first and second comparison circuits to collect the input and output interface voltages in real time, compares them with reference voltages corresponding to overshoot and undershoot thresholds, determines the matching status via an XOR gate, and then uses a counter to quantify the degree of mismatch and generate an adjustment signal. The variable impedance transmission circuit responds to the adjustment signal by dynamically adjusting the variable resistor value; the more severe the mismatch, the larger the adjustment. After adjustment, a secondary detection confirms the matching status, ensuring that the impedance always matches the external transmission line, effectively suppressing overshoot and undershoot, guaranteeing the integrity of high-speed signal transmission, and improving the long-term stability and reliability of the system.

[0008] This application achieves accurate judgment of impedance matching status and quantitative assessment of mismatch degree through a combination design of "dual comparator circuit + XOR gate + counter". The XOR gate can quickly distinguish between impedance matching (high output level) and mismatch (low output level) states based on the output signals of the two comparator circuits. The counter is triggered by a low level to count, converting the mismatch degree into a specific count value, and the count value directly corresponds to the adjustment range of the variable resistor, ensuring highly targeted adjustment actions. Simultaneously, the data transmission after adjustment undergoes impedance detection again, forming a closed-loop mechanism of "detection-adjustment-re-detection", avoiding the problem of insufficient adjustment in a single instance. This ensures both the accuracy of impedance matching and improves the response speed to impedance shifts under dynamic environments. Attached Figure Description

[0009] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a chip input / output circuit provided in an embodiment of this application; Figure 2A schematic diagram of a chip input / output circuit provided in an embodiment of this application; Figure 3 A schematic diagram of a chip input / output circuit provided in an embodiment of this application; Figure 4 A specific circuit diagram of the variable impedance transmission circuit provided in the embodiments of this application; Figure 5 A schematic diagram of a chip input / output circuit provided in an embodiment of this application; Figure 6 A specific circuit diagram of an impedance matching detection circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of impedance matching provided for an embodiment of this application; Figure 8 A waveform diagram provided for an embodiment of this application; Figure 9 This is a schematic diagram of the waveform after impedance matching provided in an embodiment of this application. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0012] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0013] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] Chip I / O PADs are chip pin processing modules that process signals from chip pins and send them to the chip's internal circuitry, and vice versa. Input signal processing includes clock signals, reset signals, and data signals, while output signals include clock signals, interrupt signals, and data signals. I / O PADs can control the levels and drive current of input and output signals, and also include detection functions. I / O PAD impedance matching refers to the impedance characteristics between the chip's output pins and the external PCB circuitry. Chip I / O PAD impedance matching has a significant impact on signal transmission and system performance, directly affecting the chip's signal integrity.

[0015] When designing existing chip I / O pads, the impedance is often fixed and cannot be adjusted. After the chip design is completed, the PCB is designed according to the impedance value of the pad to perform impedance matching. Generally, a separate impedance matching circuit needs to be added to the PCB board.

[0016] Using a fixed impedance value for the chip's I / O pads requires additional external circuitry for impedance matching, increasing design cost and complexity. Furthermore, a fixed impedance value cannot dynamically adapt to impedance shifts caused by temperature and frequency changes, potentially leading to signal integrity issues during transmission.

[0017] Embodiments of this application provide a chip input / output circuit designed to address the problems of poor adaptability and insufficient signal integrity caused by the use of fixed impedance in traditional chip input / output interfaces. It achieves adaptive impedance matching under dynamic environments, ensuring the stability and reliability of high-speed signal transmission. Figure 1 As shown, the chip's input / output circuit includes: a variable impedance transmission circuit 1, an impedance matching detection circuit 2, and an input / output interface 3 (i.e., PAD).

[0018] Specifically, the variable impedance transmission circuit 1 is the core impedance adjustment unit of the entire circuit, possessing data transmission and reception as well as dynamic impedance adjustment functions. The first end of this circuit receives the data to be transmitted from inside the chip; the second end transmits external input signals to the chip for processing; the third end is fixedly connected to the first end of the input / output interface 3, serving as a crucial transition node for signals entering and exiting the chip; the control end is connected to the second end of the impedance matching detection circuit 2, receiving adjustment signals from this detection circuit and dynamically changing its own impedance value according to the signal commands, thereby achieving impedance adaptation of the transmission path.

[0019] Optionally, such as Figure 2As shown, the variable impedance transmission circuit 1 is equipped with an input enable terminal and an output enable terminal. The data transmission direction is switched by the enable signal: when the input is enabled, external data is sent into the chip through the input buffer path; when the output is enabled, the data inside the chip is transmitted to the input / output interface 3 through the drive path and output to the outside.

[0020] Specifically, Figure 2 In the diagram, I is the data input terminal (i.e., the second terminal of the variable impedance transmission circuit 1), IE is the data input enable, OEN is the data output enable, C is the data output (i.e., the first terminal of the variable impedance transmission circuit 1), VDD is the PAD power supply, and Flag is the signal received from the impedance matching detection circuit 2.

[0021] Specifically, the impedance matching detection circuit 2 is responsible for impedance state detection and adjustment signal generation, monitoring the impedance matching status in real time and outputting targeted adjustment commands. The first terminal of this circuit is connected to the first terminal of the input / output interface 3 to collect the voltage status during signal transmission in real time; the second terminal is connected to the control terminal of the variable impedance transmission circuit 1 to output the adjustment signal. Its core working logic is as follows: First, based on the voltage standard of the input / output interface 3, a matching first reference voltage V1 and a second reference voltage V2 are generated. The first reference voltage V1 is the acceptable upper limit of overshoot voltage, and the second reference voltage V2 is the acceptable lower limit of undershoot voltage, with the first reference voltage V1 always being greater than the second reference voltage V2. Then, the collected voltage signal is compared with the two reference voltages respectively. After performing logical operations on the comparison results, the impedance mismatch degree is quantified by counting. The counting result is the adjustment signal; the more severe the mismatch, the larger the count value, and the stronger the corresponding adjustment requirement.

[0022] Specifically, the input / output interface 3 serves as the interaction interface between the chip and external circuits. Its second end is used to connect to an external transmission line to realize data input or output between the chip and external devices. The first end is connected to the third end of the variable impedance transmission circuit 1 and the first end of the impedance matching detection circuit 2. It serves as an intermediate node for signal transmission and provides a voltage acquisition point for impedance detection, ensuring that the impedance matching detection circuit 2 can obtain the signal transmission status in real time and provide an accurate basis for impedance adjustment.

[0023] Through the coordinated operation of the above modules, the impedance matching detection circuit 2 dynamically generates an adjustment signal based on the voltage state of the input / output interface 3. The variable impedance transmission circuit 1 responds to the adjustment signal and changes its own impedance, so that the impedance of the chip's input / output circuit matches the impedance of the external transmission line in real time, effectively avoiding overshoot and undershoot, and ensuring signal integrity and the stability and reliability of system operation.

[0024] In one alternative implementation, such as Figure 3As shown, the variable impedance transmission circuit 1 includes: a resistor branch 11, a first transmission sub-circuit 12, and a second transmission sub-circuit 13. The first end of the first transmission sub-circuit 12 is connected to the first end of the resistor branch 11, and the second end of the first transmission sub-circuit 12 is used to receive data to be transmitted from inside the chip. The first end of the second transmission sub-circuit 13 is used to transmit external input signals to the chip for processing, and the second end of the second transmission sub-circuit 13 is connected to the first end of the resistor branch 11. The second end of the resistor branch 11 is connected to the first end of the input / output interface 3, and the control end of the resistor branch 11 is connected to the second end of the impedance matching detection circuit 2.

[0025] Resistor branch 11 is the core of impedance adjustment in the entire circuit. It has the function of changing its own impedance characteristics in real time according to the control signal, and is a key link in realizing adaptive impedance matching. Its first end forms a common node with the first end of the first transmission sub-circuit 12 and the second end of the second transmission sub-circuit 13, serving as a convergence channel for data transmission and ensuring that the signals of the first transmission sub-circuit 12 and the second transmission sub-circuit 13 can flow stably through this branch. Its second end is fixedly connected to the first end of the input / output interface 3, forming a key transition path for signals entering and leaving the chip, which directly determines the impedance matching effect of signal transmission. The control end is connected in real time to the second end of the impedance matching detection circuit 2, specifically receiving the impedance adjustment signal from the detection circuit, and dynamically adjusting its own impedance parameters according to the signal command, so that the impedance of the transmission path tends to match the impedance of the external transmission line, effectively suppressing integrity problems such as signal overshoot and undershoot.

[0026] The first transmission sub-circuit 12 focuses on the external output processing of data to be transmitted from inside the chip. Its first terminal establishes a stable signal path with the first terminal of the resistor branch 11, and its second terminal serves as the data receiving terminal, specifically receiving the data to be transmitted generated inside the chip. This circuit has signal buffering and drive enhancement functions. After receiving the internal data, it performs signal stabilization processing to avoid the original signal fluctuations affecting the transmission quality. Then, it transmits the processed signal to the input / output interface 3 through the resistor branch 11, and finally outputs it to the external device, ensuring the stability and reliability of the external transmission of internal data.

[0027] The second transmission sub-circuit 13 is responsible for receiving and transmitting external input signals inward. Its first end serves as a signal output end, used to transmit the received and processed external signal to the core circuit inside the chip for subsequent calculations. The second end is connected to the first end of the resistor branch 11, forming an external signal receiving channel. When an external signal is received through the input / output interface 3, the second transmission sub-circuit 13 first performs preprocessing such as filtering and shaping on the signal to eliminate signal distortion caused by external interference, and then sends the shaped signal into the chip to ensure the accuracy of the transmission of external signals inward.

[0028] Through close connection and functional cooperation, the three components achieve synergy in bidirectional data transmission and dynamic impedance matching: the first transmission sub-circuit 12 and the second transmission sub-circuit 13 form a non-interfering transmission path through the resistor branch 11, and ensure data transmission quality with the help of their respective signal processing functions; the resistor branch 11 dynamically adjusts the impedance parameters according to the real-time feedback of the impedance matching detection circuit 2, ensuring that the impedance of the transmission path can match the external circuit regardless of whether the data is in the state of output or input, thereby comprehensively improving the integrity of the chip's input and output signals and the stability of system operation.

[0029] In one alternative implementation, such as Figure 4 As shown, the first transmission sub-circuit 12 includes a buffer 121, wherein the first end of the buffer 121 is connected to the first end of the resistor branch 11 (i.e., R0), and the second end of the buffer 121 is used to receive the data to be transmitted inside the chip.

[0030] The operating state of the first transmission sub-circuit 12 is controlled by the input enable signal. When the input enable signal is valid, the buffer 121 immediately starts the working mode, performs buffer amplification, noise filtering and waveform normalization on the received internal data of the chip, effectively suppresses the fluctuation interference in the original signal, and avoids the effect of subsequent impedance matching due to signal distortion. The normalized signal after processing is transmitted to the resistor branch 11 through its first end. Then, the resistor branch 11 adjusts the impedance according to the feedback of the impedance matching detection circuit 2, and transmits it to the input / output interface 3 and finally outputs it to the external device, ensuring the reliability and adaptability of data transmission to the outside.

[0031] In one alternative implementation, the second transmission sub-circuit 13 includes a CMOS circuit 131, wherein a first terminal of the CMOS circuit 131 is used to transmit external input signals to the chip for internal processing, and a second terminal of the CMOS circuit 131 is connected to the first terminal (i.e., R0) of the resistor branch 11.

[0032] The operating state of the CMOS circuit 131 coordinates with the input enable signal. When the input enable signal is valid, the circuit starts its operating mode and fully performs the reception and preprocessing of external signals. If the input enable signal is invalid, the circuit is in standby mode to avoid invalid signals interfering with the internal operation of the chip. Furthermore, the inherent impedance characteristics of the CMOS circuit 131 provide the basis for the initial impedance of the entire variable impedance transmission circuit 1, complementing the dynamic impedance adjustment of the subsequent resistor branch 11. This ensures that the impedance of the transmission path can be matched through coordinated adjustment during signal transmission, further guaranteeing the integrity and reliability of signal transmission.

[0033] In one alternative implementation, such as Figure 4As shown, the resistor branch 11 includes a variable resistor R0, wherein the first end of the resistor branch 11 is connected to the first end of the first transmission sub-circuit 12 and the first end of the second transmission sub-circuit 13, the second end of the variable resistor R0 is connected to the first end of the input / output interface 3, and the control end of the variable resistor R0 is connected to the second end of the impedance matching detection circuit 2.

[0034] When impedance matching detection circuit 2 detects impedance mismatch phenomena such as overshoot or undershoot in the signal, it sends an adjustment command to the control terminal of variable resistor R0 through an adjustment signal. Variable resistor R0 then dynamically changes its impedance value according to the command; the more severe the mismatch, the larger the adjustment range. Conversely, when the impedance is matched, variable resistor R0 maintains its current stable impedance value. Through this real-time feedback and dynamic adjustment mechanism, resistor branch 11 can continuously adapt to the impedance characteristics of the external transmission line, while also coping with impedance shifts caused by dynamic factors such as temperature drift and frequency switching. This ensures that the impedance of the entire transmission path remains matched with the external circuit during bidirectional data transmission, effectively suppressing signal distortion and guaranteeing the reliability and stability of high-speed signal transmission.

[0035] In one optional implementation, when the voltage at the first end of the input / output interface 3 is between the first reference voltage V1 and the second reference voltage V2, it indicates that the impedance of the input / output interface 3 is matched with the impedance of the external transmission line. At this time, the signal transmission will not have overshoot or undershoot, which can effectively ensure signal integrity.

[0036] like Figure 5 As shown, in order to accurately realize the detection and adjustment signal generation of impedance matching state, the impedance matching detection circuit 2 includes: a first comparison circuit 21, a second comparison circuit 22, and a timing circuit 23.

[0037] The first comparison circuit 21 serves as an overshoot detection unit, its core function being to determine whether the voltage at the input / output interface 3 exceeds the acceptable overshoot limit. The first terminal of this circuit establishes a real-time signal connection with the first terminal of the input / output interface 3, enabling accurate acquisition of voltage data during signal transmission. The second terminal is specifically connected to the first reference voltage V1, which is a preset acceptable overshoot limit voltage based on the voltage standard of the input / output interface 3, dynamically adaptable to actual application scenarios. The third terminal is fixedly connected to the first terminal of the timing circuit 23, used to output the voltage comparison result. Its operating logic is as follows: when the acquired voltage at the first terminal of the input / output interface 3 is greater than the first reference voltage V1, it indicates an overshoot and impedance mismatch, and the circuit outputs a high-level signal; when the acquired voltage is less than the first reference voltage V1, it indicates that the signal has not exceeded the overshoot limit, and the circuit outputs a low-level signal, providing a basis for subsequent logic processing.

[0038] The second comparator circuit 22, acting as an undershoot detection unit, complements the first comparator circuit 21. Its core function is to determine whether the voltage at the input / output interface 3 is below the acceptable undershoot limit. The first terminal of this circuit is also connected to the first terminal of the input / output interface 3, synchronously acquiring the signal transmission voltage. The second terminal is connected to a second reference voltage V2, which is a preset acceptable undershoot limit voltage and is always less than the first reference voltage V1. This voltage can also be dynamically adjusted according to different voltage standards. The third terminal is connected to the second terminal of the timing circuit 23, outputting another voltage comparison result. Its operating logic is as follows: when the acquired voltage is greater than the second reference voltage V2, it indicates that the signal is not below the undershoot limit, and the circuit outputs a high-level signal; when the acquired voltage is less than the second reference voltage V2, it indicates that the signal has undershooted and there is impedance mismatch, and the circuit outputs a low-level signal. This, together with the output signal of the first comparator circuit 21, constitutes a complete basis for judging the impedance matching state.

[0039] The timing circuit 23, as a logic processing and adjustment signal quantization unit, undertakes the core responsibilities of signal logic operations, mismatch quantization, and signal output adjustment. Its third terminal is connected to the control terminal of the variable impedance transmission circuit 1, enabling precise transmission of the quantized adjustment signal to the impedance adjustment unit. Its core workflow consists of two steps: The first step is logic processing. The two level signals output from the first comparator circuit 21 and the second comparator circuit 22 are XORed. When the two signals are different (i.e., the voltage at input / output interface 3 is between the first reference voltage V1 and the second reference voltage V2, indicating impedance matching), a specific logic signal is output after XOR processing. When the two signals are the same (i.e., the voltage is higher than the first reference voltage V1 or lower than the second reference voltage V2, indicating impedance mismatch), another logic signal is output, thus accurately distinguishing between matching and mismatch states. The second step is timing quantization. The mismatch logic signal after XOR processing is accumulated and timed to generate a corresponding count value, which is the final adjustment signal.

[0040] The magnitude of the count value is directly related to the degree of impedance mismatch: the more severe the mismatch, the longer the duration of the mismatch logic signal output after XOR processing, and the larger the count value; conversely, the smaller the count value. This count value corresponds to the resistance adjustment range of the variable impedance transmission circuit 1. After the timing circuit 23 outputs the count value to the control terminal of the variable impedance transmission circuit 1, the variable impedance transmission circuit 1 will dynamically adjust its own impedance according to the magnitude of the count value until the voltage of the input / output interface 3 returns to between the first reference voltage V1 and the second reference voltage V2, thus achieving precise impedance matching.

[0041] Through the coordinated operation of the three circuits mentioned above, the impedance matching detection circuit 2 can complete the impedance matching status detection, mismatch degree quantification and adjustment signal generation in real time and accurately, providing a scientific basis for the dynamic adjustment of the variable impedance transmission circuit 1, ensuring that the entire chip input and output circuit can adaptively cope with impedance shifts caused by dynamic factors such as temperature drift and frequency switching, and continuously ensuring the stability and integrity of signal transmission.

[0042] In one alternative implementation, such as Figure 6 As shown, the first comparison circuit 21 includes: a first comparator CMP1, wherein the positive input terminal of the first comparator CMP1 is connected to the first terminal of the input / output interface 3, the negative input terminal of the first comparator CMP1 is connected to the first reference voltage V1, and the third terminal of the first comparison circuit 21 is connected to the first terminal (i.e., XOR) of the timing circuit 23.

[0043] When the voltage at the input / output interface 3 acquired by the positive input terminal of the first comparator CMP1 is greater than the first reference voltage V1 at the negative input terminal, it indicates that the signal has overshoot and there is an impedance mismatch. At this time, the first comparator CMP1 outputs a high-level signal. When the acquired voltage is less than the first reference voltage V1, it indicates that the signal has not exceeded the overshoot limit, and the first comparator CMP1 outputs a low-level signal. By switching between high and low levels, the overshoot status is clearly fed back, providing a clear judgment basis for the subsequent operation of the entire impedance matching detection circuit 2.

[0044] In one alternative implementation, such as Figure 6 As shown, the second comparison circuit 22 includes: a second comparator CMP2, wherein the positive input terminal of the second comparator CMP2 is connected to the first terminal of the input / output interface 3, the negative input terminal of the second comparator CMP2 is connected to the second reference voltage V2, and the third terminal of the second comparison circuit 22 is connected to the second terminal (i.e., XOR) of the timing circuit 23.

[0045] When the voltage at the input / output interface 3 acquired by the positive input terminal of the second comparator CMP2 is greater than the second reference voltage V2 at the negative input terminal, it indicates that the signal is not below the acceptable undershoot limit, and the circuit outputs a high-level signal. When the acquired voltage is less than the second reference voltage V2, it indicates that the signal has undershoot, and there is impedance mismatch, and the circuit outputs a low-level signal. Through this clear switching between high and low levels, the undershoot state is clearly fed back. This, in conjunction with the overshoot detection result of the first comparator circuit 21, enables a comprehensive and accurate judgment of the impedance matching state, laying a solid foundation for the subsequent logic processing and adjustment signal generation of the entire impedance matching detection circuit 2.

[0046] In one alternative implementation, such as Figure 6As shown, the timing circuit 23 includes an XOR gate and a timer. The first terminal of the XOR gate is connected to the third terminal of the first comparator circuit 21, the second terminal of the XOR gate is connected to the third terminal of the second comparator circuit 22, and the third terminal of the XOR gate is connected to the first terminal of the timer. The second terminal of the timer is connected to the control terminal of the variable impedance transmission circuit 1, and the timer is triggered to count when the level is low.

[0047] When the impedance of input / output interface 3 is in a matched state, the first comparator circuit 21 outputs a low level and the second comparator circuit 22 outputs a high level. The two input signals are in different states, and the XOR gate outputs a high-level signal, indicating that impedance adjustment does not need to be started at present. When impedance mismatch occurs in input / output interface 3 (signal overshoot or undershoot), the first comparator circuit 21 and the second comparator circuit 22 will output the same level signal (both high level or both low level). The two input signals are in the same state, and the XOR gate outputs a low-level signal. This low-level signal is the mismatch indicator signal that triggers the counter Timer to count.

[0048] The timer, acting as a mismatch quantization unit, is specifically responsible for accumulating and counting the mismatch signal output from the XOR gate, and converting the count result into an adjustment signal that can drive impedance adjustment. The timer only starts counting when a low-level mismatch signal is received from the XOR gate output; if a high-level signal is received, the current count value remains unchanged.

[0049] The timer counter is connected to the control terminal of the variable impedance transmission circuit 1, enabling the quantized count value to be output as an adjustment signal in real time. The magnitude of the count value is positively correlated with the degree of impedance mismatch: the more severe the mismatch, the longer the duration of the low level output by the XOR gate, and the larger the cumulative count value of the timer counter; conversely, the smaller the count value. This count value corresponds to the resistance adjustment range of the variable impedance transmission circuit 1; the larger the count value, the larger the impedance adjustment range of the variable impedance transmission circuit 1, thereby achieving precise impedance matching through quantization feedback until the voltage of the input / output interface 3 returns to between the first reference voltage V1 and the second reference voltage V2, completing impedance matching.

[0050] In one optional embodiment, the impedance matching detection circuit 2 further includes a reference voltage circuit (i.e., R1, R2, R3), wherein the reference voltage circuit is used to output a first reference voltage V1 and a second reference voltage V2.

[0051] In a practical application scenario, based on the above implementation methods, Figure 7 This is a schematic diagram of impedance matching.

[0052] refer to Figure 7The impedance of the chip PAD is Za, and the impedance of the transmission line connected to the PAD is Zl. If Za and Zl are not equal (i.e., impedance mismatch), the transmitted signal will exhibit overshoot and undershoot phenomena. Prolonged or excessively large overshoot or undershoot can damage the electronic components at the receiving end, causing losses. Therefore, traditional PCB designs require an additional impedance matching circuit to accommodate Za and Zl, ensuring signal integrity.

[0053] When the chip needs to send data, the output enable terminal OEN is set to 0. The variable resistor R0 in the variable impedance transmission circuit 1 is initially set to the minimum resistance value (approaching 0). At this time, the data inside the chip is sent to PAD through the data input terminal I via R0 and output to the outside of the chip. Za is the fixed impedance of the complementary metal-oxide-semiconductor (CMOS) circuit.

[0054] Based on the PAD's IO voltage standard (1.0V / 1.2V / 1.8V / 2.5V / 3.3V / 5V) and the AC / DC specification (SEPC) of the IO PAD, configure the voltage divider resistors Rref1, Rref2, and Rref3, and set reasonable reference voltages V1 and V2, where V1 is the acceptable overshoot upper limit voltage and V2 is the acceptable undershoot lower limit voltage.

[0055] When Za and Zl impedances are matched, the output signal has no overshoot or undershoot, and its voltage amplitude is between V1 and V2. While outputting data to the external chip, the PAD inputs a voltage signal to impedance matching detection circuit 2: the PAD voltage and V1 are connected to comparator CMP1, and the PAD voltage and V2 are connected to comparator CMP2. Due to impedance matching, the PAD voltage is between V1 and V2, so CMP1 outputs 0 (V1 > PAD voltage), and CMP2 outputs 1 (V2 < PAD voltage), i.e., the comparison results VS1=0 and VS2=1. The two results are XORed and output as 1. The timer only records the 0 value generated by one level transition; the XOR circuit outputs 1 for all other time periods. This count result (Flag=1) is sent to the variable impedance transmitting / receiving module, indicating that the impedance is matched and no adjustment is needed.

[0056] When Za and Zl are impedance mismatched, this embodiment can achieve adaptive impedance adjustment: The PAD voltage is also input to the impedance matching detection circuit 2. Due to overshoot or undershoot, the PAD voltage will be higher than V1 or lower than V2, causing the comparators to output the same level—either CMP1 outputs 1 (V1 < PAD voltage) and CMP2 outputs 1 (V2 < PAD voltage) (VS1=1, VS2=1), or CMP1 outputs 0 (V1 > PAD voltage) and CMP2 outputs 0 (V2 > PAD voltage) (VS1=0, VS2=0). The two identical levels are XORed to output 0. The counter Timer accumulates this 0 value, and the more severe the impedance mismatch, the more 0 values ​​are accumulated, indicating a stronger need for impedance adjustment. The counter Timer sends the counting result (Flag) to the variable impedance transmitting / receiving module. The module adjusts the resistance value of the variable resistor R0 according to the Flag value. The larger the Flag value, the larger the adjustment range of R0.

[0057] After R0 is adjusted, when the chip sends data again, the data will enter the impedance matching detection circuit 2 for re-checking: if Flag is still greater than 1, it indicates that the impedance is not fully matched and needs to be adjusted again; if Flag=1, it indicates that the impedance is matched and no further operation is required.

[0058] In a specific example, refer to Figure 8 Let's take a 1.8V IO PAD high level as an example for explanation: like Figure 8 As shown, when the output of the 1.8V IO PAD changes from 0 to 1, overshoot and undershoot occur, indicating impedance mismatch.

[0059] Configure Rref1, Rref2, and Rref3 such that the reference voltage of V1 is 2.1V (1.8V + 0.3V) and the reference voltage of V2 is 1.5V (1.8V - 0.3V).

[0060] During the P0 phase, the signal level changes from low to high. In the first half of the P0 phase, the signal voltage is less than V1 and V2, i.e., VS1=0 and VS2=0. After passing through the XOR circuit, the output is 0, and the count value is 1.

[0061] In the P1 stage, which is an overshoot, the signal voltage is greater than V1 and V2, i.e., VS1=1 and VS2=1. After passing through the XOR circuit, the output is 0, and the count value is 2.

[0062] In the P2 stage, the signal is between V1 and V2, i.e., VS1=0 and VS2=1. After passing through the XOR circuit, the output is 1, and the count value is 2.

[0063] In the P3 stage, which is undershoot, the signal voltage is less than V1 and V2, i.e., VS0=1 and VS2=0. After passing through the XOR circuit, the output is 1, and the count value is 2.

[0064] In stage P4, the signal is between V1 and V2, i.e., VS1=0 and VS2=1. After passing through the XOR circuit, the output is 1, and the count value is 2.

[0065] In the P5 stage, which is an overshoot, the signal voltage is greater than V1 and V2, i.e., VS1=1 and VS2=1. After passing through the XOR circuit, the output is 0, and the count value is 3.

[0066] In stage P6, the signal is between V1 and V2, i.e., VS1=0 and VS2=1. After passing through the XOR circuit, the output is 1, and the count value is 3.

[0067] In the P7 stage, which is undershoot, the signal voltage is less than V1 and V2, i.e., VS0=1 and VS2=0. After passing through the XOR circuit, the output is 1, and the count value is 3.

[0068] In stage P8, the signal is between V1 and V2, i.e., VS1=0 and VS2=1. After passing through the XOR circuit, the output is 1, and the count value is 3.

[0069] Finally, the Flag value is 3, and this value is output to the variable impedance transmitter / receiver module to adjust the resistor R0.

[0070] After adjusting the resistor R0, the final result is as follows: Figure 9 The waveform shown has a level between V1 and V2, with no overshoot or undershoot. The flag value is recorded as 1 only in the P0 stage. In the other stages, the XOR circuit outputs 1. At this point, the impedance can be considered matched.

[0071] When temperature or environmental changes occur, and overshoot or undershoot recurs, automatic impedance adjustment will be restarted until the overshoot or undershoot is eliminated. This achieves adaptive impedance matching.

[0072] The above provides a detailed description of a chip input / output circuit provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A chip input / output circuit, characterized in that, include: The circuit includes a variable impedance transmission circuit, an impedance matching detection circuit, and input / output interfaces. The first end of the variable impedance transmission circuit is used to receive data to be transmitted inside the chip, the second end of the variable impedance transmission circuit is used to transmit external input signals to the chip for processing, and the third end of the variable impedance transmission circuit is connected to the first end of the input / output interface. The first terminal of the impedance matching detection circuit is connected to the first terminal of the input / output interface, and the second terminal of the impedance matching detection circuit is connected to the control terminal of the variable impedance transmission circuit. The impedance matching detection circuit is used to compare the voltage at the first terminal of the input / output interface with the first reference voltage and the second reference voltage, and then output an adjustment signal to the variable impedance transmission circuit. The adjustment signal is used to adjust the resistance value of the variable impedance transmission circuit. The second end of the input / output interface is used to receive or output data. The first reference voltage is related to the overshoot voltage, the second reference voltage is related to the undershoot voltage, and the first reference voltage is greater than the second reference voltage.

2. The chip input / output circuit according to claim 1, characterized in that, The variable impedance transmission circuit includes: a resistor branch, a first transmission sub-circuit, and a second transmission sub-circuit, wherein... The first end of the first transmission sub-circuit is connected to the first end of the resistor branch, and the second end of the first transmission sub-circuit is used to receive data to be transmitted inside the chip. The first end of the second transmission sub-circuit is used to transmit external input signals to the chip for processing, and the second end of the second transmission sub-circuit is connected to the first end of the resistor branch. The second end of the resistor branch is connected to the first end of the input / output interface, and the control end of the resistor branch is connected to the second end of the impedance matching detection circuit.

3. The chip input / output circuit according to claim 2, characterized in that, The first transmission sub-circuit includes: a buffer, wherein, The first end of the buffer is connected to the first end of the resistor branch, and the second end of the buffer is used to receive data to be transmitted inside the chip.

4. The chip input / output circuit according to claim 2, characterized in that, The second transmission sub-circuit includes: a CMOS circuit, wherein, The first terminal of the CMOS circuit is used to transmit external input signals to the chip for processing, and the second terminal of the CMOS circuit is connected to the first terminal of the resistor branch.

5. The chip input / output circuit according to claim 2, characterized in that, The resistor branch includes: a variable resistor, wherein, The first end of the resistor branch is connected to the first end of the first transmission sub-circuit and the first end of the second transmission sub-circuit. The second end of the variable resistor is connected to the first end of the input / output interface. The control end of the variable resistor is connected to the second end of the impedance matching detection circuit.

6. The chip input / output circuit according to claim 1, characterized in that, When the voltage at the first terminal of the input / output interface is between the first reference voltage and the second reference voltage, the impedance of the input / output interface is in a matched state. The impedance matching detection circuit then includes: a first comparator circuit, a second comparator circuit, and a timing circuit, wherein... The first terminal of the first comparison circuit is connected to the first terminal of the input / output interface, the second terminal of the first comparison circuit is connected to the first reference voltage, and the third terminal of the first comparison circuit is connected to the first terminal of the timing circuit. The first comparison circuit is used to output a high-level signal when the voltage at the first terminal of the input / output interface is greater than the first reference voltage, and to output a low-level signal when the voltage at the first terminal of the input / output interface is less than the first reference voltage. The first terminal of the second comparator circuit is connected to the first terminal of the input / output interface, the second terminal of the second comparator circuit is connected to the second reference voltage, and the third terminal of the second comparator circuit is connected to the second terminal of the timing circuit. The second comparator circuit is used to output a high-level signal when the voltage at the first terminal of the input / output interface is greater than the second reference voltage, and to output a low-level signal when the voltage at the first terminal of the input / output interface is less than the second reference voltage. The third terminal of the timing circuit is connected to the control terminal of the variable impedance transmission circuit. The timing circuit is used to perform XOR processing on the output signals of the first comparison circuit and the second comparison circuit, and output a count value after timing according to the processing result. The count value is the adjustment signal. The count value is used to adjust the resistance value of the variable impedance transmission circuit and corresponds to the resistance value of the variable impedance transmission circuit.

7. The chip input / output circuit according to claim 6, characterized in that, The first comparison circuit includes: a first comparator, wherein, The positive input terminal of the first comparator is connected to the first terminal of the input / output interface, the negative input terminal of the first comparator is connected to the first reference voltage, and the third terminal of the first comparator circuit is connected to the first terminal of the timing circuit.

8. The chip input / output circuit according to claim 6, characterized in that, The second comparison circuit includes: a second comparator, wherein, The positive input terminal of the second comparator is connected to the first terminal of the input / output interface, the negative input terminal of the second comparator is connected to the second reference voltage, and the third terminal of the second comparator circuit is connected to the second terminal of the timing circuit.

9. The chip input / output circuit according to claim 6, characterized in that, The timing circuit includes: an XOR gate and a counter, wherein... The first terminal of the XOR gate is connected to the third terminal of the first comparison circuit, the second terminal of the XOR gate is connected to the third terminal of the second comparison circuit, and the third terminal of the XOR gate is connected to the first terminal of the counter. The second terminal of the counter is connected to the control terminal of the variable impedance transmission circuit, and the counter is triggered to count when the level is low.

10. The chip input / output circuit according to claim 6, characterized in that, The impedance matching detection circuit further includes: a reference voltage circuit, wherein... The reference voltage circuit is used to output the first reference voltage and the second reference voltage.

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