A test method, a zq calibration apparatus, and a memory
By performing N ZQ calibration tests on the internal resistance of the memory, correction parameters for the fine-tuning reference voltage and offset voltage are obtained, solving the problem of low ZQ calibration accuracy caused by process deviations and achieving higher calibration accuracy and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XINCUN MICRO TECHNOLOGY (BEIJING) CO LTD
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-12
AI Technical Summary
In the prior art, process deviations lead to low ZQ calibration accuracy, which affects the internal resistance calibration accuracy of the memory.
By performing N ZQ calibration tests on the internal resistance of the memory under test, N fine-tuning reference voltages and fine-tuning offset voltages are obtained, resulting in a first correction parameter and a second correction parameter. These parameters are used to correct the original reference voltage and offset voltage of the comparator, thereby improving the ZQ calibration accuracy.
By applying the corrected parameters, the accuracy of ZQ calibration was significantly improved, the interference of process deviations on calibration was eliminated, and the stability and accuracy of the memory under different process, voltage and temperature conditions were ensured.
Smart Images
Figure CN122201390A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory technology, and in particular to a test method, a ZQ calibration device, and a memory. Background Technology
[0002] Zone Qualifier (ZQ) calibration involves adding a ZQ port to the memory chip. This ZQ port is used to connect an external high-precision calibration resistor. During calibration, the code controlling the internal resistor begins to change. The voltage divider formed by the series connection of the internal resistor and the calibration resistor is compared with a reference voltage via a comparator. The comparator output is fed back to the logic control circuit. This process is repeated, using a successive approximation algorithm, until the voltage divider value of the internal resistor approaches the reference voltage, at which point the resistance value of the internal resistor is obtained. However, due to process variations, several factors (such as comparator offset voltage and reference voltage deviation) can affect the accuracy of ZQ calibration. Therefore, a solution is urgently needed to overcome the impact of process variations on ZQ calibration accuracy and improve its precision. Summary of the Invention
[0003] A testing method, a ZQ calibration device, and a memory are provided to overcome the impact of process deviations on ZQ calibration accuracy, thereby improving the accuracy of ZQ calibration.
[0004] In a first aspect, a testing method is provided for a memory, the memory including a ZQ calibration device, the method comprising:
[0005] The internal resistance of the memory under test is subjected to N ZQ calibration tests based on N fine-tuning reference voltages and N fine-tuning offset voltages, and the test results are obtained; N is a positive integer. Based on the test results, the first correction parameter and the second correction parameter are obtained; The first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device.
[0006] In some embodiments, the test method further includes: acquiring N fine-tuning reference voltages and N fine-tuning offset voltages, including: acquiring N-bit fine-tuning parameters, an original reference voltage, and an original offset voltage; adjusting the original reference voltage and the original offset voltage according to the N-bit fine-tuning parameters to obtain N fine-tuning reference voltages and N fine-tuning offset voltages.
[0007] In some implementations, the test results include: N test resistance values; obtaining the test results includes: performing ZQ calibration tests on the internal resistance under N fine-tuning reference voltages respectively, and obtaining the test resistance value corresponding to each fine-tuning reference voltage; and / or performing ZQ calibration tests on the internal resistance under N fine-tuning offset voltages respectively, and obtaining the test resistance value corresponding to each fine-tuning offset voltage.
[0008] In some implementations, a first correction parameter and a second correction parameter are obtained based on the test results, including: among N test resistance values, the test resistance value closest to the internal resistance is obtained as the target test resistance value; The first fine-tuning parameter corresponding to the target test resistance value is used as the first correction parameter; and / or the second fine-tuning parameter corresponding to the target test resistance value is used as the second correction parameter; wherein, the first fine-tuning parameter is used to correct the original reference voltage; and the second fine-tuning parameter is used to correct the original offset voltage.
[0009] In some implementations, the internal resistance includes a pull-up resistor; based on the test results, a first correction parameter and a second correction parameter are obtained, including: among N test resistance values, obtaining the test resistance value closest to the pull-up resistor as the target test resistance value; using a first fine-tuning parameter corresponding to the target test resistance value as the first correction parameter; and / or using a second fine-tuning parameter corresponding to the target test resistance value as the second correction parameter; wherein, the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a first reference voltage for calibrating the pull-up resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
[0010] In some embodiments, the internal resistance includes a pull-down resistor; wherein, based on the test results, obtaining a first correction parameter and a second correction parameter includes: among N test resistance values, obtaining the test resistance value closest to the pull-down resistor as the target test resistance value; using a first fine-tuning parameter corresponding to the target test resistance value as the first correction parameter; and / or using a second fine-tuning parameter corresponding to the target test resistance value as the second correction parameter; wherein, the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a second reference voltage for calibrating the pull-down resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
[0011] Secondly, a ZQ calibration device is also provided for calibrating the resistance value of the memory's internal resistors by connecting an external resistor through the memory's ZQ interface. The device includes: The test module is configured to perform N ZQ calibration tests on the internal resistance of the memory under test based on N fine-tuning reference voltages to obtain a first correction parameter and a second correction parameter; the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration to obtain the target reference voltage; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration to eliminate the original offset voltage; the first correction parameter and the second correction parameter are obtained by the method provided in the second aspect; N is a positive integer; The calibration module is configured to compare the voltage divider formed by the series connection of the internal resistor and the external resistor with the target reference voltage to obtain a comparison result, and to calibrate the internal resistor based on the comparison result.
[0012] In some embodiments, the internal resistance includes a pull-up resistor and a pull-down resistor; the test module includes a first test submodule and a second test submodule; wherein, the first test submodule is configured to perform N ZQ calibration tests on the pull-up resistor of the memory under test using N fine-tuning reference voltages to obtain a first correction parameter and a second correction parameter; the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a first reference voltage for calibrating the pull-up resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage; the second test submodule is configured to perform N ZQ calibration tests on the pull-down resistor of the memory under test using N fine-tuning reference voltages to obtain a first correction parameter and a second correction parameter; the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a second reference voltage for calibrating the pull-down resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
[0013] In some embodiments, the calibration module includes: a first calibration circuit and a second calibration circuit; wherein the first calibration circuit is configured to compare the voltage divider formed by the series connection of the pull-up resistor and the external resistor with a first reference voltage to obtain a first comparison result, so as to calibrate the pull-up resistor according to the first comparison result; the second calibration circuit is configured to compare the voltage divider formed by the series connection of the pull-down resistor and the external resistor with a second reference voltage to obtain a second comparison result, so as to calibrate the pull-down resistor according to the second comparison result.
[0014] Thirdly, a memory is also provided, comprising: at least one memory chip, each memory chip having a ZQ calibration device as provided in the second aspect.
[0015] The above technical solution corrects the original reference voltage of the comparator in the ZQ calibration device by using the first correction parameter, which helps to improve the accuracy of ZQ calibration. At the same time, it corrects the original offset voltage of the comparator in the ZQ calibration device by using the second correction parameter, which can eliminate the interference of the original offset voltage on ZQ calibration, thereby improving the accuracy of ZQ calibration. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the framework for ZQ calibration according to an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of a successive approximation algorithm for ZQ calibration according to an exemplary embodiment of this disclosure; Figure 3 This is a flowchart illustrating a test method according to an exemplary embodiment of the present disclosure; Figure 4 This is a schematic diagram of ZQ calibration according to an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of the frame of the ZQ calibration device according to an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram illustrating the calibration of the pull-up resistor for ZQ calibration, as an exemplary embodiment of this disclosure. Figure 7 This is a schematic diagram illustrating the acquisition of a target reference voltage according to an exemplary embodiment of this disclosure. Detailed Implementation
[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] In the description of the embodiments of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0020] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0021] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.
[0022] In related technologies, since the internal resistance of a chip is composed of metal-oxide-semiconductor (MOS) and polysilicon (poly) resistors, the resistance value will change with process voltage and temperature (PVT) conditions. Therefore, it is usually necessary to calibrate the internal resistance.
[0023] In existing technologies, ZQ calibration is typically used to calibrate the internal resistance of memory. Internal resistance includes pull-up resistors and pull-down resistors. Figure 1 This is a schematic diagram of the framework for ZQ calibration according to an exemplary embodiment of this disclosure, as shown below. Figure 1As shown, when ZQ calibration begins, the code controlling the pull-up resistor (PUDRV<6:0>) starts to change, and the voltage divider (Vp) of the pull-up resistor and the external resistor connected in series is compared with the reference voltage (Vref) to the comparator of the ZQ calibration device; after the comparator feeds back the output result to the logic controller, the code controlling the pull-up resistor changes again, and so on. Figure 2 This is a schematic diagram of the successive approximation algorithm for ZQ calibration according to an exemplary embodiment of this disclosure. The successive approximation algorithm, such as... Figure 2 As shown, the pull-up resistor calibration is completed when the voltage divider (Vp) formed by the series connection of the pull-up resistor and the external resistor approaches the reference voltage infinitely closely using a successive approximation algorithm. However, due to process variations, the reference voltage and offset voltage of the comparator in the ZQ calibration device may deviate, resulting in lower accuracy of the ZQ calibration.
[0024] To at least partially address one or more of the aforementioned problems and other potential issues, this disclosure proposes a testing method. The method includes: performing N ZQ calibration tests on the internal resistance of the memory under test based on N fine-tuning reference voltages and N fine-tuning offset voltages, respectively, to obtain test results; where N is a positive integer; and obtaining a first correction parameter and a second correction parameter based on the test results. The first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device. Thus, correcting the original reference voltage of the comparator in the ZQ calibration device using the first correction parameter helps improve the accuracy of ZQ calibration; simultaneously, correcting the original offset voltage of the comparator in the ZQ calibration device using the second correction parameter can eliminate the interference of the original offset voltage on ZQ calibration, thereby improving the accuracy of ZQ calibration.
[0025] Figure 3 This is a flowchart illustrating a test method according to an exemplary embodiment of this disclosure, such as... Figure 3 As shown, the method includes at least: S301: Perform N ZQ calibration tests on the internal resistance of the memory under test based on N fine-tuning reference voltages and N fine-tuning offset voltages to obtain the test results; N is a positive integer.
[0026] In some embodiments, the fine-tuning reference voltage is obtained by applying different bits of fine-tuning parameters to the original reference voltage. For example, the original reference voltage is Vref0, and each of the N bits of fine-tuning parameters corresponds to a fine-tuning step size ΔVref. By combining different fine-tuning bits, N different fine-tuning reference voltages Vref1, Vref2, ..., VrefN can be generated.
[0027] In some embodiments, the offset voltage is fine-tuned by applying different bits of fine-tuning parameters to the original offset voltage. For example, the original offset voltage is Vos0, and each of the N fine-tuning parameters corresponds to a fine-tuning step size ΔVos. By combining different fine-tuning bits, N different fine-tuned offset voltages Vos1, Vos2, ..., VosN can be generated. In practical applications, the N fine-tuning reference voltages can be combined with the N fine-tuning offset voltages to achieve synchronous correction of the comparator's reference voltage and offset voltage.
[0028] In some embodiments, the memory under test refers to the memory to be ZQ calibrated. The memory under test may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR). Here, there is no limitation on the type and model of the memory under test; for example, the test method of this disclosure is applicable to memory types such as DDR4 and DDR5.
[0029] In some embodiments, the internal resistors include pull-up resistors and pull-down resistors, which are devices used in the memory for signal transmission and level matching. Pull-up resistors are used to pull the signal line high to a specific level to ensure stable signal output; pull-down resistors are used to pull the signal line low to a specific level to prevent unpredictable fluctuations in the signal during idle states. Precise calibration of the pull-up and pull-down resistors ensures the accuracy and stability of memory data transmission. During ZQ calibration, pull-up and pull-down resistor calibrations are performed separately. The pull-up resistor calibration is compared with a precision reference resistor on the external chip, and the resistance value of the pull-up resistor is adjusted according to the comparison result to maintain stable electrical characteristics under different PVT conditions.
[0030] In some embodiments, ZQ calibration test refers to setting N fine-tuning reference voltages as the reference voltages of the comparator in the ZQ calibration device, and performing N ZQ calibration tests on the internal resistance of the memory to be tested to obtain test results; and / or setting N fine-tuning offset voltages as the offset voltages of the comparator in the ZQ calibration device, and performing N ZQ calibration tests on the internal resistance of the memory to be tested to obtain test results.
[0031] In some embodiments, the test result refers to the measured resistance value of the internal resistance of the memory under test after performing N ZQ calibration tests based on N fine-tuning reference voltages and N fine-tuning offset voltages respectively, for each ZQ calibration test. For example, if in the (N-1)th ZQ calibration test, the comparator of the ZQ calibration device uses the (N-1)th fine-tuning reference voltage and the (N-1)th fine-tuning offset voltage to perform ZQ calibration on the internal resistance of the memory under test, then the resistance value of the internal resistance after performing the ZQ calibration test using the (N-1)th fine-tuning reference voltage and the (N-1)th fine-tuning offset voltage is obtained.
[0032] S302: Based on the test results, obtain the first correction parameter and the second correction parameter; In some embodiments, the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device. Obtaining the first correction parameter includes: performing ZQ calibration tests on the internal resistance under N fine-tuning reference voltages, obtaining the test resistance value corresponding to each fine-tuning reference voltage, and among the N test resistance values, obtaining the test resistance value closest to the internal resistance as the target test resistance value, and using the fine-tuning parameter corresponding to the target test resistance value as the first correction parameter.
[0033] In some embodiments, the original reference voltage refers to the reference voltage value used by the comparator in the uncorrected ZQ calibration device. The original reference voltage is typically a fixed voltage value preset according to design requirements; however, in practical applications, it may deviate from the ideal value due to factors such as process, voltage, and temperature. Adjusting the original reference voltage using a first correction parameter, for example by superimposing or compensating the original reference voltage Vref0 with the fine-tuning step size ΔVref corresponding to the first correction parameter, yields the corrected reference voltage Vref_cal = Vref0 + ΔVref. K (where K is the fine-tuning bit value corresponding to the first correction parameter) is used to make the comparator's reference voltage closer to the ideal value.
[0034] In some embodiments, the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device. Obtaining the second correction parameter includes: performing ZQ calibration tests on the internal resistors under N fine-tuning offset voltages, and obtaining the test resistance value corresponding to each fine-tuning offset voltage; using the second fine-tuning parameter corresponding to the target test resistance value as the second correction parameter. The original offset voltage Vos0 is an inherent voltage difference of the comparator, where the output is non-zero when the input is zero. The offset voltage directly affects the comparator's comparison accuracy. The second correction parameter cancels or compensates for the original offset voltage. For example, the original offset voltage Vos0 is calculated using the fine-tuning step size ΔVos corresponding to the second correction parameter to obtain the corrected offset voltage Vos_cal = Vos0 - ΔVos. M (where M is the fine-tuning bit value corresponding to the second correction parameter) can effectively reduce the interference of offset voltage on the ZQ calibration results.
[0035] It should be noted that in the above embodiments, the N-bit fine-tuning parameters include the K-bit fine-tuning parameters and the M-bit fine-tuning parameters.
[0036] In some embodiments, the second correction parameter corrects the original offset voltage of the comparator in the ZQ calibration device.
[0037] In some embodiments, the ZQ calibration device is used to connect an external resistor via the ZQ interface of the memory to calibrate the resistance value of the memory's internal resistor. A comparator is used to compare the voltage drop across the series connection of the internal and external resistors with a target reference voltage to obtain a comparison result. This comparison result is used to calibrate the internal resistor.
[0038] In this embodiment of the disclosure, the test method further includes: obtaining N fine-tuning reference voltages and N fine-tuning offset voltages, including: obtaining N-bit fine-tuning parameters, the original reference voltage, and the original offset voltage; adjusting the original reference voltage and the original offset voltage according to the N-bit fine-tuning parameters to obtain N fine-tuning reference voltages and N fine-tuning offset voltages.
[0039] In some embodiments, the N-bit trim parameter is a pre-defined digital code used to fine-tune the original reference voltage and the original offset voltage. The number of bits N can be designed according to the actual calibration accuracy requirements. Each bit in the N-bit trim parameter represents an independent control signal, and different bit combinations correspond to different trim amplitudes. For example, for a 4-bit trim parameter, it can represent 16 different trim states from 0000 to 1111, each state corresponding to a specific trim step size combination, thereby achieving multi-level, fine-tuning of the original reference voltage and the original offset voltage. In practical applications, the N-bit trim parameter can be configured through registers within the memory.
[0040] In this embodiment of the disclosure, the test results include: N test resistance values; obtaining the test results includes: performing ZQ calibration tests on the internal resistance under N fine-tuning reference voltages respectively, and obtaining the test resistance value corresponding to each fine-tuning reference voltage; and / or performing ZQ calibration tests on the internal resistance under N fine-tuning offset voltages respectively, and obtaining the test resistance value corresponding to each fine-tuning offset voltage.
[0041] In some embodiments, the test resistance value refers to the actual resistance value of the internal resistance of the memory under test after calibration during the ZQ calibration test. Specifically, after the ZQ calibration device performs calibration on the internal resistance (such as a pull-up resistor or a pull-down resistor) using a specific fine-tuning reference voltage or fine-tuning offset voltage, the real-time resistance value of the internal resistance read by the relevant measurement circuit or feedback mechanism is the test resistance value. This test resistance value can directly reflect the effect of ZQ calibration under the current fine-tuning parameter combination and is a key basis for judging whether the reference voltage and offset voltage correction are effective. For example, when calibrating a pull-down resistor, if the i-th fine-tuning reference voltage is used in a certain test, the measured resistance value of the pull-down resistor after calibration is the test resistance value corresponding to the fine-tuning reference voltage. By comparing it with the target standard resistance value, the applicability of the fine-tuning reference voltage can be evaluated.
[0042] In some embodiments, during the (N-1)th ZQ calibration test, after the ZQ calibration device sets the (N-1)th fine-tuning reference voltage as the comparator's reference voltage, the internal resistor is calibrated. After calibration, the resistance value of the calibrated internal resistor is read through the resistance measurement module inside the memory or an external testing device; this resistance value is the test resistance value corresponding to the (N-1)th fine-tuning reference voltage.
[0043] In some embodiments, during the (N-1)th ZQ calibration test, after the ZQ calibration device sets the (N-1)th fine-tuning offset voltage as the comparator's reference voltage, the internal resistor is calibrated. After calibration, the resistance value of the calibrated internal resistor is read through the resistance measurement module inside the memory or an external testing device; this resistance value is the test resistance value corresponding to the (N-1)th fine-tuning offset voltage.
[0044] In this embodiment of the disclosure, the first correction parameter and the second correction parameter are obtained based on the test results, including: among N test resistance values, the test resistance value closest to the internal resistance is obtained as the target test resistance value; a first fine-tuning parameter corresponding to the target test resistance value is used as the first correction parameter; and / or a second fine-tuning parameter corresponding to the target test resistance value is used as the second correction parameter; wherein, the first fine-tuning parameter is a parameter corresponding to the target test resistance value used to correct the original reference voltage; and the second fine-tuning parameter is a parameter corresponding to the target test resistance value used to correct the original offset voltage.
[0045] In some embodiments, the target test resistance value refers to the test resistance value among N test resistance values that is closest to the standard resistance value of the internal resistor. The standard resistance value of the internal resistor can be preset according to the requirements of the memory. For example, if the standard resistance value of the pull-down resistor of memory A is 50Ω, and test resistance values of 48Ω, 51Ω, and 49.5Ω are obtained in N ZQ calibration tests, and the deviation between 49.5Ω and 50Ω is the smallest, then 49.5Ω is taken as the target test resistance value. In this way, the fine-tuning parameters that have the best correction effect on the original reference voltage or the original offset voltage can be accurately located, thereby providing a reliable basis for correcting the original reference voltage and the original offset voltage, and further improving the accuracy of ZQ calibration.
[0046] Figure 4 This is a schematic diagram of ZQ calibration according to an exemplary embodiment of this disclosure, as shown below. Figure 4 As shown, the error of the ZQ calibration device can be equivalent to the voltage Vos at the input of the ZQ calibration comparator. Based on this, the standard resistance value of the internal resistor can be calculated using the following formula: ; in, The standard resistance value indicating the internal resistance; Indicates the resistance value of the external resistor; Indicates the supply voltage; This represents the reference voltage of the comparator in the ZQ calibration device; This represents the offset voltage of the comparator in the ZQ calibration device.
[0047] In some embodiments, the first fine-tuning parameter is a fine-tuning parameter corresponding to the target test resistance value among the N fine-tuning reference voltages, used to correct the original reference voltage of the comparator in the ZQ calibration device. Specifically, after performing N ZQ calibration tests on the internal resistance of the memory to be tested using N fine-tuning reference voltages to obtain N test resistance values, the test resistance value closest to the internal resistance among the N test resistance values is selected as the target test resistance value, and the first fine-tuning parameter corresponding to the target test resistance value is used as the first correction parameter. For example, if the test resistance value corresponding to the N-1 fine-tuning parameter is closest to the resistance value of the internal resistance, then the N-1 fine-tuning parameter is used as the first correction parameter to correct the original reference voltage of the comparator in the ZQ calibration device, so as to eliminate the reference voltage deviation caused by factors such as process, voltage, and temperature.
[0048] In some embodiments, the second fine-tuning parameter is a fine-tuning parameter corresponding to the target test resistance value among the N-bit fine-tuning offset voltages, used to correct the original offset voltage of the comparator in the ZQ calibration device. Specifically, after performing N ZQ calibration tests on the internal resistance of the memory to be tested using N fine-tuning offset voltages to obtain N test resistance values, the test resistance value closest to the internal resistance among the N test resistance values is selected as the target test resistance value, and the second fine-tuning parameter corresponding to the target test resistance value is used as the second correction parameter.
[0049] In this embodiment of the disclosure, the internal resistance includes a pull-up resistor; based on the test results, a first correction parameter and a second correction parameter are obtained, including: among N test resistance values, obtaining the test resistance value closest to the pull-up resistor as the target test resistance value; using a first fine-tuning parameter corresponding to the target test resistance value as the first correction parameter; and / or using a second fine-tuning parameter corresponding to the target test resistance value as the second correction parameter; wherein, the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a first reference voltage for calibrating the pull-up resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
[0050] In some embodiments, a pull-up resistor refers to a resistor element inside the memory used to pull signal lines to a high level. For example, when a memory I / O pin needs to output a high level, the pull-up resistor pulls the pin's level up to near the power supply voltage, ensuring stable signal transmission. The accuracy of the pull-up resistor value directly affects key performance indicators such as signal rise time, drive capability, and power consumption. If the pull-up resistor value is too large, it may cause the signal to rise slowly, affecting the data transmission rate; if the value is too small, it will increase the chip's static power consumption. Therefore, pull-up resistors need to be calibrated using a ZQ calibration device to ensure signal integrity and reliability during high-speed data read and write operations.
[0051] In some embodiments, the first reference voltage is used to calibrate the pull-up resistor.
[0052] In some embodiments, the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
[0053] In this embodiment of the disclosure, the internal resistor includes a pull-down resistor; wherein, based on the test results, a first correction parameter and a second correction parameter are obtained, including: among N test resistance values, obtaining the test resistance value closest to the pull-down resistor as the target test resistance value; using a first fine-tuning parameter corresponding to the target test resistance value as the first correction parameter; and / or using a second fine-tuning parameter corresponding to the target test resistance value as the second correction parameter; wherein, the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a second reference voltage for calibrating the pull-down resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
[0054] In some embodiments, a pull-down resistor is a resistor element inside the memory used to pull signal lines low to a low level. For example, when a memory I / O pin needs to output a low level, the pull-down resistor pulls the pin's level down to near ground, ensuring accurate signal transmission. The accuracy of the pull-down resistor value also has a significant impact on the signal fall time, interference immunity, and power consumption. If the pull-down resistor value is too large, it may cause the signal to fall slowly, affecting the stability of data transmission; if the resistance value is too small, it will increase the dynamic power consumption of the chip. Therefore, pull-down resistors need to be calibrated using a ZQ calibration device to ensure signal integrity and reliability of the memory during high-speed data read and write processes.
[0055] In some embodiments, the second reference voltage is used to calibrate the pull-down resistor.
[0056] Table 1 shows a comparison of the offset voltage before and after correction. As shown in Table 1, with VDD=1.2V as the test condition, the comparison shows the data of the original offset voltage (Vos) of the comparator in the ZQ calibration of the memory in the range of 1-10mV, the calibration value of the pull-up resistor of the 240Ω external reference resistor (Rpu_cal240), the calibration deviation (delta), and the reference voltage (vref) before and after correction. The data shows that before correction, as the offset voltage increases, the calibration value of the pull-up resistor deviates more from the standard value, and the calibration deviation climbs from 1.15% to 4.25%. The reference voltage remains fixed at 960.2mV, and the correction effect is poor. However, by adopting the solution of this application, the calibration accuracy is greatly improved by adjusting the reference voltage and eliminating the offset voltage interference. Even if the offset voltage rises to 10mV, the calibration deviation can be stabilized within 1.02%, and the deviation is as low as 0.08% under some operating conditions. Therefore, the solution proposed in this application can effectively offset the negative impact of offset voltage on ZQ calibration, and significantly improve the accuracy and stability of pull-up resistor ZQ calibration.
[0057]
[0058] Table 1 Figure 5 This is a schematic diagram of the framework of a ZQ calibration apparatus according to an exemplary embodiment of this disclosure, as shown below. Figure 5 As shown, the device includes at least: Test module 501 is configured to: perform N ZQ calibration tests on the internal resistance of the memory under test based on N fine-tuning reference voltages to obtain a first correction parameter and a second correction parameter; the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration to obtain a target reference voltage; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration to eliminate the original offset voltage; the first correction parameter and the second correction parameter are obtained according to the method provided in the first aspect; N is a positive integer; The calibration module 502 is configured to compare the voltage divider formed by the series connection of the internal resistor and the external resistor with the target reference voltage to obtain a comparison result, so as to calibrate the internal resistor based on the comparison result.
[0059] In some embodiments, an external resistor refers to a high-precision reference resistor connected externally to the memory chip. Its resistance value is typically preset to a fixed standard value, such as 240Ω or other standard resistance value determined according to the memory specifications. During ZQ calibration, the external resistor serves as a calibration reference. It is connected in series with an internal memory resistor (such as a pull-up or pull-down resistor) to form a voltage divider. The calibration module is configured to compare the voltage divider formed by the series connection of the internal and external resistors with a target reference voltage corrected by a first correction parameter, inputting it to a comparator to obtain a comparison result (such as a high or low level signal) from the comparator output. The internal resistor is then calibrated based on the comparison result. The external resistor can be a resistor element with a low temperature coefficient and high precision characteristics to ensure a stable and reliable reference during calibration.
[0060] In some embodiments, the target reference voltage refers to the reference voltage used by the comparator in the ZQ calibration device, after being corrected by a first correction parameter. This target reference voltage is used to compare with the voltage divider formed by the internal resistor and the external resistor connected in series, in order to calibrate the internal resistor.
[0061] In this embodiment, the internal resistors include pull-up resistors and pull-down resistors; the test module includes a first test submodule and a second test submodule; wherein, the first test submodule is configured to perform N ZQ calibration tests on the pull-up resistors of the memory under test using N fine-tuning reference voltages to obtain a first correction parameter and a second correction parameter; the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a first reference voltage for calibrating the pull-up resistors; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage; the second test submodule is configured to perform N ZQ calibration tests on the pull-down resistors of the memory under test using N fine-tuning reference voltages to obtain the first correction parameter and the second correction parameter; the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a second reference voltage for calibrating the pull-down resistors; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
[0062] In this embodiment of the present disclosure, the calibration module includes: a first calibration circuit and a second calibration circuit; wherein, the first calibration circuit is configured to compare the voltage divider formed by the series connection of the pull-up resistor and the external resistor with a first reference voltage to obtain a first comparison result, so as to calibrate the pull-up resistor according to the first comparison result; the second calibration circuit is configured to compare the voltage divider formed by the series connection of the pull-down resistor and the external resistor with a second reference voltage to obtain a second comparison result, so as to calibrate the pull-down resistor according to the second comparison result.
[0063] In some embodiments, the first calibration circuit is used to perform ZQ calibration on the pull-up resistor; the first comparison result can be the level signal output by the comparator in the first calibration circuit. For example, when the series voltage divider is higher than the first reference voltage, the comparator outputs a high level; when the series voltage divider is lower than the first reference voltage, the comparator outputs a low level. The first calibration circuit can adjust the resistance value of the pull-up resistor according to the first comparison result by adjusting the on and off states of the switches in the resistor network containing the pull-up resistor, so that the resistance value of the pull-up resistor gradually approaches the standard resistance value of the pull-up resistor. Specifically, if the first comparison result is high, the resistance value of the pull-up resistor is too small, so the resistance value of the pull-up resistor is increased; if the comparison result is low, the resistance value of the pull-up resistor is too large, so the resistance value of the pull-up resistor is decreased.
[0064] Figure 6 This is a schematic diagram illustrating the ZQ calibration of the pull-up resistor according to an exemplary embodiment of this disclosure, as shown below. Figure 6As shown, the ZQ calibration reference resistor array (n-bit DAC) receives the pull-up reference voltage fine-tuning signal, outputs the reference voltage, and sends it to the positive input of the comparator; the pull-up resistor array (m-bit DAC) generates dynamically adjustable pull-up resistors to be calibrated, and their node voltages (pull-up voltages) are fed into the negative input of the comparator; the comparator outputs a first comparison result by comparing the two voltages, and the first comparison result is used as a feedback signal input to the logic controller, which dynamically adjusts the configuration parameters of the pull-up resistor array to calibrate the pull-up resistors.
[0065] Figure 7 A schematic diagram illustrating the acquisition of the target reference voltage according to an exemplary embodiment of this disclosure, as shown below. Figure 7 As shown, the power supply Vddq, after being divided by a series of resistors, generates multiple voltage dividers with fixed ratios at different nodes; the pull-up reference voltage is then used for fine-tuning the signal. <rn-1:0>Under digital control, the multiplexer selects one voltage divider from multiple voltage dividers with fixed ratios as the target reference voltage.
[0066] In some embodiments, the second calibration circuit is used to perform ZQ calibration on the pull-down resistor; the second comparison result can be the level signal output by the comparator in the second calibration circuit. For example, when the series voltage divider is higher than the second reference voltage, the comparator outputs a high level; when the series voltage divider is lower than the second reference voltage, the comparator outputs a low level. The second calibration circuit can adjust the resistance value of the pull-down resistor by adjusting the on / off state of the switches in the resistor network containing the pull-down resistor, based on the second comparison result, so that the resistance value of the pull-down resistor gradually approaches its standard resistance value. Specifically, if the second comparison result is high, the resistance value of the pull-down resistor is too large, so the resistance value of the pull-down resistor is decreased; if the comparison result is low, the resistance value of the pull-down resistor is too small, so the resistance value of the pull-down resistor is increased.
[0067] This embodiment also provides a memory, including: at least one memory chip, each memory chip having a ZQ calibration device as provided in the second aspect.
[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0069] The test method, ZQ calibration device, and memory provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A testing method applied to a memory, the memory including a ZQ calibration device, characterized in that, The method includes: The internal resistance of the memory under test is subjected to N ZQ calibration tests based on N fine-tuning reference voltages and N fine-tuning offset voltages, and the test results are obtained; N is a positive integer. Based on the test results, the first correction parameter and the second correction parameter are obtained; The first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device.
2. The method according to claim 1, characterized in that, Also includes: Obtaining N of the fine-tuning reference voltages and N of the fine-tuning offset voltages includes: Obtain the N-bit fine-tuning parameters, the original reference voltage, and the original offset voltage; The original reference voltage and the original offset voltage are adjusted according to the N-bit fine-tuning parameters to obtain N fine-tuning reference voltages and N fine-tuning offset voltages.
3. The method according to claim 2, characterized in that, The test results include: N test resistance values; obtaining the test results includes: After performing ZQ calibration tests on the internal resistance at each of the N fine-tuning reference voltages, the test resistance value corresponding to each fine-tuning reference voltage is obtained; and / or Under N fine-tuning offset voltages, the internal resistance is subjected to ZQ calibration tests respectively, and the test resistance value corresponding to each fine-tuning offset voltage is obtained.
4. The method according to claim 3, characterized in that, The step of obtaining the first correction parameter and the second correction parameter based on the test results includes: Among the N test resistance values, the test resistance value that is closest to the internal resistance is selected as the target test resistance value. The first fine-tuning parameter corresponding to the target test resistance value is used as the first correction parameter; and / or The second fine-tuning parameter corresponding to the target test resistance value is used as the second correction parameter; Wherein, the first fine-tuning parameter is a fine-tuning parameter used to correct the original reference voltage; the second fine-tuning parameter is a fine-tuning parameter used to correct the original offset voltage.
5. The method according to claim 4, characterized in that, The internal resistance includes a pull-up resistor; obtaining the first correction parameter and the second correction parameter based on the test results includes: Among the N test resistance values, the test resistance value that is closest to the pull-up resistor is selected as the target test resistance value; The first fine-tuning parameter corresponding to the target test resistance value is used as the first correction parameter; and / or The second fine-tuning parameter corresponding to the target test resistance value is used as the second correction parameter; Wherein, the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a first reference voltage for calibrating the pull-up resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
6. The method according to claim 4, characterized in that, The internal resistance includes a pull-down resistor; wherein, obtaining the first correction parameter and the second correction parameter based on the test results includes: Among the N test resistance values, the test resistance value that is closest to the pull-down resistor is selected as the target test resistance value; The first fine-tuning parameter corresponding to the target test resistance value is used as the first correction parameter; and / or The second fine-tuning parameter corresponding to the target test resistance value is used as the second correction parameter; Wherein, the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a second reference voltage for calibrating the pull-down resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
7. A ZQ calibration device for calibrating the resistance value of the internal resistance of a memory by connecting an external resistor through the ZQ interface of the memory, characterized in that, The device includes: The test module is configured to perform N ZQ calibration tests on the internal resistance of the memory under test based on N fine-tuning reference voltages, to obtain a first correction parameter and a second correction parameter; the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration to obtain a target reference voltage; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration to eliminate the original offset voltage; the first correction parameter and the second correction parameter are obtained by the method according to any one of claims 1-6; N is a positive integer; The calibration module is configured to compare the voltage divider formed by the series connection of the internal resistor and the external resistor with the target reference voltage to obtain a comparison result, so as to calibrate the internal resistor based on the comparison result.
8. The apparatus according to claim 7, characterized in that, The internal resistance includes: a pull-up resistor and a pull-down resistor; the test module includes: a first test submodule and a second test submodule; wherein... The first test submodule is configured to perform N ZQ calibration tests on the pull-up resistor of the memory under test using N fine-tuning reference voltages to obtain the first correction parameter and the second correction parameter. The first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a first reference voltage for calibrating the pull-up resistor. The second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage. The second test submodule is configured to perform N ZQ calibration tests on the pull-down resistor of the memory under test using N fine-tuning reference voltages to obtain the first correction parameter and the second correction parameter; the first correction parameter is used to correct the original reference voltage of the comparator in the ZQ calibration device to obtain a second reference voltage for calibrating the pull-down resistor; the second correction parameter is used to correct the original offset voltage of the comparator in the ZQ calibration device to eliminate the original offset voltage.
9. The apparatus according to claim 8, characterized in that, The calibration module includes: a first calibration circuit and a second calibration circuit; wherein... The first calibration circuit is configured to compare the voltage divider formed by the series connection of the pull-up resistor and the off-chip resistor with the first reference voltage to obtain a first comparison result, so as to calibrate the pull-up resistor according to the first comparison result; The second calibration circuit is configured to compare the voltage divider formed by the series connection of the pull-down resistor and the external resistor with the second reference voltage to obtain a second comparison result, so as to calibrate the pull-down resistor according to the second comparison result.
10. A memory, characterized in that, The memory includes: At least one memory chip, each of which is provided with a ZQ calibration device as described in any one of claims 7 to 9.