Low complexity bit error rate estimation for coding fuzzy-fine programming

Abstract

A memory die estimates a bit error rate (BER) of a fuzzy program operation and uses the BER to determine whether to decode fuzzy program data on the memory die for a fine program operation. A controller on the die receives data from a storage device and generates parity pages based on the data. The controller performs a fuzzy program operation to write the data to memory cells in a block. The controller separates states in the memory cells into categories based on values of the parity pages associated with the states. The controller also performs a soft bit sensing operation and estimates a BER of the memory cells based on the soft bit sensing operation. Based on the BER, the memory controller performs on-die decoding of fuzzy program data with the parity pages or transfers the fuzzy program data to the storage device for decoding.

Description

Background Technology

[0001] The storage device is communicatively coupled to a host and non-volatile memory, including, for example, a NAND flash memory device, on which the storage device can store data received from the host. The storage device may include multiple dies capable of being divided into physical blocks, and the storage device can store data in blocks on the storage device. Data can be stored in blocks in various formats, defined by the number of bits that can be stored per memory cell. For example, a single-cell (SLC) format can write one information bit per memory cell, a multi-cell (MLC) format can write two information bits per memory cell, a three-cell (TLC) format can write three information bits per memory cell, a four-cell (QLC) format can write four information bits per memory cell, and so on.

[0002] The format used to store data on a memory device determines how the data is encoded within the cells of the memory device. Unlike SLC memory devices, which have a single threshold voltage and a transistor that is either on or off, QLC cell memory devices can have sixteen possible voltage states within a voltage window. Data can be encoded based on the different states of memory cells in multi-bit cells, and can be encoded into the top page, previous page, middle page, and next page.

[0003] When a controller on a storage device sends data to the memory device for storage, the controller can use, for example, a low-density parity-check (LDPC) encoder to protect the data using LDPC codes. The memory device can use fuzzy-fine programming operations to write data into sixteen voltage states in, for example, a QLC memory cell. These fuzzy-fine programming operations can include a first (fuzzy) programming operation and a second (fine) programming operation. Using fuzzy operations, the next page, middle page, previous page, and top page can be programmed into a first / approximate distribution. The first distribution may overlap and result in a higher bit error rate (BER), meaning that when reading memory cells within the first distribution, a large number of errors may occur due to overlap.

[0004] To protect data during the fuzzy phase and enable its retrieval for subsequent fine-grained programming, one or two temporary parity pages can be computed by XORing the next, middle, previous, and top pages in voltage states. These parity pages can be stored in a data cache (e.g., an SLC memory on a memory device). For a QLC memory cell with sixteen voltage states, when a parity page is computed, it indicates whether the programming state is even or odd. Adjacent states may not have the same parity. States with even parity can be assigned to a first / even category, and states with odd parity can be assigned to a second / odd category. When two parity pages are computed, they indicate whether the programming state modulo 4 equals 0 / 1 / 2 / 3 (i.e., two parity bits can divide the state into four categories). Parity pages can be used to distinguish states within the same category and can achieve greater state separation.

[0005] Before fine programming, a parity page can be used to read and decode an fuzzy page on the memory device. Any errors in the decoded fuzzy page can lead to a "hard" error that allows fine programming to continue. Therefore, the memory device ensures that the decoded fuzzy page has a sufficiently low BER before fine programming. When estimating the BER, the memory device estimates the number of cells in the overlapping region between the first / fuzzy distribution. If the memory device determines that there are several cells in the overlapping region, it can send the data to the storage device for decoding using, for example, an LDPC decoder. After decoding the data using the LDPC decoder, the storage device can send the data back to the memory device for fine programming. If the memory device determines that the BER is sufficiently low, it can use the parity page to decode the fuzzy data and perform fine programming on the decoded fuzzy data. Summary of the Invention

[0006] In some implementations, the memory die can estimate the bit error rate (BER) of the encoded fuzzy programming operation to determine whether to decode the fuzzy programmed data on the memory die for fine programming operations. The memory die may include blocks for storing data in various formats. An on-die memory controller can receive data from a storage device and generate parity pages based on that data. The memory controller can perform fuzzy programming operations to write the data into memory cells within the block. The memory controller can classify the states in the memory cells based on the values ​​of the parity pages associated with the states. The memory controller can also perform soft-bit sensing operations and estimate the BER of the memory cell based on these operations. Based on the BER, the memory controller can perform on-chip decoding of the fuzzy programmed data using the parity pages and write the decoded data into the block using fine programming operations.

[0007] In some implementations, a method is provided for estimating the BER of an encoded fuzzy programming operation to determine whether to decode fuzzy programmed data on a memory die for fine-grained programming operations. The method includes receiving data from a storage device and generating a parity page based on the data. The method further includes: performing a fuzzy programming operation to write data into memory cells in a block; classifying states in the memory cells based on the values ​​of the parity pages associated with the states; and performing a soft-bit sensing operation. The method also includes estimating the BER of the memory cells based on the soft-bit sensing operation, and performing on-chip decoding of the fuzzy programmed data using the parity pages based on the BER. The method further includes writing the decoded data into a block using fine-grained programming operations.

[0008] In some implementations, a method is provided for estimating the bit error rate (BER) of an encoded fuzzy programming operation to determine whether to decode fuzzy programmed data on a memory die for fine programming operations. The method includes receiving data from a storage device and generating at least one parity page based on the data. The method further includes: performing a fuzzy programming operation to write data into memory cells in a block; classifying states in the memory cells based on the values ​​of the parity pages associated with states; and performing a soft bit sensing operation and generating soft bit pages. The method also includes estimating the BER of the memory cells based on the soft bit pages. Based on the BER, the method includes performing on-chip decoding of the fuzzy programmed data using the parity pages, or determining that the fuzzy programmed data is to be transferred to a storage device for decoding. When the fuzzy programmed data is to be transferred to a storage device, the method includes: sending the fuzzy programmed data and the soft bit pages to the storage device; receiving the decoded fuzzy programmed data from the storage device; and writing the decoded fuzzy programmed data into a block using fine programming operations. Attached Figure Description

[0009] Figure 1 It is a schematic block diagram based on some specific implementation example systems.

[0010] Figure 2 These are example functional block diagrams based on some specific implementations of memory dies.

[0011] Figure 3 An example of fuzzy programming is illustrated, based on some specific implementations, using a group of QLC memory cells corresponding to sixteen data states and sixteen parity pages.

[0012] Figure 4 Examples of soft bit reads for BER estimation based on some specific implementations are illustrated.

[0013] Figure 5 Another example of soft bit readings for BER estimation is illustrated according to some specific implementations.

[0014] Figure 6 Examples of memory dies encoded according to a first conversion according to some specific implementations are illustrated.

[0015] Figure 7 An example of an encoding recovery table, according to some specific implementation, that can be applied to a memory die encoded according to a first conversion is illustrated.

[0016] Figure 8 This is an example flowchart based on some specific implementations for generating soft bit information for BER estimation of fuzzy programming data.

[0017] Figure 9 This is another example flowchart based on some specific implementations for generating soft bit information for BER estimation of fuzzy programming data.

[0018] Figure 10 This is an example flowchart based on some specific implementations of soft bit information generated using BER estimation for fuzzy programming data.

[0019] Figure 11 This is a diagram illustrating an example environment in which the systems and / or methods described herein are implemented.

[0020] Those skilled in the art will understand that the elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding specific embodiments of this disclosure.

[0021] Where appropriate, apparatus and method components have been indicated by conventional symbols in the accompanying drawings, which show those specific details relevant to understanding particular embodiments of this disclosure so as not to obscure the contents of this disclosure by details readily apparent to those skilled in the art.

[0022] Detailed description of the invention

[0023] The following detailed description of the example implementation is given with reference to the accompanying drawings. The same reference numerals in different drawings may identify the same or similar elements.

[0024] Figure 1 This is a schematic block diagram of an example system based on some specific implementations. System 100 includes a host 102 and a storage device 104. The host 102 can send commands to read data from or write data to the storage device 104. The host 102 and the storage device 104 may be located in the same physical location as components on a single computing device or on different computing devices that are communicatively coupled. In various implementations, the storage device 104 may be located in one or more different locations relative to the host 102, and the storage device 104 may communicate with the host 102 via protocols such as Fast Peripheral Component Interconnect (PCIe). The host 102 may include additional components (not shown in this figure for simplicity).

[0025] Storage device 104 may include random access memory (RAM) 106, controller 108, and one or more non-volatile memory devices 110a-110n (referred to herein as memory device 110). Storage device 104 may be, for example, a solid-state drive (SSD). RAM 106 may be static RAM (SRAM) or dynamic RAM (DRAM) that can be used to store information for use on storage device 104.

[0026] Controller 108 can interface with host 102 and handle foreground operations including instructions sent from host 102. For example, controller 108 can read data from and / or write data to memory device 110 based on instructions received from host 102. Controller 108 can also perform background operations to manage resources on memory device 110. For example, controller 108 can perform garbage collection, read refresh, and other relocation functions according to internal relocation algorithms to refresh, recycle, and / or relocate data on memory device 110.

[0027] Memory device 110 may be flash-based. For example, memory device 110 may be a NAND or NOR flash memory used to store host and control data throughout its operational lifetime. Memory device 110 may include one or more dies (e.g., die 0 to die X) connected to memory bus 112 (including data lines and chip enable lines). Memory bus 112 may communicate with a switching mode (TM) interface (not shown) to communicatively couple memory device 110 to controller 108. Dies may be partitioned into blocks to store data, and the data may be stored in various formats, including, for example, SLC, MLC, TLC, and / or QLC formats. Memory device 110 may be included in or otherwise communicatively coupled to storage device 104. Figure 1 This is provided as an example. Other examples may differ. Figure 1 The example described.

[0028] Figure 2 This is an example functional block diagram of a memory die according to some specific implementations. The memory die 202 may include one or more memory structures 204 and a memory controller 206. The memory structure 204 may include configurable memory segments that may include blocks for storing data in a given format. For example, the memory structure 204 may include: a QLC memory 204a, which may include a first set of blocks for storing data in a (first) QLC format; and an SLC memory 204b, which may include a second set of blocks for storing data in a (second) SLC format.

[0029] The memory controller 206 may include read / write circuitry 208, control circuitry 210, and parity check circuitry 212. Read / write circuitry 206 may include sensing circuitry to enable parallel reading or programming of memory cell pages in memory structure 204. Control circuitry 210 provides die-level control of memory operations, controlling the power and voltage supplied to word lines and bit lines during memory operations, and cooperates with read / write circuitry 206 to perform memory operations on memory structure 204. Parity check circuitry 212 generates one or more parity pages by performing an XOR operation on the next, middle, previous, and top pages under voltage conditions. Parity pages can be used to protect data during the fuzzy phase and make it readable. Parity pages may be stored in a data cache (e.g., SLC memory 204b) until fine programming is initiated, and data generated by fine programming may be stored in QLC memory 204a. This allows for fuzzy-fine programming to be performed with relatively low traffic on the bus 112 between the controller 108 and the memory device 110. Figure 2This is provided as an example. Other examples may differ. Figure 2 The example described.

[0030] Figure 3 An example of fuzzy programming is illustrated, according to some specific implementations, using a group of QLC memory cells corresponding to sixteen data states and sixteen parity pages. 302 shows a QLC memory cell with sixteen voltage states, where a parity page can be computed to indicate whether the fuzzy programmed state is even or odd. Adjacent states may not have the same parity. For example, S0 may have an even parity (e.g., 0), S1 may have an odd parity (e.g., 1), S2 may have an even parity, S3 may have an odd parity, and so on. States with even parity can be assigned to a first category, and states with odd parity can be assigned to a second category. For example, when a state with even parity is assigned to an even category, it is indicated by E on the distribution, and when a state with odd parity is assigned to an odd category, it is indicated by O on the distribution.

[0031] Figure 304 illustrates a QLC memory cell with sixteen voltage states, wherein two parity pages are computed to indicate whether the programmed state modulo 4 equals 0 / 1 / 2 / 3 (i.e., the two parity bits divide the state into four categories). For example, the two parity pages can be used to assign states to categories one, two, three, and four (shown in the distribution as 1, 2, 3, 4). Parity pages can be used to distinguish between states within the same category and can achieve greater state separation between states within the same category. Parity pages thus enable memory controller 206 to perform fuzzy data recovery. Figure 3 This is provided as an example. Other examples may differ. Figure 3 The example described.

[0032] After fuzzy programming of the cells in QLC memory 204a as shown in 302 and 304, memory controller 206 can perform low-complexity BER estimation by counting the number of cells in overlapping regions within each category, as identified by a unique parity bit value for each category. Memory controller 206 can perform soft bit (SB) reads for cells in each category. SB reads may include reads near the midpoint between states in each category. Memory controller 206 can generate SB pages from the SB reads for each category. The number of zeros in the SB page indicates how many cells have a threshold voltage within the overlapping region and are prone to error. If the number of zeros in the SB page is below a predefined threshold, then memory controller 206 can estimate the BER of the fuzzy page to be low, and the parity page can be used to decode the fuzzy page for fine-grained write operations.

[0033] If the number of zeros in the SB page is at or above a predefined threshold, then the memory controller 206 can estimate that the BER of the fuzzy page is high. The memory controller 206 can send the fuzzy page to the controller 108 for the controller 108 to use, for example, an LDPC engine to decode the data, so that the controller 108 can return the "clean" page to the memory device 110 for fine programming. Figure 3 This is provided as an example. Other examples may differ. Figure 3 The example described.

[0034] Figure 4 Examples of soft bit reads for BER estimation according to some specific implementations are illustrated. 402 shows a state from 302 with even / parity and assigned to a first / even category, and 404 shows a state from 302 with odd / parity and assigned to a second / odd category. Dashed lines in 402 are intended to indicate distributions not in the first / even category, and dashed lines in 404 are intended to indicate distributions not in the second / odd category. Taking the distributions in the even category in 402 and the odd category in 404 as examples, the memory controller 206 can perform sensing near the midpoint between the distributions / states in the categories. For example, the memory controller 206 can perform sensing at different voltage levels s0-s13, where the memory controller 206 can perform a sensing operation at s0, perform an XOR operation (NXOR) on the result with the result of the sensing operation at s1, perform an NXOR operation on the result with the result of the sensing operation at s2, perform an NXOR operation on the result with the result of the sensing operation at s3, perform an NXOR operation on the result with the result of the sensing operation at s4, and so on. The memory controller 206 can therefore perform fourteen sensing operations to obtain SB pages for each category. An SB page may include, for example, sixteen kilobytes of cells, where each cell includes a soft bit value. The memory controller 206 may store the results from the sensing operations in a latch.

[0035] 406 illustrates a mapping of SB pages, where the logical representation of an SB page is shown as 1 within a region under each distribution and as 0 between lines between two distributions. Based on the logical representation of the SB page, 0 may indicate that a cell is in a transition region. 406 illustrates an SB mapping and its size is the number of sensing operations plus 1 (e.g., in...). Figure 3 In the example, 15), where the SB page can typically be a 16KB page, with each cell on the word line corresponding to a bit indicating whether the cell's Vt is in the transition region between states ("0") or outside the transition region ("1"). Cells with an SB value of "0" are more prone to errors (because their Vt is in the transition between states), and therefore the number of "0"s in the SB page may be related to the bit error rate (BER) of the ambiguous page.

[0036] The memory controller 206 can count the number of zeros in the SB pages of the latch. If the number of zeros is below a predefined threshold, the memory controller 206 can determine that the BER is low, and can perform on-chip decoding using the parity page and continue fine programming. In rare cases, the number of zeros in the SB pages may be at or above the predefined threshold. In such cases, the memory controller 206 can determine that the BER is high, and can send a fuzzy programming page to the controller 108 for the controller 108 to decode the data using the decoder. After the controller 108 decodes the data, it can return a "clean" page to the memory device 110 for fine programming.

[0037] In a typical sensing operation, a voltage may be applied to the control gate, and a check may be performed to determine if current is flowing in the bit line. This check to determine current flow in the bit line can be performed by waiting for some integration time and checking if the bit line capacitor has dropped (i.e., current is flowing in the bit line). The memory controller 206 may apply a specific value for the control gate voltage corresponding to s0, a higher control gate voltage corresponding to s1, a higher control gate voltage corresponding to s2 than the control gate voltage corresponding to s1, a higher control gate voltage corresponding to s3 than the control gate voltage corresponding to s2, and so on. Therefore, each sensing operation may require more time to wait for the voltage to stabilize.

[0038] The memory controller 206 can perform faster sensing operations, such as s0 and s1, using a single control gate voltage and modulating / changing the integration time of the sensing amplifier. Adjusting the integration time mimics changing the control gate voltage. With the same control gate voltage, the memory controller 206 can use two integration times to sense, for example, s0 and s1. Therefore, assuming the transition is not too large, the memory controller 206 can use integration time modulation instead of control gate voltage modulation to sense transitions between states. With faster sensing operations, the memory controller 206 can perform sensing operations in a shorter time. For example, using faster sensing operations, the memory controller 206 can complete the sensing operations from s0 to s13 in the time required to perform seven to fourteen sensing operations in a conventional sensing operation. It should be noted that if a wider range of BER estimation is required, this method can be applied to three-bit or four-bit encoding. Figure 4 This is provided as an example. Other examples may differ. Figure 4 The example described.

[0039] Figure 5Another example of soft-bit reading for BER estimation according to some specific implementations is illustrated. Memory controller 206 can perform fuzzy page reading and SB sensing in the same operation. Therefore, SB sensing can be combined with hard-bit sensing for reading fuzzy pages. This can reduce the total sensing time by approximately 37 percent compared to hard-bit sensing plus soft-bit sensing alone. When performing fuzzy page reading and SB sensing in the same operation, memory controller 206 can also estimate the BER for multiple categories in a single sensing operation, such as... Figure 5 As shown. For example, memory controller 206 may perform twenty-eight sensing operations to estimate the BER of the categories shown in 402 and 404, instead of performing fourteen sensing operations for estimating the BER of one category, as shown in 402 and 404. Memory controller 206 may use parity bits to determine which sensing operations should be performed together in an NXOR operation. For example, memory controller 206 may use parity bits to determine that s0, s1, s4, s5, s8, s9, s12, s13, s16, s17, s20, s21, s24, and s25 can be performed together in an NXOR operation, and memory controller 206 may use parity bits to determine that s2, s3, s6, s7, s10, s11, s14, s15, s18, s19, s22, s23, s26, and s27 can be performed together in an NXOR operation. When the memory controller 206 executes the sensing operations s0, s1, s4, s5, s8, s9, s12, s13, s16, s17, s20, s21, s24, and s25, the memory controller 206 can store the sensing operation results of the first category (i.e., s0, s1, s4, s5, s8, s9, s12, s13, s16, s17, s20, s21, s24, and s25) into a latch for the state where the parity bit is one. When the memory controller 206 executes sensing operations s2, s3, s6, s7, s10, s11, s14, s15, s18, s19, s22, s23, s26, and s27, the memory controller 206 can store the sensing operation results of the second category (i.e., s2, s3, s6, s7, s10, s11, s14, s15, s18, s19, s22, s23, s26, and s27) into a latch for a state where the parity bit is zero. At the end of the sensing operation, an SB page can include the number of cells in the transition regions of both categories, and the memory controller 206 can count the number of zeros in the SB latch and compare the number of zeros with a threshold to determine whether the BER is low enough to allow fine programming to continue after on-chip decoding using the parity bit, or whether fuzzy data needs to be transmitted for decoding by the controller 108.

[0040] In some implementations, when memory controller 206 determines that fuzzy data needs to be transmitted for decoding in storage device 104, memory controller 206 may send SB pages along with the fuzzy data to storage device 104. The decoder in storage device 104 can use the SB pages as soft information to attach reliability to the fuzzy data and improve its error correction capabilities. For example, information in the SB pages can be used to attach a high or low probability to a fuzzy bit in a given state. A high or low probability can indicate, for example, how close the transition between the fuzzy bit and the state is. The decoder can therefore use the SB reliability information to correct more errors.

[0041] In one implementation, parity circuit 212 may also generate enhanced fuzzy data, which can be used to add more granularity when enabling memory controller 206 to separate states in the distribution. For example, the enhanced fuzzy data may be red / green (RG) bits associated with the fuzzy distribution. During data holding, green bits can be used to determine when the distribution has shifted left, and red bits can be used to determine when the distribution has shifted right. The same RG bits may not be assigned to adjacent states. Parity circuit 212 may also generate other enhanced fuzzy data, and RG bits are provided only as an example. The parity page and RG bits for the first distribution may be stored in SLC memory 204b. Memory controller 206 can use the parity page and RG bits with an encoded recovery table to recover data from the first distribution, such as shown in 302. Figure 5 This is provided as an example. Other examples may differ. Figure 5 The example described.

[0042] Figure 6 An example of a memory die encoded according to a first transition is illustrated according to some specific implementation. The memory die can be encoded such that there may be four transitions from 1 to 0 on the top row, three transitions from 1 to 0 on the next row, four transitions from 1 to 0 on the row after that, and four transitions from 1 to 0 on the bottom row, as shown in 502. Therefore, the first (i.e., 4344) transition can be used to encode the memory die. Other transitions can be used to encode the memory die, and only the 4344 transition is provided as an example.

[0043] Adjacent states can have even or odd parity and are assigned to either even or odd categories. For example, S1 can be assigned to the odd category (shown as O), S2 to the even category (shown as E), S3 to the odd category, S4 to the even category, and so on. Green states can be S0, S1; S4, S5; S8, S9; S12, S13. And red states can be S2, S3; S6, S7; S10, S11; S14, S15. 604 shows an example where the fuzzy programming distribution of state 5 (S5) may have shifted left beyond adjacent states (i.e., beyond S4 into S3). The distribution of S5 is shown as a solid line in 604, and the distribution shift is shown as a dashed line. In 602, the fuzzy data written in S5 is 0100, the parity is odd, and the assigned bits are green.

[0044] During a fuzzy read, the memory controller 206 can calculate the BER and generate SB pages. In some cases, before sending data to the storage device 104 for decoding due to a high BER, the memory controller 206 can use the RG bits allocated to the distribution to determine whether it is offset to the left or right. For example, if during a QLC read, the memory controller 206 retrieves 1101 (i.e., data from S3) due to a left offset, then the memory controller 206 can determine that the RG bits allocated to S5 are green and the parity is odd. The memory controller 206 can determine that the distribution has been offset beyond the adjacent distributions because both S3 and S5 are allocated green bits and odd parity. The memory controller 206 can use an encoded recovery table to recover the data. Figure 6 This is provided as an example. Other examples may differ. Figure 6 The example described.

[0045] Figure 7 An example of an encoding recovery table, according to some specific implementation, applicable to a memory die encoded according to a first conversion, is illustrated. The entries in the encoding recovery table 702 may be based on the manner in which the memory die is encoded. The encoding recovery table 702 may include a green bit table 704 and a red bit table 706. The green bit table 704 may include an event column associated with an event (e.g., the number of states in a distribution), a green column including retrieved bits that can be read from states allocated green bits, a parity column identifying even or odd parity values ​​assigned to states, and a recovery bit column including recovery bits that can be programmed using fine-tuning. Similarly, the red bit table 706 may include an event column associated with an event, a red column including retrieved bits that can be read from states allocated red bits, a parity column identifying even or odd parity values ​​assigned to states, and a recovery bit column including recovery bits that can be programmed using fine-tuning.

[0046] If the event in green bit table 704 or red bit table 706 is zero, no error may have occurred (i.e., the distribution has not shifted). If the event is one, a one-state data hold-off may have occurred (i.e., the distribution may have shifted to an adjacent state); if the event is two, a two-state data hold-off may have occurred (i.e., the distribution may have shifted beyond an adjacent state to the next state); if the event is three, a three-state data hold-off may have occurred (i.e., the distribution may have shifted beyond an adjacent state to the next two states). When charge is added to a nearby memory cell, the threshold voltage of the previously programmed memory cell may increase, causing a change in the threshold voltage distribution, which may be referred to as "programming interference." The events in green bit table 704 or red bit table 706 may also be one-state programming interference (PD1) or two-state programming interference (PD2).

[0047] Use recovery table 702 on the memory die encoded according to the first conversion, such as Figure 6 As shown, if, for example, memory controller 206 retrieves 1101 when reading data in S5 (because the distribution has shifted to S3), then memory controller 206 can determine that the green bit and parity are allocated to both S3 and S5. Memory controller 206 can determine that the distribution of S5 has shifted two states based on, for example, the parity pages and / or RG bits allocated to S3 and S5, i.e., the distribution of S5 has shifted beyond the adjacent distribution, because S3 and S5 may have the same parity and RG bits. As shown in the shaded area, when using green bit table 704, when event 2, the bit retrieved in the green column is 1101, and the parity is odd. Memory controller 206 can recover the bit from the recovered bit column (i.e., 0100) and program 0100 into S5 during a fine programming operation.

[0048] In some cases, memory controller 206 may use the recovery table, parity page, and RG bits to recover the fuzzy programming data instead of transferring the fuzzy programming data to storage device 104 when the BER is high and the fuzzy programming data has been offset. If memory controller 206 cannot recover the fuzzy programming data using the recovery table, parity page, and RG bits and the BER is higher than a predefined threshold, then memory controller 206 may transfer the data to storage device 104 for data decoding. Figure 7 This is provided as an example. Other examples may differ. Figure 7 The example described.

[0049] Figure 8This is an example flowchart based on some specific implementations for generating soft bit information for BER estimation of fuzzy-programmed data. At 810, the memory die can receive data from storage device 104 for storage. At 820, the memory controller 206 can fuzzy program the data in QLC memory 204a, generate parity pages of the data, and classify the states in the memory cells. At 830, the memory controller 206 can perform sensing operations at different voltage levels or at modulation integration times associated with the same control gate voltage near the midpoint between distributions in the categories. At 840, the memory controller 206 can generate SB pages from the sensing operations for each category. At 850, the memory controller 206 can count the number of zeros in the SB pages, and if the number of zeros in the SB pages is below a predefined threshold, the memory controller 206 can estimate the BER of the fuzzy page to be low, and the parity pages can be used to decode the fuzzy page for fine-grained write operations. At 860, if the number of zeros in the SB page is at or above a predefined threshold, then the memory controller 206 can estimate that the BER of the fuzzy page is high and send the fuzzy page to the controller 108 for decoding before fine programming. Figure 8 This is provided as an example. Other examples may differ. Figure 8 The example described.

[0050] Figure 9 This is another example flowchart based on some specific implementations for generating soft bit information for BER estimation of fuzzy-programmed data. At 910, the memory die can receive data from storage device 104 for storage. At 920, the memory controller 206 can fuzzy program the data in QLC memory 204a, generate parity pages of the data, and classify the states in the memory cells. At 930, the memory controller 206 can perform fuzzy page read and sensing operations at different voltage levels or at modulation integration times associated with the same control gate voltage near the midpoint between distributions in one or more categories within a single sensing operation.

[0051] At 940, the memory controller 206 can use parity bits to determine which sensing operations should be performed together in an NXOR operation, and the memory controller 206 can store the results of the sensing operations for each category into latches for cells with the same parity bits. At 950, at the end of the sensing operation, the memory controller 206 can generate an SB page that includes the number of cells in the transition regions for multiple categories.

[0052] At 960, the memory controller 206 can count the number of zeros in the SB page, and if the number of zeros in the SB page is lower than a predefined threshold, the memory controller 206 can estimate the BER of the fuzzy page to be low, and can use a parity page to decode the fuzzy page for fine writing operations. At 960, if the number of zeros in the SB page is at or above the predefined threshold, the memory controller 206 can estimate the BER of the fuzzy page to be high, and send the fuzzy page to the controller 108 for decoding before fine programming. Figure 9 This is provided as an example. Other examples may differ. Figure 9 The example described.

[0053] Figure 10 This is an example flowchart based on some specific implementations of using soft bit information generated from BER estimation for fuzzy-programmed data. At 1010, the memory die can receive data from storage device 104 for storage. At 1020, the memory controller 206 can fuzzy program the data in QLC memory 204a, generate parity pages for the data, and classify the states in the memory cells. At 1030, the memory controller 206 can perform sensing operations at different voltage levels or at modulation integration times associated with the same control gate voltage near the midpoint between distributions in the categories. At 1040, the memory controller 206 can generate SB pages from the sensing operations for each category. At 1050, the memory controller 206 can count the number of zeros in the SB pages, and if the number of zeros in the SB pages is below a predefined threshold, the memory controller 206 can estimate the BER of the fuzzy page to be low, and the parity pages can be used to decode the fuzzy pages for fine-grained write operations. At 1060, if the number of zeros in the SB page is at or above a predefined threshold, the memory controller 206 can estimate that the BER of the fuzzy page is high and send the fuzzy programming data and soft bit page to the controller 108, so that the decoder can use the SB page as soft information to attach reliability to the fuzzy programming data and improve its error correction capability. Figure 10 This is provided as an example. Other examples may differ. Figure 10 The example described.

[0054] Figure 11 This is a diagram illustrating an example environment in which the systems and / or methods described herein are implemented. For example... Figure 11As shown, environment 1100 may include hosts 102a-102n (referred to herein as host 102) and one or more storage devices 104a-104n (referred to herein as storage device 104). Memory device 110 may include memory controller 206 to estimate BER and implement enhanced fuzzy-fine operations. Host 102 and storage device 104 may communicate via fast nonvolatile memory (NVM) via Fast Peripheral Component Interconnect (PCI Express or PCIe), SD, etc.

[0055] The devices in Environment 1100 can be interconnected via wired connections, wireless connections, or a combination of wired and wireless connections. For example, Figure 11 The network may include Internet Small Computer System Interface (iSCSI) based on NVMe over Fabric (NVMe-oF), Fibre Channel (FC), Fibre Channel over Ethernet (FCoE) connections, and any other type of next-generation networking and storage protocol, Local Area Network (LAN), Wide Area Network (WAN), Metropolitan Area Network (MAN), Private Network, Self-organizing Network, Intranet, Internet, Fibre-based Network, Cloud Computing Network, and / or combinations of these or other types of networks.

[0056] Figure 11 The number and arrangement of devices and networks shown are provided as examples. In practice, additional devices and / or networks, fewer devices and / or networks, different devices and / or networks, or networks may exist. Figure 11 The devices and / or networks shown are arranged differently. Furthermore, Figure 11 The two or more devices shown can be implemented within a single device, or Figure 11 The single device shown can be implemented as multiple distributed devices. Additionally or alternatively, a group of devices in environment 1100 (e.g., one or more devices) can perform one or more functions described as being performed by another group of devices in environment 1100.

[0057] The foregoing disclosure provides illustrative and descriptive embodiments, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed herein. Those skilled in the art will understand that various modifications and alterations may be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be covered within the scope of this teaching.

[0058] As used herein, the term "component" is intended to be understood broadly as hardware, firmware, and / or combinations of hardware and software. It will be apparent that the systems and / or methods described herein can be implemented using various forms of hardware, firmware, and / or combinations of hardware and software.

[0059] Although specific combinations of features are set forth in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of each embodiment. In fact, many of these features can be combined in ways not set forth in the claims and / or not disclosed in the specification. Although each dependent claim listed below may depend directly on only one claim, the disclosure of each embodiment includes a combination of each dependent claim with all other claims in the claim set.

[0060] Unless explicitly stated otherwise, no element, action, or instruction used herein should be considered critical or necessary. Furthermore, as used herein, the articles “a” and “one” are intended to include one or more items and are used interchangeably with “one or more.” Additionally, as used herein, the term “group” is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.) and is used interchangeably with “one or more.” The term “only one” or similar wording is used to refer to the expectation that only one item is expected. Furthermore, unless explicitly stated otherwise, the phrase “based on” is intended to mean “at least partially based on.”

[0061] Furthermore, in this document, relational terms such as first and second, top and bottom may be used only to distinguish one entity or action from another entity or action, and do not necessarily require or imply any actual such relationship or order between these entities or actions. The terms “comprises,” “comprising,” “has,” “having,” “includes,” “including,” “contains,” “containing,” or any other variations thereof are intended to cover non-exclusive inclusion; therefore, a process, method, article, or apparatus that includes, has, contains, or contains a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to the process, method, article, or apparatus. An element introduced by “comprises…a,” “has…a,” “includes…a,” or “contains…a” does not, without further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes, has, contains, or contains that element. The terms “substantially,” “essentially,” “approximately,” “about,” or any other version thereof are defined as being close to what is understood by one of ordinary skill in the art, and in one non-limiting embodiment, the term is defined as within 10%, in another within 5%, in yet another within 1%, and in yet another within 0.5%. The term “coupled” as used herein is defined as a connection, although not necessarily direct or mechanical. A device or structure “configured” in some way, at least in that way, but may also be configured in ways not listed.

Claims

1. A memory die, the memory die being used to estimate the bit error rate (BER) of an encoded fuzzy programming operation to determine whether to decode fuzzy programming data on the memory die for a fine programming operation, the memory die comprising: Blocks that store data in various formats; and A memory controller is configured to receive data from a storage device, generate at least one parity page based on the data, perform fuzzy programming to write the data into memory cells in a block, classify states in the memory cells based on the values ​​of the parity pages associated with states, perform soft bit sensing, estimate the BER of the memory cells based on the soft bit sensing, perform on-chip decoding of the fuzzy programmed data using the at least one parity page based on the BER, and write the decoded data into the block using fine programming.

2. The memory die of claim 1, wherein the memory controller uses a parity page to indicate whether the fuzzy programming state is even or odd, and assigns fuzzy programming states with the same parity page value to a certain category.

3. The memory die of claim 1, wherein the memory controller uses two parity pages to divide the fuzzy programming states into four categories, and assigns fuzzy programming states with the same parity page value to a certain category.

4. The memory die of claim 1, wherein the memory controller uses the value of the at least one parity page to distinguish states in the category and enables greater state separation between states in the category.

5. The memory die of claim 1, wherein the soft bit sensing operation includes reading the midpoint between states in a category and generating a soft bit page for the category.

6. The memory die of claim 5, wherein the memory controller estimates the BER by counting the number of zeros in the soft bit pages, wherein if the number is below a threshold, the memory controller performs on-chip decoding on the fuzzy programmed data.

7. The memory die of claim 5, wherein the memory controller estimates the BER by counting the number of zeros in the soft bit pages, wherein if the number is higher than a threshold, the memory controller sends the fuzzy programming data to the storage device for decoding.

8. The memory die of claim 1, wherein the soft bit sensing operation comprises: The sensing operation is performed near the midpoint between different voltage level states; Perform an XOR NOT operation on the result of the sensing operation to generate a soft bit page; And the result of the sensing operation is stored on a latch.

9. The memory die according to claim 1, wherein the soft bit sensing operation includes: Sensing operations are performed near the midpoint between states using a single control gate voltage and modulation integration time. Perform an XOR NOT operation on the result of the sensing operation to generate a soft bit page; And the result of the sensing operation is stored on a latch.

10. The memory die of claim 1, wherein the memory controller performs fuzzy page read and soft bit sensing in a single operation.

11. The memory die of claim 1, wherein the memory controller estimates the BER of multiple categories within a single sensing operation, uses the at least one parity bit to determine the sensing operation to be performed (XOR NOT operation), stores the soft-bit sensing operation result associated with a category into a latch for states having the same parity bit value, and generates a soft-bit page comprising cells in a transition region of the multiple categories.

12. A method for estimating the bit error rate (BER) of an encoded fuzzy programming operation in a memory die to determine whether to decode fuzzy programming data on the memory die for a fine programming operation, the memory die including a controller for performing the method, the method comprising: Receive data from storage devices; Generate at least one parity check page based on the data; Perform fuzzy programming to write the data into the memory cells of the block; The states in the memory cells are categorized based on the values ​​of the parity pages associated with the states; Perform soft-bit sensing operation; The BER of the memory cell is estimated based on the soft bit sensing operation; Based on the BER, on-chip decoding of the fuzzy programming data is performed using the at least one parity check page; as well as The decoded data is written into the block using sophisticated programming operations.

13. The method of claim 12, further comprising: Use a parity page to indicate whether the fuzzy programming state is even or odd, and assign fuzzy programming states with the same parity page value to a certain category; as well as The fuzzy programming states are divided into four categories using two parity pages, and fuzzy programming states with the same parity page value are assigned to one of the four categories.

14. The method of claim 12, wherein performing the soft bit sensing operation includes reading the midpoint between states in a category and generating a soft bit page for the category.

15. The method of claim 14, wherein estimating the BER comprises counting the number of zeros in the soft bit page, wherein if the number is below a threshold, the on-chip decoding is performed on the fuzzy-programmed data, and if the number is above the threshold, the fuzzy-programmed data is sent to the storage device for decoding.

16. The method of claim 12, wherein performing the soft-bit sensing operation comprises one of the following: A sensing operation is performed near the midpoint between states of different voltage levels; the result of the sensing operation is then subjected to an XOR NOT operation to generate a soft bit page; And the result of the sensing operation is stored on a latch; as well as Sensing operations are performed near the midpoint between states using a single control gate voltage and modulation integration time. Perform an XOR NOT operation on the result of the sensing operation to generate the soft bit page; And the result of the sensing operation is stored on the latch.

17. The method of claim 12, further comprising performing fuzzy page reading and soft bit sensing in a single operation.

18. The method of claim 12, further comprising: Estimate the BER for multiple categories within a single sensing operation; The at least one parity bit is used to determine the sensing operation to be performed (XOR NOT operation); The soft bit sensing operation result associated with a category is stored in a latch for states with the same parity bit value; as well as Generate a soft bit page that includes the cells in the conversion region of the multiple categories.

19. A method for estimating the bit error rate (BER) of an encoded fuzzy programming operation in a memory die to determine whether to decode fuzzy programming data on the memory die for a fine programming operation, the memory die including a controller for performing the method, the method comprising: Receive data from storage devices; Generate at least one parity check page based on the data; Perform fuzzy programming to write the data into the memory cells of the block; The states in the memory cells are categorized based on the values ​​of the parity pages associated with the states; Perform soft-bit sensing operations and generate soft-bit pages; The BER of the memory cell is estimated based on the soft bit page; Based on the BER, perform one of the following operations: perform on-chip decoding of the fuzzy programming data using the at least one parity check page; And determine that the fuzzy programming data is to be transmitted to the storage device for decoding; as well as When the fuzzy programming data is to be transmitted to the storage device, the fuzzy programming data and the soft bit page are sent to the storage device; Receive decoded fuzzy programming data from the storage device; And by using fine-grained programming operations, the decoded fuzzy programming data is written into the block.

20. The method of claim 14, wherein when the soft bit page is sent to the storage device along with the fuzzy programming data, the soft bit page appends reliability information to the fuzzy programming data to improve error correction on the storage device.

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