A circuit for dynamic compensation of CIS horizontal stripes

Abstract

The application discloses a circuit for dynamically compensating CIS horizontal stripes, and relates to the technical field of CMOS image sensors, which provides a bias current through a bias current module and adjusts a transmission gain through an adjustable capacitor module, compares and outputs pixel voltage signals with different gains through a first amplification structure in a minimum unit sub-module on the basis of the bias current and the transmission gain, amplifies and inversely processes the signals output by the first amplification structure through a second amplification structure, and outputs pixel voltage signals after dynamic compensation of CIS horizontal stripes, so that the circuit realizes front-end compensation of analog signals for public wiring interference, realizes dynamic suppression of horizontal stripes, avoids loss of image details, has a compact structure and is compatible with an existing CIS process, and effectively improves imaging uniformity and image quality under complex lighting conditions.

Description

Technical Field

[0001] This application relates to the field of CMOS image sensor technology, specifically to a circuit for dynamically compensating for horizontal stripes in CIS. Background Technology

[0002] In existing technologies, most solutions for horizontal stripe interference caused by differences in brightness along the horizontal direction of common wiring in CMOS (Complementary Metal-Oxide-Semiconductor) image sensors (CIS) still rely on back-end image processing algorithms for filtering or correction. However, these post-processing methods not only suffer from significant lag but also consume substantial processor resources and may lead to loss of image details, affecting image fidelity. Some hardware solutions attempt to suppress interference during the chip design phase by optimizing layout or power supply design; however, these methods are one-time preset adjustments and cannot dynamically respond to changes in actual lighting after chip production. Therefore, their applicability is limited and they cannot meet the imaging needs in complex lighting environments. Summary of the Invention

[0003] The purpose of this application is to provide a circuit for dynamically compensating for horizontal stripes in CIS, which solves the problem that existing technologies cannot dynamically respond to changes in actual illumination after chip production, thus limiting their applicability and making it difficult to meet imaging needs in complex lighting environments.

[0004] This application is achieved through the following technical solution:

[0005] A circuit for dynamically compensating for horizontal stripes in CIS includes: a bias current module, a core comparator module, and an adjustable capacitor module.

[0006] The core comparison module includes multiple comparator units, each comparator unit includes multiple minimum unit sub-modules, the input of each minimum unit sub-module is connected to the pixel voltage signal, and the minimum unit sub-module corresponds one-to-one with the pixel voltage signal corresponding to the pixel; the adjustable capacitor module configures an adjustable capacitor for each minimum unit sub-module to change the transmission gain of the minimum unit sub-module; the bias current module provides bias current to the minimum unit sub-module through a multi-current mirror module structure;

[0007] Based on the transmission gain controlled by the adjustable capacitor module and the bias current provided by the bias current module, the smallest unit submodule compares and outputs pixel voltage signals with different gains through a first-stage amplification structure, and amplifies and inverts the signal output by the first-stage amplification structure through a second-stage amplification structure to output the pixel voltage signal after dynamically compensating for CIS horizontal stripes.

[0008] In one possible implementation, the first-stage amplification structure includes a first comparison branch and a second comparison branch, wherein the first comparison branch and the second comparison branch are not simultaneously turned on; the first comparison branch is used to receive a low-gain pixel voltage signal and compare the low-gain pixel voltage signal with a reference voltage to output a first comparison result; the second comparison branch is used to receive a high-gain pixel voltage signal and compare the high-gain pixel voltage signal with a reference voltage to output a second comparison result.

[0009] In one possible implementation, both the first comparison branch and the second comparison branch are biased by a bias current module, and the capacitance between the bias voltage and the VSS terminal is adjusted by an adjustable capacitor module.

[0010] In one possible implementation, the minimum unit submodule further includes a first automatic zero-adjustment switch module and a second automatic zero-adjustment switch module;

[0011] The first automatic zero-adjustment switch module is disposed on the MOS transistor that inputs the low-gain pixel voltage signal and the MOS transistor that inputs the reference voltage in the first comparison branch, and the first automatic zero-adjustment switch module is used to zero the first comparison branch to eliminate the offset voltage and noise in the first comparison branch.

[0012] The second automatic zero-adjustment switch module is disposed on the MOS transistor that inputs the high-gain pixel voltage signal and the MOS transistor that inputs the reference voltage in the second comparison branch, and the second automatic zero-adjustment switch module is used to zero the second comparison branch to eliminate the offset voltage and noise in the second comparison branch.

[0013] In one possible implementation, the secondary amplification structure includes a third comparison branch and an inverting structure; the third comparison branch receives the comparison result output by the primary amplification structure and performs a comparison on the comparison result output by the primary amplification structure; the inverting structure is used to invert the comparison result output by the third comparison branch and output the pixel voltage signal after dynamically compensating for CIS horizontal stripes.

[0014] In one possible implementation, the secondary amplification structure further includes a third automatic zero-adjustment switch module; the third automatic zero-adjustment switch module is used to zero-adjust the MOS transistor in the third comparison branch to eliminate offset voltage and noise in the third comparison branch.

[0015] In one possible implementation, the bias current module includes a first current mirror structure, a bias current ratio adjustment module, and a second current mirror structure.

[0016] The first current mirror structure is used to provide a reference bias current, and the first current mirror structure is connected to the bias current ratio adjustment module; the bias current ratio adjustment module is used to amplify the reference bias current and input it into the second current mirror structure; the second current mirror structure is used to copy and output the current output by the bias current ratio adjustment module.

[0017] In one possible implementation, the bias current proportional adjustment module includes a current mirror composed of two MOS transistors, and the size ratio between the two MOS transistors is set to 1:x. The bias current proportional adjustment module amplifies the reference bias current output by the first current mirror structure by a factor of x and inputs it into the second current mirror structure; where x is a number greater than 1.

[0018] In one possible implementation, the bias current module further includes a replication ratio adjustment structure; the replication ratio adjustment structure includes MOS transistors connected in series with the MOS transistors in the second current mirror structure, and the source and drain of the MOS transistors in the replication ratio adjustment structure are respectively connected to the drain and gate of the corresponding MOS transistors in the second current mirror structure, and the source of the MOS transistors in the replication ratio adjustment structure is independently controlled to adjust the replication ratio of the second current mirror structure.

[0019] In one possible implementation, the adjustable capacitor module includes multiple capacitors, the same number as the minimum unit sub-module, which are controlled by a switching transistor to be switched on and off. Each capacitor corresponds one-to-one with the minimum unit sub-module and is connected to the position of the bias current input minimum unit sub-module. Each capacitor is independently controlled.

[0020] Compared with the prior art, this application has the following advantages and beneficial effects:

[0021] This application provides a circuit for dynamically compensating for horizontal stripes in CIS (Computer Image Sensor). It provides a bias current through a bias current module and adjusts the transmission gain through an adjustable capacitor module. Based on the bias current and transmission gain, a first-stage amplification structure in the smallest unit submodule compares and outputs pixel voltage signals with different gains. A second-stage amplification structure amplifies and inverts the signal output from the first-stage amplification structure, outputting the pixel voltage signal after dynamically compensating for CIS horizontal stripes. This achieves compensation for common wiring interference from the analog signal front end, dynamically suppresses horizontal stripes, avoids loss of image details, has a compact structure, is compatible with existing CIS processes, and effectively improves imaging uniformity and image quality under complex lighting conditions. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the exemplary embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0023] Figure 1 This is a schematic diagram of a pixel-based readout structure provided in an embodiment of this application;

[0024] Figure 2 A schematic diagram of a conventional comparator structure provided in the embodiments of this application;

[0025] Figure 3 A circuit diagram for dynamically compensating for horizontal stripes in CIS provided in an embodiment of this application;

[0026] Figure 4 A schematic diagram of the core comparison module provided in the embodiments of this application;

[0027] Figure 5 Schematic diagrams of the first-stage and second-stage amplification structures provided in the embodiments of this application;

[0028] Figure 6 A schematic diagram of the bias current module provided in an embodiment of this application;

[0029] Figure 7 This is a timing diagram of a single frame provided in an embodiment of this application.

[0030] Figure 8 The dual-conversion gain mode control timing provided in the embodiments of this application;

[0031] Figure 9 Control timing diagram of a general-mode comparator provided in the embodiments of this application;

[0032] Figure 10 A simplified structural example diagram provided for embodiments of this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this application are only for explaining this application and are not intended to limit this application.

[0034] like Figure 1As shown, to facilitate understanding of the technical solutions described in the embodiments of this application by those skilled in the art, the application scenario of this application is first introduced. This application scenario mainly involves pixel readout through a pixel-based readout structure. This pixel-based readout structure consists of a pixel array, a pixel driving module, a load current source module, a reference ramp generation module, a transmission gain adjustable comparator, a counter module, and a data transmission module. The pixel driving module controls the operation of the pixel array, scans the pixel signal, and generates a signal voltage. The pixel array generates different voltage signals according to different illuminations through photoelectric conversion. The load current source module acts as the current source load of the pixel source follower amplifier, thereby outputting a stable pixel voltage signal (which can be denoted as Vpix). The reference ramp generation module generates a ramp reference voltage (which can be denoted as RAMP) for comparison with the pixel signal, serving as the input to the core comparison module. The bias current module provides different bias currents to the core comparator module to set its static operating point and ensure stable performance. The adjustable capacitor module changes the transmission gain of the core comparator module by flexibly adjusting the capacitor value, thereby optimizing its anti-interference capability and response characteristics. The core comparator module is responsible for performing the final signal comparison by comparing the pixel signal voltage with a reference voltage and generating different output signals (denoted as Vcomp) based on the comparison result. The entire module can automatically and collaboratively adjust the bias current and transmission gain according to the system gain requirements, thereby achieving a higher signal-to-noise ratio and overall performance optimization over a wider input signal range. The counter module processes the output signal of the core comparator module, counts signals under different lighting conditions, and obtains the light intensity from the counting results. The digital signal processing module performs noise reduction, white balance, and color correction on the digital signal to improve image quality.

[0035] like Figure 2 As shown, in a traditional comparator structure, the tail current I_Tail provided by the bias current module is fixed, and the parasitic capacitance in the circuit is also fixed. During the chip design phase, a current value that compromises power consumption, speed, and noise is determined through simulation. Simultaneously, the size of the parasitic capacitance between the bias current and the tail current (which can be denoted as I_Tail) is adjusted by optimizing the layout, thereby reducing the amount of crosstalk interference on the bias current. However, once this pre-defined adjustment scheme is completed in chip manufacturing, the current value and parasitic capacitance in the circuit cannot be changed. If horizontal stripes appear in the image, optimization can only be achieved through algorithms, which will result in loss of image details and affect the realism of the image.

[0036] Therefore, this application provides a circuit for dynamically compensating for horizontal stripes in a CIS, which can dynamically compensate for common wiring interference caused by horizontal brightness differences in the CIS under different lighting conditions, effectively suppress horizontal stripes, and thus significantly improve the imaging effect.

[0037] like Figure 3 As shown, this application embodiment provides a circuit for dynamically compensating for CIS horizontal stripes, including: a bias current module, a core comparison module, and an adjustable capacitor module;

[0038] The core comparison module includes multiple comparator units, each comparator unit includes multiple minimum unit sub-modules, the input of each minimum unit sub-module is connected to the pixel voltage signal, and the minimum unit sub-module corresponds one-to-one with the pixel voltage signal corresponding to the pixel; the adjustable capacitor module configures an adjustable capacitor for each minimum unit sub-module to change the transmission gain of the minimum unit sub-module; the bias current module provides bias current to the minimum unit sub-module through a multi-current mirror module structure;

[0039] Based on the transmission gain controlled by the adjustable capacitor module and the bias current provided by the bias current module, the smallest unit submodule compares and outputs pixel voltage signals with different gains through a first-stage amplification structure, and amplifies and inverts the signal output by the first-stage amplification structure through a second-stage amplification structure to output the pixel voltage signal after dynamically compensating for CIS horizontal stripes.

[0040] like Figure 4 As shown, the core comparison module can be composed of n comparator units, and each comparator unit is composed of m smallest unit sub-modules (where n is greater than m, and both m and n are positive integers). Therefore, the core comparison module consists of n*m smallest unit sub-modules. In this embodiment, each comparator unit is preferably composed of 4 smallest unit sub-modules. However, in actual projects, each comparator unit can be composed of other numbers of smallest unit sub-modules, not just 4.

[0041] In one possible implementation, the first-stage amplification structure includes a first comparison branch and a second comparison branch, wherein the first comparison branch and the second comparison branch are not simultaneously turned on; the first comparison branch is used to receive a low-gain pixel voltage signal and compare the low-gain pixel voltage signal with a reference voltage to output a first comparison result; the second comparison branch is used to receive a high-gain pixel voltage signal and compare the high-gain pixel voltage signal with a reference voltage to output a second comparison result.

[0042] like Figure 5 As shown, the comparator core module consists of multiple repeating minimum unit sub-modules. To simultaneously reflect the results of different gains within one cycle, the minimum unit sub-modules employ a dual-input structure. Figure 5In this diagram, devices with "MN" in their names are N-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), devices with "MP" are P-type MOSFETs, devices with "SEL" are N-type MOSFETs, devices with "Cc" are parasitic capacitors, and devices with "Cgnd" are adjustable capacitors. "SELA" is the branch control signal for the A-side (i.e., the first comparator branch), and "SELB" is the branch control signal for the B-side (i.e., the second comparator branch). "RAMP" is the ramp reference voltage, signals with "Vpix" are pixel voltage signals, signals with "RST" are zero-adjustment signals, and signals with "SW" are switching signals. "MP00" to "MP30" and "MP01" to "MP31" serve as loads for the differential inputs. For simplicity, these symbols will be used throughout the description, and further elaboration will not be provided.

[0043] In one possible implementation, both the first comparison branch and the second comparison branch are provided with bias voltage by a bias current module, and the capacitance between the bias voltage and the VSS terminal is adjusted by an adjustable capacitor module to adjust the transmission gain of the interference voltage coupled from the tail current node to the bias voltage node.

[0044] In one possible implementation, the minimum unit submodule further includes a first automatic zero-adjustment switch module and a second automatic zero-adjustment switch module; see reference to Figure 5 The first automatic zero-adjustment switch module on side A may include MP_RST_A_00 to MP_RST_A_30 and MP_RST_A_01 to MP_RST_A_31, and the second automatic zero-adjustment switch on side B may include MP_RST_B_00 to MP_RST_B_30 and MP_RST_B_01 to MP_RST_B_31; this is an overall description, and the correspondence between each MOS transistor used for zeroing and the smallest unit submodule is as follows. Figure 5 As shown, further details will not be elaborated here.

[0045] The first automatic zero-adjustment switch module is disposed on the MOS transistor that inputs the low-gain pixel voltage signal and the MOS transistor that inputs the reference voltage in the first comparison branch, and the first automatic zero-adjustment switch module is used to zero the first comparison branch to eliminate the offset voltage and noise in the first comparison branch.

[0046] The second automatic zero-adjustment switch module is disposed on the MOS transistor that inputs the high-gain pixel voltage signal and the MOS transistor that inputs the reference voltage in the second comparison branch, and the second automatic zero-adjustment switch module is used to zero the second comparison branch to eliminate the offset voltage and noise in the second comparison branch.

[0047] In one possible implementation, the secondary amplification structure includes a third comparison branch and an inverting structure; the third comparison branch receives the comparison result output by the primary amplification structure and performs a comparison on the comparison result output by the primary amplification structure; the inverting structure is used to invert the comparison result output by the third comparison branch and output the pixel voltage signal after dynamically compensating for CIS horizontal stripes.

[0048] like Figure 5 As shown, the third comparison branch can include MP02 to MP32, MN00 to MN30, and MB_RST_0 to MB_RST_3. MP02 to MP32 receive the comparison results output from the first-stage amplification structure, and the devices with "C_RST" in their names are the holding capacitors of the second-stage amplification structure. The inverting structure can include MP03 to MP33 and MN01 to MN03. The comparison results output from the third comparison branch (i.e., the signals output from the drains of MP02 to MP32) are processed by this inverting structure to generate the output signal, i.e., the signal with "Vcomp" in its name. This is an overall description; the specific correspondence between each MOS transistor and the second-stage amplification structure of each smallest unit submodule is as follows... Figure 5 As shown, further details will not be elaborated here.

[0049] In the first-stage amplification structure, a high-gain pixel signal is input on side B, and a low-gain pixel signal is input on side A. Pixel signals with different gains are processed separately. This first-stage amplification structure is controlled by branch control signals (SELA and SELB) to select the input branch of the first-stage amplification structure. Different branches are selected for different gains within one operating cycle, ultimately achieving the output of two results with different gains within one operating cycle.

[0050] In one possible implementation, the secondary amplification structure further includes a third automatic zero-adjustment switch module; the third automatic zero-adjustment switch module is used to zero-adjust the MOS transistor in the third comparator branch, eliminating offset voltage and noise in the third comparator branch. See also... Figure 5 MN_RST_0 to MN_RST_3 constitute the third automatic zeroing switch module corresponding to each smallest unit submodule. This is an overall description; the specific correspondence is as follows: Figure 5 As shown, further details will not be elaborated here.

[0051] In one possible implementation, the adjustable capacitor module includes multiple capacitors, the same number as the minimum unit sub-module, which are controlled by a switching transistor to be switched on and off. Each capacitor corresponds one-to-one with the minimum unit sub-module and is connected to the position of the bias current input minimum unit sub-module. Each capacitor is independently controlled.

[0052] like Figure 5As shown, the adjustable capacitor module consists of a set of switch-controlled capacitor arrays, including multiple parallel adjustable capacitors (i.e., Cgnd0, Cgnd1, Cgnd2, and Cgnd3), with each capacitor unit connected in series with a switch (i.e., SW0, SW1, SW2, and SW3). The switch control signal (i.e., SEL<3:0>, where SEL<3:0> includes SEL...) <0> To SEL <3> This is used to control the on / off state of each switch. Each adjustable capacitor can be connected to or disconnected from the circuit, thereby changing the total capacitance value connected to a comparator unit. Assuming the capacitance values ​​of Cgnd0, Cgnd1, Cgnd2, and Cgnd3 are cgnd0, cgnd1, cgnd2, and cgnd3 respectively, and the binary numbers corresponding to the input values ​​of SEL<3:0> are a, b, c, and d (a, b, c, and d are either 0 or 1), the total capacitance value connected to the comparator unit is: At this point, the total capacitance of the core comparator module is C = n * cgnd. Since the core comparator module consists of many comparator units, the total capacitance connected to the circuit is very large. To shorten the charging time of the capacitor, this application also provides a bias current module to improve the current drive capability.

[0053] In one possible implementation, the bias current module includes a first current mirror structure, a bias current ratio adjustment module, and a second current mirror structure.

[0054] The first current mirror structure is used to provide a reference bias current, and the first current mirror structure is connected to the bias current ratio adjustment module; the bias current ratio adjustment module is used to amplify the reference bias current and input it into the second current mirror structure; the second current mirror structure is used to copy and output the current output by the bias current ratio adjustment module.

[0055] In one possible implementation, the bias current proportional adjustment module includes a current mirror composed of two MOS transistors, and the size ratio between the two MOS transistors is set to 1:x. The bias current proportional adjustment module amplifies the reference bias current output by the first current mirror structure by a factor of x and inputs it into the second current mirror structure; where x is a number greater than 1.

[0056] In one possible implementation, the bias current module further includes a replication ratio adjustment structure; the replication ratio adjustment structure includes MOS transistors connected in series with the MOS transistors in the second current mirror structure, and the source and drain of the MOS transistors in the replication ratio adjustment structure are respectively connected to the drain and gate of the corresponding MOS transistors in the second current mirror structure, and the source of the MOS transistors in the replication ratio adjustment structure is independently controlled to adjust the replication ratio of the second current mirror structure.

[0057] like Figure 6 As shown, in the actual circuit, the first current mirror structure may include MN2 and MN3, and the bias current ratio adjustment module may include MP1 and MP2. The size ratio of MP1 to MP2 can be set to 1:x, thereby adjusting the bias ratio of the first current mirror structure to the second current mirror structure to 1:x, providing a greater current driving capability. The second current mirror structure may include MN4, MN5, and MN6, and the replication ratio adjustment structure may include MN7, MN8, and MN9. By controlling the on / off state of MN7, MN8, and MN9 in combination, the replication ratio of the current mirror can be changed, thereby precisely adjusting the magnitude of the tail current I_Tail. Figure 6 MN10 and MN11 in the circuit constitute a sample-and-hold circuit, which is controlled by SW7 and SW8 respectively, and SW7 and SW8 are inverse signals to each other.

[0058] In this bias current module, during normal operation, MN1, MP3, MP4 and MN7 are in the default conducting state. The bias current module provides bias current (denoted as I_Tail) to the tail current tube (denoted as MN_Tail) of the smallest unit submodule. At the same time, the magnitude of the comparator tail current can be adjusted by changing the replication ratio of the second current mirror structure by combining and adjusting the on and off states of MN7, MN8 and MN9.

[0059] During the imaging process of a CIS image sensor, a complete frame mainly goes through the normal operation period and the Vblank period (in an image sensor, the time from reading the last row of pixels to starting to read the first row of pixels of the next frame is the Vblank period (vertical blanking period)). The timing diagram of a frame is as follows: Figure 7 As shown.

[0060] In a CIS image sensor, the frame synchronization signal (XVS) and the line synchronization signal (XHS) are two key synchronization signals that control the timing of image frames and lines, respectively. At time T0, the frame synchronization signal is triggered, marking the start of a new frame transmission. At this time, the blanking signal (Vblank) switches from High to Low, and the system enters normal operation. During normal operation, SHEN (sample and hold enable signal) is High, the circuit is in sample and hold state, and a series of line synchronization signals are active. Each active XVS indicates that new image data is about to arrive. Between each active XHS trigger (e.g., between T1 and T2), a complete operation cycle is represented, during which one line of pixels is read out. After reading the last line of pixels, i.e., at time T3, Vblank switches from Low to High, entering the Vblank period. Figure 7In this diagram, T0 represents the beginning of a frame, and T1~T2 are illustrative, representing the time required to capture one action cycle (one AD cycle, or one line of data) within a frame. T1 is the start of a cycle, and T2 is the end of a cycle. T3 is the start of the blanking signal, and T4 is the end of the blanking signal. SELEN is the variable capacitor selection enable signal. Its function is to control whether all the capacitors in the variable capacitor module are connected to the circuit. When SELEN=Low, the internal selection signal SEL<3:0> of the variable capacitor follows the external register SELVbias<3:0>, i.e., SEL<3:0>=SELVbias<3:0>. When SELEN=High, the selection signal is determined by… Figure 8 The described action is as follows: When SELEN=High, if PC_SELVbias=High and SEL<3:0>=15d, all capacitors of the variable capacitor module are connected to the circuit; if PC_SELVbias=Low, SHEN=Low, and SEL<3:0>=15d, all capacitors of the variable capacitor module are connected to the circuit; if PC_SELVbias=Low and SHEN=High, SEL<3:0> follows the action of SELVbias, that is, SEL<3:0>= SELVbias<3:0>.

[0061] During Vblank, all adjustable capacitors in the comparator unit are connected to the circuit, and the signal SHEN=Low. At this time, the sample-and-hold circuit in the circuit is in a constant sampling state, and the bias current module continuously charges the adjustable capacitors until they are fully charged. During this period, the image sensor can perform operations such as resetting and preparing for the next frame exposure.

[0062] There are two operating modes during normal operation: dual-conversion-gain mode and normal mode. This application uses the period T1~T2 as an example for illustration. Depending on the application scenario of the image sensor, if the operating mode selected during normal operation is dual-conversion-gain mode, its control timing is as follows: Figure 8 As shown.

[0063] ① Description of Rs phase (LCG) operation; where Rs phase (Reset Sampling Phase) is the reset signal sampling phase, and LCG (low conversion gain) is the low conversion gain.

[0064] With SELA=High and SELB=Low selected, SELA_00 / SELA_01 turned on and SELB_00 / SELB_01 turned off. At this time, the input branch on side A of the smallest unit submodule is connected, and the input branch on side B is blocked.

[0065] During the period from t0 to t1, SHEN=High, SH=High, SW7=High, and SW8=Low. At this time, MN10 of the sample-and-hold circuit in the bias current module is turned on, and MN11 is turned off, so the bias current module is in the sampling state. During the period from t1 to t4, SHEN=High, SH=Low, SW7=Low, and SW8=High. At this time, MN10 of the sample-and-hold circuit in the bias current module is turned off, and MN11 is turned on, so the bias current module is in the holding state. In the comparator unit, during the period t0~t2, SELEN=High, PC_SELVbias=High. At this time, regardless of the input value of SELVbias<3:0>, the output SEL<3:0>=15d, which means that the switches (i.e., SW0, SW1, SW2, and SW3) of the adjustable capacitors (i.e., Cgnd0, Cgnd1, Cgnd2, and Cgnd3) are all turned on, and all capacitors are connected to the comparator unit circuit. During the period t2~t4, SELEN=High, PC_SELVbias=Low. At this time, SEL<3:0> follows the input signal SELVbias<3:0>, that is, the output setting of SEL<3:0> = the input setting of SELVbias<3:0>. If SELVbias<3:0>=10d, then the output SEL<3:0>=10d, meaning SW1 and SW3 of the adjustable capacitor module are turned on, SW0 and SW2 are turned off, and Cgnd1 and Cgnd3 are connected to the comparator unit. Here, SH is the sample and hold signal; SH=High, sampling action; SH=Low, hold action; SELVbias<3:0> is the register signal for selecting the variable capacitor, PC_SELVbias is the control pulse signal for selecting the variable capacitor at the beginning stage, and 15d represents the decimal number 15.

[0066] exist Figure 8 In the diagram, t0-t8 represent the action switching time points. t0 is the beginning of a cycle; t1 is the SH switching time (High→Low); t2 is the PC_SELVbias switching time (High→Low); t3 is the RST1_A switching time (Low→High); t4 is the Rs phase switching time between LCG and HCG; t5 is the RST1_B switching time (Low→High); t6 is the switch from the Rs phase of HCG to the Ss phase of HCG; t7 is the switch from the Ss phase of HCG to the Ss phase of LCG; and t8 is the end of the cycle.

[0067] During the Rs phase (LCG), the falling time t1 of SH must not be later than the falling time t2 of PC_SELVbias, meaning the switching of the adjustable capacitor module should be completed during the hold phase. At time t4, SELA switches from High to Low, and SELB switches from Low to High, initiating the system gain switching and entering the Rs phase of HCG.

[0068] During the Rs phase (LCG), from time t0 to t3, RST1_A = Low, RST2 = High, and RST1_B = High. In this phase, automatic zeroing (RST) is performed on the A-side input of the comparator unit and the two-stage amplification structure. Simultaneously, the rise time t3 of RST1_A must be later than the fall time t2 of the input signal PC_SELVbias.

[0069] ② Description of the Rs phase (HCG) and Ss phase (HCG); where Ss phase (Signal Sampling Phase) is the image signal sampling phase, and HCG (high conversion gain) is the high conversion gain.

[0070] With SELB=High and SELA=Low selected, SELB_00 / SELB_01 are turned on and SELA_00 / SELA_01 are turned off. At this time, the B-side input branch of the comparator unit is connected, and the A-side input branch is shielded.

[0071] During the period from t4 to t6, it is the Rs phase of HCG operation; during the period from t6 to t7, it is the Ss phase of HCG operation. During the period from t4 to t5, RST1_A=High, RST1_B=Low, and during this phase, the input on the B side of the comparator unit is automatically zeroed by RST. During the period from t4 to t6 to t7, SELEN=High, PC_SELVbias=Low, and at this time, the output setting of SEL<3:0> is equal to the input setting of SELVbias<3:0>. If the input signal SELVbias<3:0>=15d, then the output of SEL<3:0>=15d, that is, all switches (i.e., SW0, SW1, SW2, and SW3) are turned on, and all adjustable capacitors are connected to the comparator unit circuit.

[0072] ③ Description of actions in the Ss phase (LCG);

[0073] At time t7, SELA switches from Low to High, and SELB switches from High to Low. The system gain begins to switch, entering the Ss stage of LCG. At this time, the comparator unit switches to the A-side input.

[0074] During the period from t7 to t8, except for the SH signal, PC_SELVbias signal, RST1_A and RST2 signal, the other control signals are the same as those in the Rs stage (LCG).

[0075] The dual-input circuit structure and control method described above still apply to the normal mode. In normal mode, the comparator's signal control timing is as follows: Figure 9 As shown.

[0076] During the normal operating cycle, the input selection switch signals SELA=High and SELB=Low. In the dual-input circuit, only the A-side input is connected, while the B-side input branch is shielded. Between t0 and t3, RST1_A=Low, RST1_B=High, and RST2=High. During this period, RST1_A and RST2 operate, performing automatic zero-adjustment (RST) on the A-side input of the comparator unit and the second-stage amplification structure, respectively.

[0077] During the period from t0 to t1, SHEN=High, SH=High, SW7=High, SW8=Low. At this time, MN10 of the sample-and-hold circuit in the bias current module is turned on, MN11 is turned off, and the bias current module is in the sampling state. During the period from t1 to t5, SHEN=High, SH=Low, SW7=Low, SW8=High. At this time, MN10 of the sample-and-hold circuit in the bias current module is turned off, MN11 is turned on, and the bias current module is in the holding state.

[0078] During the period from t0 to t2, SELEN=High and PC_SELVbias=High in the comparator unit. At this time, regardless of the input value of SELVbias<3:0>, the output SEL<3:0>=15d, that is, the switches (i.e., SW0, SW1, SW2 and SW3) of the adjustable capacitors (i.e., Cgnd0, Cgnd1, Cgnd2 and Cgnd3) are all turned on, and all adjustable capacitors are connected to the comparator unit circuit.

[0079] During the period t2~t5, when SELEN=High and PC_SELVbias=Low, the input setting SELVbias<3:0>=the output setting SEL<3:0>. If the input signal SELVbias<3:0>=10d, then the output SEL<3:0>=10d, that is, SW1 and SW3 are turned on, SW0 and SW2 are turned off, and Cgnd1 and Cgnd3 are connected to the comparator unit.

[0080] In normal mode, the falling time t1 of SH must not be later than the falling time t2 of PC_SELVbias, meaning the switching of the adjustable capacitor module should be completed during the hold phase. Similarly, the rising time t3 of RST1_A must be later than the falling time t2 of the input signal PC_SELVbias.

[0081] The technical effects of the embodiments of this application are as follows:

[0082] Source elimination: Interference is compensated directly at the analog signal front end, rather than being repaired at the digital back end, avoiding loss of image detail and processing delay. Dynamic adaptation: Through a detection-feedback control loop, it can respond in real time to changes in lighting conditions and intensities in different scenes, offering strong versatility. Compact structure and easy integration: The circuit structure is compatible with existing CIS processes, requiring no complex additional modules, and occupying almost the same chip area compared to traditional comparators. Significant effect: It effectively suppresses the influence of bright areas on dark areas or dark areas on bright areas within the same row of pixels, improving horizontal stripe phenomena and significantly enhancing image uniformity and quality under complex lighting conditions.

[0083] Figure 10 The diagram shown is a simplified circuit structure of a comparator according to an embodiment of this application. It should be understood that this diagram is a reasonable simplification of the actual circuit for the purpose of clearly illustrating the core principles: specific control signal line names and some component names are omitted, and the subsequent second-stage amplifier circuit and output loop are not shown. It should be noted that in the actual complete circuit implementation, all of the above-mentioned parts are essential components.

[0084] When the illumination is unevenly distributed in the horizontal direction (assuming the left half of the image is more illuminated and the right half is unilluminated), a strong photocurrent is generated in the left half of the sensor's pixels when strong light shines on them. This causes a voltage difference between the Rs and Ss stages on the vertical signal line in the left half of the image. This voltage difference is transmitted to the tail current source node (denoted as Tail_W) of the comparator in that area. Then, there is a parasitic capacitance (denoted as Cc_W) between the tail current node and the common wiring (i.e., the line where Vbias is located), as well as the capacitance of the transistor itself. According to the principle of capacitive coupling, the voltage jitter on Tail_W will "crosstalk" to the Vbias signal line through the capacitor, resulting in a small jitter ΔV superimposed on Vbias.

[0085] Similarly, due to uneven illumination distribution in the horizontal direction, the operating points of pixel circuits in different bright and dark areas will change locally, introducing interference such as power supply noise and ground fluctuations. This interference will be parasiticly coupled to the common wiring. Vbias on the common wiring is a global signal that provides a reference bias for all comparators (including those in the right half of the image). After Vbias is transmitted to the comparators in the right half of the image, the parasitic capacitance between Vbias and Tail_E (denoted as Cc_E) and the capacitance of the transistor itself will affect the transmission gain of the tail current transistor (denoted as MN_TAIL_E). The superimposed jitter ΔV will be transmitted to Tail_E through Cc_E, thus affecting the voltage of that node and ultimately the tail current of the comparator in the right half of the image. A small change in the tail current will directly change the flip speed or threshold of Vcomp. Ultimately, the readout time (flip point) of the pixel signal in the right half of the image will be prematurely or delayed, at which point horizontal stripes will be detected in the image system.

[0086] For the tail current transistor, due to the inherent characteristics of the MOSFET, the capacitance between the Vbias and Tail nodes is Cgd, and the capacitance between the Vbias and VSS terminals is Cgs. Therefore, the transfer gain formula of the circuit is as follows.

[0087] ;

[0088] As can be seen from the above formula, the capacitive coupling from the Tail node to Vbias can be considered as a voltage divider composed of parasitic capacitances. An adjustable capacitor is actively connected between the Vbias node and ground. When the image sensor detects a difference in brightness in the horizontal direction, the control logic unit outputs a digital control signal based on the received horizontal stripe detection result, switching different switch combinations to connect capacitors of different sizes to the reference ground node of Vbias, thereby adjusting the amplitude of the interference voltage coupled to Vbias.

[0089] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0090] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0091] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0092] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0093] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0094] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A circuit for dynamically compensating for horizontal stripes in CIS, characterized in that, include: Bias current module, core comparator module, and adjustable capacitor module; The core comparison module includes multiple comparator units, each comparator unit includes multiple minimum unit sub-modules, the input of each minimum unit sub-module is connected to the pixel voltage signal, and the minimum unit sub-module corresponds one-to-one with the pixel voltage signal corresponding to the pixel; the adjustable capacitor module configures an adjustable capacitor for each minimum unit sub-module to change the transmission gain of the minimum unit sub-module; the bias current module provides bias current to the minimum unit sub-module through a multi-current mirror module structure; Based on the transmission gain controlled by the adjustable capacitor module and the bias current provided by the bias current module, the smallest unit submodule compares and outputs pixel voltage signals with different gains through a first-stage amplification structure, and amplifies and inverts the signal output by the first-stage amplification structure through a second-stage amplification structure to output the pixel voltage signal after dynamically compensating for CIS horizontal stripes. The first-stage amplification structure includes a first comparison branch and a second comparison branch, wherein the first comparison branch and the second comparison branch are not simultaneously turned on; the first comparison branch is used to receive a low-gain pixel voltage signal, compare the low-gain pixel voltage signal with a reference voltage, and output a first comparison result; the second comparison branch is used to receive a high-gain pixel voltage signal, compare the high-gain pixel voltage signal with a reference voltage, and output a second comparison result. Both the first comparison branch and the second comparison branch are biased by a bias current module, and the capacitance between the bias voltage and the VSS terminal is adjusted by an adjustable capacitor module.

2. The circuit for dynamically compensating for CIS horizontal stripes according to claim 1, characterized in that, The smallest unit submodule also includes a first automatic zero-adjustment switch module and a second automatic zero-adjustment switch module; The first automatic zero-adjustment switch module is disposed on the MOS transistor that inputs the low-gain pixel voltage signal and the MOS transistor that inputs the reference voltage in the first comparison branch, and the first automatic zero-adjustment switch module is used to zero the first comparison branch to eliminate the offset voltage and noise in the first comparison branch. The second automatic zero-adjustment switch module is disposed on the MOS transistor that inputs the high-gain pixel voltage signal and the MOS transistor that inputs the reference voltage in the second comparison branch, and the second automatic zero-adjustment switch module is used to zero the second comparison branch to eliminate the offset voltage and noise in the second comparison branch.

3. The circuit for dynamically compensating for CIS horizontal stripes according to claim 1, characterized in that, The secondary amplification structure includes a third comparison branch and an inverting structure; the third comparison branch receives the comparison result output by the primary amplification structure and performs a comparison on the comparison result output by the primary amplification structure. The inverting structure is used to invert the comparison result output by the third comparison branch and output the pixel voltage signal after dynamically compensating for CIS horizontal stripes.

4. The circuit for dynamically compensating for CIS horizontal stripes according to claim 3, characterized in that, The secondary amplification structure also includes a third automatic zero-adjustment switch module; the third automatic zero-adjustment switch module is used to zero-adjust the MOS transistor in the third comparison branch to eliminate the offset voltage and noise in the third comparison branch.

5. The circuit for dynamically compensating for CIS horizontal stripes according to claim 1, characterized in that, The bias current module includes a first current mirror structure, a bias current ratio adjustment module, and a second current mirror structure. The first current mirror structure is used to provide a reference bias current, and the first current mirror structure is connected to the bias current ratio adjustment module. The bias current ratio adjustment module is used to amplify the reference bias current and input it into the second current mirror structure. The second current mirror structure is used to copy the current output by the bias current ratio adjustment module.

6. The circuit for dynamically compensating for CIS horizontal stripes according to claim 5, characterized in that, The bias current proportional adjustment module includes a current mirror composed of two MOS transistors, and the size ratio between the two MOS transistors is set to 1:x. The bias current proportional adjustment module amplifies the reference bias current output by the first current mirror structure by a factor of x and inputs it into the second current mirror structure; where x is a number greater than 1.

7. The circuit for dynamically compensating for CIS horizontal stripes according to claim 5, characterized in that, The bias current module further includes a replication ratio adjustment structure; the replication ratio adjustment structure includes MOS transistors connected in series with the MOS transistors in the second current mirror structure, and the source and drain of the MOS transistors in the replication ratio adjustment structure are connected to the drain and gate of the corresponding MOS transistors in the second current mirror structure, respectively. The source of the MOS transistors in the replication ratio adjustment structure is independently controlled to adjust the replication ratio of the second current mirror structure.

8. The circuit for dynamically compensating for CIS horizontal stripes according to claim 1, characterized in that, The adjustable capacitor module includes multiple capacitors, the same number as the minimum unit sub-module, which are controlled by a switching transistor to be switched on and off. Each capacitor corresponds one-to-one with the minimum unit sub-module and is connected to the position of the bias current input minimum unit sub-module. Each capacitor is independently controlled.

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