Multilayer substrate, electronic device including the same, and method of manufacturing the multilayer substrate

Abstract

The present application provides a multilayer substrate, a manufacturing method of the multilayer substrate and an electronic device including the multilayer substrate, which form a sub-via hole partially overlapping with a main via hole to reduce the undercut degree of the inside of the via hole when forming the via hole on the multilayer substrate. The multilayer substrate includes: a base substrate; a first circuit wiring layer and a first via hole pad formed on the base substrate; an interlayer insulating layer covering the first circuit wiring layer and the first via hole pad; a via hole portion formed through the interlayer insulating layer and in contact with the first via hole pad; an electroplated portion filling the via hole portion; a second circuit wiring layer formed on the interlayer insulating layer; and a second via hole pad formed on the electroplated portion, wherein the via hole portion includes a main via hole and a sub-via hole partially overlapping with the main via hole.

Description

Technical Field

[0001] This invention relates to a multilayer substrate applicable to flexible circuit boards or coil substrates, a method for manufacturing a multilayer substrate, and an electronic device including a multilayer substrate. Background Technology

[0002] Vias can be formed on a multilayer substrate in the following sequence. First, a circuit pattern and a lower via pad are formed on the substrate, and an interlayer insulating layer is applied on top of it. Then, the interlayer insulating layer applied to the lower via pad is laser-processed to form vias. Next, carbides generated during laser processing are removed by a desmear or etching process. Then, a Ni / Cr (nickel / chromium) underlayer is formed on the upper and inner sides of the interlayer insulating layer, and on top of the lower via pad, to fill the undercut structure created by etching a portion of the upper part of the lower via pad that is connected to the inner side of the interlayer insulating layer. Next, a resist pattern for forming a second circuit pattern is formed on the interlayer insulating layer. Finally, electroplating is performed on the spaces between the resist patterns and inside the vias.

[0003] However, when vias are formed in the above sequence, a Ni / Cr underlayer is formed on the lower via pad containing Cu (copper), and the via is then filled with copper again on the Ni / Cr underlayer, thereby forming an upper via pad. Therefore, a dissimilar metal layer of Cu and Ni / Cr may form inside the via, weakening the bonding between the metals and reducing the reliability of the via interface.

[0004] On the other hand, the thickness of the undercut structure can be increased by enhancing the descaling or etching process, thereby forming a homogeneous metal layer consisting only of Cu inside the via. However, when forming vias using the above method, it is difficult to apply current to the lower or inner part of the undercut structure during the electroplating process. Therefore, void regions that are not filled with copper (Cu) may be generated inside the via. This can lead to via interface separation, which may ultimately reduce the reliability of the via interface. Summary of the Invention

[0005] The technical problem that the invention aims to solve

[0006] The technical problem to be solved in this invention is to provide a method for manufacturing a multilayer substrate by forming sub-vias that partially overlap with the main vias when forming vias on a multilayer substrate, thereby reducing the undercut of the vias, as well as a multilayer substrate manufactured according to the above method and an electronic device including the thereof.

[0007] It should be understood that the technical problems of the present invention are not limited to those described above, and those skilled in the art can clearly understand other unmentioned technical problems through the following description.

[0008] Technical solutions to the problem

[0009] An aspect of the multilayer substrate of the present invention for achieving the above-mentioned technical problems includes: a substrate; a first circuit wiring layer and a first via pad formed on the substrate; an interlayer insulating layer covering the first circuit wiring layer and the first via pad; a via portion formed to penetrate the interlayer insulating layer and contact the first via pad; an electroplated portion filling the via portion; a second circuit wiring layer formed on the interlayer insulating layer; and a second via pad formed on the electroplated portion, wherein the via portion includes a main via and a sub-via that partially overlaps with the main via.

[0010] One aspect of the electronic device of the present invention for achieving the above-mentioned technical problems includes the above-mentioned multilayer substrate.

[0011] An aspect of the multilayer substrate manufacturing method of the present invention for addressing the above-mentioned technical problems includes the following steps: forming a first circuit wiring layer and a first via pad on a substrate; forming an interlayer insulating layer to cover the first circuit wiring layer and the first via pad; forming a main via to penetrate the surface of the interlayer insulating layer and contact the first via pad; forming a sub-via that partially overlaps with the main via; performing an etching or cleaning process including the main via and the sub-via; forming an underlayer covering the interlayer insulating layer, the main via, and the sub-via; and forming an electroplated portion within the main via, and forming a second circuit wiring layer and a second via pad on the interlayer insulating layer and the electroplated portion.

[0012] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0013] The effects of the invention

[0014] The present invention forms a sub-via that partially overlaps with the main via, thereby reducing the undercut degree on the inner side of the via, and thus achieving the following effects.

[0015] First, a stable conductive state can be maintained between the via wall and the inner pads. During copper plating, current can be applied simultaneously to both the via wall and the inner pads to deposit copper. This invention suppresses the possibility of voids.

[0016] Secondly, after via fabrication, the spacing between the vias, via pads, and insulating layer can be controlled. This ensures the reliability of the interface between the vias and via pads in this invention.

[0017] Third, a homogeneous metal layer can be formed within the via to prevent a decrease in the reliability of the via interface. This invention also improves the bonding strength between homogeneous metals.

[0018] The effects of this invention are not limited to those mentioned above. Those skilled in the art should clearly understand other effects not mentioned below through the following description. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating a method for manufacturing a multilayer substrate according to an embodiment of the present invention.

[0020] Figure 2 This is an example diagram illustrating step S110 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0021] Figure 3 This is an example diagram illustrating step S120 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0022] Figure 4 This is an example diagram illustrating step S130 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0023] Figure 5 This is an example diagram illustrating step S140 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0024] Figure 6 This is a first example diagram illustrating step S150 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0025] Figure 7 This is a second example diagram illustrating step S150 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0026] Figure 8 This is a third example diagram illustrating step S150 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0027] Figure 9 This is a fourth example diagram illustrating step S150 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0028] Figure 10 This is an example diagram illustrating step S160 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0029] Figure 11 This is an example diagram illustrating step S180 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0030] Figure 12 This is a first example diagram illustrating step S190 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0031] Figure 13 This is a second example diagram illustrating step S190 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0032] Figure 14 This is a flowchart illustrating a method for manufacturing a multilayer substrate according to another embodiment of the present invention.

[0033] Figure 15 This is an example diagram illustrating step S430 in a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0034] Figure 16 This is a first example diagram illustrating step S440 in a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0035] Figure 17 This is a second example diagram illustrating step S440 in a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0036] Figure 18 This is a third example diagram illustrating step S440 in a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0037] Figure 19 This is a fourth example diagram illustrating step S440 in a multilayer substrate manufacturing method according to another embodiment of the present invention. Detailed Implementation

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same technical features in the drawings, and repeated descriptions thereof are omitted.

[0039] The multilayer substrate of the present invention forms sub-vias by partially overlapping with the main vias, thereby reducing the undercut on the inner side of the vias, which can suppress the possibility of void formation, improve the bonding force between the same metals, and improve the reliability of the via interface. The manufacturing method of the multilayer substrate will be described below.

[0040] Figure 1 This is a flowchart illustrating a method for manufacturing a multilayer substrate according to an embodiment of the present invention.

[0041] First, a first circuit wiring layer and a first via pad (S110) are formed on one side of the substrate.

[0042] Figure 2This is an example diagram illustrating step S110 of a multilayer substrate manufacturing method according to an embodiment of the present invention. A first direction D1 and a second direction D2 form a plane along the horizontal direction. For example, the first direction D1 can be a front-to-back direction, and the second direction D2 can be a left-to-right direction. Alternatively, the first direction D1 can be a left-to-right direction, and the second direction D2 can be a front-to-back direction. A third direction D3 is a height direction, which is perpendicular to the plane formed by the first direction D1 and the second direction D2. The third direction D3 can be a vertical direction.

[0043] refer to Figure 2 The first circuit wiring layer 220 can be formed on the wiring area CL of the substrate 210, and the first via pad 230 can be formed on the pad area PL of the substrate 210. The first circuit wiring layer 220 and the first via pad 230 can be formed simultaneously, but are not limited to this, and can also be formed at different times. In addition, the first circuit wiring layer 220 and the first via pad 230 can be formed of the same metal or different metals.

[0044] The first circuit wiring layer 220 may be formed in a linear wiring shape on a substrate 210 made of an insulating material. Alternatively, the first circuit wiring layer 220 may be formed in a spirally wound coil shape on the substrate 210. In the former case, the multilayer substrate of the present invention may be formed as a flexible circuit substrate. In the latter case, the multilayer substrate of the present invention may be formed as a coil substrate.

[0045] The first circuit wiring layer 220 can be formed using photolithography. However, it is not limited to this method; the first circuit wiring layer 220 can also be formed using various processes such as printing, bonding, coating, and electroplating. The first circuit wiring layer 220 can be formed with a thickness of 5 μm to 200 μm. Preferably, the first circuit wiring layer 220 can be formed with a thickness of 30 μm to 100 μm. More preferably, the first circuit wiring layer 220 can be formed with a thickness of 40 μm to 80 μm.

[0046] Refer again Figure 1 illustrate.

[0047] After forming the first circuit wiring layer 220 and the first via pad 230 on the substrate 210, an interlayer insulating layer is formed to cover the first circuit wiring layer 220 and the first via pad 230 (S120). The interlayer insulating layer 240 can be formed by various methods such as lamination and hot pressing.

[0048] Figure 3 This is an example diagram illustrating step S120 of a multilayer substrate manufacturing method according to an embodiment of the present invention. (Refer to...) Figure 3The interlayer insulating layer 240 can be formed to cover the top and sides of the first circuit wiring layer 220, the top and sides of the first via pad 230, and portions of the substrate 210 where the first circuit wiring layer 220 and the first via pad 230 are not formed. However, it is not limited to this; the interlayer insulating layer 240 can also be formed to selectively cover only certain areas as needed. For example, the interlayer insulating layer 240 can be formed to cover only the first circuit wiring layer 220 and the first via pad 230.

[0049] Refer again Figure 1 illustrate.

[0050] After forming an interlayer insulating layer 240 on the substrate 210, a main via is formed on the interlayer insulating layer 240 (S130).

[0051] Figure 4 This is an example diagram illustrating step S130 of a multilayer substrate manufacturing method according to an embodiment of the present invention. (Refer to...) Figure 4 The main via 250a can be formed from the upper surface of the interlayer insulating layer 240 through the thickness direction D3 of the interlayer insulating layer 240 to contact the first via pad 230. The main via 250a can be formed to have a size corresponding to the first via pad 230. For example, the main via 250a can be formed to have the same size as the first via pad 230. Alternatively, the main via 250a can be formed to have a smaller size than the first via pad 230.

[0052] The main via 250a can be formed using laser drilling. In this case, a UV laser can be used to form the main via 250a. Alternatively, a CO2 laser can be used to form the main via 250a.

[0053] The lower diameter of the main via 250a can be formed to have a width different from its upper diameter. Specifically, the width of the lower diameter of the main via 250a can be formed to be narrower than the width of its upper diameter. The width W2 of the lower diameter can be formed to be a value of 75% or more and less than 100% relative to the width W1 of the upper diameter (0.75×W1≤W2<1×W1). However, it is not limited to this; the width W2 of the lower diameter can also be formed to be less than 75% of the width W1 of the upper diameter. When the width W2 of the lower diameter is formed to be less than 75% of the width W1 of the upper diameter, the width W2 of the lower diameter can be selected to an appropriate value according to the size of the upper diameter. On the other hand, the lower diameter of the main via 250a can also be formed to have the same width as its upper diameter.

[0054] Refer again Figure 1 illustrate.

[0055] After forming the main via 250a in the interlayer insulating layer 240, a sub-via (S140) is formed in the edge region of the main via 250a.

[0056] Figure 5 This is an example diagram illustrating step S140 of a multilayer substrate manufacturing method according to an embodiment of the present invention. (Refer to...) Figure 5 The sub-via 250b may be formed as a part overlapping the main via 250a. In the following description, the main via 250a and the sub-via 250b are combined into one and defined as via portion 250.

[0057] The sub-via 250b can be formed in the same shape as the main via 250a. However, it is not limited to this; the sub-via 250b can also be formed in a different shape than the main via 250a. The planar shapes of the main via 250a and the sub-via 250b can be selected from polygons such as triangles and quadrilaterals, circles, ellipses, lines, etc.

[0058] The thickness T2 of the sub-via 250b can be less than the thickness T1 of the main via 250a. Therefore, after the sub-via 250b is formed, the interlayer insulating layer 240 beneath it is not etched but remains. For example, the residual insulating layer 241 remaining within the via portion 250 can be formed relatively thinly, to a degree of less than 5 μm.

[0059] The upper diameter of the sub-via 250b may be formed to have a width that is the same as or different from the upper diameter of the main via 250a. The width W3 of the upper diameter of the sub-via 250b may be formed to be a value of 45% to 100% relative to the width W1 of the upper diameter of the main via 250a (0.45×W1≤W3≤1.0×W1).

[0060] If the width W3 of the upper diameter of the sub-via 250b is less than 45% of the width W1 of the upper diameter of the main via 250a, the area of ​​the residual insulating layer 241 remaining in the via portion 250 may be narrower than appropriate. In this case, during the etching process, the residual insulating layer 241 may not deform in shape along the upper direction of the first via pad 230 forming the undercut. Alternatively, even if the residual insulating layer 241 deforms, it may not adhere to the upper part of the first via pad 230 forming the undercut.

[0061] If the width W3 of the upper diameter of the sub-via 250b is greater than 100% of the width W1 of the upper diameter of the main via 250a, the area of ​​the residual insulating layer 241 remaining in the via portion 250 may be larger than an appropriate value. In this case, during the etching process, the residual insulating layer 241 has strong resistance to the etching solution and may not be able to deform in shape along the upper direction of the first via pad 230 forming the undercut. That is, an undercut structure may continue to form in the via portion 250, and the void problem caused by the undercut structure cannot be solved.

[0062] The upper area of ​​the residual insulating layer 241 can be formed to be 1% to 30% of the lower area of ​​the main via 250a. Preferably, the upper area of ​​the residual insulating layer 241 can be formed to be 5% to 20% of the lower area of ​​the main via 250a. More preferably, the upper area of ​​the residual insulating layer 241 can be formed to be 9% to 15% of the lower area of ​​the main via 250a.

[0063] If the upper area of ​​the residual insulating layer 241 is less than 1%, the area of ​​the residual insulating layer 241 may be smaller than an appropriate value. In this case, during the etching process, the residual insulating layer 241 may not be deformed in the upper direction of the first via pad 230 forming the undercut. Alternatively, even if the residual insulating layer 241 is deformed, it may not bond with the upper part of the first via pad 230 forming the undercut.

[0064] If the upper area of ​​the residual insulating layer 241 exceeds 30%, the area of ​​the residual insulating layer 241 may be larger than an appropriate value. In this case, during the etching process, the residual insulating layer 241 has strong resistance to the etching solution and may not be able to deform in shape along the upper direction of the first via pad 230 forming the undercut. That is, an undercut structure may continue to form within the via portion 250, and the void problem caused by the undercut structure cannot be resolved.

[0065] Refer again Figure 1 illustrate.

[0066] After the main via 250a and the sub-via 250b are sequentially formed on the interlayer insulating layer 240, an etching process is performed to clean or modify the surface used to form the underlayer, which will be described in step S160 (S150). Alternatively, a decontamination process may be performed.

[0067] During the etching or cleaning process, the surface of the first via pad 230 exposed to the outside can be etched from the bottom of the interlayer insulating layer 240 with a thickness of 1 μm to 5 μm. At this time, undercutting may occur, that is, the etching extends to the interlayer insulating layer 240 adjacent to the lower boundary of the main via 250a.

[0068] In the above context, if the etching depth is less than 1 μm, the distribution of the same metal region inside the via 250 may be insufficient, leading to interface reliability issues caused by dissimilar metal layers. Furthermore, if the etching depth exceeds 5 μm, it creates additional undercut structures, making bonding between the interlayer insulating layer 240 and the first via pad 230 difficult. Moreover, during the etching process, the etching solution may weaken the durability or strength of the residual insulating layer 241, causing it to deform into a shape that bonds with the upper part of the undercut first via pad 230.

[0069] Finally, the vertical and horizontal sections of the through hole 250 are as follows: Figure 6 and Figure 7 As shown. Figure 6 This is a first example diagram illustrating step S150 in a multilayer substrate manufacturing method according to an embodiment of the present invention. Figure 7 This is a second example diagram illustrating step S150 of a multilayer substrate manufacturing method according to an embodiment of the present invention. (Refer to...) Figure 6 and Figure 7 The residual insulating layer 241 is joined along the contour of the upper edge region of the first via pad 230 where the undercut occurs, and one end of the residual insulating layer 241 is joined to the upper part of the first via pad 230 (A). Conversely, in the region where the sub-via 250b is not formed, the lower part of the residual insulating layer 241 is formed at an undercut thickness interval with the upper part of the first via pad 230 (B). That is, the two side cross sections of the via portion 250 can be formed as an asymmetrical structure.

[0070] Figure 7 The example shown is a case where a single sub-via 250b is formed at the edge of the main via 250a. However, it is not limited to this; multiple sub-vias can also be formed at the edge of the main via 250a.

[0071] When forming a sub-via in the edge region of the main via 250a, multiple sub-vias can be formed simultaneously. However, this is not the only possibility; when forming a sub-via in the edge region of the main via 250a, multiple sub-vias can also be formed sequentially while maintaining a time difference.

[0072] refer to Figure 8 Multiple sub-vias 250ba, 250bb, ..., 250bn can be formed along the edge of the main via 250a in a partially overlapping manner. However, this embodiment is not limited to this. (See reference...) Figure 9 Multiple sub-vias 250ba, 250bb, ..., 250bn can also be formed along the edge of the main via 250a in a mutually spaced manner. Figure 8 This is a third example diagram illustrating step S150 in a multilayer substrate manufacturing method according to an embodiment of the present invention. Figure 9This is a fourth example diagram illustrating step S150 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0073] Refer again Figure 1 illustrate.

[0074] After the etching or cleaning process is completed, a bottom layer 260 (S160) is formed on the inner side of the via 250, the top surface of the interlayer insulating layer 240, and the sides. The bottom layer 260 can be formed by a dry conductive process, i.e., sputtering, or a wet conductive process, i.e., conductive process. In this embodiment, the case of forming the bottom layer 260 using a sputtering process will be described as an example.

[0075] Figure 10 This is an example diagram illustrating step S160 of a multilayer substrate manufacturing method according to an embodiment of the present invention. The aforementioned first via pad 230 and bottom layer 260 may be formed of metal. In the following description, the metal used to form the first via pad 230 is defined as the first metal, and the metal used to form the bottom layer 260 is defined as the second metal.

[0076] The bottom layer 260 can be formed at a size of 20nm to 30nm. However, in this invention, the bottom layer 260 is not necessarily limited to the above-mentioned size. Some areas of the bottom layer 260 may be discontinuous and formed with a truncated structure. In the portion where an undercut occurs between the interlayer insulating layer 240 and the first via pad 230, the bottom layer 260 may be discontinuous.

[0077] The second metal used to form the bottom layer 260 may include at least one of Ni and Cr. However, it is not limited to this. In addition to Ni and Cr, the second metal may be selected from Cu, Ag (silver), Ti (titanium), etc., but the second metal in this invention is not necessarily limited to this.

[0078] The first metal used to form the first via pad 230 may be different from the second metal. For example, the first metal may be Cu, and the second metal may be Ni / Cr. However, it is not limited to this; the first metal may also be the same as the second metal. For example, both the first metal and the second metal may be Cu.

[0079] Refer again Figure 1 illustrate.

[0080] After forming the bottom layer 260 on the via portion 250, the interlayer insulating layer 240, etc., a resist pattern is formed on the upper part of the interlayer insulating layer 240 (S170). The resist pattern can be formed on the upper part of the interlayer insulating layer 240 to form a second circuit wiring layer, a second via pad, etc. on the upper part of the interlayer insulating layer 240.

[0081] After forming a resist pattern on the upper part of the interlayer insulating layer 240, electroplating is performed on the gaps between the resist patterns, via portions 250, etc. (S180). By performing the above electroplating, a second circuit wiring layer, a second via pad, etc., can be formed on the upper part of the interlayer insulating layer 240.

[0082] Figure 11 This is an example diagram illustrating step S180 of a multilayer substrate manufacturing method according to an embodiment of the present invention. (Refer to...) Figure 11 The electroplated portion 270 is filled in the via portion 250 by electroplating. The two ends of the electroplated portion 270 that are in contact with the inner side of the interlayer insulating layer 240 have different thicknesses, and with a virtual central axis as a reference, the two sides can have different asymmetrical structures.

[0083] The bottom layer 260 can be formed along the inner surface where the first via pad 230 and the interlayer insulating layer 240 meet, serving to introduce wiring. In the past, due to undercutting, the side of the interlayer insulating layer 240 and the first via pad 230 were not connected, resulting in a disconnected structure for the bottom layer 260. Consequently, it was difficult to effectively apply current through the bottom layer 260. Therefore, the plating of the second via pad was completed before the Cu was fully plated to the inner side of the undercut structure, creating voids and reducing the reliability of the via interface.

[0084] Conversely, in this invention, an inner region is formed where the side of the interlayer insulating layer 240 is in contact with the first via pad 230, and a bottom layer 260 can be formed along the side of the interlayer insulating layer 240 to connect with the bottom layer 260 formed on the upper part of the first via pad 230. Therefore, a current-applied channel is formed, and Cu can be completely electroplated to the inner side of the remaining undercut structure, thereby suppressing void formation and improving via interface reliability.

[0085] Refer again Figure 1 illustrate.

[0086] After electroplating is completed, the resist pattern is peeled off from the interlayer insulating layer 240 (S190).

[0087] Figure 12 This is a first example diagram illustrating step S190 in a multilayer substrate manufacturing method according to an embodiment of the present invention. After the resist pattern is stripped, the multilayer substrate 200 may include a substrate 210, a first circuit wiring layer 220, a first via pad 230, an interlayer insulating layer 240, a bottom layer 260, an electroplated portion 270, a second circuit wiring layer 320, and a second via pad 330, forming a double-layer structure.

[0088] The first circuit wiring layer 220 can be electrically connected to the first via pad 230 formed at the same level. Similarly, the second circuit wiring layer 320 can be electrically connected to the second via pad 330 formed at the same level. The first via pad 230 can be electrically connected to the second via pad 330 through the electroplated portion 270 filling the via portion 250. Thus, the first circuit wiring layer 220 and the second circuit wiring layer 320 can be electrically connected through the first via pad 230, the electroplated portion 270, and the second via pad 330.

[0089] refer to Figure 13 When the multilayer substrate 200 is formed as a double-layer structure, the second circuit wiring layer 320 and the second via pad 330 can be covered by the protective layer 380 formed on top of it. At this time, the external connection terminals can be exposed without being covered. Figure 13 This is a second example diagram illustrating step S190 in a multilayer substrate manufacturing method according to an embodiment of the present invention.

[0090] The multilayer substrate 200 can also be formed into a structure of three or more layers. For example, when the multilayer substrate 200 is formed into a three-layer structure, an insulating layer, a via portion including a main via and a sub-via, a bottom layer, a resist pattern, an electroplated portion, a third circuit wiring layer, a third via pad, and a protective layer can be sequentially formed on the second circuit wiring layer 320 and the second via pad 330. The insulating layer, via portion, bottom layer, resist pattern, electroplated portion, third circuit wiring layer, third via pad, and protective layer can be based on previous references. Figures 1 to 13 The method described is sequentially formed on the second circuit wiring layer 320 and the second via pad 330. When the multilayer substrate 200 is formed into a structure of 4 or more layers, the above method can of course be applied repeatedly.

[0091] The above is for reference only. Figures 1 to 13 The case of forming a single main via 250a and a single sub-via 250b on the first via pad 230 is explained. Furthermore, the case of forming a single main via 250a and multiple sub-vias 250ba, 250bb, ..., 250bn on the first via pad 230 is explained.

[0092] However, this is not the only possibility. In this invention, multiple main vias and a single sub-via 250b can also be formed on the first via pad 230. Alternatively, multiple main vias and multiple sub-vias 250ba, 250bb, ..., 250bn can also be formed on the first via pad 230. This will be explained below.

[0093] Figure 14 This is a flowchart illustrating a method for manufacturing a multilayer substrate according to another embodiment of the present invention. Figure 14The example illustrates the case where two main vias and a single sub-via 250b are formed on the first via pad 230.

[0094] First, a first circuit wiring layer 220 and a first via pad 230 are formed on one side of the substrate 210 (S410). Step S410 can be performed in the same manner as step S110 described above, so a detailed description of it is omitted here.

[0095] Subsequently, an interlayer insulating layer 240 is formed to cover the first circuit wiring layer 220 and the first via pad 230 (S420). Step S420 can be performed in the same manner as step S120 described above, so a detailed description of it is omitted here.

[0096] Subsequently, two main vias are formed in the interlayer insulating layer 240, namely the first main via 250c and the second main via 250d (S430).

[0097] Figure 15 This is an example diagram illustrating step S430 of a multilayer substrate manufacturing method according to another embodiment of the present invention. (Refer to...) Figure 15 The first main via 250c and the second main via 250d can be formed using the same processing method as the main via 250a described above. For example, the first main via 250c and the second main via 250d can be formed by laser drilling using a UV laser. Alternatively, the first main via 250c and the second main via 250d can be formed by laser drilling using a CO2 laser.

[0098] The first main via 250c and the second main via 250d may have the same shape as the main via 250a described above. That is, the first main via 250c and the second main via 250d may be formed to have the same shape. For example, the lower diameter of the first main via 250c and the second main via 250d may be formed to have a width different from its upper diameter. Alternatively, the lower diameter of the first main via 250c and the second main via 250d may be formed to have the same width as its upper diameter. However, this is not a limitation, and the first main via 250c and the second main via 250d may also be formed to have different shapes.

[0099] The first main via 250c and the second main via 250d can be formed to have the same size as the previously described main via 250a. That is, the first main via 250c and the second main via 250d can be formed to have the same size. Furthermore, the first main via 250c and the second main via 250d can be formed simultaneously. However, this is not a limitation; the first main via 250c and the second main via 250d can also be formed sequentially.

[0100] The first main via 250c and the second main via 250d can be formed alternately. The spacing between the first main via 250c and the second main via 250d is preferably 10μm to 50μm, but the above spacing can of course be changed to different values ​​depending on the size of the first via pad 230.

[0101] On the other hand, when three or more main vias are formed on the first via pad 230, the nth main via (where n is a natural number of 3 or more) can be formed in the same way as the first main via 250c or the second main via 250d.

[0102] Re-reference Figure 14 illustrate.

[0103] After forming the first main via 250c and the second main via 250d in the interlayer insulating layer 240, a sub-via 250b is formed in the space between the first main via 250c and the second main via 250d (S440).

[0104] Figure 16 This is a first example diagram illustrating step S440 of a multilayer substrate manufacturing method according to another embodiment of the present invention. (Refer to...) Figure 16 The sub-via 250b may be formed as a part of the first main via 250c and the second main via 250d, respectively. In the following description, the first main via 250c, the second main via 250d and the sub-via 250b are combined into one and defined as via portion 250.

[0105] The shape and size of the sub-via 250b, and the extent of the residual insulating layer 241 remaining in the via portion 250 according to the size of the sub-via 250b, and reference. Figure 1 The descriptions are the same, so a detailed explanation is omitted here.

[0106] The upper diameter of the sub-via 250b can be formed to have a width different from the upper diameters of the first main via 250c and the second main via 250d. Specifically, the width of the upper diameter of the sub-via 250b can be formed to be smaller than the width of the upper diameters of the first main via 250c and the second main via 250d. The width W6 of the upper diameter of the sub-via 250b can be formed to be a value of 40% to 80% relative to the width W4 of the upper diameter of the first main via 250c and the width W5 of the upper diameter of the second main via 250d (0.4×W4, W5≤W6≤0.8×W4, W5).

[0107] If the width W6 of the upper diameter of the sub-via 250b is less than 40% relative to the widths W4 and W5 of the upper diameters of the first main via 250c and the second main via 250d, the area of ​​the residual insulating layer 241 remaining in the via portion 250 may be narrower than appropriate. In this case, during the etching process, the residual insulating layer 241 may not be deformed along the upper direction of the undercut first via pad 230. Alternatively, even if the residual insulating layer 241 is deformed, it may not bond with the upper part of the undercut first via pad 230.

[0108] If the width W3 of the upper diameter of the sub-via 250b is greater than 80% of the widths W4 and W5 of the upper diameters of the first main via 250c and the second main via 250d, although the bonding between the residual insulating layer 241 and the first via pad 230 can be achieved, it may reduce the production efficiency of the product.

[0109] The first main via 250c, the second main via 250d, and the sub-via 250b may overlap by 10% to 30% of the area of ​​the lower area of ​​the first main via 250c. If the overlap area between the first main via 250c and the sub-via 250b and / or the overlap area between the second main via 250d and the sub-via 250b is less than 10%, it may cause the same problem as the aforementioned case where the overlap area between the main via 250a and the sub-via 250b is less than 1%. Similarly, if the overlap area between the first main via 250c and the sub-via 250b and / or the overlap area between the second main via 250d and the sub-via 250b exceeds 30%, it may cause the same problem as the aforementioned case where the overlap area between the main via 250a and the sub-via 250b exceeds 30%.

[0110] The sub-via 250b can be formed in various shapes such as circular, polygonal, or linear. Depending on the width, thickness, and area of ​​the sub-via 250b, the laser processing level at the lower center of the sub-via 250b may be higher than that of other areas. As a result, a portion of the upper part of the first via pad 230 corresponding to the lower center area of ​​the sub-via 250b may be exposed, potentially resulting in an undercut structure.

[0111] When forming the sub-via 250b, the laser is irradiated and processed multiple times, depending on the area or thickness of the sub-via 250b. In this case, processing is performed multiple times while changing the laser position, resulting in overlapping processing areas. A high degree of laser processing means that the processing depth of the overlapping areas is greater than that of other areas.

[0112] To address the above problems, in this invention, the sub-via 250b can be formed in a ring shape. Forming it in a ring shape means that the sub-via 250b is formed to connect simultaneously to both the first main via 250c and the second main via 250d. That is, the sub-via 250b can be formed such that a portion of it overlaps with both the first main via 250c and the second main via 250d. When the sub-via 250b is formed in a ring shape, its formation method can be similar to... Figure 17 The first sub-via 250ba or the second sub-via 250bb is the same, as will be described below. Alternatively, the sub-via 250b can be formed in the same way as... Figure 18 The first sub-via 250ba is the same. If the sub-via 250b is formed in a ring shape, the area of ​​process overlap (e.g., the lower center of the sub-via 250b) can be minimized, and the upper exposure of the first via pad 230 can be controlled.

[0113] Re-reference Figure 14 illustrate.

[0114] After forming a first main via 250c, a second main via 250d, and a sub-via 250b sequentially on the interlayer insulating layer 240, an etching process is performed to clean or modify the surface used to form the underlayer, which will be described in step S460 (S450). In this invention, a decontamination process can also be performed instead of the etching process. Step S450 can be performed in the same manner as step S150 described above, so a detailed description of it is omitted here.

[0115] After the etching or cleaning process is completed, a bottom layer 260 (S460) is formed on the inside of the via 250, on the top and sides of the interlayer insulating layer 240. The S460 step can be performed in the same manner as the S160 step described above, so its detailed description is omitted here.

[0116] After forming the underlayer 260 on the via 250, interlayer insulating layer 240, etc., a resist pattern is formed on the upper part of the interlayer insulating layer 240 (S470). The S470 step can be performed in the same manner as the S170 step described above, so its detailed description is omitted here.

[0117] After forming a resist pattern on the upper part of the interlayer insulating layer 240, electroplating is performed on the gaps between the resist patterns, the via portions 250, etc. (S480). Step S480 can be performed in the same manner as step S180 described above, so a detailed description of it is omitted here.

[0118] After electroplating is completed, the resist pattern is peeled off from the interlayer insulating layer 240 (S490). Step S490 can be performed in the same manner as step S190 described above, so a detailed description of it is omitted here.

[0119] As previously described, multiple main vias and multiple sub-vias can be formed on the first via pad 230. In this case, the multiple sub-vias can overlap with the multiple main vias, respectively. For example, refer to... Figure 17 A portion of the first sub-via 250ba and the second sub-via 250bb may overlap with the first main via 250c and the second main via 250d, respectively. Figure 17 This is a second example diagram illustrating step S440 in a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0120] However, this is not the only possibility; some of the sub-vias may overlap with multiple main vias, and the remaining sub-vias may not overlap with multiple main vias. For example, see reference... Figure 18 A portion of the first sub-via 250ba may overlap with the first main via 250c and the second main via 250d, and a portion of the second sub-via 250bb may overlap only with the first main via 250c. Figure 18 This is a third example diagram illustrating step S440 in a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0121] Alternatively, multiple sub-vias may not overlap with multiple main vias. For example, see reference. Figure 19 A portion of the first sub-via 250ba may overlap only with the first main via 250c, and a portion of the second sub-via 250bb may overlap only with the second main via 250d. Figure 19 This is a fourth example diagram illustrating step S440 in a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0122] Based on the above, Figures 1 to 19 A method for manufacturing a multilayer substrate according to various embodiments of the present invention has been described. Hereinafter, the multilayer substrate manufacturing method described in the background art will be defined as prior art, and reference will be made to... Figure 1 The described multilayer substrate manufacturing method is defined as the first embodiment, and reference will be made to... Figure 14 The described multilayer substrate manufacturing method is defined as the second embodiment.

[0123] To demonstrate the effectiveness of this invention, a comparative experiment on the reliability of the via interface was conducted using a bending test and a thermal cycle test. First, the experimental conditions for the bending test are as follows.

[0124] - Test Scale: 400g

[0125] - Test Point: Additional analysis location

[0126] - Number of bends: 100 (one 90° reciprocation on the left / right axis is counted as one bend).

[0127] - Film fixing clamp R-value: 0.5mm

[0128] - One 90° left / right rotation = 1 count (180°)

[0129] Secondly, the experimental conditions for the thermal cycling test are as follows.

[0130] - Temperature: -40℃~125℃ / 20 minutes

[0131] - Cycle: 50 times

[0132] Based on the results of bending tests and thermal cycling tests, interface separation occurred in the prior art, while it did not occur in the first and second embodiments. Therefore, the present invention improves the reliability of the via interface compared to the prior art.

[0133] As described above, the multilayer substrate 200 of the present invention can be used as a flexible circuit substrate or a coil substrate. When the multilayer substrate 200 is formed as a flexible circuit substrate, an electronic device can be configured as a device including the multilayer substrate 200 and a semiconductor chip mounted on the multilayer substrate 200. Furthermore, when the multilayer substrate 200 is formed as a coil substrate, an electronic device can be configured as a device including the multilayer substrate 200 and applied in fields requiring electromagnetic force.

[0134] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art should understand that the present invention is not limited to the above embodiments but can be manufactured in various different forms and implemented in other specific forms without departing from the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary and not limiting in all respects.

[0135] Industrial applicability

[0136] This invention relates to a multilayer substrate. This invention can be applied to flexible circuit boards or coil substrates.

Claims

1. A multilayer substrate, wherein, include: Substrate; A first circuit wiring layer and a first via pad are formed on the substrate. An interlayer insulating layer covers the first circuit wiring layer and the first via pad; The via portion is formed to penetrate the interlayer insulating layer and contact the first via pad; The electroplating section fills the via portion; The second circuit wiring layer is formed on the interlayer insulation layer; as well as A second via pad is formed on the electroplated portion. The via portion includes a main via and sub-vias that partially overlap with the main via.

2. The multilayer substrate according to claim 1, wherein, The lower diameter of the main via is smaller than the upper diameter of the main via.

3. The multilayer substrate according to claim 1, wherein, The depth of the sub-via is shallower than the depth of the main via.

4. The multilayer substrate according to claim 1, wherein, The upper diameter of the sub-via is smaller than the upper diameter of the main via.

5. The multilayer substrate according to claim 1, wherein, The main vias are formed in multiple ways.

6. The multilayer substrate according to claim 5, wherein, Multiple main vias are spaced apart.

7. The multilayer substrate according to claim 5, wherein, The sub-vias partially overlap with multiple main vias.

8. The multilayer substrate according to claim 1, wherein, The sub-via is formed in a ring shape relative to the main via.

9. The multilayer substrate according to claim 5, wherein, The sub-vias are formed in multiple ways.

10. The multilayer substrate according to claim 9, wherein, Each sub-via partially overlaps with each main via.

11. The multilayer substrate according to claim 9, wherein, At least one of the multiple sub-vias partially overlaps with multiple main vias.

12. The multilayer substrate according to claim 1, wherein, It also includes a bottom layer, which is formed between the main via and the electroplating section, and between the sub-via and the electroplating section.

13. The multilayer substrate according to claim 12, wherein, The bottom layer includes discontinuous sections.

14. The multilayer substrate according to claim 12, wherein, The first via pad includes a first metal, and the bottom layer includes a second metal.

15. An electronic device, wherein, include: The multilayer substrate according to any one of claims 1 to 14.

16. A method for manufacturing a multilayer substrate, wherein, Includes the following steps: A first circuit wiring layer and a first via pad are formed on a substrate. An interlayer insulating layer is formed to cover the first circuit wiring layer and the first via pad; A main via is formed to penetrate the surface of the interlayer insulating layer and contact the first via pad; A sub-via is formed that partially overlaps with the main via; Perform etching or decontamination treatment, including the main via and the sub-via; A bottom layer is formed covering the interlayer insulation layer, the main via, and the sub-via; as well as An electroplated portion is formed within the main via, and a second circuit wiring layer and a second via pad are formed on the interlayer insulating layer and the electroplated portion.

17. The method for manufacturing a multilayer substrate according to claim 16, wherein, In the step of forming the sub-via The depth of the sub-via is made shallower than the depth of the main via, so that the interlayer insulating layer remains in the lower part of the sub-via in an area that does not overlap with the main via.

18. The method for manufacturing a multilayer substrate according to claim 16, wherein, In the etching or decontamination step, The surface of the first via pad exposed below the main via is etched, and the depth of the sub-via is formed to be shallower than the depth of the main via, so that the interlayer insulating layer remains in the lower part of the sub-via in the area that does not overlap with the main via.

19. The method for manufacturing a multilayer substrate according to claim 16, wherein, It also includes the following steps: forming an underlayer covering the interlayer insulating layer, the main via, and the sub-via after the etching process or the decontamination process.

20. The method for manufacturing a multilayer substrate according to claim 16, wherein, It also includes the following steps: Before forming the electroplated portion, the second circuit wiring layer, and the second via pad, a resist pattern is formed on the underlying layer; and After forming the electroplated portion, the second circuit wiring layer, and the second via pad, the resist pattern is stripped.

Images