High-speed digital processing micro-module and layered packaging screening method thereof

Abstract

The application discloses a high-speed digital processing micro module and a layered packaging screening method thereof, the micro module comprising a CPU, a firmware Flash, m DDR modules and m LDO power supplies which are collectively packaged on a substrate; each DDR module is pre-packaged before being collectively packaged; the CPU comprises m DDR controllers, a QSPI controller and various high-speed / low-speed interface controllers; each LDO power supply is arranged between each DDR module and an external power supply ball site and is used for converting a required termination voltage and a reference voltage of each DDR module. The application improves the micro module integrated architecture, integrates the LDO power supply for generating the termination voltage and the reference voltage required by the DDR into the micro module, and pre-packages and screens the stacked DDR modules first, and then performs system-level packaging screening on the CPU, the Flash and other devices, so that unqualified products can be effectively screened out, and the problem of low yield in conventional one-time packaging is overcome.

Description

Technical Field

[0001] This invention relates to the technical field of microsystem packaging and testing, specifically to a high-speed digital processing micromodule and its layered packaging screening method. Background Technology

[0002] System-in-a-Package (SIP) integrates multiple functional chips (including processors, memory, etc.) into a single package to achieve a basic, complete function. High-speed digital processing micro-modules typically consist of a central processing unit (CPU), memory (DDR), firmware flash, and other components forming the smallest computing unit. Compared to the smallest computing unit composed of discrete chips, micro-modules occupy a significantly smaller PCB area, which is beneficial for device integration and miniaturization.

[0003] In current system-in-package (SoC) architectures, to improve chip reliability, after the bare dies are packaged into finished chips, they undergo high-temperature aging screening to remove chips that fail early in the failure rate bathtub curve. However, due to differences in chip design, manufacturing process, and aging conditions, the yield after aging varies for different types of chips. At the same time, since micromodules integrate multiple types of bare dies for packaging, if even one type of bare die fails after aging, the micromodule chip will fail, resulting in a low yield for microsystem chips.

[0004] Therefore, with the trend of equipment integration and miniaturization, micro-modules integrating chips with multiple functions have become a development trend. However, how to strike a balance between the specialization and versatility of micro-modules, while ensuring the screening yield of microsystem chips, has become an important issue in the field of micro-module packaging and testing. Summary of the Invention

[0005] To address the aforementioned problems, the purpose of this invention is to propose a high-speed digital processing micro-module and its layered packaging screening method. Through this invention, the integrated architecture of the micro-module is improved, integrating the LDO power supply that generates the termination voltage and reference voltage required for DDR into the micro-module. Furthermore, the stacked DDR modules are pre-packaged and screened for good products, and then the system-level packages of devices such as CPU and Flash are screened again. This effectively eliminates defective products and overcomes the problem of low yield of finished chips in conventional one-time packaging.

[0006] This was achieved through the following technical solutions: A high-speed digital processing micro-module includes a CPU, firmware Flash, m DDR modules and m LDO power supplies, all co-packaged on a substrate; each DDR module is pre-packaged before co-packaging to screen for good products. The CPU includes m DDR controllers, 1 QSPI controller, and various high-speed / low-speed interface controllers. Each DDR controller is connected to each corresponding DDR module. The firmware Flash is connected to the QSPI controller. Various high-speed / low-speed interface controllers fan out various high-speed / low-speed interface balls through the substrate. The CPU, each DDR module, firmware Flash, and each LDO power supply are connected to the external power supply ball in various high-speed / low-speed interface balls through corresponding traces on the substrate. Each LDO power supply is located between each corresponding DDR module and the external power supply ball, and is used to convert the external power supply voltage of the external power supply ball into the termination voltage Vtt and reference voltage Vref required by each DDR module.

[0007] Optionally, each DDR module uses multiple bare DDR dies stacked and packaged. The capacity and interface width of each DDR module meet the single-rank drive requirements of the corresponding DDR controller in the CPU. Stacking technology significantly improves the storage capacity and bandwidth of a single module, while ensuring that the pre-packaged DDR module, as a standardized single-rank component, can be directly matched with a single controller of the CPU, simplifying system integration design.

[0008] Optionally, multiple DDR bare dies are stacked in a V-shape with staggered placement and bonded to the substrate. The V-shape staggered structure facilitates heat dissipation between the bare dies in the stack, avoids excessive heat concentration, and improves the long-term operational reliability of the module. At the same time, the staggered design facilitates lead routing operations at the edges of the bare dies, optimizes the signal transmission path, and improves the yield of the packaging process.

[0009] Optionally, the various high-speed / low-speed interface controllers include at least UART, SPI, LPC, NAND, GPIO, CAN, I2C, SRIO, PCIe, and SDIO. Providing an extremely rich selection of peripheral interfaces allows this micromodule to flexibly adapt to various industry application scenarios as a core board.

[0010] Optionally, each DDR module and CPU are connected to a bus group of the following types: DM, DQS, DQ, ADDR, BA, BG. This defines the complete set of key signals necessary for high-speed DDR, ensuring reliable transmission of data (DQ, DQS, DM) and command / address signals (ADDR, BA, BG).

[0011] Optionally, the substrate includes built-in inter-board traces for connecting the signal or address lines of each DDR module to various high-speed / low-speed interface sockets. These inter-board traces provide electrical connections and signal routing capabilities from the core device to external interfaces.

[0012] Optionally, the substrate is also provided with a termination resistor, which connects the inter-board traces to force any signal of each DDR module to be connected to the corresponding high-speed / low-speed interface ball after passing through the termination resistor.

[0013] Secondly, a layered packaging and screening method is proposed for processing the aforementioned high-speed digital processing micro-module. This method includes the following steps: S1. Stack and pre-package multiple DDR bare chips to form independent DDR modules. Perform first-level aging screening on each DDR module to select qualified DDR modules. S2. Divide the qualified DDR modules into multiple groups. Each group is installed together with the corresponding CPU, firmware Flash and each LDO power supply and electrically interconnected on the corresponding packaging substrate. Perform system-level packaging to form multiple high-speed digital processing micro-module semi-finished products. S3. Perform a second-stage aging and screening process to obtain the final high-speed digital processing micro-module: Perform a second-stage aging and screening process on multiple high-speed digital processing micro-module semi-finished products to select qualified high-speed digital processing micro-module finished products.

[0014] The beneficial effects of this invention compared to the prior art are: The technical solution of this invention improves the integrated architecture of the micro-module by integrating the LDO power supply that generates the termination voltage and reference voltage required for DDR into the micro-module. Furthermore, it pre-packages and screens the stacked DDR modules for good products, and then screens the system-level packages of devices such as CPU and Flash, which can effectively screen out unqualified products and overcome the problem of low yield of finished chips in conventional one-time packaging. Attached Figure Description

[0015] Figure 1 A schematic diagram of the framework of a high-speed digital processing micro-module; Figure 2 This is a schematic diagram of a structure in which five bare DDR dies are stacked in a V-shape staggered manner on a packaging substrate. Detailed Implementation

[0016] The following will be based on embodiments of the present invention. Figure 1 and Figure 2 The technical solutions in the embodiments of the present invention will be described in detail below.

[0017] like Figure 1 The diagram shows a framework schematic of a high-speed digital processing micro-module. This micro-module integrates a CPU, firmware Flash, m DDR modules, and m LDO power supplies on a packaging substrate, improving integration and simplifying power supply design. At the same time, it greatly improves the yield of finished chips by utilizing the first-stage aging of the DDR module pre-packaged and the second-stage aging after system-level packaging.

[0018] In this embodiment, each DDR module is stacked and packaged using multiple bare DDR dies. Simultaneously, the capacity and interface width of each DDR module are controlled to meet the single-rank drive requirements of the corresponding DDR controller in the CPU. By stacking multiple bare dies, the storage capacity and bandwidth of a single module can be increased, while ensuring that the pre-packaged DDR module, as a standardized single-rank component, can be directly matched with a single controller of the CPU, simplifying system integration design.

[0019] like Figure 2 The diagram shows a V-shaped staggered stack of five DDR bare dies on a packaging substrate. For stacking multiple DDR bare dies, a V-shaped staggered stack can be used and bonded to the packaging substrate. Taking five DDR bare dies (Die1-Die5) as an example, Die1 and Die2 can be led to the packaging substrate on the right side, and Die3-Die5 can be led to the packaging substrate on the left side. This staggered design facilitates the wiring operation of the bare die edges, improves the long-term working reliability of the module, optimizes the signal transmission path, and improves the yield of the packaging process.

[0020] It should be noted that each DDR module needs to undergo pre-packaging before co-packaging (SIP packaging) to screen for good products. Since the yield of the final chip is determined by components such as the CPU, firmware Flash, DDR module, and LDO power supply, the traditional method of packaging multiple DDR bare dies at once means that if one DDR bare die fails, the entire finished chip will be defective. Therefore, this solution constructs each DDR module in a V-shaped staggered stack and performs a preliminary first-stage aging test on a module-by-module basis to initially screen out qualified DDR modules. As a result, the yield of the final chip can be greatly improved during subsequent SIP packaging.

[0021] In this embodiment, a single CPU specifically includes m DDR controllers, 1 QSPI controller, and various high-speed / low-speed interface controllers. Each DDR controller is connected to each corresponding DDR module through the corresponding DDR interface. The firmware Flash is connected to the QSPI controller (for example, through the DQ[3:0] data line, CLK clock line, and CS# chip select signal for interconnection). Various high-speed / low-speed interface controllers fan out various high-speed / low-speed interface pads (PADs) through the substrate.

[0022] Each individual CPU, its corresponding DDR module, its individual firmware Flash, and its corresponding LDO power supply are all connected to the external power supply sockets in various high-speed / low-speed interface sockets via corresponding traces on the package substrate. For example, Figure 2The single CPU connected to multiple PADs in the lower right corner is labeled with VDDCORE_0VB, VDDCORE_DSP_0VB, etc. These labels indicate the positive power supply voltage of the CPU, the power supply voltage of the CPU core area, etc.

[0023] In this embodiment, each LDO power supply is located between each corresponding DDR module and the external power supply ball, and is used to convert the external power supply voltage of the external power supply ball into the termination voltage Vtt and reference voltage Vref required by each corresponding DDR module.

[0024] The various high-speed / low-speed interface controllers include at least: UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), LPC (Low Pin Count Interface), NAND (NAND Flash Memory), GPIO (General Purpose Input / Output), CAN (Controller Area Network), I2C (Integrated Circuit Interoperability), SRIO (Serial Fast I / O), PCIe (Peripheral Component Interconnect High-Speed ​​Bus Standard), and SDIO (Secure Digital Input / Output). It provides an extremely rich selection of peripheral interfaces, enabling this micromodule to flexibly adapt to various industry application scenarios as a core board. Furthermore, each CPU and its corresponding DDR module are connected to at least the following types of bus groups: DM (Data Line), DQS (Data Strobe), DQ (Data Mask), ADDR (Address Line), BA (Bank Address), and BG (Bank Group). All the key signals necessary for high-speed DDR are clearly defined, ensuring reliable transmission of data DM, DQS, DQ and command / address ADDR, BA, BG.

[0025] Combination Figure 2 As shown, the packaging substrate is constructed using a multi-layer substrate stacked from L1 to L6. Internally, the packaging substrate also incorporates inter-board traces to connect the signal or address lines of each DDR module to various high-speed / low-speed interface sockets, forming an effective signal path. These inter-board traces provide electrical connections and signal routing capabilities from the core device to external interfaces.

[0026] In this embodiment, a termination resistor is also provided on the packaging substrate. The termination resistor connects the inter-board traces and is used to force any signal of each DDR module to be distributed through the termination resistor, filter out noise, and then connect to the corresponding high-speed / low-speed interface ball.

[0027] Secondly, a layered packaging and screening method is proposed for processing the aforementioned high-speed digital processing micro-module. This method includes the following steps: S1. Stack and pre-package multiple DDR bare chips to form independent DDR modules. Perform first-level aging screening on each DDR module to select qualified DDR modules. S2. Divide the qualified DDR modules into multiple groups. Each group is installed together with the corresponding CPU, firmware Flash and each LDO power supply and electrically interconnected on the corresponding packaging substrate. Perform system-level packaging to form multiple high-speed digital processing micro-module semi-finished products. S3. Perform a second-stage aging and screening process to obtain the final high-speed digital processing micro-module: Perform a second-stage aging and screening process on multiple high-speed digital processing micro-module semi-finished products to select qualified high-speed digital processing micro-module finished products.

[0028] Taking an integrated package of 1 CPU die, 1 firmware Flash die, 1 LDO power supply, and 10 DDR dies as an example, assuming the yield rates after aging screening for a single CPU, Flash, LDO, and DDR are 60%, 95%, 98%, and 80%, respectively, the yield rates of the micro-module after one integrated packaging and aging screening versus layered packaging screening are 5.7% and 47.89%, respectively. The calculation process is shown in the table below: Table 1: Yield Prediction for First-Stage Integration Packaging

[0029] Table 2: Estimated Yield of Layered Packaging Screening in This Solution

[0030] In summary, this invention improves the integrated architecture of the micro-module by integrating the LDO power supply, which generates the termination voltage and reference voltage required for DDR, into the micro-module. Furthermore, it pre-packages and screens the stacked DDR modules for good products, and then further screens the system-level packages of devices such as CPU and Flash. This effectively eliminates defective products and overcomes the problem of low yield of finished chips in conventional one-time packaging, demonstrating significant progress.

[0031] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A high-speed digital processing micro-module, characterized in that, It includes a CPU, firmware Flash, m DDR modules and m LDO power supplies, all packaged together on the substrate; each DDR module is pre-packaged before co-packaging to screen for good products. The CPU includes m DDR controllers, 1 QSPI controller, and various high-speed / low-speed interface controllers. Each DDR controller is connected to each corresponding DDR module. The firmware Flash is connected to the QSPI controller. Various high-speed / low-speed interface controllers fan out various high-speed / low-speed interface balls through the substrate. The CPU, each DDR module, firmware Flash, and each LDO power supply are connected to the external power supply ball in various high-speed / low-speed interface balls through corresponding traces on the substrate. Each LDO power supply is located between each corresponding DDR module and the external power supply ball, and is used to convert the external power supply voltage of the external power supply ball into the termination voltage Vtt and reference voltage Vref required by each DDR module.

2. The high-speed digital processing micro-module according to claim 1, characterized in that, Each DDR module uses multiple bare DDR dies stacked and packaged. The capacity and interface width of each DDR module meet the single-rank drive requirements of the corresponding DDR controller in the CPU.

3. A high-speed digital processing micro-module according to claim 2, characterized in that, Multiple DDR bare cells are stacked in a V-shape and bonded to the substrate.

4. A high-speed digital processing micromodule according to claim 1, characterized in that, Various high-speed / low-speed interface controllers include at least UART, SPI, LPC, NAND, GPIO, CAN, I2C, SRIO, PCIe, and SDIO.

5. A high-speed digital processing micro-module according to claim 1, characterized in that, Each DDR module and CPU is connected to the following types of bus groups: DM, DQS, DQ, ADDR, BA, BG.

6. A high-speed digital processing micromodule according to claim 1, characterized in that, The substrate has built-in inter-board traces for connecting the signal lines or address lines of each DDR module to various high-speed / low-speed interface sockets.

7. A high-speed digital processing micromodule according to claim 6, characterized in that, The substrate is also equipped with termination resistors, which connect the inter-board traces to force any signal from each DDR module to pass through the termination resistors before being connected to the corresponding high-speed / low-speed interface ball.

8. A layered packaging and screening method for processing a high-speed digital processing micromodule as described in any one of claims 1 to 7, characterized in that, The method includes the following steps: S1. Stack and pre-package multiple DDR bare chips to form independent DDR modules. Perform first-level aging screening on each DDR module to select qualified DDR modules. S2. Divide the qualified DDR modules into multiple groups. Each group is installed together with the corresponding CPU, firmware Flash and each LDO power supply and electrically interconnected on the corresponding packaging substrate. Perform system-level packaging to form multiple high-speed digital processing micro-module semi-finished products. S3. Perform a second-stage aging and screening process to obtain the final high-speed digital processing micro-module: Perform a second-stage aging and screening process on multiple high-speed digital processing micro-module semi-finished products to select qualified high-speed digital processing micro-module finished products.

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