3D stack dram co-package method with vision chip

Abstract

The application discloses a 3D stack DRAM and visual chip co-encapsulation method, which comprises the following steps: firstly, TSV etching and metallization processing, CMP polishing and micro-bump preparation are performed on a logic chip and a DRAM chip; then, micro-lenses and copper pads are arranged on a CIS chip after polishing and cleaning; the logic chip and the DRAM chip are mixedly bonded and stacked, and EMC encapsulation is performed; precise alignment of the CIS chip is realized through hydrophilic-hydrophobic pattern induced self-alignment; three-dimensional integration is completed through low-temperature mixed bonding at 200-250 DEG C; subsequently, a light-transmitting protective layer is prepared, a heat dissipation channel is etched and a high-thermal-conductivity layer is deposited; an active heat dissipation system is constructed in combination with a MEMS liquid cooling chip; and finally, the stack is attached to an FPC board with a test circuit. The encapsulation body takes the FPC board as a carrier, three-dimensional stacking of CIS, DRAM and logic chips is realized, copper-copper interconnection is realized to achieve high-bandwidth transmission, and high-precision, high-efficiency and high-performance three-dimensional heterogeneous integration of the DRAM and the CIS is realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically a method for co-packaging 3D stacked DRAM and a vision chip (CIS, CMOS Image Sensor) based on TSV (Through Silicon Vis) and hybrid bonding technologies. This method is suitable for high-bandwidth, low-latency applications such as AI vision processing, autonomous driving, and edge computing, aiming to solve the interconnect bandwidth bottlenecks, heat dissipation problems, and size limitations in traditional packaging. Background Technology

[0002] With the surge in demand for AI vision processing, traditional 2D packaging technology faces significant challenges. For example, in high-speed image processing at 4K / 120fps and above, bandwidth requirements have exceeded 800GB / s, but 2D packaging is limited by planar interconnect constraints, leading to increased interconnect latency and power consumption. Furthermore, the separate packaging of DRAM and logic chips limits data transmission efficiency, while CIS chips require rapid caching of large amounts of data in high-speed processing, and traditional methods cannot effectively integrate DRAM as a temporary cache.

[0003] While existing 3D packaging technology can improve integration, it still has shortcomings: • TSV technology shortens the signal path through vertical interconnects, but traditional processes (such as Via-First and Via-Middle) face challenges in thermal stress and mechanical strength in heterogeneous chip integration.

[0004] • Hybrid bonding enables bumpless direct bonding, reducing the pitch to below 1μm, but it has extremely high requirements for bonding accuracy (≤0.1μm) and surface roughness (≤1nm), and its application in high-density DRAM stacks is not yet mature.

[0005] • Heat dissipation issues are prominent. For example, HBM's heat dissipation efficiency decreases when stacked in multiple layers, requiring the reliance on transitional technologies such as MR-MUF.

[0006] Industry trends indicate that while HBM4 plans to use hybrid bonding and HBM5 expands to a 20-layer stack, neither has resolved the heterogeneous integration issue of DRAM and CIS. Existing patents primarily focus on DRAM and logic chip integration, lacking optimized solutions for co-packaging DRAM and CIS. Summary of the Invention

[0007] The purpose of this invention is to provide a method for co-packaging 3D stacked DRAM and vision chip. Through TSV, microdroplet-driven self-assembly, low-temperature hybrid bonding and thermal management technology, high-precision, high-efficiency and high-performance three-dimensional heterogeneous integration of DRAM and CIS is achieved.

[0008] The objective of this invention is achieved through the following technical solution: A method for co-packaging 3D stacked DRAM and a vision chip includes the following steps: Step 1: Modify the logic chip: Through silicon vias with a diameter of 1-5 micrometers are formed by etching with Bosch Process through deep reactive ion etching. The first signal pin is formed by filling with copper electroplating. The surface roughness of the logic chip is controlled to below 0.5nm by chemical mechanical polishing, and the first microbump is prepared to be electrically connected to the first signal pin. Step 2: Modify the DRAM chip: Through silicon vias with a diameter of 1-5 micrometers are formed by Bosch Process etching with deep reactive ion etching. The vias are then filled with copper electroplating to form the second signal pins. Chemical mechanical polishing is used to control the surface roughness of the DRAM chip to below 0.5 nm, and a second microbump electrically connected to the second signal pins is prepared. Step 3: Modify the CIS chip: Use chemical mechanical polishing to control the surface roughness of the CIS chip to below 0.5nm. After cleaning with oxygen plasma, set a microlens on one side of the photosensitive area and prepare a copper pad on the other side. Step 4: Set a first temporary substrate on the back of the logic chip, invert the DRAM chip to make the second microbump and the first microbump precisely aligned, and use a hybrid bonding process to realize direct copper-copper interconnection to complete the three-dimensional vertical stacking of the logic chip and the DRAM chip. Step 5: Thin and grind the back of the DRAM chip to expose the second signal pin and prepare the third microbump. After removing the first temporary substrate, invert the chip stack and place it on the second temporary substrate. Thin and grind the back of the logic chip to expose the first signal pin and prepare the fourth microbump. Step 6: On the second temporary substrate, the DRAM chip and logic chip are packaged into an EMC package using epoxy molding compound. The fourth microbump is exposed by grinding. A hydrophilic pad matching the CIS chip is made on the upper surface of the EMC package. A hydrophobic photoresist is placed around the hydrophilic pad. After the hydrophilic pad is coated with water droplets, the CIS chip is placed. The self-alignment of the CIS chip is achieved by the difference between hydrophilic and hydrophobic surface energies. Step 7: Perform room temperature pre-bonding on the CIS chip, remove the peripheral hydrophobic dielectric photoresist, and complete the final hybrid bonding by hot pressing annealing in the temperature range of 200°C-250°C to achieve copper-copper atom interdiffusion and direct bonding of dielectric materials between the fourth microbump and the copper pad. Step 8: Use a high-transmittance material to cover and encapsulate the CIS chip to form a transparent material layer; Step 9: Deposit a silicon dioxide layer on the surface of the light-transmitting material layer, and form a vertically penetrating heat dissipation channel through photolithography and etching. Deposit a high thermal conductivity passivation layer on the inner wall of the heat dissipation channel and the exposed area of ​​the silicon dioxide layer. Step 10: Fix the tempered glass to the silicon dioxide layer by gold-silicon eutectic bonding, and bond the MEMS liquid-cooled chip to the upper end of the tempered glass by gold-silicon eutectic bonding, forming a closed heat dissipation cavity filled with coolant together with the heat dissipation channel. Step 11: Remove the second temporary substrate, attach the third microbump of the chip stack to the FPC board, prepare a solder ball array on the back of the FPC board, and set the test circuit on the front of the FPC board.

[0009] A high-bandwidth 3D stacked integrated chip package for AI vision processing is prepared by the above method. The package includes a flexible printed circuit board and a chip stack and a test circuit disposed thereon. The back of the FPC board is provided with a solder ball array, and the front is formed with a circuit pattern adapted to the third micro bump through redistribution layer technology. The chip stack consists of a CIS chip, a DRAM chip, and a logic chip stacked vertically in three dimensions. The CIS chip is located at the top with its photosensitive area facing upwards and is covered with a light-transmitting material layer. The logic chip is located at the bottom and is electrically connected to the FPC board. The chips in each layer are vertically electrically connected through copper-copper direct interconnects formed by hybrid bonding or through microbump structures. The chip stack integrates an active heat dissipation system, which includes a vertically penetrating heat dissipation channel, a high thermal conductivity passivation layer deposited on the inner wall of the heat dissipation channel, a reinforced glass bonded to a silicon dioxide layer, and a MEMS liquid-cooled chip bonded to the reinforced glass. The reinforced glass, the MEMS liquid-cooled chip, and the heat dissipation channel together form a closed heat dissipation cavity, which is filled with coolant. The test circuit is electrically connected to the FPC board circuitry and is used to perform electrical testing on the vertical interconnects of the three-dimensional stacked structure and to achieve online repair and functional reconstruction of failed links.

[0010] As a further improvement of the present invention, in steps 1 and 2, the aspect ratio of the through-silicon via is 10:1.

[0011] As a further improvement of the present invention, in step 7, the room temperature pre-bonding relies on the hydrogen bonding between the hydroxyl groups on the back of the CIS chip and the surface of the hydrophilic pad to achieve chip adsorption and fixation; the bonding conditions of the hot-press annealing are 225°C temperature and 30kN pressure for 60 minutes to form gapless copper-copper bonds and dielectric-dielectric bonds.

[0012] As a further improvement of the present invention, in step 6, the hydrophilic pad is made by photolithography, first coating a photoresist, then exposing it with a mask and developing it to form a pattern, and then depositing or processing it to form a hydrophilic surface; the hydrophobic photoresist is a fluorinated polymer, the aqueous droplets are deionized water, and the droplet distribution is achieved by micro-dispensing technology.

[0013] As a further improvement of the present invention, in step 8, the light-transmitting material layer is a low-refractive-index optical adhesive, selected from epoxy resin, silicone or acrylate UV-curable adhesive.

[0014] As a further improvement of the present invention, in step 9, the silicon dioxide layer is prepared by plasma-enhanced chemical vapor deposition, and the pattern avoids the photosensitive area above the CIS chip; the high thermal conductivity passivation layer is a diamond coating or graphene.

[0015] As a further improvement of the present invention, in step 11, the test circuit is an independent test chip or a functional circuit integrated in the FPC board (10) circuit, and its repair mechanism is to fuse / program redundant interconnection lines or dynamically reconstruct the signal path through a reconfigurable switch network.

[0016] As a further improvement of the present invention, the chips in each layer of the chip stack are integrated in a high-density, short-distance three-dimensional manner through through-silicon vias, hybrid bonding and rewiring technologies to achieve sensing, storage and computing units.

[0017] The above technical solution has the following beneficial effects: 1. By adopting an interconnect structure of through silicon via (TSV) + hybrid bonding + microbumps, direct copper-copper interconnects and bumpless hybrid bonding can be achieved, reducing the interconnect pitch to less than 1 micrometer (or even less than 0.5 micrometers). Compared with traditional 2.5D packaging, the interconnect bandwidth is increased by more than 10 times, the data transmission latency is reduced to the nanosecond level, and the overall interconnect resistance and transmission power consumption are reduced.

[0018] 2. Employing a hydrophilic-hydrophobic pattern-induced self-assembly alignment technology, this technology utilizes surface energy differences to achieve synchronous self-alignment of thousands of CIS chips of different sizes within one second, with an alignment accuracy better than ±0.5 micrometers. This avoids the speed limitations and alignment errors of traditional processes, significantly improving the efficiency and accuracy of multi-chip packaging.

[0019] 3. Design a low-temperature hot-pressing annealing bonding process at 200°C-250°C to effectively protect temperature-sensitive optical structures such as microlenses and color filters of the CIS chip from high-temperature damage while satisfying atomic diffusion and chemical bond formation.

[0020] 4. An active heat dissipation system is integrated, consisting of a vertical heat dissipation channel, a high thermal conductivity passivation layer, a MEMS liquid-cooled chip, and reinforced glass. The theoretical heat dissipation efficiency of the MEMS liquid-cooled chip reaches 3000W / cm², which can efficiently conduct and remove heat from the chip stack, solving the thermal management problem of high-density 3D stacking and ensuring the reliable operation of the package under high power density.

[0021] 5. By integrating test circuitry on the FPC board, electrical tests can be performed on the vertical interconnects of 3D stacked products. Online repair and functional reconstruction of failed links can be achieved by fusing redundant lines and reconstructing signal paths, significantly improving the test yield and long-term reliability of complex 3D stacked packaged products.

[0022] 6. Achieve high-density, short-distance three-dimensional vertical stacking of CIS vision chips, DRAM memory chips, and logic chips. Combined with system-level packaging of flexible printed circuit boards, the package size is reduced. At the same time, through the integrated integration of sensing, storage, and computing units, it adapts to the comprehensive requirements of AI vision processing in terms of bandwidth, power consumption, and size.

[0023] 7. The chips are standardized by using chemical mechanical polishing and deep reactive ion etching processes. Combined with epoxy molding compound (EMC) encapsulation and light-transmitting material layer protection, the mechanical strength, electrical insulation and environmental adaptability of the package are improved, while ensuring the smooth light path of the photosensitive area of ​​the CIS chip. Attached Figure Description

[0024] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0025] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0026] Figure 1 This is a schematic diagram of the process provided by the present invention.

[0027] Figure 2 This is a schematic diagram of the product structure prepared in step 1.

[0028] Figure 3 A schematic diagram of the product structure prepared in step 2.

[0029] Figure 4 A schematic diagram of the product structure prepared in step 3.

[0030] Figure 5 A schematic diagram of the product structure prepared in step 4.

[0031] Figure 6 A schematic diagram of the product structure prepared in step 5.

[0032] Figure 7 A schematic diagram of the product structure prepared in step 6.

[0033] Figure 8 A schematic diagram of the product structure prepared in step 8.

[0034] Figure 9 A schematic diagram of the product structure prepared in step 9.

[0035] Figure 10 A schematic diagram of the product structure prepared in step 10.

[0036] Figure 11 This is a schematic diagram of the structure of the finished product prepared in step 11.

[0037] In the picture: 1. Logic chip; 11. First signal pin; 12. First microbump; 13. Fourth microbump; 2. DRAM chip; 21. Second signal pin; 22. Second microbump; 23. Third microbump; 3. CIS chip; 31. Glass substrate; 32. Solder pads; 41. First temporary substrate; 42. Second temporary substrate; 5. Package; 6. Hydrophobic photoresist; 7. Transparent material layer; 8. SiO2 layer; 9. Heat dissipation channel; 91. Passivation layer; 92. Tempered glass; 93. MEMS liquid-cooled chip; 10. FPC board; 100. Test circuit. Detailed Implementation

[0038] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0039] like Figure 1 As shown, a method for co-packaging 3D stacked DRAM and a vision chip includes the following steps: Step 1: Modify Logic Chip 1: First, accurately locate the processing area according to the wiring diagram provided by the chip manufacturer. Use Bosch Process with Deep Reactive Ion Etching (DRIE) technology to perform through-silicon via (TSV) etching on the surface of logic chip 1. The aperture range of the etched holes is controlled between 1 and 5 micrometers to accommodate different interconnection requirements. Then, fill the etched holes with copper electroplating to complete the metallization process, thereby forming the first signal pin 11 that can directly transmit signals. After electroplating, chemical mechanical polishing (CMP) is used to control the surface roughness (RMS) of logic chip 1 to below 0.5 nm to ensure sufficient surface flatness. Next, fabricate the first microbump 12 (μ-bump) on the surface of logic chip 1, which is electrically connected to the first signal pin 11, for electrical interconnection during subsequent chip stacking. The fabricated product structure is as follows: Figure 2 As shown.

[0040] Step 2: Modifying DRAM Chip (Memory Chip) 2: First, the processing area is precisely located according to the wiring diagram provided by the chip manufacturer. Using the Bosch process in deep reactive ion etching technology, through-silicon vias (TSVs) are etched on the surface of DRAM chip 2. The aperture range of the etched holes is controlled between 1 and 5 micrometers to accommodate different interconnection requirements. Next, copper electroplating is used to fill the etched holes, completing the metallization process and forming the second signal pin 21 that can directly transmit signals. After electroplating, chemical mechanical polishing (CMP) is used to control the surface roughness (RMS) of DRAM chip 2 to below 0.5 nm to ensure sufficient surface flatness. Then, a second microbump 22 (μ-bump) electrically connected to the second signal pin 21 is fabricated on the surface of DRAM chip 2 for electrical interconnection during subsequent chip stacking. Through the above steps, DRAM chip 2 is modified to have a structure with TSV copper pillars and bumps, laying the technical foundation for three-dimensional stacking and co-packaging with logic chip 1 and vision chip. The fabricated product structure is as follows: Figure 3 As shown.

[0041] Step 3: Modifying the CIS chip (vision chip) 3: First, chemical mechanical polishing (CMP) is used to control the surface roughness (RMS) of the CIS chip 3 to below 0.5 nm to obtain a flat surface. Subsequently, the CIS chip 3 is cleaned with oxygen plasma to remove surface contaminants and improve its surface activity, which is beneficial for subsequent processes. A microlens 31 is placed on one side of the photosensitive area of ​​the CIS chip 3 to converge incident light. On the other side of the CIS chip 3 opposite to the photosensitive area, several copper pads 32 are fabricated for signal transmission. These copper pads 32 serve as external electrical connection points, providing an interface for electrical interconnection between the chip and other components in the stacked package. The fabricated product structure is as follows... Figure 4 As shown.

[0042] Step 4: First, a first temporary substrate 41 is formed on the back of the logic chip 1 to provide support. This temporary substrate can be made of glass, silicon, or other materials with sufficient rigidity and heat resistance. Next, the DRAM chip 2 is inverted so that its second microbump 22 faces downwards and is precisely aligned with the first microbump 12 on the front of the logic chip 1. Subsequently, a hybrid bonding process is used to achieve direct copper-copper interconnection between the first microbump 12 and the second microbump 22. Direct copper-copper bonding can form a low-resistance, high-reliability interconnect interface, which helps to reduce overall interconnect resistance and transmission power consumption, and improve heat dissipation efficiency. This step completes the three-dimensional vertical stacking and electrical connection between the logic chip 1 and the DRAM chip 2, and the resulting product structure is shown below. Figure 5 As shown.

[0043] Step 5: First, the back side of the bonded DRAM chip 2 is thinned and polished to expose one end of the integrated second signal pin 21. Then, the exposed end face of the second signal pin 21 is cleaned to remove residual dielectric or contaminants. After cleaning, a third microbump 23 electrically connected to the second signal pin 21 is fabricated on this end face.

[0044] Next, the first temporary substrate 41 supporting the back of the logic chip 1 is removed. The entire chip stack is inverted so that the newly fabricated third microbump 23 faces downwards, and placed on the second temporary substrate 42. The second temporary substrate 42 can be made of silicon, glass, or organic materials. Its design ensures that when the combination of DRAM chip 2 and logic chip 1 is placed on it, sufficient space is left around the substrate, providing the necessary operating area for subsequent molding compound filling, heat dissipation structure installation, or other packaging processes, which is beneficial for optimizing the heat dissipation and reliability of the overall package.

[0045] Next, a similar thinning and grinding process is performed on the back side of logic chip 1 to expose one end of the first signal pin 11 inside. After the same or similar cleaning process, a fourth microbump 13 electrically connected to the first signal pin 11 is fabricated on this end face. At this point, bump structures for vertical interconnection are fabricated on both sides of the stack, preparing for further three-dimensional integration with the vision chip. The fabricated product structure is shown below. Figure 6 As shown.

[0046] Step 6: First, a packaging operation is performed on the second temporary substrate 42 to encapsulate the combination of DRAM chip 2 and logic chip 1 within the EMC package 5. The EMC package 5 is typically made of epoxy molding compound and formed by compression molding to provide mechanical protection and electrical insulation. After packaging, the upper surface of the EMC package 5 is ground to expose the fourth microbump 13 on the back of the logic chip 1, facilitating subsequent connection.

[0047] Subsequently, a hydrophilic pad with a specific pattern is fabricated on the upper surface of the EMC package 5 using photolithography. Specifically, photoresist is first coated, and the pattern is formed by exposure and development using a mask, followed by deposition or processing to form a hydrophilic surface. The hydrophilic pad is surrounded by a hydrophobic photoresist 6, which can be a fluorinated polymer or other low surface energy material to limit the diffusion of aqueous droplets. The area containing the hydrophilic pad is defined as the hydrophilic region, and its pattern shape and size match those of the CIS chip 3. Within this region, the position of the fourth microbump 13 precisely corresponds to the position of the copper pad 32 on the CIS chip 3 to ensure the accuracy of electrical interconnection.

[0048] Next, micro-level aqueous droplets are precisely distributed onto the hydrophilic pad. Droplet distribution can be achieved using micro-dispensing technology. Then, a large number of CIS chips 3 are placed on the hydrophilic region. Due to the surface energy difference between the hydrophilic and hydrophobic regions, the aqueous droplets spread in the hydrophilic region and generate surface tension. When the CIS chips 3 are placed, the droplets' "restoring force" drives the chips to automatically slide to the center position of the preset hydrophilic pattern. This self-alignment process can drive thousands of CIS chips of different sizes to achieve synchronous alignment in a short time (e.g., within 1 second), with an alignment accuracy better than ±0.5 micrometers. The above-mentioned hydrophilic automatic calibration technology can be found in publicly available literature in the relevant field, such as that cited by engineers Ray Yarema et al. at the Fermi National Accelerator Laboratory (Fermi Lab) when introducing the application of 3D integrated circuit technology in high-energy physics experiments.

[0049] Using the above method, self-assembly induced by hydrophilic-hydrophobic patterns enables large-scale, high-efficiency multi-chip alignment, avoiding the speed limitations and alignment errors of traditional pick-and-place processes, and significantly improving packaging efficiency and accuracy. This step provides a precise pre-alignment basis for the subsequent bonding and interconnection of the CIS chip 3 with the logic chip 1 and DRAM chip 2 stack, and the resulting product structure is shown below. Figure 7 As shown.

[0050] Step 7: After completing the self-assembly alignment of the CIS chip, pre-bonding is first performed at room temperature. This process relies on the hydrogen bonds formed between the hydroxyl groups on the back of the CIS chip and the surface of the hydrophilic pad to generate intermolecular attraction, thereby achieving the initial adsorption and fixation of the chip.

[0051] Subsequently, the peripheral hydrophobic photoresist 6 is removed. Then, thermo-press annealing is performed in a lower temperature range of 200°C to 250°C to complete the final bonding. This temperature range is selected to provide sufficient energy to drive atomic diffusion and chemical bond formation, while avoiding performance degradation or damage to temperature-sensitive optical structures such as the microlens 31 and color filters on the CIS chip due to high temperatures.

[0052] During the hot-press annealing process, copper-copper atomic interdiffusion occurs between the fourth microbump 13 on the back of logic chip 1 and the copper pad 32 on CIS chip 3, while the surrounding dielectric material (such as silicon dioxide) also undergoes direct bonding. This process forms a bumpless hybrid bonding interface, realizing direct interconnection between copper and dielectric materials.

[0053] This bumpless structure enables a significant reduction in interconnect pitch, for example, to less than 1 micrometer, thereby integrating more vertical interconnect points within a unit area. This greatly improves the bandwidth of inter-chip data transmission while effectively reducing signal transmission latency and interconnect power consumption. This step ultimately completes the high-density, high-performance three-dimensional integration of CIS chip 3 with the underlying chip stack.

[0054] Step 8: After the CIS chip 3 is installed in place using the aforementioned bonding process, its photosensitive area faces upwards. Subsequently, a light-transmitting material layer 7 is formed by covering and encapsulating the CIS chip 3 with a material having high light transmittance. This light-transmitting material must allow imaging light to effectively pass through and reach the photosensitive area; its light transmittance can be comparable to that of glass. Low-refractive-index optical adhesives, such as epoxy resin, silicone, or acrylate UV-curable adhesives, are typically used. After curing, the light-transmitting material layer 7 provides reliable physical protection, mechanical support, and environmental isolation for the underlying CIS chip 3 and its interconnect structure, while ensuring unobstructed light paths above it. The final structure of the completed product is shown below. Figure 8 As shown.

[0055] Step 9: First, a silicon dioxide (SiO2) layer 8 is deposited on the surface of the light-transmitting material layer 7 using a plasma-enhanced chemical vapor deposition process. The pattern of the silicon dioxide layer 8 is designed to avoid the photosensitive area above the CIS chip 3 to ensure unobstructed light transmission.

[0056] Next, photoresist is coated on the surface of the silicon dioxide layer 8, and the pattern of the area to be etched is defined through exposure and development processes. Subsequently, using the photoresist as a mask, anisotropic etching is performed on the silicon dioxide layer 8, the underlying light-transmitting material layer 7, and the EMC package 5 to form a vertically penetrating heat dissipation channel 9. This etching process can employ reactive ion etching, deep silicon etching, or other dry etching techniques capable of achieving high aspect ratio structures.

[0057] Finally, a passivation layer 91 composed of a high thermal conductivity material is deposited on the inner wall of the heat dissipation channel 9 and the exposed area of ​​the silicon dioxide layer 8. The high thermal conductivity material can be diamond coating or graphene, etc. This passivation layer 91 serves two purposes: firstly, it provides insulation and protection; secondly, it efficiently conducts the heat generated inside the chip stack to the heat dissipation channel through a high thermal conductivity path, improving the overall heat dissipation performance and reliability of the package. The resulting product structure is shown below. Figure 9 As shown.

[0058] Step 10: First, the tempered glass 92 is fixed to the silicon dioxide layer 8 surrounding the heat dissipation channel 9 using a gold-silicon eutectic bonding process. The tempered glass 92 has an "L"-shaped structure to enclose the side walls and top cover of the heat dissipation cavity.

[0059] Next, the MEMS liquid-cooled chip 93 is bonded to the upper end of the reinforced glass 92 using a gold-silicon eutectic bonding process. The MEMS liquid-cooled chip 93, the reinforced glass 92, and the inner wall of the heat dissipation channel 9 together form a closed heat dissipation cavity filled with coolant. In this solution, the MEMS liquid-cooled chip 93 is based on a piezoelectric micropump driving the coolant, utilizing the inverse piezoelectric effect to generate unidirectional liquid flow, forming ultra-low power consumption and ultra-quiet active heat dissipation. Its structure includes a piezoelectric micropump, a liquid-cooled film integrating microchannels and coolant, and a liquid-cooled driving chip. It achieves the cooling effect through phase change, with a theoretical heat dissipation efficiency of 3000W / cm² and a power consumption of only 1W / cm². The overall size is in the millimeter range, suitable for the needs of high-density three-dimensional stacked packaging.

[0060] In use, the enclosed heat dissipation cavity and the internal high thermal conductivity passivation layer 91 work together to rapidly conduct the heat generated by the chip stack to the coolant, and then remove the heat through the flow and phase change of the liquid, thus achieving efficient and quiet heat dissipation. This step ultimately completes the chip stack with integrated active cooling function, and the fabricated product structure is as follows. Figure 10 As shown.

[0061] Step 11: First, remove the second temporary substrate 42, which serves as a temporary carrier. Then, mount the third microbump 23, which is exposed on the back of the chip stack, onto the flexible printed circuit board (FPC) 10. The FPC 10 serves as the final packaging carrier and system interconnect board, and its front side is formed with fine circuit patterns through redistribution layer technology to accommodate the layout of the third microbump 23.

[0062] On the back of the FPC board 10, a solder ball array is formed through a ball-planting process, which serves as the input / output interface for surface mounting of the package with the external circuit board.

[0063] A test circuit 100 is also provided on the front side of the FPC board 10. This test circuit can be a standalone test chip or a specific functional circuit integrated into the circuitry of the FPC board 10. Its function is to perform electrical testing on the vertical interconnects (such as interconnects via microbumps or through-silicon vias) between chips in the three-dimensional stacked structure. When failures such as open circuits, short circuits, or performance drift are detected, the test circuit can trigger a built-in repair mechanism. For example, by bypassing failed physical connections through fuses or programmed redundant interconnects, or by dynamically reconstructing signal paths through a reconfigurable switching network, online repair and functional reconfiguration of interconnects can be achieved. This design significantly improves the final test yield and long-term reliability of complex three-dimensional stacked packaged products. The final chip stack structure after fabrication is shown below. Figure 11 As shown.

[0064] like Figure 11 As shown, a high-bandwidth 3D stacked integrated chip package for AI vision processing is fabricated using the method described above. The package includes a flexible printed circuit board (PC) 10 fabricated using rewiring technology. The FPC 10 serves as the system-in-package carrier, with a test circuit 100 and a chip stack disposed on its front side, both electrically connected to the circuitry on the FPC 10. The test circuit 100 is used to test the stacked interconnects and enables dynamic repair and functional reconfiguration of failed links, thereby improving product yield and reliability. A solder ball array is fabricated on the back side of the FPC 10, serving as an input / output interface for surface mount interconnection between the package and external system circuitry.

[0065] The chip stack is the core functional component, comprising a CIS chip 3, a DRAM chip 2, and a logic chip 1 stacked vertically in three dimensions. The CIS chip 3 is located on top, with its photosensitive area facing upwards and sealed by a light-transmitting material layer 7; the logic chip 1 is located at the bottom and connected to the FPC board 10. The chips are directly interconnected via copper-copper bonding using a hybrid bonding process, or through micro-bump structures to achieve vertical electrical connections and high-bandwidth signal transmission. The chip stack integrates an active cooling system consisting of a vertical heat dissipation channel 9, a high thermal conductivity passivation layer 91, and a closed cavity formed by a MEMS liquid-cooled chip 93 and reinforced glass 92, to address the thermal management challenges of three-dimensional integration. This chip stack achieves high-density, short-distance three-dimensional integration of sensing, storage, and computing units through through-silicon vias, hybrid bonding, and redistribution technologies to meet the stringent requirements of high-performance AI vision processing in terms of bandwidth, power consumption, and size. Example

[0066] A high-bandwidth 3D stacked integrated chip package for AI vision processing is fabricated using the aforementioned method. The logic chip 1, DRAM chip 2, and CIS chip 3 can be manufactured using a 12-inch wafer to achieve greater integration economy. On the logic chip 1 and DRAM chip 2, through-silicon vias (TSVs) formed by deep reactive ion etching have a diameter of 3 micrometers and an aspect ratio of approximately 10:1.

[0067] A hydrophilic pad, for example, with a diameter of 50 micrometers, is fabricated on the EMC package 5. The amount of liquid droplet distributed on each hydrophilic pad is, for example, 5 picoliters of deionized water. In the low-temperature hybrid bonding process, the bonding conditions are, for example, hot-press annealing at 225°C and 30 kN for 60 minutes. These conditions allow for the formation of void-free copper-copper and dielectric-dielectric bonds. Through this process, the interconnect pitch can reach 0.8 micrometers, and can even be further reduced to below 0.5 micrometers. The heat dissipation channel 9 formed in step 9 has a cross-sectional dimension of, for example, 100 μm x 100 μm. Other steps are the same as described above. Products prepared using this method can achieve more than 10 times higher interconnect bandwidth and reduce data transmission latency to the nanosecond level compared to conventional 2.5D packages using interposers or silicon interposers. Simultaneously, the integrated high-efficiency active cooling system ensures reliable operation under high power density.

[0068] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0069] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for co-packaging 3D stacked DRAM and a vision chip, characterized in that, Includes the following steps: Step 1: Modify the logic chip: Through silicon vias with a diameter of 1-5 micrometers are formed by etching with Bosch Process through deep reactive ion etching. The first signal pin is formed by filling with copper electroplating. The surface roughness of the logic chip is controlled to below 0.5nm by chemical mechanical polishing, and the first microbump is prepared to be electrically connected to the first signal pin. Step 2: Modify the DRAM chip: Through silicon vias with a diameter of 1-5 micrometers are formed by Bosch Process etching with deep reactive ion etching. The vias are then filled with copper electroplating to form the second signal pins. Chemical mechanical polishing is used to control the surface roughness of the DRAM chip to below 0.5 nm, and a second microbump electrically connected to the second signal pins is prepared. Step 3: Modify the CIS chip: Use chemical mechanical polishing to control the surface roughness of the CIS chip to below 0.5nm. After cleaning with oxygen plasma, set a microlens on one side of the photosensitive area and prepare a copper pad on the other side. Step 4: Set a first temporary substrate on the back of the logic chip, invert the DRAM chip to make the second microbump and the first microbump precisely aligned, and use a hybrid bonding process to realize direct copper-copper interconnection to complete the three-dimensional vertical stacking of the logic chip and the DRAM chip. Step 5: Thin and grind the back of the DRAM chip to expose the second signal pin and prepare the third microbump. After removing the first temporary substrate, invert the chip stack and place it on the second temporary substrate. Thin and grind the back of the logic chip to expose the first signal pin and prepare the fourth microbump. Step 6: On the second temporary substrate, the DRAM chip and logic chip are packaged into an EMC package using epoxy molding compound. The fourth microbump is exposed by grinding. A hydrophilic pad matching the CIS chip is made on the upper surface of the EMC package. A hydrophobic photoresist is placed around the hydrophilic pad. After the hydrophilic pad is coated with water droplets, the CIS chip is placed. The self-alignment of the CIS chip is achieved by the difference between hydrophilic and hydrophobic surface energies. Step 7: Perform room temperature pre-bonding on the CIS chip, remove the peripheral hydrophobic dielectric photoresist, and complete the final hybrid bonding by hot pressing annealing in the temperature range of 200°C-250°C to achieve copper-copper atom interdiffusion and direct bonding of dielectric materials between the fourth microbump and the copper pad. Step 8: Use a high-transmittance material to cover and encapsulate the CIS chip to form a transparent material layer; Step 9: Deposit a silicon dioxide layer on the surface of the light-transmitting material layer, and form a vertically penetrating heat dissipation channel through photolithography and etching. Deposit a high thermal conductivity passivation layer on the inner wall of the heat dissipation channel and the exposed area of ​​the silicon dioxide layer. Step 10: Fix the tempered glass to the silicon dioxide layer by gold-silicon eutectic bonding, and bond the MEMS liquid-cooled chip to the upper end of the tempered glass by gold-silicon eutectic bonding, forming a closed heat dissipation cavity filled with coolant together with the heat dissipation channel. Step 11: Remove the second temporary substrate, attach the third microbump of the chip stack to the FPC board, prepare a solder ball array on the back of the FPC board, and set the test circuit on the front of the FPC board.

2. A high-bandwidth 3D stacked integrated chip package for AI vision processing, characterized in that, The package is prepared by the co-packaging method of 3D stacked DRAM and vision chip as described in claim 1, wherein the package includes a flexible printed circuit board and a chip stack and a test circuit disposed thereon; The back of the FPC board is provided with a solder ball array, and the front is formed with a circuit pattern adapted to the third micro bump through redistribution layer technology. The chip stack consists of a CIS chip, a DRAM chip, and a logic chip stacked vertically in three dimensions. The CIS chip is located at the top with its photosensitive area facing upwards and is covered with a light-transmitting material layer. The logic chip is located at the bottom and is electrically connected to the FPC board. The chips in each layer are vertically electrically connected through copper-copper direct interconnects formed by hybrid bonding or through microbump structures. The chip stack integrates an active heat dissipation system, which includes a vertically penetrating heat dissipation channel, a high thermal conductivity passivation layer deposited on the inner wall of the heat dissipation channel, a reinforced glass bonded to a silicon dioxide layer, and a MEMS liquid-cooled chip bonded to the reinforced glass. The reinforced glass, the MEMS liquid-cooled chip, and the heat dissipation channel together form a closed heat dissipation cavity, which is filled with coolant. The test circuit is electrically connected to the FPC board circuitry and is used to perform electrical testing on the vertical interconnects of the three-dimensional stacked structure and to achieve online repair and functional reconstruction of failed links.

3. The method for co-packaging 3D stacked DRAM and vision chip according to claim 1, characterized in that, In steps 1 and 2, the aspect ratio of the through-silicon via is 10:

1.

4. The method for co-packaging 3D stacked DRAM and vision chip according to claim 1, characterized in that, In step 7, the room temperature pre-bonding relies on the hydrogen bonding between the hydroxyl groups on the back of the CIS chip and the surface of the hydrophilic pad to achieve chip adsorption and fixation; the bonding conditions of the hot-press annealing are 225°C temperature and 30kN pressure for 60 minutes to form gapless copper-copper bonds and dielectric-dielectric bonds.

5. The method for co-packaging 3D stacked DRAM and vision chip according to claim 1, characterized in that, In step 6, the hydrophilic pad is fabricated using photolithography. First, photoresist is coated, exposed through a mask, and developed to form a pattern. Then, a hydrophilic surface is formed by deposition or processing. The hydrophobic photoresist is a fluorinated polymer, and the aqueous droplets are deionized water. Droplet distribution is achieved using micro-dispensing technology.

6. The method for co-packaging 3D stacked DRAM and vision chip according to claim 1, characterized in that, In step 8, the light-transmitting material layer is a low-refractive-index optical adhesive, selected from epoxy resin, silicone or acrylate UV-curable adhesive.

7. The method for co-packaging 3D stacked DRAM and vision chip according to claim 1, characterized in that, In step 9, the silicon dioxide layer is prepared by plasma-enhanced chemical vapor deposition, and the pattern avoids the photosensitive area above the CIS chip; the high thermal conductivity passivation layer is a diamond coating or graphene.

8. The method for co-packaging 3D stacked DRAM and vision chip according to claim 1, characterized in that, In step 11, the test circuit is an independent test chip or a functional circuit integrated in the FPC board (10) circuit. Its repair mechanism is to fuse / program redundant interconnect lines or dynamically reconstruct the signal path through a reconfigurable switch network.

9. The high-bandwidth 3D stacked integrated chip package according to claim 2, characterized in that, The chip stack achieves high-density, short-distance three-dimensional integration of sensing, storage, and computing units between the various layers of chips through through-silicon vias, hybrid bonding, and rewiring technologies.

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