A power chip packaging structure and a preparation method thereof

Abstract

The application relates to the chip packaging technical field and discloses a power chip packaging structure and a preparation method thereof. The packaging structure comprises a first plastic sealing body, a first through hole and a second through hole arranged on the two sides respectively, a recess arranged at the middle position of the first plastic sealing body, and multiple openings arranged at the bottom of the recess in a spaced manner; a power chip is arranged in the recess, and a drain electrode of the power chip is located above the openings; a source electrode lead-out end is arranged in the first through hole and connected with a source electrode of the power chip; a gate electrode lead-out end is arranged in the second through hole and connected with a gate electrode of the power chip; a drain electrode lead-out end is arranged in the multiple openings and connected with the drain electrode of the power chip; and a second plastic sealing body is arranged on the first plastic sealing body and covers the first through hole and the second through hole. The application realizes the connection area of the drain electrode lead-out end by adopting the opening mode of the plastic sealing body at the bottom of the power chip, reduces the deposition and subsequent removal of the non-functional area copper, shortens the process flow, and reduces the cost.

Description

Technical Field

[0001] This application relates to the field of power chip packaging and testing technology, and in particular to a power chip packaging structure and its fabrication method. Background Technology

[0002] Power chips are responsible for controlling, converting, and amplifying high voltage and high current, including SiC (silicon carbide) power chips and GaN (gallium nitride) power chips. Among them, SiC power chips are wide-bandgap power devices with 4H-SiC single crystal as the substrate. Their core value lies in high voltage, high frequency, low loss, and high temperature resistance, making them a core upgrade solution for new energy vehicles, photovoltaics, fast charging, and industrial power supplies.

[0003] In high-current, high-switching-speed applications, SiC power chips often employ board-level packaging to build thick copper conductors on the substrate and achieve chip interconnection in order to reduce conduction losses and improve heat dissipation. Existing solutions typically use immersion copper / electroplating to thicken the entire copper layer before patterning and removing non-target areas to obtain the required thick traces and pads. The technical contradictions of the above-mentioned immersion copper / electroplating method are: on the one hand, thicker copper is needed to increase current carrying capacity and reduce resistance; on the other hand, the electroplating thickening and subsequent removal processes are time-consuming and costly, and a large amount of copper is wasted.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a power chip packaging structure and its preparation method, so as to reduce the manufacturing complexity of the power chip packaging structure and improve the material utilization rate.

[0006] The technical solution of this application is as follows: In a first aspect, this application provides a power chip packaging structure, which includes: A first molding body, wherein a first through hole and a second through hole are respectively provided on both sides of the first molding body, and a groove is provided in the middle position of the first molding body, wherein multiple openings are provided at intervals at the bottom of the groove; A power chip is disposed within the groove, with the drain of the power chip located above the opening; The source lead is disposed in the first through hole and connected to the source of the power chip; The gate lead is disposed in the second through hole and connected to the gate of the power chip; The drain lead is disposed within the plurality of openings and connected to the drain of the power chip; A second molding compound is disposed on the first molding compound and covers the first through hole and the second through hole.

[0007] In a further embodiment of this application, the plurality of openings are arranged side by side, and the openings are one or more of square openings and circular openings.

[0008] In a further embodiment of this application, the power chip has an inverted electrode-shaped protective structure on its source electrode, and the protective structure is connected to the source electrode lead-out terminal.

[0009] In a further provision of this application, the end of the source lead-out terminal connected to the source terminal is provided with a plurality of connection portions at intervals.

[0010] In a further embodiment of this application, the connection portion of the source lead-out terminal is connected to the source of the power chip by a copper wire; the gate of the power chip is connected to the gate lead-out terminal by a copper wire.

[0011] In a further embodiment of this application, both the source lead-out terminal and the protection structure are sintered copper structures.

[0012] In a further embodiment of this application, the source lead-out terminal has two connection portions.

[0013] In a further provision of this application, the plurality of openings are interconnected.

[0014] In a further provision of this application, the bottom of the openings on both sides of the first molding body has a stepped structure.

[0015] Secondly, this application also provides a method for fabricating a power chip packaging structure as described above, the method comprising the following steps: A first molding compound and a protective layer are provided, and the first molding compound is placed on the protective layer; A first through hole, a second through hole, a groove, and multiple openings are formed on the first molding body by laser drilling or stamping. The gate leads are plated and molded at the second through-hole, and the drain leads are plated and molded at the plurality of openings; wherein the gate leads are higher than the surface of the first molding compound. The power chip is mounted on the first plastic package; A source lead is sintered and formed in the first through hole, and the source lead is made to protrude above the surface of the first molding compound; A protective structure in the shape of an inverted electrode is sintered on the source electrode of the power chip; Wire bonding is performed between the protection structure and the source terminal, and between the gate of the power chip and the gate terminal; The power chip, the source terminal, and the gate terminal are further encapsulated.

[0016] This application provides a power chip packaging structure and its fabrication method. The power chip packaging structure includes: a first molding compound, with a first through-hole and a second through-hole respectively on both sides of the first molding compound, and a groove in the middle of the first molding compound, with multiple openings spaced apart at the bottom of the groove; a power chip disposed in the groove, with the drain of the power chip located above the openings; a source lead disposed in the first through-hole and connected to the source of the power chip; a gate lead disposed in the second through-hole and connected to the gate of the power chip; a drain lead disposed in the multiple openings and connected to the drain of the power chip; and a second molding compound disposed on the first molding compound and covering the first and second through-holes. This application reduces copper deposition and subsequent removal in non-functional areas by using openings in the molding compound at the bottom of the power chip to achieve controllable copper content, reducing material waste, and shortening the process flow, processing time, and cost. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the power chip packaging structure in one embodiment of this application.

[0019] Figure 2 This is a schematic flowchart of a method for fabricating a power chip packaging structure in one embodiment of this application.

[0020] Figure 3 This is a schematic diagram of the initial state of the molding compound in a power chip packaging structure fabrication method according to one embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the structure for preparing the first encapsulated body in one embodiment of this application.

[0022] Figure 5 This is a schematic diagram of the structure for fabricating the gate lead and drain lead in one embodiment of this application.

[0023] Figure 6 This is a schematic diagram of the structure of a power chip patch in one embodiment of this application.

[0024] Figure 7 This is a schematic diagram of the structure for fabricating the source lead-out terminal in one embodiment of this application.

[0025] Figure 8 This is a schematic diagram of the protective structure prepared in one embodiment of this application.

[0026] Figure 9 This is a schematic diagram of the wire bonding structure of a power chip in one embodiment of this application.

[0027] Figure 10 This is a schematic diagram of the encapsulated structure in one embodiment of this application.

[0028] The markings in the attached diagram are as follows: 1. First molding compound; 11. First through-hole; 12. Second through-hole; 13. Groove; 14. Opening; 2. Power chip; 21. Drain; 22. Gate; 23. Source; 3. Source lead-out; 31. Connector; 4. Gate lead-out; 5. Drain lead-out; 6. Second molding compound; 7. Protective structure; 8. Copper wire; 9. Stepped structure; 10. Protective layer. Detailed Implementation

[0029] This application provides a power chip packaging structure and its fabrication method. To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description is provided with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0030] In the implementation methods and scope of the claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of this application involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0031] It should be further understood that the term "comprising" as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any units and all combinations thereof of one or more associatedly listed items.

[0032] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0033] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0034] The inventors discovered that SiC (Silicon Carbide) is the core material of third-generation wide-bandgap semiconductors, boasting advantages such as high temperature resistance, high voltage resistance, high thermal conductivity, and low loss. It is a key upgrade material for power electronics, new energy, and radio frequency communications. SiC power chips are widely used in high-current, high-switching applications, such as main drive inverters for new energy vehicles, on-board chargers (OBCs), photovoltaic inverters, energy storage converters, industrial power supplies, and rail transit traction systems. In these systems, SiC devices can achieve higher switching frequencies and faster current rise / fall rates, significantly reducing switching losses, improving system efficiency, and reducing the size of magnetic components and filters, driving power systems towards higher power density, miniaturization, and lighter weight. Simultaneously, its high-temperature operating capability helps simplify heat dissipation design, improve overall system reliability, and enhance its ability to adapt to complex operating conditions.

[0035] Board-level packaging solutions are commonly used to construct thick copper conductors on a substrate and achieve chip interconnection. Current practices often involve thickening the entire copper layer through copper plating / immersion plating, followed by patterning to remove non-target areas to obtain the required thick traces and pads. The technical contradictions of this approach are: on the one hand, thicker copper is needed to increase current carrying capacity and reduce resistance; on the other hand, the electroplating thickening and subsequent removal processes are time-consuming and costly, and a large amount of copper is removed, resulting in material waste, and the processing window for thick copper is also limited; at the same time, in order to meet the requirements of high current output, current solutions often connect multiple thick copper lines in parallel and solder them to the same copper layer or the same busbar area. The technical dilemma lies in the following: while increasing the number of parallel conductors can reduce the equivalent resistance, the concentrated arrangement of conductors leads to an increase in loop area and parasitic coupling, exacerbating inter-line electromagnetic interference and uneven current distribution, and making dynamic voltage spikes and electromagnetic interference (EMI) problems more prominent. Furthermore, large-size SiC chips require a larger bottom soldering / mount area to reduce thermal resistance, but this increased area amplifies stress concentration caused by thermal expansion mismatch, easily leading to edge cracking, delamination, and thermal resistance degradation, resulting in decreased reliability. These contradictions make it difficult for existing board-level packaging to balance efficiency, cost, electrical performance, and reliability.

[0036] With the continuous improvement of electronic device performance and the shrinking of size, efficient packaging technology has become increasingly important. To meet these needs, efficient substrate manufacturing and chip wire bonding processes are indispensable. In traditional processes, immersion copper plating and coarse copper wire bonding are commonly used methods, but they have many shortcomings in practical applications.

[0037] To address the aforementioned technical problems, this application provides a power chip packaging structure and its fabrication method. This solution employs a multi-port parallel via structure as the current channel and connection interface in the interconnect / conductivity construction beneath the chip. This reduces the need for large-area copper plating thickening and subsequent removal and forming processes while meeting current carrying and conduction requirements, and also reduces the amount of copper used. The source electrode on the upper surface of the power chip features an inverted hat-shaped protective structure formed by sintered copper. This structure expands / stabilizes the wire bonding area and buffers the pressing and pulling loads during the bonding of thick copper wires, reducing the risk of mechanical damage to the pad metal layer. The current leads employ a branched bus / connection structure, with thick copper wires bonded to different branch positions. This makes the geometric path of the parallel branches more controllable, reducing inter-branch coupling and mutual interference of current paths.

[0038] Please also refer to Figure 1 and Figure 4 This application provides a preferred embodiment of a power chip packaging structure.

[0039] In some embodiments, such as Figure 1 and Figure 4As shown, this application provides a power chip packaging structure, which includes: a first molding compound 1, with a first through hole 11 and a second through hole 12 respectively provided on both sides of the first molding compound 1, and a groove 13 provided in the middle of the first molding compound 1, with a plurality of openings 14 spaced apart at the bottom of the groove 13; a power chip 2 disposed in the groove 13, with the drain 21 of the power chip 2 located above the opening 14; a source lead-out terminal 3 disposed in the first through hole 11 and connected to the source 23 of the power chip 2; a gate lead-out terminal 4 disposed in the second through hole 12 and connected to the gate 22 of the power chip 2; a drain lead-out terminal 5 disposed in the plurality of openings 14 and connected to the drain 21 of the power chip 2; and a second molding compound 6 disposed on the first molding compound 1 and covering the first through hole 11 and the second through hole 12.

[0040] In this embodiment, the power chip 2 can be a gallium nitride power chip or a silicon carbide power chip, etc. This embodiment uses a silicon carbide power chip for description. In the power chip 2 package provided in this application, the power chip 2 is encapsulated and protected by the first molding compound 1 and the second molding compound 6 to form a complete packaged device. The drain lead 5 is directly connected to the drain 21 of the power chip 2 and partially protrudes from the bottom of the first molding compound 1. The source lead 3 is connected to the source 23 of the power chip 2 by wire bonding and protrudes from the bottom of the first molding compound 1. The gate lead 4 is connected to the gate 22 of the power chip 2 by wire bonding and protrudes from the bottom of the first molding compound 1.

[0041] The groove 13 is located on the top of the first molding compound 1 and communicates with the opening 14. The power chip 2 can be partially accommodated within the groove 13. The drain lead 5 is formed within the opening 14 of the first molding compound 1 by electroplating copper. This reduces the connection area between the drain lead 5 and the drain 21 of the power chip 2, thereby reducing the area requiring copper plating, reducing material waste, reducing subsequent removal and forming processes, reducing copper usage, and shortening the process flow, processing time, and cost.

[0042] In the above technical solution, this application addresses the problems of numerous processes, low efficiency, high cost, and low copper utilization caused by the existing board-level packaging's reliance on copper plating / electroplating to thicken thick copper conductors, followed by removal and forming. It proposes a packaging implementation method that, while meeting the high-current interconnection requirements of SiC power chips, reduces copper plating-related operations and achieves controllable copper usage and material savings through a multi-aperture parallel hole structure on the bottom of the chip. This reduces manufacturing complexity and improves material utilization.

[0043] In some embodiments, such as Figure 1 and Figure 4 As shown, the plurality of openings are arranged side by side, and the opening 14 is one or more of a square opening and a circular opening.

[0044] In this embodiment, there are multiple openings 14, which are arranged side by side on the first molding compound 1 to form a multi-opening side-by-side hole structure. The shape of the openings 14 can be square or circular. Since there are multiple openings 14 on the first molding compound, the openings 14 can also be a combination of square and circular openings. In one implementation, the openings 14 are square, and the number of openings 14 is four.

[0045] Furthermore, the plurality of openings 14 are interconnected.

[0046] In this embodiment, the multiple openings 14 are interconnected and arranged side-by-side to form an opening array, i.e., a multi-opening side-by-side hole array structure. This opening array serves as a current channel and interface. The interconnection of the openings 14 can, to a certain extent, disperse the thermal load at the connection interface, reduce the tendency of edge stress concentration in large-area connections, help reduce the risk of failure such as cracking and delamination, and improve the overall reliability under thermal / power cycling conditions. The conductive structure formed by the opening array through the drain lead 5 can reduce the need for large-area copper plating thickening and subsequent removal and forming processes while meeting current carrying and conduction requirements, and also reduce the amount of copper used.

[0047] In some embodiments, such as Figure 1 As shown, the power chip 2 has an inverted electrode-shaped protective structure 7 on its source electrode 23, and the protective structure 7 is connected to the source electrode lead-out terminal 3.

[0048] It is important to understand that during the wire bonding process on the upper surface (S pole, i.e., source 23) of power chip 2, mechanical damage to the metal layer / pad can easily occur due to crimping, pulling force or local stress, which in turn leads to a decrease in connection reliability.

[0049] In this embodiment, the present application provides mechanical buffering and protection for the wire bonding area by setting an inverted hat-shaped protective structure of sintered copper layer / copper body in the S-polar region, thereby improving damage resistance and long-term connection stability. Specifically, the protective structure 7 is attached to the source electrode 23 of the power chip 2, which can be used to expand or stabilize the wire bonding area to buffer the pressing and pulling loads during the bonding process of the thick copper wire 8, reducing the risk of mechanical damage such as local stress concentration on the solder pads and metal layer peeling or cracking, and improving the stability and lifespan of the thick copper wire 8 interconnect.

[0050] In some embodiments, such as Figure 1As shown, the end of the source lead-out terminal 3 connected to the source terminal 23 is provided with a plurality of connection portions 31 at intervals.

[0051] In this embodiment, the source terminal 3 serves as a current output terminal and needs to carry a large current. Therefore, multiple thick copper wires 8 are usually used to connect it to the source terminal 23 of the power chip 2. In this embodiment, the protective layer 10 is electrically connected to the source terminal 23 of the power chip 2.

[0052] In this embodiment, a plurality of connection portions 31 are provided at intervals on the side where the source lead-out terminal 3 is connected to the power chip 2. Each connection portion 31 can connect a thick copper wire 8, so that the thick copper wire 8 is bonded to different branch positions of the source lead-out terminal 3. Compared with the prior art, which has problems such as increased circuit parasitic parameters, enhanced inter-line electromagnetic coupling, uneven dynamic current distribution, and mutual interference of current paths due to the concentrated welding of multiple thick copper wires 8 in the same copper foil / bus area, this application can make the geometric path of the parallel branch more controllable, thereby reducing the problems of inter-branch coupling and mutual interference of current paths, improving the repeatability and consistency of current paths, and improving the electrical performance stability under high di / dt (i.e., current change rate condition, which refers to the dynamic working state of the circuit where the current changes rapidly with time (large di / dt value), which is a core dynamic characteristic indicator in the fields of power electronics, motor drive, and power system) conditions. In one implementation, there are two connection portions 31, and the source lead-out terminal 3 is approximately Y-shaped. It should be noted that this application does not limit the number of the connecting parts 31. The number of the connecting parts 31 can be designed according to the number of thick copper wires 8 that need to be connected. It can have 5 connecting parts 31 or 7 connecting parts 31, etc.

[0053] In some embodiments, both the source lead-out terminal 3 and the protective structure 7 are sintered copper structures.

[0054] In this embodiment, the source lead 3, like the protective structure 7, is a conductive structure formed by sintered copper. Furthermore, since the source lead 3 needs to be significantly higher than the first molding compound, using sintered copper to fabricate the source lead 3 shortens the process flow compared to copper plating. Similarly, the protective structure 7 of the power chip 2 is also fabricated using sintered copper, which further shortens the process flow.

[0055] In some embodiments, such as Figure 1 and Figure 4 As shown, the bottom of the openings 14 on both sides of the first molding body 1 has a stepped structure 9.

[0056] In this embodiment, the first molding compound 1 has multiple openings 14, and the bottom of the two openings 14 on both sides has a stepped structure 9. In this way, when the drain lead 5 is prepared by copper plating, the contact area between the copper plating surface and the first molding compound 1 can be increased, thereby improving the bonding force between the first molding compound 1 and the drain lead 5 during service, and thus improving the reliability of the power chip package.

[0057] In some embodiments, such as Figure 2 As shown, this application also provides a method for fabricating a power chip packaging structure as described above, the method comprising the following steps: S100. A first molding compound and a protective layer are provided, and the first molding compound is placed on the protective layer; Specifically, please combine Figure 3 Before fabricating the power chip 2 package structure, materials need to be prepared in advance, such as the molding compound, copper materials for preparing sintered copper and copper plating, and coarse copper wire 8. In addition, before fabricating the first molding compound, a protective layer 10 needs to be pre-attached to the bottom of the pre-prepared molding compound. The protective layer 10 can serve as a temporary substrate to provide protection for subsequent drilling, copper plating and other operations.

[0058] S200. A first through hole, a second through hole, a groove 13 and multiple openings are formed on the first molding body by laser drilling or stamping. Specifically, please combine Figure 4 The through holes and openings on the first molding compound can be achieved by laser drilling or stamping. In this embodiment, laser drilling is used to obtain the first through hole 11, the second through hole 12, the groove 13, and a plurality of openings 14 arranged side by side.

[0059] The plurality of openings 14 are interconnected and arranged side by side to form an opening array, which serves as a current channel and interface. The interconnection of the openings 14 can, to a certain extent, disperse the thermal load at the connection interface, reduce the tendency for edge stress concentration in large-area connections, and help reduce the risk of failures such as cracking and delamination, thereby improving overall reliability under thermal / power cycling conditions. The conductive structure formed by the opening array at the drain lead 5 can reduce the need for large-area copper plating thickening and subsequent removal and forming processes while meeting current carrying and conduction requirements, and also reduce the amount of copper used.

[0060] In addition, the bottom of the two openings 14 on both sides has a stepped structure 9. In this way, when the drain lead 5 is made by copper plating, the contact area between the copper plating surface and the first molding compound can be increased, thereby improving the bonding force between the first molding compound and the drain lead 5 during service, and thus improving the reliability of the power chip 2 package.

[0061] S300, A gate lead is plated and molded at the second through-hole, and a drain lead is plated and molded at the plurality of openings; wherein the gate lead is higher than the surface of the first molding compound; Specifically, please combine Figure 5 After the first through-hole 11 and the second through-hole 12 are fabricated, the second through-hole 12 is filled with metal using copper plating to obtain the gate lead-out terminal 4. The gate lead-out terminal 4 protrudes 100-150 μm above the surface of the first molding compound, for example, 100 μm, 120 μm, or 150 μm above the end face of the first molding compound. This enhances the bonding strength of subsequent molding processes, improves reliability, and facilitates subsequent wire bonding operations using coarse copper wire 8. In this embodiment, the gate lead-out terminal 4 protrudes 120 μm above the surface of the first molding compound. The drain lead 5 is formed in the opening 14 by electroplating copper. The non-full-surface electroplating reduces the amount of metal in the copper plating and increases the unit per hour (UPH) of the process. Electroless copper plating (D electrode, i.e., drain 21) can reduce mechanical stress caused by reliability issues, reduce delamination, and optimize the current path and switching consistency. In addition, the porous stepped structure 9 (the bottom of the opening 14 on both sides of the first molding compound 1 has a stepped structure 9) can increase the contact area between the copper plating surface and the first molding compound 1, which can improve the bonding force between the two during service and improve reliability.

[0062] S400: Mount the power chip onto the first plastic package; Specifically, please combine Figure 6 The power chip 2 is mounted in the groove 13 of the first encapsulation body. During fixation, it is fixed and connected by pressurized silver or copper sintering at 250-270℃ and 20MPa for 3-5 minutes. Pressurized silver refers to the densification of nano silver powder / silver paste under heating and pressure conditions through atomic diffusion and plastic deformation to form a high-density, highly conductive and thermally conductive silver bonding layer. Copper sintering refers to the formation of a metallurgically bonded dense body by heating and controlling the atmosphere / pressure at a temperature below the melting point of copper (1085℃) to allow atomic diffusion, grain boundary migration and plastic flow between copper powder / nano copper paste particles.

[0063] S500, a source lead is sintered in the first through hole and the source lead is made to protrude above the surface of the first molding compound; Specifically, please combine Figure 7 After the power chip 2 is mounted, the source lead 3 is sintered in the first through-hole 11 of the first molding compound. In this embodiment, the source lead 3 is a conductive structure formed by sintering copper, wherein the sintering temperature is 250-270℃, the pressure is 20MPa, and the duration is controlled at 3-5min. Using sintered copper to prepare the source lead 3 can shorten the process flow compared to copper plating. The source lead 3 needs to be significantly higher than the first molding compound, generally above 300μm, to enhance the bonding force of the subsequent molding, improve reliability, and facilitate the subsequent wire bonding operation of the coarse copper wire 8.

[0064] In this embodiment, a plurality of connection portions 31 are provided at intervals on the side where the source lead 3 is connected to the power chip 2. Each connection portion 31 can be connected to a thick copper wire 8, so that the thick copper wire 8 is bonded to different branch positions of the source lead 3, thereby making the geometric path of the parallel branch more controllable, so as to reduce the problems of coupling between branches and mutual interference of current paths. In one implementation, two connection portions 31 are provided, and the source lead 3 is approximately Y-shaped. It should be noted that this application does not limit the number of connection portions 31. The number of connection portions 31 can be designed according to the number of thick copper wires 8 to be connected, and can be 5 connection portions 31, 7 connection portions 31, etc.

[0065] S600, A protective structure in the shape of an inverted electrode is sintered on the source electrode of the power chip; Specifically, please combine Figure 8 The protective structure 7 is fabricated using sintered copper and is inverted onto the source electrode 23 of the power chip 2. The thickness of the protective structure 7 is 80-100 μm, for example, 80 μm, 90 μm, or 100 μm. In this embodiment, the thickness of the protective structure 7 is 90 μm. By sintering the protective structure 7 as an electrode onto the source electrode 23 of the power chip 2, the risk of chip cracking and leakage caused by the coarse copper wire 8 interconnection can be reduced, improving the stability and lifespan of the coarse copper wire 8 interconnection.

[0066] S700, wire bonding is performed between the protection structure and the source lead-out terminal, and between the gate of the power chip and the gate lead-out terminal; Specifically, please combine Figure 9After completing the source lead-out 3, gate lead-out 4, and protective structure 7, wire bonding is performed between the gate lead-out 4 and the gate 22 of the power chip 2, and between the source lead-out 3 and the source 23 of the power chip 2. Because of the sintered micro / nano metal layer, it can withstand the wire bonding process of 15 mil (one-thousandth of an inch) thick copper wire 8. The sintered layer reduces the craters caused by direct wire bonding on the chip's functional layers, thereby reducing the risk of failure and improving packaging yield. It should be noted that, in addition to thick copper wire 8, thick aluminum wire can also be used for wire bonding.

[0067] S800, further encapsulate the power chip, the source terminal, and the gate terminal.

[0068] Specifically, please combine Figure 10 After the wire bonding process is completed, a molding process is performed to obtain a second molded body 6, wherein the second molded body 6 covers the first molded body 1, the power chip 2 and the thick copper wire 8, wherein the projected area of ​​the second molded body 6 on the first molded body 1 at least covers the first through hole 11 and the second through hole 12, so as to complete the encapsulation protection of the power chip 2, the bonding wires (e.g., the thick copper wire 8 and the thick aluminum wire) and the local semiconductors (e.g., the source lead 3 and the gate lead 4), and obtain the power chip 2 package.

[0069] In summary, the power chip packaging structure and its fabrication method provided in this application have the following beneficial effects: 1) Reduce process complexity and manufacturing cost: By adopting a multi-port parallel hole-type conductive / interconnect structure at the bottom of the power chip, the required current-carrying channel can be localized, reducing the need for thick copper plating and subsequent removal and forming steps, thereby shortening the process flow and reducing processing time and cost. 2) Improve copper utilization: Traditional thick copper solutions often require overall thickening before removing excess copper layers, resulting in low material utilization. This application uses a hole-type structure to form conductor connection areas as needed, which can reduce the deposition and subsequent removal of copper in non-functional areas, achieve controllable copper usage, and reduce material waste. 3) Reduce parallel interconnection interference and improve current path consistency: Connect thick copper wires to the Y-shaped branch structure to make the connection point and routing of parallel branches more controllable, reduce the current distribution deviation caused by electromagnetic coupling between wires and uneven parasitic parameters, thereby reducing mutual interference of current paths and improving the electrical performance stability under high di / dt conditions. 4) Improve the resistance to mechanical damage and interconnect reliability of the wire bonding area: The inverted hat-shaped sintered copper protection structure set on the S pole of the chip can provide a buffer for bonding and tensile loads and expand the stress area, reduce the risk of local stress concentration on the pad and metal layer peeling / cracking, and improve the stability and life performance of the thick copper wire interconnect. 5) Enhance the structural robustness of large-size chip interconnects: Bottom-hole interconnects can disperse the thermal and mechanical loads at the connection interface to a certain extent, reduce the tendency of edge stress concentration in large-area connections, help reduce the risk of failure such as cracking and delamination, and improve the overall reliability under thermal cycling / power cycling conditions.

[0070] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A power chip packaging structure, characterized in that, include: A first molding body, wherein a first through hole and a second through hole are respectively provided on both sides of the first molding body, and a groove is provided in the middle position of the first molding body, wherein multiple openings are provided at intervals at the bottom of the groove; A power chip is disposed within the groove, with the drain of the power chip located above the opening; The source lead is disposed in the first through hole and connected to the source of the power chip; The gate lead is disposed in the second through hole and connected to the gate of the power chip; The drain lead is disposed within the plurality of openings and connected to the drain of the power chip; A second molding compound is disposed on the first molding compound and covers the first through hole and the second through hole.

2. The power chip packaging structure according to claim 1, characterized in that, The plurality of openings are arranged side by side, and the openings are one or more of square openings and circular openings.

3. The power chip packaging structure according to claim 1, characterized in that, The power chip has an inverted electrode-shaped protective structure on its source electrode, and the protective structure is connected to the source electrode lead-out terminal.

4. The power chip packaging structure according to claim 1, characterized in that, The end of the source lead-out terminal connected to the source terminal is provided with several connection parts at intervals.

5. The power chip packaging structure according to claim 4, characterized in that, The connection portion of the source lead-out terminal is connected to the source of the power chip by a copper wire; the gate of the power chip is connected to the gate lead-out terminal by a copper wire.

6. The power chip packaging structure according to claim 3, characterized in that, Both the source lead-out terminal and the protective structure are sintered copper structures.

7. The power chip packaging structure according to claim 4, characterized in that, The source terminal has two connection parts.

8. The power chip packaging structure according to claim 1, characterized in that, The multiple openings are interconnected.

9. The power chip packaging structure according to claim 8, characterized in that, The bottom of the openings on both sides of the first molding body has a stepped structure.

10. A method for fabricating a power chip packaging structure as described in any one of claims 1-9, characterized in that, The method includes the following steps: A first molding compound and a protective layer are provided, and the first molding compound is placed on the protective layer; A first through hole, a second through hole, a groove, and multiple openings are formed on the first molding body by means of laser drilling or punching. The gate leads are plated and molded at the second through-hole, and the drain leads are plated and molded at the plurality of openings; wherein the gate leads are higher than the surface of the first molding compound. The power chip is mounted on the first plastic package; A source lead is sintered and formed in the first through hole, and the source lead is made to protrude above the surface of the first molding compound; A protective structure in the shape of an inverted electrode is sintered on the source electrode of the power chip; Wire bonding is performed between the protection structure and the source terminal, and between the gate of the power chip and the gate terminal; The power chip, the source terminal, and the gate terminal are further encapsulated.

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