Stream data processing method and synchronous acquisition system for distributed optical fiber sensing

Abstract

This invention belongs to the field of data processing technology. It proposes a streaming data processing method and synchronous acquisition system for distributed fiber optic sensing. The method calculates the precise delay cycle number by taking into account the system's inherent delay and blind zone length. A counter is started after laser triggering, and when the count reaches the specified number of cycles, an effective data acquisition window is opened to mask invalid blind zones. During the window period, real-time data acquired by the dual-channel ADC and historical accumulated data read from external memory are stored separately in FIFOs. When both FIFOs are not empty, an adder is driven to align and add the data and write it back to storage. After the accumulation count reaches a certain threshold, a shifted average is performed on the result to obtain noise-reduced data. This invention utilizes an FPGA to implement streaming buffering and real-time hardware accumulation, combined with a ping-pong storage mechanism, effectively eliminating channel phase differences and significantly improving the data processing speed and signal-to-noise ratio of the distributed fiber optic sensing system.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and specifically to a streaming data processing method and synchronous acquisition system for distributed optical fiber sensing. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Distributed fiber optic temperature measurement (DTS) is a sensing system that measures the continuous temperature distribution along an optical fiber based on the principles of optical time-domain reflectometry and Raman scattering. The system demodulates temperature by injecting narrow-pulse laser light into the fiber and detecting the intensity ratio of the backscattered Stokes and anti-Stokes scattered light signals. To achieve meter-level or sub-meter-level spatial positioning accuracy, the data acquisition system needs a high-speed sampling capability of over 100 Mbps and requires strict synchronization between the two signals.

[0004] Traditional DTS temperature sensing systems suffer from the following technical bottlenecks and shortcomings in their data acquisition schemes: (1) Channel synchronization error leads to temperature measurement distortion: Traditionally, multiple independent ADCs are spliced ​​together to achieve multi-channel sampling. Due to the difference in sampling clock source allocation path or the discreteness of device parameters, it is difficult for the two optical signals to be absolutely aligned on the time axis. At the same time, blind acquisition will lead to the recording of invalid blind zone data at the fiber front end, resulting in serious errors in intensity ratio calculation and affecting temperature measurement accuracy.

[0005] (2) High-order accumulation is limited by on-chip storage bottleneck: In order to improve the signal-to-noise ratio (detecting weak signals at long distances), the DTS temperature sensing system needs to accumulate and average a large number of pulse echoes tens of thousands of times. Traditional solutions rely on the internal BRAM resources of the FPGA for whole-frame caching and accumulation, but due to the small on-chip resources, the maximum number of accumulations and the sensing distance are severely limited. If a large-capacity external storage chip is used for data caching, it will consume high hardware costs. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a streaming data processing method and synchronous acquisition system for distributed optical fiber sensing. It solves the problems of difficult timing alignment of multi-channel signals, large redundancy of invalid background data, and severe limitation of high-order accumulation denoising on FPGA on-chip storage resources in long-distance DTS systems. It achieves higher-precision temperature demodulation by extracting high-precision reference data.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a streaming data processing method for distributed optical fiber sensing.

[0008] A streaming data processing method for distributed fiber optic sensing includes the following steps: The inherent delay of the optical path system, the response delay of the photodetector, and the length of the initial dead zone of the fiber under test are obtained, and the precise number of delay cycles to reach the effective fiber starting point is calculated based on the system sampling rate. When a laser pulse trigger signal is received, a high-precision counter is started. When the count value of the high-precision counter is equal to the number of precise delay cycles, a data write enable signal is generated to open the effective data capture window. During the effective data capture window, the real-time discrete data acquired by the dual-channel analog-to-digital converter is stored in the real-time acquisition write FIFO, and the historical accumulated data is read from the first buffer address space of the external memory and stored in the historical readout FIFO. The non-empty flags of the real-time acquisition write FIFO and the historical read FIFO are detected. When both non-empty flags are valid, a double non-empty logical AND operation is performed to generate an adder enable signal. In response to the adder enable signal, the current acquired data output from the real-time acquisition write FIFO is aligned and added with the historical accumulated data output from the historical read FIFO to obtain the current accumulation result; Write the current accumulation result into the second buffer address space of the external memory; When the accumulated count reaches the preset number of accumulations, a shift operation is performed on the final accumulated result stored in the external memory to obtain the average noise reduction data.

[0009] In one implementation of the first aspect of the present invention, the inherent delay of the optical path system, the response delay of the photodetector, and the initial dead zone length of the fiber under test are obtained, and the precise delay period to reach the effective fiber starting point is calculated based on the system sampling rate, including: Based on the refractive index of light in optical fiber, the speed of light in vacuum, and the system sampling rate, combined with the inherent delay of the optical path system, the response delay of the photodetector, and the initial dead zone length of the optical fiber under test, the precise number of delay periods is calculated. Among them, the precise delay period is used to compensate for the sum of optical path transmission time and circuit response time, so as to ensure that the start time of the effective data acquisition window corresponds to the true physical starting point of the optical fiber under test.

[0010] In one implementation of the first aspect of the present invention, during the effective data acquisition window, real-time discrete data acquired by the dual-channel analog-to-digital converter is stored in a real-time acquisition write FIFO, and historical accumulated data is read from the first buffer address space of the external memory and stored in a historical readout FIFO, including: During the Kth laser pulse acquisition process, the memory controller is controlled to read the historical accumulated data of the K-1th pulse from the first buffer address space of the external memory in burst mode; The historical accumulated data read in the (K-1)th time is cached in the historical read FIFO; Simultaneously, the real-time discrete data generated by the Kth laser pulse is cached into the real-time acquisition and write FIFO through the data interface; The first buffer address space and the second buffer address space are two address spaces of equal capacity that are pre-divided in the external memory.

[0011] In one implementation of the first aspect of the present invention, after writing the current accumulation result into the second buffer address space of the external memory, the method further includes: After completing the accumulation and writing operations of all data points corresponding to the Kth laser pulse, switch the read / write pointer to point; During the K+1th laser pulse acquisition process, the second buffer address space of the external memory is used as the new first buffer address space to read the accumulated result of the Kth pulse, and the first buffer address space of the external memory is used as the new second buffer address space to write the accumulated result of the K+1th pulse.

[0012] In one implementation of the first aspect of the present invention, when the accumulated count reaches a preset number of accumulations, a shift operation is performed on the final accumulated result stored in the external memory to obtain average noise reduction data, including: Determine if the current accumulated count is equal to the preset accumulated count; If the current accumulated count equals the preset accumulated count, then the final accumulated result is read from the external memory; The number of bits to be shifted is determined based on the preset number of accumulations, and a right shift operation is performed on the final accumulated result read out. The shifted data is rounded using low-order compensation to output the average noise reduction data.

[0013] Secondly, the present invention provides a data processing device for distributed optical fiber sensing.

[0014] A data processing device for distributed fiber optic sensing, comprising: The delay calculation unit is configured to: acquire the inherent delay of the optical path system, the response delay of the photodetector, and the length of the initial dead zone of the fiber under test, and calculate the precise number of delay cycles to reach the effective fiber starting point based on the system sampling rate; The window control unit is configured to: start a high-precision counter when a laser pulse trigger signal is received; and generate a data write enable signal to open the valid data capture window when the count value of the high-precision counter is equal to the number of precise delay cycles. The streaming buffer unit is configured to: store the real-time discrete data acquired by the dual-channel analog-to-digital converter into the real-time acquisition write FIFO during the effective data acquisition window, and at the same time read the historical accumulated data from the first buffer address space of the external memory and store it into the historical readout FIFO. The logic judgment unit is configured to: detect the non-empty flags of the real-time acquisition write FIFO and the historical read FIFO; and perform a double non-empty logical AND operation to generate an adder enable signal when both non-empty flags are valid. The alignment and accumulation unit is configured to: respond to the adder enable signal, align and add the current acquisition data output by the real-time acquisition write FIFO with the historical accumulation data output by the historical read FIFO to obtain the current accumulation result; The data storage unit is configured to write the current accumulation result into the second buffer address space of the external memory; The shift averaging unit is configured to perform a shift operation on the final accumulation result stored in the external memory to obtain the average noise reduction data when the accumulation count reaches a preset accumulation number.

[0015] In one implementation of the second aspect of the present invention, the alignment accumulation unit includes: The first state detection subunit is configured to output a non-empty flag bit of the real-time acquisition write FIFO; The second state detection subunit is configured to output the non-empty flag of the history readout FIFO; The logic operation subunit is configured to perform a logical AND operation on the non-empty flag bit output by the first state detection subunit and the non-empty flag bit output by the second state detection subunit. The adder driver subunit is configured to enable the adder to perform the addition operation of the currently acquired data and the historical accumulated data when the logic operation subunit outputs a valid level.

[0016] Thirdly, the present invention provides a high-speed synchronous acquisition system for distributed optical fiber sensing.

[0017] A high-speed synchronous acquisition system for distributed fiber optic sensing includes: A dual-channel analog-to-digital converter is used to share the same sampling clock and perform synchronous analog-to-digital conversion on Stokes photoelectric signals and anti-Stokes photoelectric signals, outputting real-time discrete data. A field-programmable gate array, connected to a dual-channel analog-to-digital converter, is used to execute the streaming data processing method of the first aspect of the present invention; An external memory, connected to a field-programmable gate array, is used to store accumulated data divided into a first buffer address space and a second buffer address space; The field-programmable gate array (FPGA) is internally configured with a high-precision counter, a real-time acquisition write FIFO, a historical read FIFO, and a hardware adder. The high-precision counter is used to generate a valid data capture window. The real-time acquisition write FIFO is used to buffer real-time discrete data. The historical read FIFO is used to buffer historical accumulated data read from external memory. When the hardware adder detects that the double NOT-empty logical AND operation of the real-time acquisition write FIFO and the historical read FIFO is valid, it adds the data output from the two FIFOs.

[0018] In one implementation of the third aspect of the present invention, the dual-channel analog-to-digital converter receives a configuration signal sent via the SPI bus during the system initialization phase. The configuration signal is used to clear the phase of the frequency divider and digital filter inside the dual-channel analog-to-digital converter to achieve physical-level phase synchronization of the two signals.

[0019] In one implementation of the third aspect of the present invention, the field-programmable gate array is further used for: During the system initialization phase, a configuration signal is sent to the dual-channel analog-to-digital converter via the SPI interface to force the phases of all frequency dividers and digital filters inside the dual-channel analog-to-digital converter to be cleared. Upon receiving the laser pulse trigger signal, a high-precision counter is started, and the data write enable signal is kept off to shield invalid background noise until the count value of the high-precision counter reaches the precise delay period.

[0020] Compared with the prior art, the beneficial effects of the present invention are: This invention innovatively proposes a multi-level precise synchronization mechanism based on hardware and algorithm collaboration. At the hardware level, a dual-channel ADC chip is selected and shares a sampling clock. The acquisition and transmission synchronization of the two channels is achieved through SPI bus configuration. At the algorithm level, a "delay triggering and window enabling" mechanism is introduced. The optical path delay is dynamically compensated by an FPGA high-precision counter, which accurately crosses the physical blind zone of the optical fiber and ensures that the first discrete point of the effective data acquisition window strictly corresponds to the real physical starting point of the optical fiber, thus realizing the spatiotemporal synchronization of the "spatial domain" and the "digital time domain".

[0021] This invention innovatively proposes a lightweight streaming multi-frame accumulation mechanism: abandoning the traditional whole-frame caching scheme that consumes FPGA internal BRAM resources, it designs a streaming algorithm architecture based on external SDRAM, namely "ping-pong rotation - double-end alignment - pipelined computation". It uses the "double non-empty logical AND" operation of real-time acquisition write FIFO and historical read FIFO as the alignment trigger condition of the adder, avoiding the bus latency caused by external memory read / write switching. Finally, it combines shift operation to replace the divider, achieving rapid accumulation and averaging of large amounts of data with "zero dead zone" with extremely low on-chip resource consumption.

[0022] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0023] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0024] Figure 1 A schematic diagram of the hardware architecture of a synchronous high-speed acquisition system provided as an exemplary embodiment of the present invention; Figure 2 A schematic diagram of the multi-level precise delay synchronization triggering and sampling window enabling timing logic provided as an exemplary embodiment of the present invention; Figure 3 A schematic diagram of a streaming multi-frame data accumulation processing flow provided as an exemplary embodiment of the present invention; Figure 4 This is a schematic diagram of a data processing apparatus for distributed optical fiber sensing provided as an exemplary embodiment of the present invention. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0026] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0027] This implementation proposes a multi-level synchronous acquisition method based on a combination of hardware and algorithms. This method aims to solve the problems of phase skew in multi-channel signals and spatiotemporal misalignment between laser triggering and sampling windows, improving spatial positioning accuracy and eliminating resource waste. Through a perfect combination of hardware ADC low-level configuration and FPGA algorithm layer delay triggering, effective spatial reflection segment data is directly captured at the low-level hardware. This eliminates the occupation of high-speed bus and cache resources by a large amount of invalid background data from the source, achieving physical-level synchronization of multiple signals. It breaks through the resource barrier of deep accumulation, abandoning the traditional on-chip accumulation mode. A single-channel computing core relies on only two sets of extremely small-capacity shallow FIFOs and an adder, utilizing ping-pong address alternating read / write and combined with the strict timing alignment logic of dual FIFOs, completely avoiding the page swapping delay of external memory. This transfers all the pressure of large-capacity cache to external SDRAM, greatly enhancing the system's ability to detect weak Raman signals at a distance.

[0028] Specifically, the hardware architecture of the synchronous high-speed acquisition system is as follows: Figure 1As shown, the diagram illustrates the interconnections of a multi-channel ADC synchronous sampling module, an FPGA streaming data processing module, and an SDRAM external storage structure. The core process begins with a laser driver generating controlled optical pulses that are injected into the fiber under test. The resulting backscattered light is separated by a wavelength division multiplexer and converted into an electrical signal by a dual-channel photodetector. This signal then enters a dual-channel ADC sharing the same sampling clock for synchronous analog-to-digital conversion to eliminate inter-channel phase differences. The converted digital signal is transmitted to the FPGA, where a delay calculation and window control module first calculates the precise delay cycle number based on the system's inherent delay and dead zone length, generating an effective data capture window to shield against invalid noise. Then, during the window's open period, streaming buffer management... The module writes real-time acquired data into the real-time acquisition write FIFO while simultaneously reading historical data from external memory (using ping-pong switching of the first / second buffer address space) into the historical read FIFO. Subsequently, the alignment and accumulation operation module generates an enable signal by performing a double non-empty logical AND operation on the non-empty flags of the two FIFOs, driving the hardware adder to perform point-by-point alignment and addition of the current data and historical data, and writes the result back to the external memory. Finally, after reaching the preset number of accumulations, the shift averaging output module performs a shift operation to obtain the average noise-reduced data, thus realizing high-speed processing across the entire chain from light pulse excitation, high-speed synchronous acquisition, FIFO-based streaming buffering, hardware real-time accumulation to ping-pong storage management.

[0029] In this implementation, the timing logic diagram for multi-level precise delay synchronization triggering and sampling window enable is as follows: Figure 2 As shown, when the laser trigger signal is emitted and a laser pulse is generated, due to the inherent delay (dead zone) in the optical path and circuit, the photodetector signal is in an invalid state in the initial stage, until a delay compensation count value N accumulated by the FPGA delay counter is reached. delay Only after a certain period of time does an effective Raman scattering signal curve appear and align with the true starting point of the fiber. During this period, the system performs hardware forced shielding (invalid blind zone) operation to filter out noise by keeping the data write enable (WR_EN) at a low level. The write enable is only pulled high when the counter reaches a preset value and an effective signal arrives, thereby opening a continuous acquisition window for effective data to ensure that only real sensor data is collected.

[0030] The proposed multi-level synchronous acquisition method based on a combination of hardware and algorithms is implemented in the following steps: Step (1-1) Hardware-level multi-channel precise synchronization: Stokes and anti-Stokes photoelectric signals are input to the same dual-channel high-speed ADC. At the physical level, the two channels share the same low-jitter 250MHz sampling clock tree. During system initialization, the FPGA sends a configuration signal to the ADC via the SPI interface, forcibly clearing the phase of all internal frequency dividers and digital filters, ensuring that the two signals achieve physical-level phase synchronization during the analog-to-digital conversion stage, and eliminating inter-channel timing skew errors caused by splicing multiple ADCs.

[0031] Step (1-2) Trigger and Spatiotemporal Synchronization Delay Calculation: When the system starts temperature measurement, the FPGA sends a pulse trigger signal to the laser. Assume the inherent delay of the optical path system (fiber optic patch cord, wavelength division multiplexer, etc.) is... The response delay of the photodetector and the front-end amplifier circuit is The initial dead zone length of the fiber under test is The refractive index of light in optical fiber is The speed of light in a vacuum is The system sampling rate is f s The FPGA internally calculates the precise number of delay cycles required to reach the effective fiber optic starting point. : ; Step (1-3) Algorithm layer sampling window synchronization enable: At the instant the FPGA emits the laser trigger signal, the internal high-precision counter with a frequency of 250MHz is started synchronously. At this time, the ADC continues analog-to-digital conversion, but the write enable (WR_EN) of the data receiving end inside the FPGA remains closed, thereby shielding the invalid blind zone background noise.

[0032] Steps (1-4) When the counter's count value is strictly equal to At the same time, the FPGA simultaneously pulls up the dual-channel data write enable (WR_EN) to officially begin capturing valid fiber scattering data. The "delay synchronization" mechanism ensures that the first discrete data point acquired is precisely aligned with the true physical starting point of the fiber under test. In this way, spatiotemporal synchronization between the "fiber spatial domain" and the "digital time domain" is achieved.

[0033] To overcome the bottleneck of extremely limited internal BRAM resources in FPGAs and achieve deep noise reduction accumulation of tens of thousands or even hundreds of thousands of times, this invention designs a streaming multi-frame data accumulation processing algorithm architecture built using external SDRAM, which is described as "ping-pong rotation - double-end alignment - pipelined computation". The flowchart of the streaming multi-frame data accumulation processing is shown below. Figure 3 As shown, its specific implementation logic and process are as follows: Step (2-1) Ping-pong address mapping for external SDRAM storage: In the external SDRAM physical memory, two address spaces with absolutely equal capacity are pre-divided: Buffer A and Buffer B.

[0034] Step (2-2) Real-time streaming double-ended aligned read / write: When the Kth laser pulse is acquired (K≥2): the newly acquired real-time discrete data enters the "ADC write FIFO" inside the FPGA. Simultaneously, the FPGA's internal memory controller, in burst mode, reads the first K pulses from the external SDRAM's Buffer A space. One historical accumulated data is read out and stored in the "SDRAM read FIFO" inside the FPGA.

[0035] Step (2-3) Dual FIFO Logic and Synchronous Accumulation: A hardware adder (ADDER) driven by a high-frequency clock (250MHz) is responsible for the accumulation operation. To prevent intermittent pauses in data readout from the external SDRAM due to automatic refresh or bus arbitration, this invention uses a pulse signal and a non-empty flag to jointly control the adder's enable port: the adder's enable signal is valid only when both the "ADC Write FIFO" and the "SDRAM Read FIFO" are not empty. At this time, both FIFOs simultaneously dequeue one data item, and the adder aligns and adds the "currently acquired data" and the "historically accumulated data." This mechanism forcibly locks the phase of the new and old data, further ensuring the synchronous alignment of inter-frame data.

[0036] Step (2-4) Alternating write-back operation: The accumulated result output by the adder is buffered and written to the Buffer B space of the SDRAM in continuous burst mode. During the (K+1)th pulse acquisition, the read and write pointers are flipped (reading Buffer B, writing Buffer A). This pipelined alternating operation completely avoids the extremely long bus turnaround delay caused by "read-modify-write" at the same address, and achieves zero dead-time data processing.

[0037] Step (2-5) Fast averaging by shifting instead of division: Determine whether the current accumulated count has reached the preset number of accumulations. If not, repeat steps (2-2) to (2-4). If it has reached the preset number of accumulations, when reading the accumulated sum for the last time, the data averaging module does not call the hardware divider that consumes a lot of FPGA logic resources. Instead, it directly performs a right shift operation on the data at the bottom layer, and performs rounding in combination with low-bit compensation to output high-precision average noise-reduced data.

[0038] Step (2-) Low FPGA resource utilization: Due to the adoption of a single-channel pipeline loop mode using only "2 shallow FIFOs + 1 adder", all accumulated data is cached in low-cost external SDRAM. Compared with the traditional scheme that calls a large amount of internal BRAM of the FPGA for caching, this architecture compresses the BRAM resource utilization to an extremely low level (occupying only a few Block RAM as a cross-clock domain FIFO), which has significant advantages in terms of lightweight and low cost.

[0039] Figure 4 A data processing apparatus for distributed fiber optic sensing is shown, comprising: The delay calculation unit 401 is configured to: acquire the inherent delay of the optical path system, the response delay of the photodetector, and the length of the initial dead zone of the fiber under test, and calculate the precise number of delay cycles to reach the effective fiber starting point based on the system sampling rate; The window control unit 402 is configured to: start a high-precision counter when a laser pulse trigger signal is received; and generate a data write enable signal to open a valid data capture window when the count value of the high-precision counter is equal to the number of precise delay cycles. The streaming buffer unit 403 is configured to: store the real-time discrete data acquired by the dual-channel analog-to-digital converter into the real-time acquisition write FIFO during the effective data acquisition window, and at the same time read the historical accumulated data from the first buffer address space of the external memory and store it into the historical readout FIFO. The logic judgment unit 404 is configured to: detect the non-empty flags of the real-time acquisition write FIFO and the historical read FIFO; and perform a double non-empty logical AND operation to generate an adder enable signal when both non-empty flags are valid. The alignment and accumulation unit 405 is configured to: in response to the adder enable signal, align and add the current acquisition data output by the real-time acquisition write FIFO with the historical accumulation data output by the historical read FIFO to obtain the current accumulation result; Data storage unit 406 is configured to write the current accumulation result into the second buffer address space of external memory; The shift averaging unit 407 is configured to perform a shift operation on the final accumulation result stored in the external memory to obtain average noise reduction data when the accumulation count reaches a preset accumulation number.

[0040] The alignment accumulation unit in this implementation includes: The first state detection subunit 405-1 is configured to output the non-empty flag of the real-time acquisition write FIFO; The second state detection subunit 405-2 is configured to output the non-empty flag of the history readout FIFO; The logic operation subunit 405-3 is configured to perform a logical AND operation on the non-empty flag bit output by the first state detection subunit and the non-empty flag bit output by the second state detection subunit. The adder driver subunit 405-4 is configured to enable the adder to perform the addition operation of the currently acquired data and the historical accumulated data when the logic operation subunit outputs a valid level.

[0041] It is understood that the aforementioned units can be individually or entirely merged into one or more other units, or some of the units can be further divided into multiple functionally smaller units. This achieves the same operation without affecting the technical effects of the embodiments of the present invention. The aforementioned units are based on logical functional division. In practical applications, the function of one unit can be implemented by multiple units, or the function of multiple units can be implemented by one unit. In other embodiments of the present invention, the system may also include other units. In practical applications, these functions can also be implemented with the assistance of other units, and can be implemented collaboratively by multiple units.

[0042] According to another embodiment of the present invention, the system of this embodiment can be constructed by running a computer program (including program code) capable of performing the steps involved in the corresponding method of the present invention on a general-purpose computing device, such as a computer, which includes processing elements and storage elements such as a central processing unit (CPU), random access memory (RAM), and read-only memory (ROM). The computer program can be recorded on, for example, a computer-readable recording medium, loaded into the aforementioned computing device through the computer-readable recording medium, and run therein.

[0043] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A streaming data processing method for distributed fiber optic sensing, characterized in that, Includes the following steps: The inherent delay of the optical path system, the response delay of the photodetector, and the length of the initial dead zone of the fiber under test are obtained, and the precise number of delay cycles to reach the effective fiber starting point is calculated based on the system sampling rate. When a laser pulse trigger signal is received, a high-precision counter is started. When the count value of the high-precision counter is equal to the number of precise delay cycles, a data write enable signal is generated to open the effective data capture window. During the effective data capture window, the real-time discrete data acquired by the dual-channel analog-to-digital converter is stored in the real-time acquisition write FIFO, and the historical accumulated data is read from the first buffer address space of the external memory and stored in the historical readout FIFO. The non-empty flags of the real-time acquisition write FIFO and the historical read FIFO are detected. When both non-empty flags are valid, a double non-empty logical AND operation is performed to generate an adder enable signal. In response to the adder enable signal, the current acquired data output by the real-time acquisition write FIFO is aligned and added with the historical accumulated data output by the historical read FIFO to obtain the current accumulation result; Write the current accumulation result into the second buffer address space of the external memory; When the accumulated count reaches the preset number of accumulations, a shift operation is performed on the final accumulated result stored in the external memory to obtain the average noise reduction data.

2. The streaming data processing method for distributed optical fiber sensing as described in claim 1, characterized in that, The inherent delay of the optical path system, the response delay of the photodetector, and the initial dead zone length of the fiber under test are obtained. Based on the system sampling rate, the precise number of delay cycles required to reach the effective fiber starting point is calculated, including: Based on the refractive index of light in the optical fiber, the speed of light in vacuum, and the sampling rate of the system, combined with the inherent delay of the optical path system, the response delay of the photodetector, and the initial dead zone length of the optical fiber under test, the precise delay period is calculated. The precise delay period is used to compensate for the sum of optical path transmission time and circuit response time, so as to ensure that the start time of the effective data acquisition window corresponds to the true physical starting point of the optical fiber under test.

3. The streaming data processing method for distributed optical fiber sensing as described in claim 1, characterized in that, During the effective data acquisition window, real-time discrete data acquired by the dual-channel analog-to-digital converter is stored in the real-time acquisition write FIFO, and historical accumulated data is read from the first buffer address space of the external memory and stored in the historical readout FIFO, including: During the Kth laser pulse acquisition process, the memory controller is controlled to read the historical accumulated data of the (K-1)th pulse from the first buffer address space of the external memory in burst mode; The historical accumulated data read from the (K-1)th time is cached in the historical readout FIFO; Simultaneously, the real-time discrete data generated by the Kth laser pulse is cached into the real-time acquisition and write FIFO through the data interface; The first buffer address space and the second buffer address space are two address spaces of equal capacity that are pre-divided in the external memory.

4. The streaming data processing method for distributed optical fiber sensing as described in claim 1, characterized in that, After writing the current accumulation result into the second buffer address space of the external memory, the process further includes: After completing the accumulation and writing operations of all data points corresponding to the Kth laser pulse, switch the read / write pointer to point; During the (K+1)th laser pulse acquisition process, the second buffer address space of the external memory is used as the new first buffer address space to read the accumulated result of the Kth pulse, and the first buffer address space of the external memory is used as the new second buffer address space to write the accumulated result of the (K+1)th pulse.

5. The streaming data processing method for distributed optical fiber sensing as described in claim 1, characterized in that, When the accumulated count reaches a preset number of accumulations, a shift operation is performed on the final accumulated result stored in the external memory to obtain the average noise reduction data, including: Determine whether the current accumulated count is equal to the preset accumulated count; If the current accumulated count is equal to the preset accumulated count, then the final accumulated result is read from the external memory; The number of bits to be shifted is determined according to the preset number of accumulations, and a right shift operation is performed on the read final accumulation result; The shifted data is rounded using low-order compensation to output the average noise reduction data.

6. A data processing device for distributed optical fiber sensing, characterized in that, include: The delay calculation unit is configured to: acquire the inherent delay of the optical path system, the response delay of the photodetector, and the length of the initial dead zone of the fiber under test, and calculate the precise number of delay cycles to reach the effective fiber starting point based on the system sampling rate; The window control unit is configured to: activate a high-precision counter when a laser pulse trigger signal is received; and generate a data write enable signal to open a valid data capture window when the count value of the high-precision counter is equal to the number of precise delay cycles. The streaming buffer unit is configured to: during the effective data capture window, store the real-time discrete data acquired by the dual-channel analog-to-digital converter into the real-time acquisition write FIFO, and at the same time read historical accumulated data from the first buffer address space of the external memory and store it into the historical readout FIFO. The logic judgment unit is configured to: detect the non-empty flags of the real-time acquisition write FIFO and the historical read FIFO; and perform a double non-empty logical AND operation to generate an adder enable signal when both non-empty flags are valid. The alignment and accumulation unit is configured to: in response to the adder enable signal, align and add the current acquisition data output by the real-time acquisition write FIFO with the historical accumulation data output by the historical read FIFO to obtain the current accumulation result; The data storage unit is configured to write the current accumulation result into the second buffer address space of the external memory; The shift averaging unit is configured to perform a shift operation on the final accumulation result stored in the external memory to obtain average noise reduction data when the accumulated count reaches a preset number of accumulations.

7. The data processing apparatus for distributed optical fiber sensing as described in claim 6, characterized in that, The alignment accumulation unit includes: The first state detection subunit is configured to output the non-empty flag of the real-time acquisition write FIFO; The second state detection subunit is configured to output the non-empty flag of the historical readout FIFO. The logic operation subunit is configured to perform a logical AND operation on the non-empty flag bit output by the first state detection subunit and the non-empty flag bit output by the second state detection subunit. The addition driver subunit is configured to: when the logic operation subunit outputs a valid level, enable the adder to perform the addition operation of the currently acquired data and the historical accumulated data.

8. A high-speed synchronous acquisition system for distributed fiber optic sensing, characterized in that, include: A dual-channel analog-to-digital converter is used to share the same sampling clock and perform synchronous analog-to-digital conversion on Stokes photoelectric signals and anti-Stokes photoelectric signals, outputting real-time discrete data. A field-programmable gate array, connected to the dual-channel analog-to-digital converter, is used to execute the streaming data processing method as described in any one of claims 1 to 5; An external memory, connected to the field-programmable gate array, is used to store accumulated data divided into a first buffer address space and a second buffer address space; The field-programmable gate array (FPGA) is internally configured with a high-precision counter, a real-time acquisition write FIFO, a historical read FIFO, and a hardware adder. The high-precision counter is used to generate a valid data capture window. The real-time acquisition write FIFO is used to buffer the real-time discrete data. The historical read FIFO is used to buffer historical accumulated data read from the external memory. When the hardware adder detects that the double NOT-empty logical AND operation of the real-time acquisition write FIFO and the historical read FIFO is valid, it adds the data output from the two FIFOs.

9. The high-speed synchronous acquisition system for distributed optical fiber sensing as described in claim 8, characterized in that, During the system initialization phase, the dual-channel analog-to-digital converter receives a configuration signal sent via the SPI bus. The configuration signal is used to clear the phase of the frequency divider and digital filter inside the dual-channel analog-to-digital converter to achieve physical-level phase synchronization of the two signals.

10. The high-speed synchronous acquisition system for distributed optical fiber sensing as described in claim 8, characterized in that, The field-programmable gate array is also used for: During the system initialization phase, a configuration signal is sent to the dual-channel analog-to-digital converter via the SPI interface to force the phases of all frequency dividers and digital filters inside the dual-channel analog-to-digital converter to be cleared. The high-precision counter is started simultaneously with the laser pulse trigger signal, and the data write enable signal is kept off to shield invalid background noise until the count value of the high-precision counter reaches the precise delay period.

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