Method for optimizing the position of a decoupling capacitor to improve the quality of a cross-sectioned signal on a PCB

Abstract

This invention relates to a method for optimizing the placement of bridging capacitors to improve signal quality across split regions on a PCB board. The method includes the following steps: establishing a bridging capacitor simulation model for signal lines crossing a split region of a reference plane; setting the bridging capacitor simulation model to a movable state, using the distance between the bridging capacitor and the signal line as a scanning variable; performing a step-by-step scan within a preset distance range to obtain signal quality parameters at different distances; determining the maximum effective compensation distance of the bridging capacitor relative to the signal line based on the scan results and a preset judgment criterion; and determining the number of bridging capacitors and their placement positions based on the maximum effective compensation distance and the actual width of the cross-segment signal region to be compensated. This invention quantifies the impact of capacitor placement distance on signal quality, scientifically determines the maximum effective compensation distance of the bridging capacitors, and enables reasonable planning of the number and placement of capacitors, balancing wiring density and cost while ensuring signal quality.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and more specifically, to a method for optimizing the location of bridging capacitors to improve the quality of cross-segment signals on a PCB board. Background Technology

[0002] Printed Circuit Boards (PCBs) are fundamental components in electronic products that carry electrical connections and signal transmissions. With the continuous increase in the operating frequency of digital systems, signal integrity has become an increasingly significant challenge in PCB design. In high-density wiring or low-layer PCB designs, it is common for high-speed signal lines to cross reference plane partitions. A reference plane partition refers to the boundary between a power plane and a ground plane, or between two power planes at different potentials. When a high-speed signal line crosses this boundary, the return current loop is forced to detour at the partition, significantly increasing inductive impedance and causing a sudden change in the characteristic impedance at the partition crossing point. This also leads to a considerable degradation in insertion loss. Taking a typical 50-ohm high-speed signal line as an example, simulations have shown that without any intervention, the characteristic impedance at the partition crossing point can abruptly increase to over 60 ohms, and the insertion loss at 5GHz can deteriorate by up to 3dB, severely impacting the system's signal transmission quality.

[0003] To address the aforementioned signal quality degradation issues, a common industry practice is to place bridging capacitors near the reference plane split region. These bridging capacitors are typically 100nF 0402 packaged chip capacitors. Their bridging effect provides a local low-impedance path for the signal return current, effectively suppressing abrupt changes in inductive impedance, thereby improving the impedance continuity and insertion loss of the signal line at the split location. Simulation results show that after using bridging capacitors, the insertion loss of the split signal line can be restored to near the level of an ideal reference plane without splits, demonstrating a significant improvement.

[0004] However, existing technologies face two unresolved key issues in the practical engineering applications of jumper capacitors. First, the effective operating distance of jumper capacitors is unclear. The signal quality improvement effect of jumper capacitors decreases with increasing distance from the signal line being improved. However, in current engineering practice, this attenuation pattern lacks a quantitative description for specific design scenarios. Designers cannot accurately determine the maximum distance from the signal line where a jumper capacitor can be placed under given signal quality requirements, leading to layout decisions relying primarily on empirical estimations and lacking objective basis. Second, in scenarios where multiple signal lines cross the same segmented area in parallel, the determination of the number and location of jumper capacitors lacks a systematic method. In high-density wiring designs, limitations imposed by trace spacing and component placement space often prevent the placement of a jumper capacitor at the nearest point for each signal line. If the number of jumper capacitors is insufficient, blind spots exist in the coverage area, and the quality degradation of some signal lines cannot be effectively improved; blindly increasing the number of jumper capacitors further exacerbates wiring density pressure and causes unnecessary cost increases. The two problems mentioned above are intertwined, making it difficult for engineers to make effective decisions when faced with cross-segment layout scenarios, and becoming a major bottleneck restricting the design quality of signal integrity on high-speed printed circuit boards. Summary of the Invention

[0005] To overcome the problems in existing technologies, such as unclear effective working distance of bridging capacitors and lack of systematic determination of the number and placement of capacitors when multiple signal lines cross the same segment, this invention provides a method for optimizing the placement of bridging capacitors to improve the signal quality across segments on PCB boards.

[0006] The technical solution of this invention is as follows: A method for improving the signal quality across a PCB board by optimizing the location of bridging capacitors, applied to signal regions on a printed circuit board divided by a reference plane, includes the following steps: Step S1: Establish a capacitance model; A simulation model of bridging capacitors is established for signal lines that cross the segmented region of the reference plane on a printed circuit board. Step S2: Set the distance variable; The bridging capacitor simulation model is set to a movable state, and the distance between the bridging capacitor and the signal line is used as the scanning variable; Step S3: Parametric scan simulation; Within a preset distance range, the distance variable is scanned step by step at a preset step size. Electromagnetic simulation is performed for each distance value to obtain signal quality parameters at different distances. Step S4: Determine the maximum effective compensation distance; Based on the scanning results obtained in step S3, and according to the preset judgment criteria, the maximum effective compensation distance of the bridging capacitor relative to the signal line is determined. Step S5: Determine the capacitor placement location: The number and placement of bridging capacitors are determined based on the maximum effective compensation distance and the actual width of the cross-segment signal region to be compensated.

[0007] As a preferred technical solution of the present invention, in step S1, the bridging capacitor simulation model is constructed in the form of a surface, the width of which is consistent with the width of the bridging capacitor of the target package, and the corresponding capacitance value is assigned through lumped RLC boundary conditions.

[0008] Furthermore, in step S1, the surface is a rectangular plane, which is placed in the reference plane segmentation area directly below the signal line. On the projection plane parallel to the reference plane, the short side of the rectangular plane extends along the trace direction of the signal line, and the long side is perpendicular to the trace direction of the signal line. The length of the long side is consistent with the width of the bridging capacitor of the target package.

[0009] Furthermore, in step S1, the capacitance value assigned in the lumped RLC boundary condition is 10nF to 470nF; the target package is a chip package, including any one of 0201 package, 0402 package or 0603 package.

[0010] As a preferred technical solution of the present invention, in step S2, the distance is a lateral distance, which is the vertical distance between the projection center of the bridging capacitor simulation model on the reference plane and the projection center line of the signal line on the reference plane; the bridging capacitor simulation model moves outward along the direction perpendicular to the signal line, and the moving distance is the change in the lateral distance.

[0011] As a preferred technical solution of the present invention, in step S3, the preset distance range is 0 to 200 mil, and the preset step size is 5 mil to 50 mil.

[0012] As a preferred embodiment of the present invention, the signal quality parameters include the impedance characteristics and insertion loss of the signal line at the reference plane split position; wherein, the impedance characteristics are obtained by extracting the time-domain reflection simulation waveform or frequency-domain impedance curve of the signal line at the reference plane split position to obtain the characteristic impedance value corresponding to each distance value; the insertion loss is obtained by extracting the curve of the S21 amplitude as a function of frequency in the S-parameters of the signal line to obtain the insertion loss value corresponding to each distance value at the target operating frequency.

[0013] As a preferred embodiment of the present invention, in step S4, the preset judgment criterion is: the impedance characteristic satisfies a preset impedance deviation threshold, and the insertion loss satisfies a preset loss degradation threshold; wherein, the preset impedance deviation threshold is ±16% of the target characteristic impedance value of the signal line; the preset loss degradation threshold is that the degradation of the insertion loss of the signal line at the target operating frequency relative to the ideal insertion loss when the reference plane is not split does not exceed 1dB; the maximum lateral distance that simultaneously satisfies the preset impedance deviation threshold and the preset loss degradation threshold is the maximum effective compensation distance.

[0014] As a preferred technical solution of the present invention, in step S5, the formula for determining the number N of the bridging capacitors is: N=⌈W / 2d⌉; where W is the actual width of the bridging signal region, d is the maximum effective compensation distance determined in step S4, and ⌈⌉ represents rounding up; N bridging capacitors are evenly distributed along the direction perpendicular to the signal line, with a spacing of no more than 2d, in the segmented signal area, and the distance between the signal line at both ends of the segmented signal area and the nearest bridging capacitor does not exceed the maximum effective compensation distance.

[0015] As a preferred embodiment of the present invention, in step S1, the signal line is a high-speed signal line, which includes a single-ended high-speed signal line or a differential high-speed signal line pair; the reference plane segmentation region includes the segmentation boundary between the power plane and the ground plane, or the segmentation boundary between two power planes with different potentials.

[0016] According to the above-described solution, the beneficial effects of this invention are as follows: This invention uses parametric scanning simulation of the lateral distance between the bridging capacitor and the signal line to obtain the impedance characteristics and insertion loss of the signal line at different distances. The maximum effective compensation distance is determined by using impedance deviation threshold and loss degradation threshold as dual judgment criteria. The quantitative result reflects the spatial boundary of the effective compensation role of the bridging capacitor in a specific design scenario, providing a repeatable and verifiable technical basis for layout decision-making, and realizing the quantitative characterization of the effective compensation distance of the bridging capacitor.

[0017] This invention clarifies the maximum acceptable placement distance for signal quality through simulation quantification, enabling designers to make reasonable layout compromises based on objective simulation data even in scenarios where it is impossible to place bridging capacitors near each signal line. This avoids the two extreme design risks of increasing the number of unnecessary components or introducing unacceptable signal quality degradation. Attached Figure Description

[0018] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is a schematic diagram of the model structure of the present invention; Figure 3 This is a schematic diagram showing the movement of the simulation model of the bridging capacitor; Figure 4 This is a comparison diagram of impedance curves for a specific embodiment; Figure 5 This is a comparison chart of insertion loss curves for a specific embodiment.

[0019] In the diagram, 1 represents the signal line; 2 represents the bridging capacitor simulation model; 31 represents the power plane; 32 represents the ground plane; and 33 represents the segmented region. Detailed Implementation

[0020] To better understand the purpose, technical solution, and technical effects of this invention, the invention will be further explained and described below in conjunction with the accompanying drawings and embodiments. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It is also stated that the embodiments described below are only for explaining this invention and are not intended to limit this invention.

[0021] like Figures 1 to 3 As shown, to overcome the problems of unclear effective working distance of bridging capacitors and lack of systematic determination methods for the number and placement of capacitors when multiple signal lines cross the same segmented area in existing technologies, this invention provides a method for optimizing the placement of bridging capacitors to improve signal quality across PCB segments. This invention addresses signal integrity issues such as impedance abrupt changes and insertion loss deterioration caused by discontinuous signal return paths when high-speed signal lines cross a reference plane segmented area in printed circuit boards. It abandons the crude approach of relying on manual experience to qualitatively place bridging capacitors in existing technologies. Through a full-process quantitative approach including parametric simulation modeling, distance variable scanning, performance threshold determination, and regional layout calculation, it achieves for the first time accurate characterization of the effective compensation distance of bridging capacitors and systematic design of capacitor placement in scenarios with multiple signal lines crossing segments.

[0022] This invention applies to signal regions on printed circuit boards that are segmented by a reference plane. The reference plane segmentation includes the segmentation between a ground plane and a power plane, and the segmentation between power planes at different potentials. The signal region is an area where one or more high-speed signal lines cross the reference plane segmentation in parallel. This invention quantifies the correlation between capacitance distance and signal performance through electromagnetic simulation, and then completes the engineering layout based on the quantization results. Specifically, it includes the following steps: Step S1: Establish a capacitor model: For signal line 1 spanning the reference plane segmentation region 33 on the printed circuit board, establish a bridging capacitor simulation model 2 that matches the electrical characteristics and structural dimensions of the actual physical device. This step abandons the conventional method of directly calling general-purpose device models, and instead constructs a dedicated simulation model based on the actual bridging capacitor to be used, restoring the electrical coupling effect and physical occupancy characteristics of the capacitor at the PCB reference plane segmentation. Using the segmented signal line 1 as the simulation benchmark, it ensures that the model completely corresponds to the actual signal transmission path and reference plane structure, eliminating the interference of model deviations on subsequent simulation results. Step S1 provides an accurate and equivalent simulation basis for subsequent distance scanning and performance analysis, ensuring that the simulation results can be directly mapped to actual PCB engineering applications.

[0023] Step S2: Set the distance variable: Set the bridging capacitor simulation model 2 to a movable state along the direction perpendicular to the signal line 1, using the relative distance between the bridging capacitor and signal line 1 as the core scanning variable. The compensation effect of the bridging capacitor on the cross-segment signal essentially restores the electrical continuity of the reference plane through capacitive coupling. Its compensation capability decreases as the lateral distance from signal line 1 increases. Setting this distance as an adjustable scanning variable is a prerequisite for achieving a quantitative correlation between "distance and compensation effect." The movable state ensures that the distance variable can be continuously and accurately adjusted, fully covering the possible placement range of capacitors in the actual PCB layout. This step transforms the fuzzy influence of distance into a quantitatively studyable scanning variable, breaking through the technical bottleneck of existing technologies that cannot quantify the relationship between capacitor distance and signal performance.

[0024] Step S3, Parametric Scan Simulation: Within a preset distance range, the distance variable is scanned step-by-step at a preset step size. Full-band electromagnetic simulation is performed for each distance value, extracting and recording key signal quality parameters of signal line 1 at different distances. Step S3 uses parametric scanning to automate the traversal of the distance variable. The preset distance range covers the conventional layout space of high-density PCB wiring, and the preset step size ensures the continuity and accuracy of the scan results. Electromagnetic simulation recreates the transmission and return process of high-speed signals across the segmented region 33, obtaining core parameters directly reflecting signal quality, such as impedance characteristics and insertion loss, and fully presenting the impact of capacitance distance changes on signal performance. This step yields continuous and quantified performance change curves, replacing manual experience judgment with objective simulation data, providing reliable data support for subsequent effective compensation distance determination.

[0025] Step S4: Determine the maximum effective compensation distance: Based on the scanning simulation results obtained in Step S3, and according to the preset signal performance acceptable judgment criteria, the maximum effective compensation distance of the bridging capacitor relative to signal line 1 is screened and determined. The preset judgment criteria in Step S4 are formulated in conjunction with high-speed PCB signal integrity design standards, while also considering impedance continuity and transmission loss requirements. The maximum effective compensation distance refers to the farthest critical distance at which the bridging capacitor can still meet signal performance requirements; it is the spatial boundary where the capacitor effectively compensates. This value is objectively derived from simulation data, rather than being manually estimated. This is the first time that a precise quantitative characterization of the effective operating distance of the bridging capacitor has been achieved, completely solving the problems of unclear effective operating distance and lack of objective basis for layout in existing technologies.

[0026] Step S5: Determine the capacitor placement: Based on the maximum effective compensation distance determined in Step S4, and combined with the actual total width of the cross-segment signal area to be compensated, the number of bridging capacitors required in the entire area and their uniform placement positions are determined through standardized calculation methods. It is evident that the compensation of cross-segment signals by bridging capacitors is regional coverage, not single-point compensation. When multiple parallel signal lines cross the same segment area 33, they can share the effective compensation range of the same capacitor. The number of capacitors is calculated based on the mathematical relationship between the maximum effective compensation distance and the area width, and the positions are determined according to uniform placement rules, ensuring no compensation blind spots and no redundant placement throughout the entire area. This forms a systematic design method for capacitor placement in multi-signal-line cross-segment scenarios, minimizing the number of capacitors used while ensuring signal quality, alleviating the space pressure of high-density wiring, and balancing performance and engineering feasibility. This is an original design logic that has never been achieved in existing technologies.

[0027] In step S1 of this invention, the bridging capacitor simulation model 2 is constructed in the form of a surface, the width of which is consistent with the width of the bridging capacitor in the target package. A corresponding capacitance value is assigned through lumped RLC boundary conditions, giving the planar model pure capacitive characteristics and achieving electrical equivalence with the actual bridging capacitor. In the PCB, the bridging capacitor is mounted on the surface of the reference plane. Its compensation effect on the signal return path is mainly manifested as planar coupling between the reference planes, rather than a three-dimensional volume effect. Modeling in the form of a surface eliminates parasitic inductance and resistance interference from irrelevant physical structures such as capacitor pins and package housings, retaining only the core capacitive coupling characteristics. Strictly matching the width of the model surface with the width of the target package ensures that the physical footprint and coupling area of ​​the simulation model are completely consistent with the capacitor in actual engineering applications, guaranteeing that the simulation results are identical to the actual PCB effect. This embodiment simplifies the model structure while maximizing simulation equivalence, avoiding interference from redundant parameters in the three-dimensional model, and providing a clean and accurate basic model for subsequent distance variable simulations.

[0028] Furthermore, in step S1, the surface is a rectangular plane, placed at the reference plane segmentation area 33 directly below signal line 1, on a projection plane parallel to the reference plane. This location is the core area where the return path breaks and impedance changes most severely when high-speed signals cross segments, and it is also the optimal position for the bridging capacitor to exert its compensation effect. From the projection view parallel to the reference plane, the orientation of the rectangular plane is perfectly matched to the actual capacitor mounting posture: the short side extends along the trace direction of signal line 1, corresponding to the length direction of the capacitor, without occupying additional trace space; the long side extends perpendicular to the trace direction, corresponding to the width direction of the capacitor. This direction is the core direction for the capacitor to electrically couple to the reference plane, and the length of the long side is strictly consistent with the target package width. From a physical structure perspective, the simulation model and the actual device are matched in all dimensions, eliminating simulation errors caused by modeling position, orientation, and size deviations, and restoring the coupling coverage of the actual capacitor.

[0029] 10nF to 470nF is a commonly used effective capacitance range for cross-segment compensation in high-speed PCBs. This range can cover the return current compensation requirements of mid-to-high frequency signals. Chip packages (0201 / 0402 / 0603) are the mainstream capacitor package forms for high-density PCB wiring. Different packages correspond to different physical widths: 0201 package width is approximately 20mil; 0402 package width is approximately 40mil; 0603 package width is approximately 60mil. During implementation, the length of the long side of the rectangular plane can be adjusted synchronously according to the target package width to achieve adaptive matching between the model and the package. In the lumped RLC boundary conditions, only the capacitance parameters are set, and the resistance and inductance are both set to 0 to simulate the compensation characteristics of an ideal cross-connect capacitor, which conforms to the actual usage logic of cross-connect capacitors in engineering. The modeling method of this invention has strong versatility and can be adapted to the capacitor selection requirements of most high-speed PCB cross-segment compensation in the industry. There is no need to redesign the modeling logic for different capacitance values ​​and packages, which improves the engineering feasibility of the method.

[0030] like Figure 2 As shown, in step S2 of this invention, the distance is the lateral distance, which is the vertical distance between the projection center of the bridging capacitor simulation model 2 on the reference plane and the projection center line of the signal line 1 on the reference plane; here, "projection center" refers to the geometric center of the rectangular plane model in the direction of the reference plane, and "projection center line" refers to the axis of the projection of the signal line 1 on the reference plane. When the lateral distance is 0, it means that the center of the bridging capacitor is aligned with the center line of the signal line 1, that is, the capacitor is located on the positive side of the signal line 1 (coinciding with the center line of the signal line 1 in the projection on the reference plane); as the lateral distance increases, the capacitor gradually moves away from the signal line 1, and its compensation capability for the signal return path decreases accordingly.

[0031] Taking a PCB operating on a DDR5 bus as an example, assume that data signal line 1 (50Ω at one end) crosses the partition region 33 between the power plane 31 and the ground plane 32. Initially, the center of the bridging capacitor is aligned with the center line of signal line 1 (lateral distance = 0). In the scanning simulation of step S3, the bridging capacitor simulation model 2 will gradually move outward along the direction perpendicular to the signal line 1. With each step, the lateral distance of the simulation model increases by one step value, corresponding to a new simulation condition, thereby allowing the system to evaluate the law of compensation effect changing with position.

[0032] The lateral distance is used as the scanning variable, rather than distances in other directions, because the primary function of the bridging capacitor is to provide a low-impedance path for signal return at the reference plane split seam. Its compensation effect is mainly affected by its offset in the direction perpendicular to the signal trace (i.e., along the split seam direction), while the offset along the signal trace direction (vertical distance) has a relatively small impact on the compensation effect and is usually negligible in actual layouts. Therefore, using the lateral distance as the scanning variable can accurately capture the key variation patterns of the compensation effect, which has clear physical significance and engineering guidance value.

[0033] The preset distance range is 0 to 200 mil. When the lateral distance is 0, the bridging capacitor is located on the positive side of signal line 1, resulting in the strongest compensation effect. As the lateral distance increases, the bridging effect of the capacitor on the signal return path gradually weakens. Based on engineering experience and simulation verification, for common high-speed signals and common PCB stack-up structures, when the lateral distance exceeds approximately 150 to 200 mil, the improvement effect of the bridging capacitor on impedance characteristics and insertion loss is usually below the acceptable level for engineering applications, and further increasing the lateral distance has no substantial compensation significance. Therefore, setting the scan upper limit to 200 mil can cover most practical engineering scenarios while avoiding meaningless over-scanning.

[0034] The selection of the step size needs to strike a balance between simulation accuracy and computational efficiency. A smaller step size results in higher resolution of the scanning results and more accurate positioning of the boundary of the maximum effective compensation distance, but this increases the number of simulations and computation time. A larger step size results in higher computational efficiency, but may reduce the accuracy of determining the maximum effective compensation distance. In this embodiment, the preset step size is set to 5mil to 50mil. For example, for an LPDDR5 signal, scanning within the range of 0 to 200mil using a 20mil step size can obtain a complete family of curves showing the variation of signal quality parameters with lateral distance, providing sufficient data for the determination in step S4, while keeping the overall simulation time within an acceptable range.

[0035] The impact of reference plane segmentation on signal integrity is mainly reflected in two dimensions: the continuity of characteristic impedance along the signal transmission path and the magnitude of signal energy loss during transmission. This invention selects impedance characteristics and insertion loss as signal quality parameters, enabling a comprehensive and objective evaluation of the compensation effect of bridging capacitors from these two dimensions.

[0036] Impedance characteristics reflect the continuity of the characteristic impedance of signal line 1 at the reference plane segmentation. When the reference plane is segmented, the equivalent transmission line parameters (decreased unit capacitance, increased unit inductance) at the segmentation point change abruptly, leading to an increase in local characteristic impedance, forming impedance discontinuities, and causing signal reflection. Connecting a bridging capacitor, by supplementing the equivalent capacitance to ground at the segmentation point, can partially restore the local characteristic impedance and reduce the amplitude of the impedance abrupt change. The impedance characteristics are obtained by extracting the time-domain reflection simulation waveform or frequency-domain impedance curve of signal line 1 at the reference plane segmentation location, and obtaining the characteristic impedance value corresponding to each distance value.

[0037] Insertion loss reflects the energy transfer efficiency of a signal from the input to the output. Reference plane splitting interrupts the return path, forcing the return current to detour, which is equivalent to introducing additional parasitic inductance into the signal transmission path, causing additional attenuation of high-frequency signals. Insertion loss is obtained by extracting the amplitude of S21 as a function of frequency from the S-parameters of signal line 1, and obtaining the insertion loss value corresponding to each distance value at the target operating frequency.

[0038] In this invention, the preset judgment criteria are: the impedance characteristics meet a preset impedance deviation threshold, and the insertion loss meets a preset loss degradation threshold. By employing a dual-criteria judgment method combining the impedance deviation threshold and the loss degradation threshold, it is possible to ensure that the determined maximum effective compensation distance meets engineering requirements in both impedance continuity and signal transmission quality dimensions.

[0039] The preset impedance deviation threshold is set to ±16% of the target characteristic impedance value. This indicator is derived from industry-standard signal integrity design specifications (such as IPC-2141 and related JEDEC standards). For a single-ended signal line 1 with a target characteristic impedance of 50Ω, the allowable range corresponding to ±16% is 42Ω to 58Ω; for a differential signal line pair with a target characteristic impedance of 100Ω, the allowable range is 84Ω to 116Ω. If the characteristic impedance at the segmented position obtained from the simulation is still within this range at a certain lateral distance, the impedance characteristics are considered to meet the requirements.

[0040] The preset loss degradation threshold is set so that the insertion loss deteriorates by no more than 1 dB relative to the ideal value when the reference plane is unsplit. A 1 dB degradation tolerance is a widely adopted engineering boundary value in high-speed digital signal design, corresponding to approximately 20.6% signal energy loss, and is explicitly reserved in the signal budget of most high-speed interfaces (such as DDR, PCIe, USB, etc.). Taking signal line 1 with a target operating frequency of 5 GHz and an ideal insertion loss of -1.2 dB as an example, if the measured S21 at a certain distance is -1.8 dB, the degradation is 0.6 dB, meeting the threshold requirement; if S21 is -2.3 dB, the degradation is 1.1 dB, exceeding the threshold, and the distance does not meet the requirements.

[0041] In the actual judgment process, all the scanning results of step S3 are organized into a curve with the horizontal distance as the horizontal axis and the impedance deviation and insertion loss degradation as the vertical axis. Starting from the minimum distance (0), the curve is traversed to the maximum value to find the maximum horizontal distance value that simultaneously satisfies the impedance deviation threshold and the loss degradation threshold, which is the maximum effective compensation distance d.

[0042] For example, for a high-speed signal line 1 (target impedance 50Ω, operating frequency 5GHz), the scan range is set from 0 to 120mil, and the scan step size is set to 20mil. The simulation software will automatically calculate the model performance at d=0mil, 20mil, 40mil, 60mil, 80mil, 100mil, and 120mil: the impedance characteristic curve and the insertion loss curve. It can be seen that the impedance scan results are: when d=0mil, the target impedance is 50Ω; when d=120mil, the impedance reaches 60 ohms; when d=80mil, the impedance is less than 58 ohms, which is within the allowable range of ±16% for the target impedance of 50Ω (42Ω to 58Ω). Figure 4 The insertion loss scan results are as follows: When d = 0 mil, the insertion loss is ideal, at which point it is -1.2 dB at 5 GHz; when d increases to 100 mil and 120 mil, the insertion loss exceeds -2.1 dB and -2.3 dB respectively, with a degradation exceeding 1 dB; when d = 80 mil, the insertion loss is close to -1.94 dB, meeting the requirement that the degradation does not exceed 1 dB. Figure 5 Therefore, the maximum lateral distance d that satisfies both of the above conditions is 80 mil; this value is the reference parameter for calculating the capacitor spacing in step S5.

[0043] After determining the maximum effective compensation distance d, for a cross-segment signal region with a certain width W (i.e., an area where multiple signal lines 1 cross the segmentation gap side by side), it is necessary to determine how many bridging capacitors to place and the specific location of each capacitor to ensure that all signal lines 1 in the region are effectively compensated. In step S5 of this invention, the formula for determining the number N of bridging capacitors is: N = ⌈W / 2d ⌉; where W is the actual width of the cross-segment signal region, d is the maximum effective compensation distance determined in step S4, and ⌈⌉ indicates rounding up. N bridging capacitors are evenly distributed in the cross-segment signal region along the direction perpendicular to the signal line 1, with a spacing not greater than 2d, and the distance between the signal lines 1 at both ends of the cross-segment signal region and the nearest bridging capacitor does not exceed the maximum effective compensation distance. The principle is as follows: Each bridging capacitor can provide effective compensation up to a distance d extending to both sides of it. Therefore, the effective coverage width of a single capacitor is 2d (extending d to both sides from the capacitor as the center). To ensure that the entire cross-segment signal region of width W is covered, the theoretical minimum number of capacitors required is W / 2d. Since the number of capacitors must be an integer, the result is rounded up to obtain N = ⌈W / 2d⌉.

[0044] To illustrate with a concrete example: Suppose a PCB has a row of DDR5 data signal lines 1, spanning a segmented signal area with a total width W = 350 mil. The simulation determines the maximum effective compensation distance d = 80 mil. Then N = ⌈350 / (2×80)⌉ = ⌈350 / 160⌉ = ⌈2.19⌉ = 3, meaning 3 bridging capacitors are needed. Spanning the segmented area 33 with a width of 350 mil, placing 3 capacitors with a uniform spacing of approximately 350 / 2 ≈ 116 mil (less than 2d = 160 mil, meeting the requirement). The distance between signal line 1 at both edges of the area and the nearest capacitor is approximately 116 / 2 ≈ 58 mil (less than d = 80 mil, meeting the requirement). Therefore, it can be confirmed that the uniform placement of 3 capacitors can achieve full coverage compensation for the entire 350 mil wide segmented signal area.

[0045] The method of this invention is applicable to the two most common high-speed signal line types and two typical reference plane splitting scenarios in PCB design. Regarding signal line types, single-ended high-speed signal lines are typically used for address / command signals, control signals, and some high-speed single-ended buses. Their signal return path is a mirrored current in the reference plane directly below the signal line, requiring high continuity of the reference plane. Differential high-speed signal pairs (such as PCIe, USB 3.0 / 4.0, HDMI, MIPI, DDR differential clock, etc.) have some resistance to interference through the common-mode rejection mechanism of differential signals. However, when the differential pair as a whole crosses the reference plane splitting area, the return paths of both signal lines are affected. Reference plane discontinuity also causes differential impedance deviation and increased common-mode noise, requiring compensation through bridging capacitors. The method of this invention is applicable to both signal line types. When establishing the simulation model, for differential signal pairs, both signal lines need to be modeled as a whole to evaluate differential impedance characteristics and differential insertion loss.

[0046] Regarding reference plane segmentation types, the segmentation boundary between the power plane and the ground plane is the most common type, typically appearing in multi-power domain PCB designs. There is a clear separation between the power copper pours and the ground plane in different power supply areas. When a signal line crosses this segmentation, the continuity of the underlying reference plane (whether ground or power) is disrupted. Segmentation boundaries between two power planes at different potentials (such as the segmentation between a 1.8V power region and a 3.3V power region) are also prevalent in multi-power PCBs. If a signal line crosses this type of segmentation with a power plane as a reference, it also faces the problem of reference plane discontinuity. Both types of segmentation scenarios are physically identical, achieving compensation by establishing a low-impedance AC bypass path at the segmentation seam using a bridging capacitor. Therefore, the method of this invention can be applied indiscriminately to both types of segmentation scenarios.

[0047] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0048] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for improving the signal quality across a PCB board by optimizing the location of bridging capacitors, applied to a signal region on a printed circuit board divided by a reference plane, characterized in that... Includes the following steps: Step S1: Establish a capacitance model; A simulation model of bridging capacitors is established for signal lines that cross the segmented region of the reference plane on a printed circuit board. Step S2: Set the distance variable; The bridging capacitor simulation model is set to a movable state, and the distance between the bridging capacitor and the signal line is used as the scanning variable; Step S3: Parametric scan simulation; Within a preset distance range, the distance variable is scanned step by step at a preset step size. Electromagnetic simulation is performed for each distance value to obtain signal quality parameters at different distances. Step S4: Determine the maximum effective compensation distance; Based on the scanning results obtained in step S3, and according to the preset judgment criteria, the maximum effective compensation distance of the bridging capacitor relative to the signal line is determined. Step S5: Determine the capacitor placement location: The number and placement of bridging capacitors are determined based on the maximum effective compensation distance and the actual width of the cross-segment signal region to be compensated.

2. The method for improving the quality of cross-segment signals on a PCB board by optimizing the position of the bridging capacitor according to claim 1, characterized in that, In step S1, the bridging capacitor simulation model is constructed in the form of a surface, the width of which is consistent with the width of the bridging capacitor of the target package, and the corresponding capacitance value is assigned through lumped RLC boundary conditions.

3. The method for improving the quality of cross-segment signals on a PCB board by optimizing the location of bridging capacitors according to claim 2, characterized in that, In step S1, the surface is a rectangular plane, which is placed in the reference plane segmentation area directly below the signal line. On the projection plane parallel to the reference plane, the short side of the rectangular plane extends along the routing direction of the signal line, and the long side is perpendicular to the routing direction of the signal line. The length of the long side is consistent with the width of the bridging capacitor of the target package.

4. The method for improving the quality of cross-segment signals on a PCB board by optimizing the position of the bridging capacitor according to claim 2, characterized in that, In step S1, the capacitance value assigned in the lumped RLC boundary condition is 10nF to 470nF; the target package is a chip package, including any one of 0201 package, 0402 package or 0603 package.

5. The method for improving the quality of cross-segment signals on a PCB board by optimizing the position of the bridging capacitor according to claim 1, characterized in that, In step S2, the distance is the lateral distance, which is the vertical distance between the projection center of the bridging capacitor simulation model on the reference plane and the projection center line of the signal line on the reference plane; the bridging capacitor simulation model moves outward along the direction perpendicular to the signal line, and the moving distance is the change in the lateral distance.

6. The method for improving the quality of cross-segment signals on a PCB board by optimizing the location of bridging capacitors according to claim 1, characterized in that, In step S3, the preset distance range is 0 to 200 mil, and the preset step size is 5 mil to 50 mil.

7. The method for improving the quality of cross-segment signals on a PCB board by optimizing the location of bridging capacitors according to claim 1, characterized in that, In step S3, the signal quality parameters include the impedance characteristics and insertion loss of the signal line at the reference plane split position; wherein, the impedance characteristics are obtained by extracting the time-domain reflection simulation waveform or frequency-domain impedance curve of the signal line at the reference plane split position to obtain the characteristic impedance value corresponding to each distance value; the insertion loss is obtained by extracting the curve of the S21 amplitude as a function of frequency in the S-parameters of the signal line to obtain the insertion loss value corresponding to each distance value at the target operating frequency.

8. The method for improving the quality of cross-segment signals on a PCB board by optimizing the position of the bridging capacitor according to claim 1, characterized in that, In step S4, the preset judgment criterion is: the impedance characteristic satisfies a preset impedance deviation threshold, and the insertion loss satisfies a preset loss degradation threshold; wherein, the preset impedance deviation threshold is ±16% of the target characteristic impedance value of the signal line; the preset loss degradation threshold is that the degradation of the insertion loss of the signal line at the target operating frequency relative to the ideal insertion loss when the reference plane is not split does not exceed 1dB; the maximum lateral distance that simultaneously satisfies the preset impedance deviation threshold and the preset loss degradation threshold is the maximum effective compensation distance.

9. The method for improving the quality of cross-segment signals on a PCB board by optimizing the position of the bridging capacitor according to claim 1, characterized in that, In step S5, the formula for determining the number N of the bridging capacitors is: N = ⌈W / 2d ⌉; where W is the actual width of the bridging segmented signal region, d is the maximum effective compensation distance determined in step S4, and ⌈⌉ represents rounding up; N bridging capacitors are evenly distributed along the direction perpendicular to the signal line, with a spacing of no more than 2d, in the segmented signal area, and the distance between the signal line at both ends of the segmented signal area and the nearest bridging capacitor does not exceed the maximum effective compensation distance.

10. The method for improving the quality of cross-segment signals on a PCB board by optimizing the location of bridging capacitors according to claim 1, characterized in that, In step S1, the signal line is a high-speed signal line, which includes a single-ended high-speed signal line or a differential high-speed signal line pair; the reference plane segmentation region includes the segmentation boundary between the power plane and the ground plane, or the segmentation boundary between two power planes with different potentials.

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