Buffer-based nand programming control method, apparatus, and storage medium

Abstract

This application discloses a buffer-based NAND programming control method, device, and storage medium. Relating to the field of data technology, the buffer-based NAND programming control method includes: if the current programming page is a secondary programming page determined by preset programming requirements, generating backup data of the page data of the current programming page from the main controller's internal cache; allocating buffer units for the backup data in the host memory buffer; storing the backup data in the buffer units, and associating the storage address of the buffer units with the programming address or host logical address of the page data of the current programming page as a mapping record. This application can achieve the technical effect of expanding the compatibility range of storage devices with different NAND Flash chips.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a buffer-based NAND programming control method, device, and storage medium. Background Technology

[0002] In the field of NAND Flash programming, some models of mainstream TLC and QLC chips have physical structure characteristics that require the programming to follow a specific order in the operation manual. Some programming pages need to be programmed twice or even three times to reach a stable state, ensuring that the data is correctly saved and not easily lost.

[0003] During secondary programming, the storage controller chip needs to re-enter the programming sequence. Furthermore, the programming sequence requires a significant gap between the first and second programming of some pages. However, the storage controller chip has limited cache resources, and most storage firmware algorithms employ a superblock binding mechanism for performance and management considerations. This results in the data on these programming pages being flushed during secondary programming and no longer existing in the controller chip's cache. Summary of the Invention

[0004] The main objective of this application is to provide a buffer-based NAND programming control method, device, and storage medium, which aims to solve the technical problem of abandoning support for some NAND flash memory due to resource constraints.

[0005] To achieve the above objectives, this application provides a buffer-based NAND programming control method, which includes:

[0006] If the current programming page is a secondary programming page determined by preset programming requirements, backup data of the page data of the current programming page is generated from the main control internal cache. In the host memory buffer, allocate buffer units for backup data; The backup data is stored in the buffer unit, and the storage address of the buffer unit is associated with the programming address or host logical address of the page data of the current programming page and stored as a mapping record.

[0007] In one embodiment, if the current programming page is a secondary programming page determined by preset programming requirements, before the step of generating backup data of the page data of the current programming page from the main controller's internal cache, the following steps are included: Determine the amount of temporary programming page data based on the preset programming requirements; Request cache resources from the host memory buffer based on the amount of temporary programming page data; If the application is successful, it will be determined whether the current programming page is a secondary programming page determined by the preset programming requirements; If the application fails, page programming is performed based on the SLC cache.

[0008] In one embodiment, the step of determining the amount of temporary programming page data according to preset programming requirements includes: Determine the primary and secondary programming identifiers for each programming page according to the preset programming requirements; In each programming page, determine the first program number corresponding to the primary programming identifier and the second program number corresponding to the secondary programming identifier; Determine the difference in sequence number between the first and second program numbers; The amount of temporary programming page data is determined based on the difference in the sequence number corresponding to each programming page.

[0009] In one embodiment, the step of generating backup data of the page data of the currently active programming page includes: Determine the unencoded raw data corresponding to the page data; Backup data is generated based on the unencoded raw data and a random seed.

[0010] In one embodiment, after the steps of storing backup data in a buffer unit and associating the storage address of the buffer unit with the programming address or host logical address of the page data of the currently located programming page as a mapping record, the method includes: Release the page data of the current programming page and the cache resources of the corresponding cache area in the main controller's internal cache; Mark the cache area as reusable.

[0011] In one embodiment, after the steps of storing backup data in a buffer unit and associating the storage address of the buffer unit with the programming address or host logical address of the page data of the currently located programming page as a mapping record, the method includes: In response to a secondary programming instruction for the target programming page, the target page data is determined in the host memory buffer based on the programming address or host logical address of the target programming page and the mapping record. The target page data is transferred to the main controller's internal cache via the DMA channel; The control storage chip performs secondary programming operations on the target programming page according to the programming sequence.

[0012] In one embodiment, after the step of transferring the target page data to the main controller's internal cache via the DMA channel, the following steps are included: Release the target buffer unit corresponding to the target page data in the host memory buffer; Mark the target buffer unit as reusable.

[0013] In one embodiment, before the step of releasing the target page data in the host memory buffer corresponding to the target buffer unit, the method includes: Determine the stability metrics of the main controller's internal cache; If the stability index is lower than the stability threshold, after the secondary programming operation of the target programming page is determined to be successful, the step of releasing the target page data in the corresponding target buffer unit in the host memory buffer is executed.

[0014] In addition, to achieve the above objectives, this application also provides a buffer-based NAND programming control device, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor. The computer program is configured to implement the steps of the buffer-based NAND programming control method described above.

[0015] In addition, to achieve the above objectives, this application also provides a storage medium, which is a computer-readable storage medium, storing a program that implements a buffer-based NAND programming control method. The program that implements the buffer-based NAND programming control method is executed by a processor to implement the steps of the buffer-based NAND programming control method as described above.

[0016] This application provides a buffer-based NAND programming control method. If the current programming page is a secondary programming page determined by preset programming requirements, backup data of the page data of the current programming page is generated from the main controller's internal cache. A buffer unit is allocated for the backup data in the host memory buffer. The backup data is stored in the buffer unit, and the storage address of the buffer unit is associated with the programming address or host logical address of the page data of the current programming page, stored as a mapping record. By generating backup data and allocating a dedicated buffer unit in the host memory buffer, the limitations of main controller cache resources and superblock binding mechanisms are eliminated. Simultaneously, the buffer unit address is associated with the programming or host logical address, ensuring accurate data retrieval during secondary programming. This method does not rely on the characteristics of the NAND flash memory and adapts to the secondary programming requirements of different NAND flash chips, effectively expanding the compatibility range of storage devices with different NAND flash chips. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating an embodiment of the buffer-based NAND programming control method of this application. Figure 2 This is a flowchart illustrating Embodiment 2 of the buffer-based NAND programming control method of this application; Figure 3 This is a schematic diagram of a programming page provided in Embodiment 3 of the buffer-based NAND programming control method of this application; Figure 4 This is a flowchart illustrating Embodiment 5 of the buffer-based NAND programming control method of this application; Figure 5 This is a flowchart illustrating Embodiment Six of the NAND programming control method based on a buffer in this application; Figure 6 This is a flowchart illustrating Embodiment Seven of the NAND programming control method based on a buffer in this application; Figure 7 This is a flowchart illustrating Embodiment 8 of the buffer-based NAND programming control method of this application; Figure 8 This is a flowchart illustrating the buffer-based NAND programming control method of this application; Figure 9 This is a schematic diagram of the structure of a buffer-based NAND programming control device in an embodiment of this application.

[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of this application and are not intended to limit this application.

[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] Currently, during secondary programming, the storage controller chip requires re-entering the programming sequence. Furthermore, the programming sequence requires a significant gap between the first and second programming of some pages. However, the storage controller chip has limited cache resources, and most storage firmware algorithms employ a superblock binding mechanism for performance and management considerations. This results in the data on these programming pages being flushed during secondary programming and no longer existing in the controller chip's cache.

[0024] The main solution of this application is as follows: If the current programming page is a secondary programming page determined by preset programming requirements, backup data of the page data of the current programming page is generated from the main controller's internal cache; a buffer unit is allocated for the backup data in the host memory buffer; the backup data is stored in the buffer unit, and the storage address of the buffer unit is associated with the programming address or host logical address of the page data of the current programming page as a mapping record. By generating backup data and allocating a dedicated buffer unit in the host memory buffer, the limitations of main controller cache resources and superblock binding mechanism are eliminated. At the same time, the buffer unit address is associated with the programming or host logical address, ensuring that data can be accurately retrieved during secondary programming without relying on the characteristics of the NAND flash memory. This adapts to the secondary programming requirements of different NAND flash memory chips and has the technical effect of expanding the compatibility range of storage devices with different NAND flash memory chips.

[0025] It should be noted that the execution subject in this embodiment can be a buffer-based NAND programming control device, or a computing service device with data processing, network communication, and program execution functions, such as a server, personal computer, virtual machine, etc., or a buffer-based NAND programming control device capable of implementing the above functions, etc. This embodiment does not specifically limit it. The following uses a buffer-based NAND programming control device as the execution subject as an example to describe this embodiment and the following embodiments.

[0026] Based on this, Embodiment 1 of this application proposes a buffer-based NAND programming control method, please refer to... Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the buffer-based NAND programming control method of this application. The buffer-based NAND programming control method includes steps S10 to S30: Step S10: If the current programming page is a secondary programming page determined by preset programming requirements, generate backup data of the page data of the current programming page from the main control internal cache.

[0027] A programming page is the smallest independent unit that carries programming logic, parameter configuration, and function definition. A secondary programming page is a programming page that meets preset programming requirements and needs to perform secondary operations. The main control unit's internal cache is a high-speed temporary storage area in the main control unit, such as the CPU or controller core, used to temporarily store the programming page data currently being edited or run. Backup data is a copy of the current programming page data, derived from the main control unit's internal cache, used for data recovery, version tracking, and fault rollback.

[0028] In this embodiment, the unique identifier of the current programming page is read, a preset list of secondary programming pages is retrieved, and the current programming page identifier is compared with the list of secondary programming pages. If they match, the full page data of the current programming page is extracted from the main controller's internal cache. Backup identifiers, such as backup timestamps, current page identifiers, and backup version numbers, are added to the extracted data. The data is then packaged into a backup file or backup data package according to a preset format to obtain the backup data of the page data of the current programming page. By reading the unique identifier of the programming page and comparing it with the preset list, the secondary programming pages that need to be backed up can be accurately located. Backup operations are only performed on pages that meet the requirements, reducing the meaningless consumption of main controller CPU and storage resources and shortening the overall backup process time.

[0029] In a first feasible implementation, step S10 may include: reading the full-dimensional identifier of the current programming page, such as page ID, physical storage address, editing session ID, last modification time, etc. Calling the secondary programming page verification rules in the preset programming requirements, multi-level judgments are performed, such as page identifier matching verification, editing permission compliance verification, and cached data integrity pre-verification. If all levels of judgment pass, the snapshot lock of the master control cache is triggered, freezing the cached data of the current programming page, generating a read-only snapshot, extracting the full data of the current programming page from the cache snapshot, and performing dual verification, such as MD5 and SHA256. The full data and dual verification codes are then AES encrypted, and a backup identifier is attached, including the backup batch number, master control device number, and verifier information, generating encrypted backup data. Through full-dimensional identifier verification, cache snapshot locking, MD5 and SHA256 dual verification, and AES encryption, malicious tampering is prevented at every stage from page location to data storage. It can identify single-byte parameter modifications and minor damage to cached data, and can accurately trace the responsible person, data source, and encryption method of each backup operation, greatly improving security.

[0030] For example, to locate the target programming page, the full-dimensional identification information of the current programming page is retrieved, including: basic identifiers such as page ID, page name, and the functional module to which the page belongs; physical layer identifiers such as the physical storage address of the programming page in the main control storage and the cache partition number; operation layer identifiers such as the last modification time and the account of the last modifier; and status identifiers such as the current editing status of the programming page and the cache data version number. Unlike locating the page using only the page ID, in high-security scenarios, the target programming page must be uniquely located using multiple dimensions such as the physical address and session ID to avoid backup errors due to duplicate page IDs or session conflicts.

[0031] Furthermore, to improve reliability, MD5 and SHA256 hash values ​​are calculated for the entire dataset, and the original results of both hash values ​​are recorded. Simultaneously, the hash values ​​are compared with a pre-defined data feature database, which stores the hash values ​​of historically valid versions of the programming page. Significant discrepancies indicate data anomalies. MD5 verification is fast and can quickly detect obvious data corruption, while SHA256 offers stronger collision resistance and can accurately identify minor data tampering. This dual verification compensates for the limitations of a single hash algorithm, enabling the detection of malicious data tampering or corrupted cache snapshots, thus avoiding invalid backups.

[0032] Furthermore, by integrating the MD5 and SHA256 hash values ​​of all data, a data packet to be encrypted is formed. The main controller's built-in hardware encryption module is then invoked to encrypt the data packet using a preset AES-256 encryption key. After encryption, the integrity of the encrypted data packet is verified. After decryption, the hash value is recalculated and compared with the original hash value to ensure no data loss during the encryption process. In high-security scenarios, software encryption is easily reverse-engineered. By using a hardware encryption module and a security chip to store the key, encryption security is significantly improved, preventing backup data from being illegally stolen and decrypted.

[0033] In a second feasible implementation, step S10 may include: identifying the page type identifier of the current programming page, quickly matching it with the secondary programming page type list in the preset programming requirements, and if the match is successful, directly reading the core data segment of the current programming page from the main controller's internal cache, which contains only logic code and key parameters, adding a minimal backup identifier to the core data segment containing only a backup timestamp and page ID, and generating compressed backup data. By extracting only the core data segment and using the minimal backup identifier, the consumption of the main controller's CPU computing power, memory, and storage resources is significantly reduced, improving execution efficiency.

[0034] In a third feasible implementation, step S10 may include: reading the complete identification information of the current programming page, such as page ID, page name, and current editing version number; retrieving the structured secondary programming page rule base in the preset programming requirements; verifying whether the current page meets all the judgment conditions for a secondary programming page; if so, locking all data of the current programming page in the main control's internal cache; extracting the full page data, including basic configuration, core programming data, and metadata; generating backup data containing the full data, checksum, backup timestamp, page identifier, and editor information; and encapsulating it according to a preset format. By extracting the full page data, the integrity of the backup is ensured. Combined with the full condition verification of the secondary programming page rules, it is possible to accurately determine whether the current programming page is a secondary programming page that needs to be backed up, ensuring that the backup operation is only performed on the target page that meets the preset requirements, thereby improving the efficiency of backup resource utilization.

[0035] The above are only three feasible implementation methods of step S10 provided in this embodiment. This embodiment does not specifically limit the specific implementation method of step S10.

[0036] Step S20: Allocate buffer units for backup data in the host memory buffer.

[0037] The Host Memory Buffer (HMB) is a dedicated logical area of ​​host system memory borrowed by an SSD (Solid State Drive) via the NVMe (Non-Volatile Memory Express) protocol. A buffer unit is an independent storage area within the host memory buffer, defined with fixed boundaries and specific attributes, dedicated to temporarily storing specific data; it is the smallest manageable storage unit within the memory buffer.

[0038] In this embodiment, core parameters such as the estimated size and format of the backup data are extracted to determine the required capacity of the buffer unit. The host memory buffer is scanned to filter for contiguous free memory blocks that meet the capacity requirements. If no free blocks are available, memory defragmentation is performed; if insufficient, low-priority non-core data is temporarily released and the process is retried. Free blocks are designated as dedicated buffer units for backup data, each with a unique ID. Allocation information is recorded in the memory management log, and the backup data processing module is informed of allocation success or failure results and related information, such as the unit ID and memory address. By extracting parameters such as the estimated size and format of the backup data, the buffer unit capacity is accurately determined, avoiding resource waste caused by indiscriminate memory allocation. Simultaneously, contiguous free memory blocks are prioritized to ensure smooth read and write operations for backup data.

[0039] In a first feasible implementation, step S20 may include: extracting the estimated size and format of the backup data, determining the required capacity of the buffer unit (e.g., including 10%-20% redundancy); scanning the host memory buffer, filtering for contiguous free memory blocks that meet the capacity requirements; if available blocks exist, designating them as buffer units, marking their physical boundaries, and setting access permissions (e.g., allowing only the backup process to read and write); assigning a unique ID to the buffer unit, recording the allocation information in the memory management log, and feeding back the allocation result to the backup data processing module. By defining physical boundaries and setting access permissions, the buffer unit is completely isolated from other data in memory, fundamentally preventing the backup data from being tampered with, overwritten, or misread during the memory transfer stage, ensuring the purity of the backup data.

[0040] For example, to ensure accurate adaptation and avoid resource waste, the backup data packet metadata is read to extract the estimated total size of the backup data, including all encapsulated content such as full page data, checksum, backup identifier, and editor information. The backup data format is also extracted, such as binary, JSON, or XML. Different data formats require different alignment space when stored in memory; for example, binary data is aligned by bytes, while JSON data requires reserved space for character encoding extension. Based on these parameters, the total capacity required for the buffer unit is determined according to the rule of estimated size + 10%-20% redundancy. If the estimated backup data size is 8KB, 8.8KB-9.6KB is allocated for binary format, and 9KB-9.8KB for JSON format, i.e., additional encoding redundancy is reserved. By determining the capacity according to the actual data characteristics, both excessive allocation leading to memory idleness and insufficient capacity to accommodate the complete backup data are avoided, balancing resource utilization and backup needs. Adjusting the capacity based on the format can prevent data storage anomalies caused by encoding alignment issues.

[0041] Furthermore, to improve data flow efficiency, the free block scanning interface of the host memory management module is invoked to perform a full scan of the memory buffer, filtering out memory blocks that meet capacity requirements, such as estimated size + 10%-20% redundancy, contiguous physical addresses, and not marked as being used by the system core. During the scan, free blocks are sorted from low to high address, prioritizing those with contiguous addresses and adjacent to the memory addresses of the backup data processing module, reducing address jump time during data read / write operations. By filtering contiguous blocks, multiple address seeks and segmented read / write operations caused by fragmented memory can be avoided, improving data flow efficiency.

[0042] Furthermore, to improve the modular collaboration efficiency of the backup process, standardized allocation results are pushed to the backup data processing module through an inter-process communication interface. If the allocation is successful, the buffer unit ID, start and end memory addresses, available capacity, and permission configuration information are returned, and the write-ready status is marked. If the allocation fails, the reason for the failure is returned, such as no consecutive free blocks meeting the conditions or permission setting failure, along with statistics on the current free resources of the memory buffer. This standardized result feedback allows the buffer unit allocation stage to seamlessly connect with subsequent stages without additional adaptation, improving the modular collaboration efficiency of the backup process.

[0043] In a second feasible implementation, step S20 may include: extracting the estimated size of the backup data and calculating the required buffer unit capacity. The host memory buffer is scanned, and the first free memory block that meets the capacity requirements is quickly allocated; this memory block serves as the buffer unit. This lightweight operation significantly reduces the consumption of CPU and memory on resource-constrained devices, preventing the main control core functions from becoming sluggish due to backup operations.

[0044] Step S30: Store the backup data in the buffer unit, and associate the storage address of the buffer unit with the programming address or host logical address of the page data of the current programming page as a mapping record.

[0045] A programming address is a logical, business-oriented address identifier for programming page data. It is a dedicated identifier used at the programming level to locate secondary programming page data. It is assigned by the programming system or controller according to preset rules and is decoupled from the specific physical storage location. A host logical address is a logical block address issued by the host, such as the CPU, to the storage controller. It is an addressing identifier for storage data at the host level, decoupled from the physical address of the flash memory chip, and assigned by the host file system or storage protocol.

[0046] In this embodiment, backup data is written to the allocated buffer unit according to a preset format via a DMA (Direct Memory Access Channel). The storage address of the buffer unit, i.e., the start address and end address, is extracted, and the length of the storage address is calculated. The associated address type is selected according to preset rules, and the programming address or host logical address of the current programming page data is extracted to generate an address mapping record. This ensures that the backup data is completely stored in the buffer unit, and establishes the association link between the buffer unit address and the programming or host logical address through the mapping record, adapting to the dual requirements of controller low-level addressing and host high-level interaction in TLC / QLC particle secondary programming scenarios.

[0047] In a first feasible implementation, step S30 may include: writing backup data to a buffer unit via a DMA channel, locking access permissions to the buffer unit during the writing process, and verifying data integrity after writing. The complete storage address of the buffer unit is extracted, including the start and end addresses, a unique ID, and the programming address or host logical address of the current programming page. A standardized mapping record is generated, containing the mapping record ID, buffer unit address, associated address, data checksum, write time, and effective status. Through data integrity verification, damage and tampering issues during data transmission can be accurately identified, preventing erroneous data from participating in secondary programming and reducing the probability of data loss and programming failure.

[0048] For example, to avoid data transmission consuming the main controller's computing power, a DMA transfer command is issued, and the DMA controller independently completes the transfer of backup data from the main controller's internal cache to the buffer unit. The main controller only monitors the transfer progress and does not participate in data movement. During the transfer, the access permissions of the buffer unit are set to be operable only by the DMA write process. After the DMA transfer is completed, the DMA channel is released first, and then the access lock state of the buffer unit is maintained. By using the DMA channel to avoid data transmission consuming the main controller's computing power, the continuity of core operations such as secondary programming command issuance and granular status monitoring is ensured. During the write process, interference from other processes is isolated to prevent data from being tampered with, overwritten, or misread, ensuring the purity of the backup data during the transfer and write phase.

[0049] Furthermore, to address the address confusion issue during parallel backup of multiple programming pages, the complete storage address of the buffer unit is extracted, including the start and end addresses and the buffer unit's unique ID. The associated address type is selected according to preset rules: if the operation is for the controller's low-level programming of TLC / QLC particles, the programming address is extracted; if it's for upper-level interaction between the host and controller, the host logical address is extracted. The start and end addresses of the buffer unit accurately define the data storage range, avoiding the ambiguity caused by using only the start address. The programming address adapts to the controller's low-level programming addressing requirements for TLC / QLC particles, while the host logical address adapts to the host's upper-level data interaction requirements, satisfying the addressing needs of both low-level operations and upper-level interactions in secondary programming scenarios.

[0050] In a second feasible implementation, step S30 may include: directly writing backup data to the buffer unit via the DMA channel, extracting the starting storage address of the buffer unit and the programming address or host logical address of the current programming page, and generating a mapping record that contains only the buffer unit starting address, programming address or host logical address, and backup data size. By only writing core data and generating mapping records, the computational power and non-volatile storage resources required by the storage controller chip are significantly reduced, avoiding main controller lag caused by complex operations.

[0051] This embodiment provides a buffer-based NAND programming control method. If the current programming page is a secondary programming page determined by preset programming requirements, backup data of the page data of the current programming page is generated from the main controller's internal cache. A buffer unit is allocated for the backup data in the host memory buffer. The backup data is stored in the buffer unit, and the storage address of the buffer unit is associated with the programming address or host logical address of the page data of the current programming page as a mapping record. By generating backup data and allocating a dedicated buffer unit in the host memory buffer, the limitations of main controller cache resources and superblock binding mechanism are eliminated. At the same time, associating the buffer unit address with the programming or host logical address ensures that data can be accurately retrieved during secondary programming without relying on the characteristics of the NAND flash memory. This method adapts to the secondary programming requirements of different NAND flash memory chips and has the technical effect of expanding the compatibility range of storage devices with different NAND flash memory chips.

[0052] Based on Embodiment 1, in Embodiment 2 of this application, the content that is the same as or similar to that in Embodiment 1 can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 , Figure 2 This is a flowchart illustrating Embodiment 2 of the NAND programming control method based on a buffer in this application. Before the step of generating backup data of the page data of the current programming page from the main controller's internal cache, if the current programming page is a secondary programming page determined by preset programming requirements, the following steps are included: Step S01: Determine the amount of temporary programming page data according to the preset programming requirements.

[0053] The amount of temporary programming page data refers to the total size of the page data corresponding to the secondary programming page that needs to be temporarily stored in the host memory buffer, based on the preset secondary programming requirements of NAND Flash chips such as TLC / QLC.

[0054] In this embodiment, based on the programming rules of NAND Flash chips such as TLC / QLC, including data format, byte alignment, and redundancy reservation requirements, combined with the chip's preset programming requirements, and by adding redundancy capacity and alignment padding capacity, the total amount of data that needs to be temporarily stored in the host memory buffer, i.e., the amount of temporary programming page data, is calculated. By accurately determining the required capacity of the buffer unit, excessive resource allocation that wastes memory or insufficient allocation that cannot accommodate data is avoided, providing a basis for subsequent cache resource requests and adapting to the storage characteristics of different chips.

[0055] Step S02: Request cache resources from the host memory buffer based on the amount of temporary programming page data.

[0056] In this embodiment, the master controller sends a resource request instruction to the host memory buffer, carrying the specified amount of temporary programming page data, data alignment requirements, and contiguous memory block requirements. The host memory buffer's memory management module scans free memory areas and filters for memory blocks that meet the capacity and contiguousness requirements. If a suitable memory block exists, the area is marked as pending allocation, and the master controller is notified of a successful request along with the memory block address or capacity information, indicating a successful cache resource request. If no suitable memory block is found, the request fails, and the current free resource status of the host memory buffer is reported. By requesting resources on demand, the free space of the host memory buffer is maximized, reducing unnecessary memory usage.

[0057] Step S03: If the application is successful, determine whether the current programming page is the secondary programming page determined by the preset programming requirements.

[0058] In this embodiment, if the host memory buffer resource allocation is successful, the unique identifier of the current programming page is extracted, a preset list of secondary programming pages is retrieved, and the current programming page identifier is compared with the list. If they match, it is determined to be a secondary programming page, and subsequent operations are performed. If they do not match, the allocated host memory buffer resource is released. By performing subsequent operations on pages that truly require secondary programming, invalid temporary storage of ordinary pages is avoided, reducing the unnecessary consumption of main control computing power and resources, and improving the overall programming process efficiency. Resources are released promptly when there is a mismatch, optimizing memory resource utilization.

[0059] Step S04: If the application fails, perform page programming based on the SLC cache.

[0060] SLC cache (Single-Level Cell Cache) is a high-speed caching mechanism in the NAND Flash storage field based on single-level cell technology. SLC (Single-Level Cell) is a NAND Flash storage architecture where each storage cell stores only 1 bit of data. Compared to TLC and QLC, it has core advantages such as faster read / write speeds, longer erase / write lifespan, and higher stability. SLC cache is not a physically independent SLC chip; rather, the storage controller temporarily simulates some storage cells of TLC / QLC chips as SLC mode, or allocates a small number of dedicated SLC areas to form a high-speed cache space for temporarily storing data to be programmed or read / written.

[0061] In this embodiment, if a resource request fails, a programming flow switching instruction is triggered, redirecting the current programming page data to the SLC cache. Upon receiving the data, the SLC cache module writes the data according to the programming timing of the SLC particles and executes page programming. By providing a fault-tolerance scheme, programming flow interruptions due to insufficient host memory buffer resources are avoided.

[0062] In this embodiment, memory resource utilization and programming process efficiency are improved through resource computation and on-demand allocation. The use of SLC cache as a fallback effectively avoids process interruptions caused by insufficient resources, ensuring stable system operation under various conditions. Leveraging the universality of SLC cache overcomes the limitations of a single NAND flash chip on the programming process, significantly expanding the compatibility of the storage device with different NAND flash chips.

[0063] Based on any of the above embodiments of this application, Embodiment 3 of this application proposes a buffer-based NAND programming control method, which can be referred to the above description and will not be repeated hereafter. Based on this, the step of determining the amount of temporary programming page data according to preset programming requirements includes: Step S011: Determine the primary programming identifier and secondary programming identifier for each programming page according to the preset programming requirements.

[0064] The primary programming identifier is a basic programming status identifier assigned by the storage controller to a NAND Flash programming page. It indicates whether the programming page has completed its first programming operation and identifies the core attributes of the first programming. It is typically a number, character code (e.g., 0x01), a status bit (e.g., bit 0 set to 1), or a structured tag. The secondary programming identifier is a unique programming status or type identifier assigned to NAND Flash programming pages that require secondary programming according to preset rules. It indicates whether the programming page requires secondary programming and identifies the specific requirements for secondary programming. It can be associated with the primary programming identifier (e.g., 0x02 indicates that it has been programmed once and requires secondary programming), or it can be an independent identifier.

[0065] In this embodiment, preset programming rules are retrieved, including the range of pages requiring secondary programming and programming trigger conditions. All pages to be programmed are traversed, and each page is assigned a basic status identifier. The primary programming identifier is based on whether the initial programming has been completed, such as 0x01 = programmed once, 0x00 = not programmed, along with basic attributes such as the physical address of the granular material and the write time of the initial programming. The secondary programming identifier is assigned to pages requiring secondary programming, such as 0x02 = requires secondary programming, and is associated with the timing requirements and data verification rules for secondary programming. These two types of identifiers distinguish between primary and secondary programming pages, providing a core basis for subsequent selection of target pages.

[0066] Step S012: Determine the first program number corresponding to the primary programming identifier and the second program number corresponding to the secondary programming identifier in each programming page.

[0067] The first program number is the initial programming execution sequence number assigned by the memory controller to the NAND Flash programming page. It is used to mark the order in which the programming page completes its first programming operation. It is usually a consecutive positive integer, incremented according to the execution order of the first programming. The second program number is the secondary programming execution sequence number assigned to the NAND Flash programming page that requires secondary programming according to preset rules. It is used to mark the order in which the secondary programming operation is performed on the programming page. It is usually a consecutive positive integer, incremented according to the execution order of the secondary programming, and must form a reasonable interval with the first program number.

[0068] In this embodiment, as Figure 3 , Figure 3 This diagram illustrates the programming page provided in Embodiment 3 of the buffer-based NAND programming control method of this application. String represents a programming page for a single programming iteration, 1st represents the first programming iteration, 2nd represents the second programming iteration, and the blue, orange, and yellow boxes indicate the programming order. In the diagram, the 6th programming iteration is the first programming iteration of WL#1 String0, and the 13th programming iteration is the second programming iteration of WL#1 String0. That is, the first program number corresponding to WL#1 String0 is 6, and the corresponding second program number is 13. By transforming the abstract programming identifier into a calculable program number, the granular programming timing requirements are grounded in numerical rules, facilitating subsequent interval quantization analysis.

[0069] Step S013: Determine the sequence number difference between the first program number and the second program number.

[0070] In this embodiment, for programming pages with secondary programming identifiers, the difference between the second program number and the first program number is calculated, such as... Figure 3 The first and second program numbers of WL#1 String0 are 6 and 13 respectively, meaning the difference is 13-6=7. This difference in program numbers visually reflects the execution interval between the first and second programming iterations, accurately identifying whether the interval meets granularity requirements and providing early warnings of timing violations.

[0071] Step S014: Determine the amount of temporary programming page data based on the difference in the sequence number corresponding to each programming page.

[0072] In this embodiment, the sequence number difference represents the number of programming operations that need to be temporarily stored, the total number of temporarily stored programming pages = difference - 1, and the amount of programming page data = the total number of temporarily stored programming pages. Data volume per page. For example... Figure 3The 6th programming iteration is the first programming iteration of WL#1 String0, and the 13th iteration is the second programming iteration of WL#1 String0. The intermediate programming iterations (7th-12th) correspond to the first programming iterations of the remaining 5 Strings (String1-String5) of WL#1 and the first programming iteration of WL#2 String0, covering a total of 6 programming pages and corresponding to 7 Strings. A mapping rule is established between the sequence number difference and the amount of temporary data. For example, the larger the difference, the longer the interval between the two programming iterations, requiring more redundant capacity to prevent data corruption. For instance, if the difference is ≤5, the amount of temporary programming page data = the amount of programming page data + 10% redundancy; if 5 < difference ≤ 10, the amount of temporary programming page data = the amount of programming page data + 15% redundancy; if the difference > 10, the amount of temporary programming page data = the amount of programming page data + 20% redundancy. Redundancy capacity is adapted based on the sequence number difference to avoid resource waste or insufficiency caused by uniform allocation, achieving refined resource management. The longer the data interval, the more redundancy is reserved, which can offset the risk of data corruption caused by long-term temporary storage and ensure the integrity of the data for secondary programming.

[0073] In this embodiment, precise page classification and differentiated resource planning improve cache resource utilization and programming efficiency. Quantified programming intervals and dynamic redundancy reservation effectively mitigate the risk of data corruption during temporary storage, ensuring stable system operation under various conditions.

[0074] Based on any of the above embodiments of this application, Embodiment 4 of this application proposes a buffer-based NAND programming control method, which can be referred to the above description and will not be repeated hereafter. Based on this, the step of generating backup data of the page data of the currently located programming page includes: Step S11: Determine the unencoded raw data corresponding to the page data.

[0075] In this embodiment, the physical address of the current secondary programming page is identified, and the page data already stored in that page is retrieved from the internal cache. A decoding operation is performed on the retrieved page data to remove preprocessing layers such as ECC error correction encoding, compression encoding, and encryption encoding, restoring the original data without any encoding processing—that is, the unencoded original data. Stripping away the encoding layers to restore the unencoded original data avoids encoding information interfering with the availability of backup data and ensures that the backup data is completely consistent with the core data from the initial programming. Unencoded original data refers to the raw data byte stream read from the physical page of the NAND flash memory or obtained from host memory without any encoding processing.

[0076] Step S12: Generate backup data based on the unencoded raw data and the random seed.

[0077] In this embodiment, a unique 64-bit random seed is generated based on a hardware random number generator or a software pseudo-random algorithm. The random seed is strongly associated with the programming address or host logical address of the target programming page. That is, after the random seed is generated, a hash algorithm is used to perform a one-way mapping between the seed and the target programming page address. The mapping identifier is synchronously stored in a non-volatile register inside the main controller, forming a one-to-one correspondence between the random seed and the programming page address. The random seed is appended to the end of the unencoded original data, forming a data block of unencoded original data + random seed. This avoids carrying redundant Parity data encoded with LDPC (Low-Density Parity-Check Code), reducing the data volume by 512 bytes per 4KB of data. A compression module is called to compress the data stored in the host memory buffer, obtaining backup data. By removing LDPC-encoded Parity data, the storage pressure on the host memory buffer is reduced. Compression of the appended data further reduces the backup data volume, solving the problem of secondary programming failure caused by insufficient host memory buffer resources in high-data-volume scenarios.

[0078] In this embodiment, encoding stripping and integrity verification ensure complete consistency between the backup data and the original data, providing a precise data source for secondary programming. Unique and tamper-resistant backup data is generated through random seeds and lightweight obfuscation, enhancing data security. High-quality backup data strengthens the fault tolerance of the NAND storage system, ensuring the continuity and stability of the secondary programming process.

[0079] Based on any of the embodiments described above, Embodiment 5 of this application proposes a buffer-based NAND programming control method, which can be referred to the above description and will not be repeated hereafter. Based on this, please refer to... Figure 4 , Figure 4 This is a flowchart illustrating Embodiment 5 of the NAND programming control method based on a buffer in this application. Following the steps of storing backup data into a buffer unit and associating the storage address of the buffer unit with the programming address or host logical address of the page data of the currently located programming page as a mapping record, the method includes: Step S301: Release the page data of the current programming page and the cache resources of the corresponding cache area in the main controller's internal cache.

[0080] In this embodiment, based on the identifier of the current programming page, the cache region address information corresponding to that programming page in the main controller's internal cache is retrieved from the stored mapping records. A cache data erasure operation is performed to completely clear all associated data within that region, including backup data, random seeds, and verification information, freeing up storage space. Accurately locating and releasing the target cache region avoids accidental operations on other cache resources, improving the accuracy of cache management. Thoroughly clearing backup data and associated information prevents the leakage of sensitive data from the programming page, enhancing the security of cached data.

[0081] Step S302: Mark the cache area as reusable.

[0082] In this embodiment, it is checked whether the clearing operation of the target cache region is completely completed to ensure that there is no residual data. The status of the cache region is then updated to reusable, and its physical address information is recorded. The released cache region is marked as reusable to avoid idle cache resources and maximize the utilization of the main controller's internal cache space.

[0083] In this embodiment, precise location and thorough erasure ensure data security and privacy. Efficient reuse maximizes the utilization of the main controller's internal cache resources, improving system operating efficiency. Standardized state management enhances system compatibility and scalability, adapting to the needs of different NAND flash memory chips and programming scenarios.

[0084] Based on any of the embodiments described above, Embodiment Six of this application proposes a buffer-based NAND programming control method, which can be referred to the above description and will not be repeated hereafter. Based on this, please refer to... Figure 6 , Figure 6 This is a flowchart illustrating Embodiment Seven of the NAND programming control method based on a buffer in this application. Following the steps of storing backup data in a buffer unit and associating the storage address of the buffer unit with the programming address or host logical address of the page data of the currently located programming page as a mapping record, the method includes: Step S303: In response to a secondary programming instruction for the target programming page, determine the target page data in the host memory buffer based on the programming address or host logical address of the target programming page and the mapping record.

[0085] In this embodiment, a secondary programming instruction for the target programming page is received, and core information is extracted from the instruction, including the physical programming address, host logical address, and secondary programming trigger timestamp of the target programming page. Based on the stored mapping record, the physical address of the buffer unit storing the backup data of that page in the host memory buffer is accurately located using the address information of the target programming page. Simultaneously, additional information, such as the compression algorithm type of the backup data, the length of the compressed data, and the pre-decompression flag, is read from the mapping record. The interval between the current trigger timestamp for secondary programming and the first programming completion timestamp is calculated to obtain the secondary programming interval duration, which is compared with a preset threshold. If the interval duration is less than the threshold, it is determined to be a short interval, and pre-decompression logic is triggered. If the interval duration is greater than or equal to the threshold, regular decompression logic is executed. If the secondary programming interval is determined to be short, a pre-decompression process is performed. The pre-decompression flag of the host memory buffer unit is checked. If the flag is not pre-decompressed, the pre-decompression action is immediately triggered. Compressed backup data is read from the host memory buffer, the decompression module is called to complete decompression, the decompressed data is written back to the pre-decompression buffer area of ​​the host memory buffer, and the pre-decompression flag is updated to "completed." If the flag indicates pre-decompression, the decompressed target data in the pre-decompression area of ​​the host memory buffer is read directly. The pre-decompressed data is marked as the target page data. If the interval is greater than or equal to a threshold, the normal decompression process is performed, a read command is sent to the host memory buffer, and the compressed target backup data in the buffer unit is read. The compressed data read from the host memory buffer is decompressed, and the decompressed data is the target page data. The interval is determined by the timestamp; for short intervals, compressed data is read from the host memory buffer in advance and pre-decompressed to avoid the delay of real-time decompression triggered by secondary programming commands.

[0086] Step S304: Transfer the target page data to the main controller's internal cache via the DMA channel.

[0087] DMA, or Direct Memory Access, is a computer hardware technology that allows data transfer between peripherals and memory directly, bypassing the CPU. In traditional data transfer, data must first be transferred from the peripheral to the CPU, and then forwarded to memory by the CPU. This process consumes CPU resources and impacts efficiency. DMA technology, however, uses a DMA controller to directly control data transfer between peripherals, such as storage devices, and memory. The CPU issues a transfer command to the DMA controller, which autonomously completes the data transfer without CPU intervention. After the transfer is complete, the DMA controller sends a completion interrupt signal to the CPU, which then performs further processing.

[0088] In this embodiment, DMA controller parameters are configured, including data transfer source address, destination address, data transfer length, and transfer priority. The master controller sends a transfer command to the DMA controller, triggering a direct transfer of target page data from the host memory buffer to the master controller's internal cache. The DMA channel enables direct data transfer from memory to cache, bypassing CPU intervention, significantly reducing system resource consumption and improving data transfer efficiency.

[0089] Step S305: Control the storage control chip to perform a secondary programming operation on the target programming page according to the programming order.

[0090] In this embodiment, programming parameters, including programming voltage, programming timing, and data write address, are sent to the memory control chip according to the target programming page's chip type and secondary programming rules. Programming sequence instructions are sent synchronously to ensure that the timing interval between secondary programming and primary programming meets the chip's preset requirements. After receiving the parameters, the memory control chip reads the target page data from its internal cache and writes the data to the target programming page of the NAND Flash chip according to the preset programming order. By performing secondary programming according to the programming parameters and the preset programming order, programming failures and chip damage caused by parameter or timing errors are avoided.

[0091] In this embodiment, pre-decompression and DMA transfer optimization are used to solve the problems of decompression delay and high CPU usage in short-interval scenarios, thereby improving the response speed of secondary programming instructions.

[0092] Based on any of the above embodiments of this application, Embodiment Seven of this application proposes a buffer-based NAND programming control method, which can be referred to the above description and will not be repeated hereafter. Based on this, please refer to... Figure 6 , Figure 6 This is a flowchart illustrating Embodiment Seven of the NAND programming control method based on a buffer in this application. After the step of transferring the target page data to the main controller's internal cache via the DMA channel, the method includes: Step S306: Release the target buffer unit corresponding to the target page data in the host memory buffer.

[0093] In this embodiment, the mapping record is retrieved to match the physical address, unit number, and occupied range of the buffer unit storing the target page data in the host memory buffer. A data erase command is sent to the host memory buffer controller, specifying the target buffer unit address, to completely erase the target page data within the target buffer unit. Based on the mapping record, the target buffer unit is accurately located, releasing only idle units after secondary programming is completed, avoiding the accidental release of buffer units containing other valid data. The target page data within the buffer unit is thoroughly cleared to prevent the residual or leakage of sensitive data related to secondary programming, while also preventing old data from interfering with the reuse of subsequent buffer units.

[0094] Step S307: Mark the target buffer unit as reusable.

[0095] In this embodiment, the release status of the target buffer unit is verified to confirm that there is no residual data, no unresolved association bindings, and no hardware anomalies, ensuring that the unit meets the reuse conditions. The status of the target buffer unit is updated to reusable. The released buffer unit is marked as reusable, enabling idle host memory buffer space to flow back quickly and improving overall resource utilization.

[0096] In this embodiment, by releasing the target buffer unit, idle resources are promptly reclaimed after secondary programming is completed. By using status markers, the released unit can quickly adapt to subsequent tasks, ensuring efficient utilization of the target buffer unit resources and further improving the stability and resource utilization of the entire secondary programming process.

[0097] Based on any of the above embodiments of this application, Embodiment Eight of this application proposes a buffer-based NAND programming control method, which can be referred to the above description and will not be repeated hereafter. Based on this, please refer to... Figure 7 , Figure 7 This is a flowchart illustrating Embodiment 8 of the buffer-based NAND programming control method of this application. Before the step of releasing the target page data in the host memory buffer corresponding to the target buffer unit, the method includes: Step S308: Determine the stability indicators of the main controller's internal cache.

[0098] The stability metrics of the main controller's internal cache are a set of key parameters used to quantitatively evaluate the hardware reliability, data consistency, and operational health of the cache chip during data storage and processing. These metrics directly determine whether the cache is in a safe-to-release state before releasing the host memory buffer unit. The core dimensions of the stability metrics include: hardware health metrics, reflecting the physical and electrical state of the cache chip itself, including bit flip rate, read / write error rate, and operating temperature; data integrity metrics, used to ensure that the secondary programming target data stored in the cache is completely consistent with the original data source and has not been tampered with or damaged, including data consistency and data content stability; and resource management efficiency metrics, reflecting the dynamic allocation and usage of cache resources, ensuring that cache space is used reasonably and without abnormal growth, including real-time occupancy rate and memory leak rate.

[0099] In this embodiment, hardware health metrics are acquired by real-time data collection of bit flip rate (number of data bit errors per unit time), read / write error rate (number of failed read / write operations per unit time), and operating temperature via the cache controller's hardware monitoring module. Data integrity metrics are also acquired, including data consistency metrics calculated by periodically performing hash comparisons on critical data stored in the cache using a data verification module; the success rate of the hash comparison reflects data consistency. Data content stability is also calculated, indicating higher stability with more consecutive reads of the same data block without changes. Resource management efficiency metrics are obtained by statistically analyzing the real-time cache occupancy rate and memory leak rate (the increase in unreleased cache space per unit time). These metrics, including hardware health, data integrity, and resource management efficiency, form a stability index. This stability index system, built from hardware, data, and resource dimensions, enables comprehensive, seamless monitoring of the main controller's internal cache, allowing for timely detection of potential hardware failures, data corruption, or resource management issues. Real-time acquisition and calculation of these metrics allow the main controller to dynamically monitor the cache's operational status, providing data support for subsequent resource management and fault warnings.

[0100] Step S309: If the stability index is lower than the stability threshold, after determining that the secondary programming operation of the target programming page is successful, the step of releasing the target page data in the host memory buffer corresponding to the target buffer unit is executed.

[0101] In one feasible approach, raw metric data, such as bit flip rate and temperature, is converted into specific scores, such as a score from 0 to 100. A weighted scoring method is used to calculate a comprehensive stability metric. For example, bit flip rate has a weight of 30%, read / write error rate has a weight of 20%, operating temperature has a weight of 10%, data consistency has a weight of 20%, data content stability has a weight of 10%, real-time utilization rate has a weight of 5%, and memory leak rate has a weight of 5%. The final comprehensive stability metric score is obtained. By applying a fixed weight to each metric, the overall stability of the cache can be objectively and comprehensively reflected.

[0102] In another possible approach, raw metrics such as bit flip rate and temperature are converted into specific scores, such as a 0-100 scale. The lifecycle status of the SSD (Solid State Drive) is read to identify its current stage: break-in period (power-on time < 100 hours, or cumulative programming cycles < 1000); normal use period (100 hours ≤ power-on time < 1000 hours, or 1000 ≤ cumulative programming cycles < 10000); aging period (power-on time ≥ 1000 hours, or cumulative programming cycles ≥ 10000). Based on the SSD's lifecycle stage, weighting is adjusted to calculate a comprehensive stability score. For example, during the break-in period, to ensure system stability in the initial startup phase, data integrity is monitored, and the weight of bit flip rate is increased to 35%, read / write error rate to 25%, and operating temperature to 15%. During the break-in period, hardware parameters are not yet fully stable, and fluctuations in hardware failure metrics such as bit flip rate and read / write error rate may be more frequent. The weighting for data consistency is reduced to 10%, and the weighting for data content stability is reduced to 5%. During the break-in period, the system has relatively low requirements for data integrity, and data errors can be corrected through subsequent reprogramming or self-healing mechanisms. The weighting for real-time occupancy rate and memory leak rate is maintained at 5%. By adjusting the evaluation focus according to the actual operation stage, a more targeted and predictive stability assessment can be provided.

[0103] In this embodiment, the overall stability score is compared with a preset stability threshold. If the score is greater than or equal to the threshold, the stability of the main controller's internal cache is deemed satisfactory, and the target buffer unit corresponding to the target page data in the host memory buffer is directly released. If the score is less than the threshold, the cache stability is deemed unsatisfactory, and a delayed release is performed, without immediately releasing the target buffer unit. A secondary programming completion signal is received from the storage control chip, and it is determined whether the secondary programming operation of the target programming page was successful. If successful, the step of releasing the target buffer unit corresponding to the target page data in the host memory buffer is executed. The release timing is determined based on cache stability to avoid data loss in unstable states.

[0104] In this embodiment, data security and integrity are ensured through cache stability metric evaluation. System stability and fault tolerance are ensured through delayed release and continuous monitoring.

[0105] For example, to help understand the implementation flow of the buffer-based NAND programming control method obtained in this embodiment in conjunction with the above embodiments, please refer to... Figure 8 , Figure 8 This is a flowchart illustrating the buffer-based NAND programming control method of this application.

[0106] As an optional approach, HMB resource allocation is performed. It is determined whether the current HMB (Host Memory Buffer) has successfully allocated sufficient resource space for data storage. If allocation fails, the SLC caching algorithm is used for writing, programming, and completion. If allocation is successful, the TLC / QLC direct programming algorithm is used for writing, programming the programming page. It is determined whether this is the first or second programming of that page. If it is the first programming, it is determined whether a second programming is needed. If not, programming is performed directly and completion is achieved. If a second programming is needed, the sufficiency of HMB resources is checked. If insufficient, the system waits for HMB resources to be released and then checks again until sufficient HMB resources are available. If sufficient, DMA (Direct Memory Access Channel) transfers data to the HMB, records the data's storage address and length in the HMB, and establishes a mapping relationship with the programming address or host logical address. Resources in the main controller's internal cache are released. Programming then proceeds and completion is achieved. If this programming is the second programming of a programming page, the mapping record is searched to find the corresponding data's storage address in the HMB. DMA is initiated to transfer the data from the HMB to the main controller's internal cache. After the transfer is complete, the corresponding cache resources in the HMB are released. Programming is then performed and completed. By utilizing the host memory buffer, the problem of abandoning support for certain NAND flash chips due to resource constraints is solved, overcoming the technical limitations of traditional solutions that involve increasing SRAM / DRAM capacity, optimizing cache replacement algorithms, adjusting programming order, or reducing bonding strength. By using the HMB, an external resource used to store the mapping table, to temporarily store programming pages, pages requiring secondary programming are dynamically identified during the first programming, data is backed up to the HMB and a mapping is established, and precise recall is achieved during the second programming, thus expanding the compatibility range of storage devices with different NAND Flash chips.

[0107] For example, in practical applications, when performing a NAND Flash programming page data writing task, the program first calls the HMB resource allocation interface to allocate resources. If HMB resource allocation fails, it proceeds to SLC. The caching algorithm's write process involves programming and completing the programming. If HMB resource allocation is successful, the TLC / QLC direct programming algorithm's write process is followed, programming the programming page and determining whether this is the first or second programming of that page. If it's the first programming, it checks if the current page requires secondary programming; if not, programming proceeds and completes. If secondary programming is required, it checks if HMB resources are sufficient. If resources are insufficient, the program suspends and listens for HMB resource release interrupts, waiting for HMB resources to be released. After HMB resources are released, data is transferred to the HMB via DMA, recording the data's storage address and length in the HMB, mapping it to the programming address or host logical address, releasing the main controller's internal cache resources, and then programming. If the current programming is determined to be the second programming of that page, the mapping record is searched to find the corresponding data's storage address in the HMB, and a DMA transfer is initiated to transfer the data from the HMB to the main controller's internal cache. After the transfer is complete, the corresponding HMB cache is released, and programming proceeds and completes.

[0108] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the buffer-based NAND programming control method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0109] This application provides a buffer-based NAND programming control device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the buffer-based NAND programming control method in Embodiment 1 above.

[0110] The following is for reference. Figure 9 This diagram illustrates a structure suitable for implementing a buffer-based NAND programming control device according to embodiments of this application. The buffer-based NAND programming control device in these embodiments may include, but is not limited to, mobile terminals such as servers, laptops, and tablets, as well as fixed terminals such as desktop computers. Figure 9 The buffer-based NAND programming control device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0111] like Figure 9As shown, the buffer-based NAND programming control device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the buffer-based NAND programming control device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the buffer-based NAND programming control device to communicate wirelessly or wiredly with other devices to exchange data. Although buffer-based NAND programming control devices with various systems are shown in the figures, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0112] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0113] The buffer-based NAND programming control device provided in this application, employing the buffer-based NAND programming control method described in the above embodiments, can solve the technical problem of abandoning support for some NAND chips due to resource constraints. Compared with the prior art, the beneficial effects of the buffer-based NAND programming control device provided in this application are the same as those of the buffer-based NAND programming control device provided in the above embodiments, and other technical features in this buffer-based NAND programming control device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0114] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0115] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0116] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the buffer-based NAND programming control method in the above embodiments.

[0117] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, radio frequency (RF), or any suitable combination thereof.

[0118] The aforementioned computer-readable storage medium may be included in a buffer-based NAND programming control device; or it may exist independently and not assembled into a buffer-based NAND programming control device.

[0119] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by a buffer-based NAND programming control device, the buffer-based NAND programming control device: if the current programming page is a secondary programming page determined by preset programming requirements, generates backup data of the page data of the current programming page from the main controller's internal cache; allocates a buffer unit for the backup data in the host memory buffer; stores the backup data in the buffer unit, and associates the storage address of the buffer unit with the programming address or host logical address of the page data of the current programming page as a mapping record.

[0120] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0121] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0122] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0123] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described buffer-based NAND programming control method, which can solve the technical problem of abandoning support for some chips due to resource constraints. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the buffer-based NAND programming control method provided in the above embodiments, and will not be repeated here.

[0124] This application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the buffer-based NAND programming control method described above.

[0125] The computer program product provided in this application can solve the technical problem of abandoning support for some particles due to resource constraints. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the buffer-based NAND programming control method provided in the above embodiments, and will not be repeated here.

[0126] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent scope of this application.

Claims

1. A buffer-based NAND programming control method, characterized in that, The buffer-based NAND programming control method includes: If the current programming page is a secondary programming page determined by preset programming requirements, backup data of the page data of the current programming page is generated from the main control internal cache. In the host memory buffer, a buffer unit is allocated for the backup data; The backup data is stored in the buffer unit, and the storage address of the buffer unit is associated with the programming address or host logical address of the page data of the current programming page and stored as a mapping record.

2. The NAND programming control method based on a buffer as described in claim 1, characterized in that, Before the step of generating backup data of the page data of the current programming page from the main control's internal cache if the current programming page is a secondary programming page determined by preset programming requirements, the following steps are included: Determine the amount of temporary programming page data based on the preset programming requirements; Request cache resources from the host memory buffer based on the amount of temporary programming page data; If the application is successful, it will be determined whether the current programming page is a secondary programming page determined by the preset programming requirements; If the application fails, page programming is performed based on the SLC cache.

3. The buffer-based NAND programming control method as described in claim 2, characterized in that, The step of determining the amount of temporary programming page data according to preset programming requirements includes: Determine the primary and secondary programming identifiers for each programming page according to the preset programming requirements; In each programming page, determine the first program number corresponding to the primary programming identifier and the second program number corresponding to the secondary programming identifier; Determine the difference in sequence number between the first and second program numbers; The amount of temporary programming page data is determined based on the difference in the sequence number corresponding to each programming page.

4. The NAND programming control method based on a buffer as described in claim 1, characterized in that, The step of generating backup data for the page data of the currently active programming page includes: Determine the unencoded raw data corresponding to the page data; Backup data is generated based on the unencoded raw data and a random seed.

5. The buffer-based NAND programming control method as described in claim 1, characterized in that, After the step of storing the backup data into the buffer unit and associating the storage address of the buffer unit with the programming address or host logical address of the page data of the current programming page as a mapping record, the following steps are included: Release the page data of the current programming page and the cache resources of the corresponding cache area in the main control's internal cache; The cache area is marked as reusable.

6. The buffer-based NAND programming control method as described in claim 1, characterized in that, After the step of storing the backup data into the buffer unit and associating the storage address of the buffer unit with the programming address or host logical address of the page data of the current programming page as a mapping record, the following steps are included: In response to a secondary programming instruction for a target programming page, the target page data is determined in the host memory buffer based on the programming address or host logical address of the target programming page and the mapping record. The target page data is transferred to the main control internal cache via a DMA channel; The control storage chip performs secondary programming operations on the target programming page according to the programming sequence.

7. The buffer-based NAND programming control method as described in claim 6, characterized in that, After the step of transferring the target page data to the main controller's internal cache via the DMA channel, the following steps are included: Release the target buffer unit corresponding to the target page data in the host memory buffer; The target buffer unit is marked as reusable.

8. The buffer-based NAND programming control method as described in claim 7, characterized in that, Before the step of releasing the target page data in the host memory buffer corresponding to the target buffer unit, the following steps are included: Determine the stability metrics of the main controller's internal cache; If the stability index is lower than the stability threshold, after the secondary programming operation of the target programming page is determined to be successful, the step of releasing the target buffer unit corresponding to the target page data in the host memory buffer is executed.

9. A buffer-based NAND programming control device, characterized in that, The buffer-based NAND programming control device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the buffer-based NAND programming control method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the buffer-based NAND programming control method as described in any one of claims 1 to 8.

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