Mcu multi-port abnormality protection control circuit
By designing a multi-port anomaly protection control circuit for an MCU, and utilizing a power supply module, a port detection module, and an anomaly detection module to detect changes in the voltage of the MCU's I/O ports, intelligent control and safety protection of the MCU's operating state are achieved, solving the problem of low intelligence in existing technologies.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI HENGSHUO SEMICON CO LTD
- Filing Date
- 2025-11-03
- Publication Date
- 2026-06-19
AI Technical Summary
Existing MCUs have low port status detection and control intelligence, and cannot effectively control the MCU's working state based on input or output status, resulting in insufficient security.
Design a multi-port anomaly protection control circuit for an MCU, including a power supply module, an MCU module, a port detection module, an anomaly detection module, and a protection module. By detecting the degree of voltage change at the MCU's I/O ports, the protection module cuts off power to protect the MCU in abnormal situations.
It enables intelligent control of the MCU's operating status based on the MCU's I/O port status, improving the security and intelligence of the MCU's multi-port functionality.
Smart Images
Figure CN122246651A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of MCU protection technology, specifically to a multi-port anomaly protection control circuit for MCUs. Background Technology
[0002] MCU, or Microcontroller Unit, also known as a single-chip microcomputer, is a microcomputer that integrates the central processing unit, memory, input / output interfaces, and other main components of a computer onto a single chip. This MCU has output and input modes for its ports and detects voltage anomalies using voltage divider and voltage comparator circuits. When a voltage anomaly occurs, the MCU stops working. However, it cannot control the MCU's operating state based on its input or output status, resulting in low intelligence, and therefore requires improvement. Summary of the Invention
[0003] This invention provides a multi-port fault protection control circuit for an MCU to solve the problems mentioned in the background art.
[0004] According to an embodiment of the present invention, an MCU multi-port anomaly protection control circuit is provided, comprising: a power supply module, an MCU module, a port detection module, an anomaly detection module, and a protection module; The power module is used to regulate the voltage of the input DC power and output the first power. The MCU module, connected to the power supply module, is used to receive the first electrical energy and connect to the IO1, IO2 and IO3 ports of the MCU under test, control the transmission path of the signal, and perform data interaction processing between the signals output from the MCU's IO1, IO2 and IO3 ports and the connected external devices. The port detection module, connected to the power module and the MCU module, receives the first electrical energy and, when it is necessary to detect the IO port status of the MCU under test connected to the MCU module, controls the MCU module to disconnect from the external device, detects whether there is an electrical signal on the IO1, IO2 and IO3 ports of the MCU under test, outputs the first detection signal when there is an electrical signal on the IO1 port of the MCU, the second detection signal when there is an electrical signal on the IO2 port of the MCU, and the third detection signal when there is an electrical signal on the IO3 port of the MCU. The anomaly detection module, connected to the port detection module and the power module, is used to sample the voltage and detect the degree of voltage change at the IO1, IO2 and IO3 ports of the MCU. When the degree of voltage change at the IO1 port of the MCU exceeds the set threshold, a first control signal is output; when the degree of voltage change at the IO2 port of the MCU exceeds the threshold, a second control signal is output; and when the degree of voltage change at the IO3 port of the MCU exceeds the threshold, a third control signal is output. When the first control signal is output and the first detection signal is received, the second control signal is output and the second detection signal is received, or the third control signal is output and the third detection signal is received, the power supply module is powered off. The protection module, connected to the MCU module and the anomaly detection module, is used to control the MCU's IO1 port to stop receiving signals when a first control signal is received, control the MCU's IO2 port to stop receiving signals when a second control signal is received, and control the MCU's IO3 port to stop receiving signals when a third control signal is received.
[0005] As a further embodiment of the present invention: the power module includes a regulated power supply, a first resistor, a first capacitor, a fifth resistor, a first power transistor, and a first switching transistor; The first terminal of the regulated power supply is connected to the drain of the first power transistor and one terminal of the first capacitor, and is connected to the gate of the first power transistor and the collector of the first switching transistor through the first resistor. The source of the first power transistor is connected to the first terminal of the fifth resistor. The emitter of the first switching transistor is connected to the other terminal of the first capacitor, the second terminal of the regulated power supply and the ground terminal. The base of the first switching transistor is connected to the abnormal detection module.
[0006] As a further embodiment of the present invention: the MCU module includes an MCU interface under test, a first analog switch, a second resistor, a third resistor, a fourth resistor, a first device port, a fifth switch, a sixth switch, a seventh switch, a second device port, and a third device port; The power supply terminal of the MCU interface under test is connected to the source of the first power transistor. The ground terminal of the MCU interface under test is connected to the emitter of the fifth, sixth, and seventh switching transistors and the second terminal of the regulated power supply. The IO1, IO2, and IO3 terminals of the MCU interface under test are connected to the third, eighth, and first terminals of the first analog switch, respectively. The sixth terminal of the first analog switch is connected to the collector of the fifth switching transistor and is connected to the first terminal of the fifth resistor, one terminal of the third resistor, and one terminal of the fourth resistor through the second resistor. The other terminal of the third resistor is connected to the collector of the sixth switching transistor and the fifth terminal of the first analog switch. The other terminal of the fourth resistor is connected to the collector of the seventh switching transistor and the thirteenth terminal of the first analog switch. The fourth, ninth, and second terminals of the first analog switch are connected to the first device interface, the second device interface, and the third device interface, respectively. The base of the fifth switching transistor is connected to the base of the sixth and seventh switching transistors.
[0007] As a further embodiment of the present invention: the port detection module includes a first push-button switch, a first diode, a second diode, a third diode, and a first logic device; The first terminal of the first push-button switch is connected to the second terminal of the fifth resistor. The second terminal of the first push-button switch is connected to the base of the sixth switching transistor and the anode of the first diode. The cathode of the first diode is connected to the cathode of the third diode and the B terminal of the first logic device. The A terminal of the first logic device is connected to the cathode of the second diode. The Y terminal of the first logic device is connected to the anode of the third diode and the abnormal detection module. The anode of the second diode is connected to the IO3 terminal of the interface of the MCU under test.
[0008] As a further embodiment of the present invention: the port detection module further includes a first detection device and a second detection device; The first input terminal of the first detection device is connected to the first input terminal of the second detection device and the second terminal of the first push-button switch. The second input terminal of the first detection device and the second input terminal of the second detection device are respectively connected to the IO2 terminal and IO1 terminal of the interface of the MCU under test. The output terminal of the first detection device and the output terminal of the second detection device are connected to the anomaly detection module.
[0009] As a further embodiment of the present invention: the protection module includes a second switch, a third switch, and a fourth switch; The collectors of the second, third, and fourth switching transistors are connected to the IO1, IO2, and IO3 terminals of the MCU interface under test, respectively. The emitter of the second switching transistor is connected to the emitters of the third and fourth switching transistors and ground. The bases of the second, third, and fourth switching transistors are connected to the anomaly detection module.
[0010] As a further embodiment of the present invention: the anomaly detection module includes a sixth resistor, a seventh resistor, a voltage change detection device, a fourth diode, a first comparator, a first reference power supply, and a second logic device. One end of the sixth resistor is connected to the IO3 terminal of the MCU interface under test, and the other end of the sixth resistor is connected to the input terminal of the voltage change detection device and grounded through the seventh resistor. The output terminal of the voltage change detection device is connected to the anode of the fourth diode. The cathode of the fourth diode is connected to the non-inverting terminal of the first comparator. The inverting terminal of the first comparator is connected to the first reference power supply. The output terminal of the first comparator is connected to the base of the fourth switching transistor and the A terminal of the second logic device. The B terminal of the second logic device is connected to the Y terminal of the first logic device. The Y terminal of the second logic device is connected to the base of the first switching transistor.
[0011] As a further embodiment of the present invention: the anomaly detection module further includes a third detection device, a fourth detection device, a third logic unit, and a fourth logic unit; The input terminals of the third and fourth detection devices are connected to the IO2 and IO1 terminals of the interface of the MCU under test, respectively. The output terminal of the third detection device is connected to the base of the third switch and the A terminal of the third logic device. The output terminal of the fourth detection device is connected to the base of the second switch and the A terminal of the fourth logic device. The B terminal of the third logic device and the B terminal of the second logic device are connected to the output terminals of the first and second detection devices, respectively. The Y terminal of the third logic device is connected to the Y terminal of the fourth logic device and the base of the first switch.
[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: The MCU multi-port abnormal protection control circuit of the present invention can be powered by a regulated power supply. The MCU module is connected to the power supply terminal and IO terminal of the MCU and the control device to realize data interaction between the MCU IO terminal and the control device. The port detection module detects whether the MCU IO terminal is an output terminal, and the abnormal detection module detects the voltage change of the MCU module IO terminal. When the voltage change of the IO terminal exceeds the set change threshold, the signal transmission of the IO terminal with the abnormal voltage change can be disconnected through the protection module. If the IO terminal is an output terminal, the power supply module will be directly controlled to perform power-off protection. The working state of the MCU can be controlled according to the input or output state of the MCU IO terminal, which has a high degree of intelligence and improves the security of the MCU multi-port. Attached Figure Description
[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0014] Figure 1 A schematic block diagram of a multi-port anomaly protection control circuit for an MCU provided in an embodiment of the present invention; Figure 2 A circuit diagram of an MCU multi-port fault protection control circuit provided in an embodiment of the present invention; Figure 3 The circuit diagram is provided for an anomaly detection module in an embodiment of the present invention. Detailed Implementation
[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0016] In one embodiment, see Figure 1 A multi-port anomaly protection control circuit for an MCU includes: a power supply module 1, an MCU module 2, a port detection module 3, an anomaly detection module 4, and a protection module 5. Specifically, power module 1 is used to regulate the voltage of the input DC power and output the first power. MCU module 2, connected to power module 1, is used to receive the first electrical energy and connect to the IO1, IO2 and IO3 ports of the MCU under test, control the transmission path of the signal, and perform data interaction processing between the signals output from the IO1, IO2 and IO3 ports of the MCU and the connected external devices. The port detection module 3 is connected to the power supply module 1 and the MCU module 2. It is used to receive the first power and, when it is necessary to detect the IO port status of the MCU under test connected to the MCU module 2, control the MCU module 2 to disconnect from the external device, detect whether there is an electrical signal at the IO1 port, IO2 port and IO3 port of the MCU under test. When there is an electrical signal at the IO1 port of the MCU, it outputs the first detection signal; when there is an electrical signal at the IO2 port of the MCU, it outputs the second detection signal; when there is an electrical signal at the IO3 port of the MCU, it outputs the third detection signal. The anomaly detection module 4, connected to the port detection module 3 and the power module 1, is used to sample the voltage and detect the voltage change of the IO1, IO2 and IO3 ports of the MCU. When the voltage change of the IO1 port of the MCU is greater than the set change threshold, a first control signal is output. When the voltage change of the IO2 port of the MCU is greater than the change threshold, a second control signal is output. When the voltage change of the IO3 port of the MCU is greater than the change threshold, a third control signal is output. When the first control signal is output and the first detection signal is received, the second control signal is output and the second detection signal is received, or the third control signal is output and the third detection signal is received, the power supply module 1 is powered off. Protection module 5, connected to MCU module 2 and anomaly detection module 4, is used to control MCU IO1 port to stop receiving signals when receiving the first control signal, control MCU IO2 port to stop receiving signals when receiving the second control signal, and control MCU IO3 port to stop receiving signals when receiving the third control signal.
[0017] In a specific embodiment, the power supply module 1 can be a power circuit composed of a regulated power supply, a field-effect transistor, and resistors, which can regulate the input DC power and control the power transmission state; the MCU module 2 can be an MCU circuit composed of an MCU interface under test, an analog switch, and a device port, which can be connected to the MCU's I / O terminal, power supply terminal, and ground terminal, and connected to the control device that needs to be controlled or provides data, and completes the data interaction between the MCU's I / O terminal and the control device through the control signal transmission path; the port detection module 3 can be a port detection circuit composed of diodes, logic devices, push-button switches, and detection devices, which controls the MCU module 2 to disconnect from the control device. The system detects the output status of the MCU's I / O terminals and performs high-level self-locking when an electrical signal is received. It identifies the I / O terminal as an output terminal by providing a high-level signal. The above-mentioned abnormal detection module 4 can be an abnormal detection circuit composed of resistors, voltage change detection devices, comparators, logic devices, etc. It can perform voltage division sampling and voltage change detection on the I / O terminals and detect the degree of voltage change by setting a change threshold, so as to control the protection module 5 to perform protection work. During the protection period, it controls the power supply status of the power module 1 according to the status of the I / O terminals. The above-mentioned protection module 5 can be a protection circuit composed of transistors to control the potential status of the I / O terminals of the MCU connected to the MCU module 2.
[0018] In this embodiment, please refer to Figure 2 and Figure 3 The power module 1 includes a regulated power supply, a first resistor R1, a first capacitor C1, a fifth resistor R5, a first power transistor Q1, and a first switching transistor V1. Specifically, the first terminal of the regulated power supply is connected to the drain of the first power transistor Q1 and one terminal of the first capacitor C1, and is connected to the gate of the first power transistor Q1 and the collector of the first switching transistor V1 through the first resistor R1. The source of the first power transistor Q1 is connected to the first terminal of the fifth resistor R5. The emitter of the first switching transistor V1 is connected to the other terminal of the first capacitor C1, the second terminal of the regulated power supply and the ground terminal. The base of the first switching transistor V1 is connected to the abnormal detection module 4.
[0019] In a specific embodiment, the aforementioned regulated power supply may be composed of a voltage regulator; the aforementioned first power transistor Q1 may be an N-channel MOSFET; and the aforementioned first switching transistor V1 may be an NPN transistor.
[0020] Furthermore, MCU module 2 includes an MCU interface under test, a first analog switch U1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first device port, a fifth switch V5, a sixth switch V6, a seventh switch V7, a second device port, and a third device port; Specifically, the power supply terminal of the MCU interface under test is connected to the source of the first power transistor Q1. The ground terminal of the MCU interface under test is connected to the emitter of the fifth switch transistor V5, the emitter of the sixth switch transistor V6, the emitter of the seventh switch transistor V7, and the second terminal of the regulated power supply. The IO1, IO2, and IO3 terminals of the MCU interface under test are connected to the third, eighth, and first terminals of the first analog switch U1, respectively. The sixth terminal of the first analog switch U1 is connected to the collector of the fifth switch transistor V5 and is connected to the first terminal of the fifth resistor R5, one terminal of the third resistor R3, and one terminal of the fourth resistor R4 through the second resistor R2. The other terminal of the third resistor R3 is connected to the collector of the sixth switch transistor V6 and the fifth terminal of the first analog switch U1. The other terminal of the fourth resistor R4 is connected to the collector of the seventh switch transistor V7 and the thirteenth terminal of the first analog switch U1. The fourth, ninth, and second terminals of the first analog switch U1 are connected to the first device interface, the second device interface, and the third device interface, respectively. The base of the fifth switch transistor V5 is connected to the base of the sixth switch transistor V6 and the base of the seventh switch transistor V7.
[0021] In a specific embodiment, the first analog switch U1 can be a CD4066 chip; the fifth switch V5, the sixth switch V6 and the seventh switch V7 can all be NPN transistors; the first device port, the second device port and the third device port are connected to the control device.
[0022] Furthermore, the port detection module 3 includes a first push button switch K1, a first diode D1, a second diode D2, a third diode D3, and a first logic device J1; Specifically, the first end of the first push button switch K1 is connected to the second end of the fifth resistor R5, the second end of the first push button switch K1 is connected to the base of the sixth switch transistor V6 and the anode of the first diode D1, the cathode of the first diode D1 is connected to the cathode of the third diode D3 and the B end of the first logic device J1, the A end of the first logic device J1 is connected to the cathode of the second diode D2, the Y end of the first logic device J1 is connected to the anode of the third diode D3 and the abnormal detection module 4, and the anode of the second diode D2 is connected to the IO3 end of the interface of the MCU under test.
[0023] In a specific embodiment, the first logic device J1 can be an AND gate, which, together with the first diode D1, the second diode D2 and the third diode D3, can perform self-locking.
[0024] Furthermore, the port detection module 3 also includes a first detection device and a second detection device; Specifically, the first input terminal of the first detection device is connected to the first input terminal of the second detection device and the second terminal of the first push button switch K1. The second input terminal of the first detection device and the second input terminal of the second detection device are respectively connected to the IO2 terminal and IO1 terminal of the MCU interface under test. The output terminal of the first detection device and the output terminal of the second detection device are connected to the anomaly detection module 4.
[0025] In a specific embodiment, the circuit structure of the first detection device and the circuit structure of the second detection device are the same as the circuit structure of the first diode D1, the second diode D2, the third diode D3 and the first logic device J1.
[0026] Furthermore, the protection module 5 includes a second switch V2, a third switch V3, and a fourth switch V4; Specifically, the collectors of the second switch V2, the third switch V3, and the fourth switch V4 are connected to the IO1, IO2, and IO3 terminals of the MCU interface under test, respectively. The emitter of the second switch V2 is connected to the emitters of the third switch V3 and the fourth switch V4 and ground. The bases of the second switch V2, the third switch V3, and the fourth switch V4 are connected to the anomaly detection module 4.
[0027] In a specific embodiment, the second switch V2, the third switch V3, and the fourth switch V4 can all be NPN transistors.
[0028] Furthermore, the anomaly detection module 4 includes a sixth resistor R6, a seventh resistor R7, a voltage change detection device, a fourth diode D4, a first comparator A1, a first reference power supply VF1, and a second logic unit J2. Specifically, one end of the sixth resistor R6 is connected to the IO3 terminal of the MCU interface under test, and the other end of the sixth resistor R6 is connected to the input terminal of the voltage change detection device and grounded through the seventh resistor R7. The output terminal of the voltage change detection device is connected to the anode of the fourth diode D4. The cathode of the fourth diode D4 is connected to the non-inverting terminal of the first comparator A1. The inverting terminal of the first comparator A1 is connected to the first reference power supply VF1. The output terminal of the first comparator A1 is connected to the base of the fourth switching transistor V4 and the A terminal of the second logic device J2. The B terminal of the second logic device J2 is connected to the Y terminal of the first logic device J1. The Y terminal of the second logic device J2 is connected to the base of the first switching transistor V1.
[0029] In a specific embodiment, the voltage change detection device can be composed of an amplification circuit consisting of an operational amplifier and a resistor, and an inverse function type differential detection circuit to amplify the signal and convert the signal into a differential signal to detect the degree of voltage change; the first comparator A1 can be an LM358; the first reference power supply VF1 provides the change threshold; the second logic device J2 can be an AND gate.
[0030] Furthermore, the anomaly detection module 4 also includes a third detection device, a fourth detection device, a third logic unit J3, and a fourth logic unit J4; Specifically, the input terminals of the third and fourth detection devices are connected to the IO2 and IO1 terminals of the interface of the MCU under test, respectively. The output terminal of the third detection device is connected to the base of the third switch V3 and the A terminal of the third logic device J3. The output terminal of the fourth detection device is connected to the base of the second switch V2 and the A terminal of the fourth logic device J4. The B terminal of the third logic device J3 and the B terminal of the second logic device J2 are connected to the output terminals of the first and second detection devices, respectively. The Y terminal of the third logic device J3 is connected to the Y terminal of the fourth logic device J4 and the base of the first switch V1.
[0031] In a specific embodiment, the circuit structure of the third detection device and the circuit structure of the fourth detection device are the same as the circuit structure of the sixth resistor R6, the seventh resistor R7, the voltage change detection device, the fourth diode D4, the first comparator A1 and the first reference power supply VF1; the third logic device J3 and the fourth logic device J4 can both be AND gates.
[0032] In this embodiment of an MCU multi-port fault protection control circuit, a regulated power supply provides first electrical energy, which is transmitted to the power supply terminals of the first analog switch U1 and the interface of the MCU under test via a first power transistor Q1. This causes the third and fourth terminals, the eighth and ninth terminals, and the first and second terminals of the first analog switch U1 to conduct. The IO1, IO2, and IO3 terminals of the interface of the MCU under test are respectively connected to the three sets of IO terminals of the connected MCU. The first device port, the second device port, and the third device port are connected to three sets of control devices so that the first analog power supply can conduct power through the first analog power supply. Switch U1 enables data interaction between the MCU's three sets of I / O pins and three sets of control devices. When it is necessary to detect the input / output status of the MCU's three sets of I / O pins, pressing the first button switch K1 turns on the fifth switch V5, the sixth switch V6, and the seventh switch V7, thereby controlling the first analog switch U1 to disconnect the circuit. Then, it individually detects whether there is an electrical signal at the I / O1, I / O2, and I / O3 pins of the MCU interface under test. When there is an electrical signal at I / O3, it indicates that I / O3 is an output pin. The first logic unit J1, in conjunction with the first diode D1, the second diode D2, and the third diode D... 3. High-level self-locking is performed. Similarly, when an electrical signal exists at IO2, the first detection device self-locks and outputs a high level. When an electrical signal exists at IO3, the second detection device self-locks and outputs a high level. Voltage division sampling and voltage change detection are performed by the sixth resistor R6, the seventh resistor R7, and the voltage change detection device. When the output signal during detection is greater than the change threshold set by the first reference power supply VF1, the first comparator A1 controls the fourth switch V4 to conduct, pulling down the potential of the IO3 terminal of the MCU interface under test. If the IO3 terminal is an output terminal at this time, the second logic device J2 will control the first... When switch V1 is turned on, the first power transistor Q1 is directly de-energized, and the MCU stops working. Similarly, the third and fourth detection devices detect the voltage change at the IO2 and IO1 terminals of the MCU interface under test, respectively. When the voltage change at the IO2 terminal is greater than the change threshold, the third switch V3 is turned on to pull down the potential of the IO2 terminal. When the voltage change at the IO1 terminal is greater than the change threshold, the second switch V2 is turned on to pull down the potential of the IO1 terminal. If the IO2 or IO1 terminal is an output terminal, the first switch V1 will also be turned on to perform power-off protection.
[0033] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0034] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A multi-port fault protection control circuit for an MCU, characterized in that, The circuit includes: a power supply module, an MCU module, a port detection module, an anomaly detection module, and a protection module; The power module is used to regulate the voltage of the input DC power and output the first power. The MCU module, connected to the power supply module, is used to receive the first electrical energy and connect to the IO1, IO2 and IO3 ports of the MCU under test, control the transmission path of the signal, and perform data interaction processing between the signals output from the MCU's IO1, IO2 and IO3 ports and the connected external devices. The port detection module, connected to the power module and the MCU module, receives the first electrical energy and, when it is necessary to detect the IO port status of the MCU under test connected to the MCU module, controls the MCU module to disconnect from the external device, detects whether there is an electrical signal on the IO1, IO2 and IO3 ports of the MCU under test, outputs the first detection signal when there is an electrical signal on the IO1 port of the MCU, the second detection signal when there is an electrical signal on the IO2 port of the MCU, and the third detection signal when there is an electrical signal on the IO3 port of the MCU. The anomaly detection module, connected to the port detection module and the power module, is used to sample the voltage and detect the degree of voltage change at the IO1, IO2 and IO3 ports of the MCU. When the degree of voltage change at the IO1 port of the MCU exceeds the set threshold, a first control signal is output; when the degree of voltage change at the IO2 port of the MCU exceeds the threshold, a second control signal is output; and when the degree of voltage change at the IO3 port of the MCU exceeds the threshold, a third control signal is output. When the first control signal is output and the first detection signal is received, the second control signal is output and the second detection signal is received, or the third control signal is output and the third detection signal is received, the power supply module is powered off. The protection module, connected to the MCU module and the anomaly detection module, is used to control the MCU's IO1 port to stop receiving signals when a first control signal is received, control the MCU's IO2 port to stop receiving signals when a second control signal is received, and control the MCU's IO3 port to stop receiving signals when a third control signal is received.
2. The MCU multi-port fault protection control circuit according to claim 1, characterized in that, The power module includes a regulated power supply, a first resistor, a first capacitor, a fifth resistor, a first power transistor, and a first switching transistor. The first terminal of the regulated power supply is connected to the drain of the first power transistor and one terminal of the first capacitor, and is connected to the gate of the first power transistor and the collector of the first switching transistor through the first resistor. The source of the first power transistor is connected to the first terminal of the fifth resistor. The emitter of the first switching transistor is connected to the other terminal of the first capacitor, the second terminal of the regulated power supply and the ground terminal. The base of the first switching transistor is connected to the abnormal detection module.
3. The MCU multi-port fault protection control circuit according to claim 2, characterized in that, The MCU module includes an MCU interface under test, a first analog switch, a second resistor, a third resistor, a fourth resistor, a first device port, a fifth switch, a sixth switch, a seventh switch, a second device port, and a third device port; The power supply terminal of the MCU interface under test is connected to the source of the first power transistor. The ground terminal of the MCU interface under test is connected to the emitter of the fifth, sixth, and seventh switching transistors and the second terminal of the regulated power supply. The IO1, IO2, and IO3 terminals of the MCU interface under test are connected to the third, eighth, and first terminals of the first analog switch, respectively. The sixth terminal of the first analog switch is connected to the collector of the fifth switching transistor and is connected to the first terminal of the fifth resistor, one terminal of the third resistor, and one terminal of the fourth resistor through the second resistor. The other terminal of the third resistor is connected to the collector of the sixth switching transistor and the fifth terminal of the first analog switch. The other terminal of the fourth resistor is connected to the collector of the seventh switching transistor and the thirteenth terminal of the first analog switch. The fourth, ninth, and second terminals of the first analog switch are connected to the first device interface, the second device interface, and the third device interface, respectively. The base of the fifth switching transistor is connected to the base of the sixth and seventh switching transistors.
4. The MCU multi-port fault protection control circuit according to claim 3, characterized in that, The port detection module includes a first push-button switch, a first diode, a second diode, a third diode, and a first logic unit; The first end of the first push button switch is connected to the second end of the fifth resistor. The second end of the first push button switch is connected to the base of the sixth switching transistor and the anode of the first diode. The cathode of the first diode is connected to the cathode of the third diode and the B terminal of the first logic device. The A terminal of the first logic device is connected to the cathode of the second diode. The Y terminal of the first logic device is connected to the anode of the third diode and the abnormal detection module. The anode of the second diode is connected to the IO3 terminal of the MCU interface under test.
5. The MCU multi-port fault protection control circuit according to claim 4, characterized in that, The port detection module further includes a first detection device and a second detection device; The first input terminal of the first detection device is connected to the first input terminal of the second detection device and the second terminal of the first push-button switch. The second input terminal of the first detection device and the second input terminal of the second detection device are respectively connected to the IO2 terminal and IO1 terminal of the MCU interface under test. The output terminal of the first detection device and the output terminal of the second detection device are connected to the anomaly detection module.
6. The MCU multi-port fault protection control circuit according to claim 5, characterized in that, The protection module includes a second switch, a third switch, and a fourth switch; The collectors of the second, third, and fourth switching transistors are connected to the IO1, IO2, and IO3 terminals of the MCU interface under test, respectively. The emitter of the second switching transistor is connected to the emitters of the third and fourth switching transistors and ground. The bases of the second, third, and fourth switching transistors are connected to the anomaly detection module.
7. The MCU multi-port fault protection control circuit according to claim 6, characterized in that, The anomaly detection module includes a sixth resistor, a seventh resistor, a voltage change detection device, a fourth diode, a first comparator, a first reference power supply, and a second logic device. One end of the sixth resistor is connected to the IO3 terminal of the MCU interface under test, and the other end of the sixth resistor is connected to the input terminal of the voltage change detection device and grounded through the seventh resistor. The output terminal of the voltage change detection device is connected to the anode of the fourth diode. The cathode of the fourth diode is connected to the non-inverting terminal of the first comparator. The inverting terminal of the first comparator is connected to the first reference power supply. The output terminal of the first comparator is connected to the base of the fourth switching transistor and the A terminal of the second logic device. The B terminal of the second logic device is connected to the Y terminal of the first logic device. The Y terminal of the second logic device is connected to the base of the first switching transistor.
8. The MCU multi-port fault protection control circuit according to claim 7, characterized in that, The anomaly detection module further includes a third detection device, a fourth detection device, a third logic unit, and a fourth logic unit; The input terminals of the third and fourth detection devices are connected to the IO2 and IO1 terminals of the interface of the MCU under test, respectively. The output terminal of the third detection device is connected to the base of the third switch and the A terminal of the third logic device. The output terminal of the fourth detection device is connected to the base of the second switch and the A terminal of the fourth logic device. The B terminal of the third logic device and the B terminal of the second logic device are connected to the output terminals of the first and second detection devices, respectively. The Y terminal of the third logic device is connected to the Y terminal of the fourth logic device and the base of the first switch.