Automatic gain controller

Abstract

This invention provides an automatic gain controller, comprising: multiple resistors connected in series between an input terminal for receiving input signals and an inverting input terminal of an operational amplifier; multiple switching switches, each having a first terminal coupled to a corresponding resistor and a second terminal coupled to the inverting input terminal, the switching switches being controlled by multiple switching signals to be turned on or off; a buffer generating a buffer signal based on the voltage at the inverting input terminal; a charge pump circuit generating a boost voltage based on the buffer signal and a clock signal; and a voltage level shifter performing voltage level conversion on the multiple control signals based on the buffer signal and the boost voltage to generate the switching signals respectively and output them to the switching switches respectively. This invention utilizes the combination of the charge pump circuit and the voltage level shifter to generate switching signals that ensure a constant on-resistance when the switching switches are on, thereby providing a constant gain for the audio amplifier and minimizing total harmonic distortion.

Description

Technical Field

[0001] This invention relates to a controller, and more particularly to an automatic gain controller. Background Technology

[0002] See Figure 1 A Class D amplifier (audio amplifier) ​​1 includes an integrating circuit 11, a signal generation circuit 12, and other necessary components. The integrating circuit 11 receives an input signal Vin (e.g., an audio signal) and generates an integrated signal Is based on the input signal Vin. The signal generation circuit 12 receives the integrated signal Is and performs pulse width modulation (PWM) and amplification on the integrated signal Is to generate an amplified signal Am, which is then output to a speaker 10, causing the speaker 10 to play a sound signal based on the amplified signal Am.

[0003] However, each switch sw1 to sw4 within the automatic gain controller 111 included in the integrating circuit 11 for controlling the gain of the Class D amplifier 1 is a transmission gate. Taking four switches sw1 to sw4 as an example, each switch sw1 to sw4 is controlled by four control signals C1 to C4 to be either turned on or off. The transmission gate is a switch composed of a P-type MOSFET and an N-type MOSFET. Because the on-resistance of each transmission gate changes with the input signal Vin, the total input resistance value (for example, when switch sw4 is on while the other switches sw1 to sw3 are off, the total input resistance value is r1 + r2 + r3 + Ron, where r1 to r3 are the resistance values ​​of resistors R1 to R3, and Ron is the on-resistance of switch sw4 (not a constant value)) also changes. This causes the Class D amplifier 1 to lack constant gain and has a large total harmonic distortion (THD), thus affecting the playback quality of the speaker 10. Although existing technology can improve the problem of large total harmonic distortion by increasing the size of each transmission gate, this method will result in the Class D amplifier 1 having a large circuit area. Summary of the Invention

[0004] Therefore, the object of the present invention is to provide an automatic gain controller in an integrating circuit for an audio amplifier, which has a constant on-resistance to enable the audio amplifier to have a constant gain, and has a small total harmonic distortion and circuit area, thereby overcoming the disadvantages of the prior art.

[0005] Therefore, the present invention provides an automatic gain controller suitable for the integrating circuit of an audio amplifier, the integrating circuit including an operational amplifier, the automatic gain controller comprising: a plurality of resistors connected in series between an input terminal and an inverting input terminal of the operational amplifier, the input terminal being used to receive an input signal; a plurality of switching switches, each of the switching switches having a first terminal coupled to a corresponding one of the resistors and a second terminal coupled to the inverting input terminal of the operational amplifier, the switching switches being controlled by a plurality of switching signals to be turned on or off; a buffer coupled to the inverting input terminal of the operational amplifier, and generating a buffer signal based on a voltage at the inverting input terminal related to the input signal; a charge pump circuit coupled to the buffer to receive the buffer signal, and generating a boost voltage based on the buffer signal and a clock signal; and a voltage level shifter coupled to the switching switches, and coupled to the buffer and the charge pump circuit to receive the buffer signal and the boost voltage respectively, and performing voltage level shifting on a plurality of control signals based on the buffer signal and the boost voltage to generate the switching signals respectively and output them to the switching switches respectively.

[0006] In some embodiments, each of the switching switches in the automatic gain controller of the present invention is an N-type metal-oxide-semiconductor field-effect transistor.

[0007] In some embodiments, the charge pump circuit of the automatic gain controller of the present invention includes: an inverting unit for receiving the clock signal and generating a first inverted signal and a second inverted signal according to the clock signal; a first transistor having a first terminal and a second terminal coupled to the buffer to receive the buffered signal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal respectively coupled to the first terminal, the control terminal, and the second terminal of the first transistor; a first capacitor having a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the inverting unit to receive the first inverted signal; and a second capacitor having a first terminal coupled to the second terminal of the second transistor, and a second terminal coupled to the inverting unit to receive the first inverted signal. The second terminal of the second inverted signal; the third transistor and the fourth transistor, each having a first terminal and a second terminal coupled to the first terminal of the second capacitor, and a control terminal coupled to the first terminal of the first capacitor; the fifth transistor and the sixth transistor, each having a first terminal and a second terminal coupled to the first terminal of the first capacitor, and a control terminal coupled to the first terminal of the second capacitor, the second terminal of the fifth transistor being coupled to the second terminal of the third transistor, the second terminal of the sixth transistor being coupled to the second terminal of the fourth transistor; and the seventh transistor, having a first terminal and a second terminal coupled to the buffer to receive the buffered signal, and a control terminal coupled to the second terminal of the fourth transistor and providing the boost voltage.

[0008] In some embodiments, the inverting unit of the automatic gain controller of the present invention includes a first inverter, a second inverter and a third inverter connected in series. The input terminal of the first inverter is used to receive the clock signal, the output terminal of the second inverter is coupled to the second terminal of the first capacitor and outputs the first inverted signal, and the output terminal of the third inverter is coupled to the second terminal of the second capacitor and outputs the second inverted signal.

[0009] In some embodiments, in the charge pump circuit of the automatic gain controller of the present invention, the first transistor, the second transistor and the seventh transistor are each N-type metal-oxide-semiconductor field-effect transistors with low dropout voltage, and the third transistor to the sixth transistor are each P-type metal-oxide-semiconductor field-effect transistors with low dropout voltage.

[0010] In some embodiments, the voltage level shifter of the automatic gain controller of the present invention includes a plurality of voltage level shifting circuits, each of which is coupled to a corresponding one of the switching switches and coupled to the buffer and the charge pump circuit to receive the buffer signal and the boost voltage respectively, and performs voltage level conversion on a corresponding one of the control signals according to the buffer signal and the boost voltage to generate a corresponding one of the switching signals and output it to the corresponding one of the switching switches.

[0011] In some embodiments, each of the voltage level shifting circuits of the automatic gain controller of the present invention includes: an inverter having an input terminal for receiving the corresponding of the control signals and an output terminal for outputting an inverted signal; a first transistor having a first terminal and a second terminal coupled to the charge pump circuit to receive the boost voltage and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal respectively coupled to the first terminal, the control terminal, and the second terminal of the first transistor; a third transistor having a first terminal and a second terminal coupled to the second terminal of the first transistor and a control terminal coupled to the buffer to receive the buffer signal; and a fourth transistor having a first terminal coupled to the second terminal of the second transistor and providing the switching signal. The second terminal of the corresponding transistor in the diagram, and a control terminal coupled to the buffer to receive the buffered signal; the fifth transistor, having a first terminal and a second terminal coupled to the second terminal of the third transistor, and a control terminal for receiving the supply voltage; the sixth transistor, having a first terminal and a second terminal coupled to the second terminal of the fourth transistor, and a control terminal for receiving the supply voltage; the seventh transistor, having a first terminal and a second terminal coupled to the second terminal of the fifth transistor, and a control terminal coupled to the output terminal of the inverter to receive the inverted signal; and the eighth transistor, having a first terminal coupled to the second terminal of the sixth transistor, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to the input terminal of the inverter.

[0012] In some embodiments, in each of the voltage level shifting circuits of the automatic gain controller of the present invention, the first to the fourth transistors are each P-type metal-oxide-semiconductor field-effect transistors, and the fifth to the eighth transistors are each N-type metal-oxide-semiconductor field-effect transistors.

[0013] In some embodiments, in each of the voltage level shifting circuits of the automatic gain controller of the present invention, the first transistor to the eighth transistor are each low-dropout transistors.

[0014] In some embodiments, the audio amplifier to which the automatic gain controller of the present invention is applied is a Class D amplifier.

[0015] Therefore, the switching signal generated by the combination of the charge pump circuit and the voltage level shifter can ensure that the switching switch has a constant on-resistance when it is turned on, thereby the audio amplifier has a constant gain and low total harmonic distortion. In this way, the present invention does not need to improve the problem of high total harmonic distortion by increasing the size of each transmission gate as required by the prior art. Moreover, all transistors in the present invention are implemented by low dropout transistors, which makes the audio amplifier have a small circuit area. Attached Figure Description

[0016] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:

[0017] Figure 1 This is a circuit block diagram illustrating an embodiment of a conventional Class D amplifier;

[0018] Figure 2 This is a circuit block diagram illustrating an embodiment of the automatic gain controller of the present invention used in an audio amplifier;

[0019] Figure 3 This is a waveform diagram illustrating a switching signal, a buffer signal, and a boost voltage in an embodiment of the present invention;

[0020] Figure 4 This is a circuit diagram illustrating a charge pump circuit according to an embodiment of the present invention;

[0021] Figure 5 This is a circuit diagram illustrating a voltage level shifting circuit in a voltage level shifter according to an embodiment of the present invention.

[0022] Figure Labels

[0023] 1 Class D amplifier

[0024] 1a Audio Amplifier

[0025] 2 Automatic Gain Controller

[0026] 10 speakers

[0027] 11 Integrating Circuit

[0028] 11a Integrating Circuit

[0029] 12 Signal Generation Circuit

[0030] 13 Operational Amplifier

[0031] 21 Buffer

[0032] 22 Charge Pump Circuit

[0033] 23 Voltage Level Shifter

[0034] 23a Voltage Level Shifting Circuit

[0035] 111 Automatic Gain Controller

[0036] 220 Inverting Unit

[0037] 221–227 First to Seventh Transistors

[0038] 228 First Capacitor

[0039] 229 Second capacitor

[0040] 230 inverter

[0041] 231-238 First to Eighth Transistors

[0042] 2201 First Inverter

[0043] 2202 Second Inverter

[0044] 2203 Third Inverter

[0045] Am amplified signal

[0046] C1~C4 control signals

[0047] CLK clock signal

[0048] Is integral signal

[0049] Iv0 inverted signal

[0050] Iv1 First Inverting Signal

[0051] Iv2 Second Inverting Signal

[0052] Iv4 Inverted signal

[0053] resistors R1 to R4

[0054] S1~S4 switching signals

[0055] Sw1~Sw4 toggle switch

[0056] SW1 to SW4 switch

[0057] Va signal

[0058] Vb buffer signal

[0059] Vcp boost voltage

[0060] Vdd supply voltage

[0061] Vin input signal Detailed Implementation

[0062] This invention will be described in detail through the following embodiments and accompanying drawings to help those skilled in the art understand the purpose, features, and effects of the invention. It should be noted that in the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should not be construed as closed terms such as "consisting of...". Additionally, the term "coupled" is intended to indicate indirect or direct coupling. Therefore, if one device is coupled to another device, this connection can be direct coupling or indirect coupling via other devices and connections. Furthermore, in the following description and claims, terms such as "first," "second," and "third" are used to distinguish between components, not to limit the components themselves or indicate a specific order of components. Before the invention is described in detail, it should be noted that in the following description, similar components in different embodiments are represented by the same designation.

[0063] See Figure 2 This invention describes an embodiment of the automatic gain controller 2 applicable to an integrating circuit 11a of an audio amplifier 1a. The audio amplifier 1a is, for example, a Class D amplifier and includes an integrating circuit 11a, a signal generation circuit 12, and other necessary components. The integrating circuit 11a is an integrator including an operational amplifier 13 and other necessary components. The integrating circuit 11a receives an input signal Vin (e.g., an audio signal) and generates an integrated signal Is at the output of the operational amplifier 13 based on the input signal Vin. The integrated signal Is is the integral of the input signal Vin over time. The signal generation circuit 12 is coupled to the output of the operational amplifier 13 to receive the integrated signal Is and performs pulse width modulation (PWM) and amplification based on the integrated signal Is to generate an amplified signal Am, which is then output to a speaker 10, causing the speaker 10 to play a sound signal based on the amplified signal Am. It should be noted that the configuration and operation of the signal generation circuit 12 are well known to those skilled in the art, and will not be described in detail here for the sake of brevity.

[0064] In this embodiment, the automatic gain controller 2 receives the input signal Vin and is coupled to an inverting input terminal of the operational amplifier 13. The automatic gain controller 2 generates an output signal based on the input signal Vin and outputs it to the inverting input terminal of the operational amplifier 13 for integration, and outputs the integrated signal Is at the output terminal of the operational amplifier 13. The automatic gain controller 2 includes multiple resistors R1, R2, R3, R4, multiple switches Sw1, Sw2, Sw3, Sw4, a buffer 21, a charge pump circuit 22, and a voltage level shifter 23.

[0065] The resistors R1 to R4 are connected in series between an input terminal for receiving the input signal Vin and the inverting input terminal of the operational amplifier 13. Each of the switching switches Sw1 to Sw4 has a first terminal coupled to a corresponding resistor R1 to R4 and a second terminal coupled to the inverting input terminal of the operational amplifier 13. For example, the first terminal and the second terminal of the switching switch Sw1 are respectively coupled to the first terminal of the resistor R1 and the inverting input terminal of the operational amplifier 13. The switching switches Sw1 to Sw4 are controlled to be turned on or off by a plurality of switching signals S1 to S4. In this embodiment, each of the switching switches Sw1 to Sw4 is an N-type metal-oxide-semiconductor field-effect transistor, and the gate of the N-type metal-oxide-semiconductor field-effect transistor receives a corresponding switching signal S1 to S4. The drain and source of the N-type metal-oxide-semiconductor field-effect transistor are respectively the first terminal and the second terminal of a corresponding switching switch Sw1 to Sw4. The number of resistors is the same as the number of switching switches, and for example, four of each, but not limited to this.

[0066] The buffer 21 is coupled to the inverting input of the operational amplifier 13 and generates a buffer signal Vb (e.g., 0-5V) based on a voltage at the inverting input related to the input signal Vin (i.e., the voltage of the aforementioned output signal). The charge pump circuit 22 is coupled to the buffer 21 to receive the buffer signal Vb and generates a boost voltage Vcp (e.g., Vcp = Vb + 5V, 5-10V) based on the buffer signal Vb and a clock signal CLK. Figure 3The diagram illustrates the waveforms of the switching signal S1, the buffer signal Vb, and the boost voltage Vcp in the embodiment described above. The symbol Va represents the signal received by the buffer 21 (i.e., the signal before the buffer signal Vb passes through the buffer 21). The clock signal CLK has the same clock as the amplified signal Am. The voltage level shifter 23 is coupled to the switching switches Sw1-Sw4 and to the buffer 21 and the charge pump circuit 22 to receive the buffer signal Vb and the boost voltage Vcp, respectively. It performs voltage level conversion on multiple control signals C1-C4 (e.g., 0-5V) based on the buffer signal Vb and the boost voltage Vcp to generate the switching signals S1-S4 (e.g., 0-10V) and output them to the switching switches Sw1-Sw4, respectively. In this way, the switching signals S1 to S4 generated by the combination of the charge pump circuit 22 and the voltage level shifter 23 can respectively make the gate-source voltage Vgs of each of the switching switches Sw1 to Sw4 a constant voltage (e.g., 5V) when they are turned on, and will not change with the input signal Vin. As a result, the switching switches Sw1 to Sw4 have constant on-resistance, so that the audio amplifier 1a has constant gain and low total harmonic distortion (THD).

[0067] Further reading Figure 4 In this embodiment, the charge pump circuit 22 includes an inverting unit 220, a first transistor 221 to a seventh transistor 227, a first capacitor 228 and a second capacitor 229.

[0068] The inverter unit 220 receives the clock signal CLK and generates a first inverted signal Iv1 and a second inverted signal Iv2 based on the clock signal CLK. In this embodiment, the inverter unit 220 includes a first inverter 2201, a second inverter 2202, and a third inverter 2203 connected in series. An input terminal of the first inverter 2201 receives the clock signal CLK and generates an inverted signal Iv0 accordingly. An input terminal of the second inverter 2202 receives the inverted signal Iv0 and generates and outputs the first inverted signal Iv1 based on the inverted signal Iv0 at one of its output terminals. The third inverter 2203 receives the first inverted signal Iv1 and generates and outputs the second inverted signal Iv2 based on the first inverted signal Iv1 at one of its output terminals.

[0069] The first transistor 221 has a first terminal and a second terminal coupled to the buffer 21 to receive the buffered signal Vb, and a control terminal. The second transistor 222 has a first terminal, a second terminal, and a control terminal respectively coupled to the first terminal, the control terminal, and the second terminal of the first transistor 221. The first capacitor 228 has a first terminal coupled to the second terminal of the first transistor 221, and a second terminal coupled to the output terminal of the second inverter 2202 to receive the first inverted signal Iv1. The second capacitor 229 has a first terminal coupled to the second terminal of the second transistor 222, and a second terminal coupled to the output terminal of the third inverter 2203 to receive the second inverted signal Iv2. The third transistor 223 and the fourth transistor 224 each have a first terminal and a second terminal coupled to the first terminal of the second capacitor 229, and a control terminal coupled to the first terminal of the first capacitor 228. The fifth transistor 225 and the sixth transistor 226 each have a first terminal and a second terminal coupled to the first terminal of the first capacitor 228, and a control terminal coupled to the first terminal of the second capacitor 229. The second terminal of the fifth transistor 225 is coupled to the second terminal of the third transistor 223. The second terminal of the sixth transistor 226 is coupled to the second terminal of the fourth transistor 224. The seventh transistor 227 has a first terminal and a second terminal coupled to the buffer 21 to receive the buffer signal Vb, and a control terminal coupled to the second terminal of the fourth transistor 224 and providing the boost voltage Vcp. In this embodiment, the first transistor 221, the second transistor 222, and the seventh transistor 227 are each N-type metal-oxide-semiconductor field-effect transistors, the seventh transistor 227 is used as a metal-oxide-semiconductor capacitor, and the third transistor 223 to the sixth transistor 226 are each P-type metal-oxide-semiconductor field-effect transistors, but are not limited thereto.

[0070] In this embodiment, the voltage level shifter 23 includes multiple independent and unconnected voltage level shifting circuits (not shown). The number of voltage level shifting circuits is the same as the number of switching switches Sw1 to Sw4, that is, the voltage level shifter 23 includes four voltage level shifting circuits. Each of the voltage level shifting circuits is coupled to a corresponding one of the switching switches Sw1 to Sw4, and coupled to the buffer 21 and the charge pump circuit 22 to receive the buffer signal Vb and the boost voltage Vcp, respectively. Based on the buffer signal Vb and the boost voltage Vcp, it performs voltage level conversion on a corresponding one of the control signals C1 to C4 to generate a corresponding one of the switching signals S1 to S4 and outputs it to the corresponding one of the switching switches Sw1 to Sw4. For example, the first voltage level shifting circuit is coupled to the switching switch Sw1, and to the buffer 21 and the charge pump circuit 22 to receive the buffer signal Vb and the boost voltage Vcp, respectively. It then performs voltage level shifting on the control signal C1 based on the buffer signal Vb and the boost voltage Vcp to generate the switching signal S1, which is output to the switching switch Sw1. The second voltage level shifting circuit is coupled to the switching switch Sw2, and to the buffer 21 and the charge pump circuit 22 to receive the buffer signal Vb and the boost voltage Vcp, respectively. It then performs voltage level shifting on the control signal C2 based on the buffer signal Vb and the boost voltage Vcp to generate the switching signal S2, which is output to the switching switch Sw2. The connection relationships and operations of subsequent voltage level shifting circuits follow the same pattern.

[0071] Further reading Figure 5 Each of the voltage level shifting circuits is as follows: Figure 5 The voltage level shifting circuit 23a is shown, which includes an inverter 230 and a first transistor 231 to an eighth transistor 238. Figure 5 In this document, the voltage level shifting circuit 23a is used as the first voltage level shifting circuit to generate the switching signal S1 to control the switching switch Sw1 as an example for related connection and operation description. The related connection and operation description of the other three voltage level shifting circuits are similar, and will not be repeated here for the sake of brevity.

[0072] The inverter 230 has an input terminal for receiving the counterpart of the control signals C1 to C4 (i.e., the control signal C1), and an output terminal for outputting an inverted signal Iv4. The first transistor 231 has a first terminal and a second terminal coupled to the charge pump circuit 22 to receive the boost voltage Vcp, and a control terminal. The second transistor 232 has a first terminal, a second terminal, and a control terminal respectively coupled to the first terminal, the control terminal, and the second terminal of the first transistor 231. The third transistor 233 has a first terminal and a second terminal coupled to the second terminal of the first transistor 231, and a control terminal coupled to the buffer 21 to receive the buffer signal Vb. The fourth transistor 234 has a first terminal coupled to the second terminal of the second transistor 232, a second terminal providing the counterpart of the switching signals S1 to S4 (i.e., the switching signal S1), and a control terminal coupled to the buffer 21 to receive the buffer signal Vb. The fifth transistor 235 has a first terminal and a second terminal coupled to the second terminal of the third transistor 233, and a control terminal for receiving a supply voltage Vdd (e.g., 5V). The sixth transistor 236 has a first terminal and a second terminal coupled to the second terminal of the fourth transistor 234, and a control terminal for receiving the supply voltage Vdd. The seventh transistor 237 has a first terminal and a second terminal coupled to the second terminal of the fifth transistor 235, and a control terminal coupled to the output terminal of the inverter 230 to receive the inverted signal Iv4. The eighth transistor 238 has a first terminal coupled to the second terminal of the sixth transistor 236, a second terminal coupled to the second terminal of the seventh transistor 237, and a control terminal coupled to the input terminal of the inverter 230. In this embodiment, the first transistor 231 to the fourth transistor 234 are each a P-type metal-oxide-semiconductor field-effect transistor, and the fifth transistor 235 to the eighth transistor 238 are each an N-type metal-oxide-semiconductor field-effect transistor, but are not limited thereto.

[0073] In summary, the present invention utilizes the switching signals S1 to S4 generated by the combination of the charge pump circuit 22 and the voltage level shifter 23 to ensure that the gate-source voltage Vgs of each of the switching switches Sw1 to Sw4 is constant when they are turned on, and does not change with the input signal Vin. This results in the switching switches Sw1 to Sw4 having constant on-resistance, thus keeping the total input resistance constant. For example, when switching switch Sw4 is turned on while the other switching switches Sw1 to Sw3 are not turned on, the total input resistance is a constant (i.e., r1 + r2 + r3 + Ron, where r1 to r3 are the resistance values ​​of resistors R1 to R3 (constant values), and Ron is the on-resistance of switching switch Sw4 (constant value)). Consequently, the audio amplifier 1a has a constant gain and low total harmonic distortion, resulting in better playback quality for the speaker 10. In this way, the present invention does not require the improvement of the large total harmonic distortion problem by increasing the size of each transmission gate as in the prior art, and all transistors in the present invention are implemented by low dropout (5V) transistors, so that the audio amplifier 1a has a small circuit area.

[0074] The present invention has been disclosed above with reference to preferred embodiments. However, those skilled in the art should understand that the embodiments are merely illustrative of the invention and should not be construed as limiting its scope. It should be noted that any variations and substitutions equivalent to the described embodiments should be considered to be within the scope of the present invention. Therefore, the scope of protection of the present invention is determined by the claims.

Claims

1. An automatic gain controller suitable for an integrating circuit of an audio amplifier, said integrating circuit comprising an operational amplifier, characterized in that, The automatic gain controller includes: Multiple resistors are connected in series between the input terminal and the inverting input terminal of the operational amplifier, the input terminal being used to receive the input signal; A plurality of switching switches, each of the switching switches having a first terminal coupled to a corresponding one of the resistors and a second terminal coupled to the inverting input of the operational amplifier, the switching switches being controlled by a plurality of switching signals to be turned on or off respectively; A buffer is coupled to the inverting input of the operational amplifier and generates a buffer signal based on the voltage of the inverting input relative to the input signal. A charge pump circuit, coupled to the buffer, receives the buffered signal and generates a boost voltage based on the buffered signal and a clock signal; and A voltage level shifter is coupled to the switching switch and to the buffer and the charge pump circuit to receive the buffer signal and the boost voltage respectively, and to perform voltage level conversion on multiple control signals according to the buffer signal and the boost voltage to generate the switching signal respectively and output it to the switching switch respectively.

2. The automatic gain controller according to claim 1, characterized in that, Each of the switching switches is an N-type metal-oxide-semiconductor field-effect transistor.

3. The automatic gain controller according to claim 1, characterized in that, The charge pump circuit includes: An inverting unit is used to receive the clock signal and generate a first inverted signal and a second inverted signal according to the clock signal; The first transistor has a first terminal, a second terminal, and a control terminal coupled to the buffer to receive the buffered signal; The second transistor has a first terminal, a second terminal, and a control terminal respectively coupled to the first terminal, the control terminal, and the second terminal of the first transistor; The first capacitor has a first end coupled to the second end of the first transistor, and a second end coupled to the inverting unit to receive the first inverted signal; The second capacitor has a first end coupled to the second terminal of the second transistor, and a second end coupled to the inverting unit to receive the second inverted signal; The third transistor and the fourth transistor each have a first terminal and a second terminal coupled to the first terminal of the second capacitor, and a control terminal coupled to the first terminal of the first capacitor. The fifth transistor and the sixth transistor each have a first terminal and a second terminal coupled to the first terminal of the first capacitor, and a control terminal coupled to the first terminal of the second capacitor. The second terminal of the fifth transistor is coupled to the second terminal of the third transistor, and the second terminal of the sixth transistor is coupled to the second terminal of the fourth transistor. The seventh transistor has a first terminal and a second terminal coupled to the buffer to receive the buffered signal, and a control terminal coupled to the second terminal of the fourth transistor and providing the boost voltage.

4. The automatic gain controller according to claim 3, characterized in that, The inverting unit includes a first inverter, a second inverter, and a third inverter connected in series. The input terminal of the first inverter is used to receive the clock signal. The output terminal of the second inverter is coupled to the second terminal of the first capacitor and outputs the first inverted signal. The output terminal of the third inverter is coupled to the second terminal of the second capacitor and outputs the second inverted signal.

5. The automatic gain controller according to claim 3, characterized in that, The first transistor, the second transistor, and the seventh transistor are each N-type metal-oxide-semiconductor field-effect transistors with low dropout voltage, and the third to the sixth transistors are each P-type metal-oxide-semiconductor field-effect transistors with low dropout voltage.

6. The automatic gain controller according to claim 1, characterized in that, The voltage level shifter includes multiple voltage level shifting circuits, each of which is coupled to a corresponding one of the switching switches and coupled to the buffer and the charge pump circuit to receive the buffer signal and the boost voltage, respectively, and performs voltage level conversion on a corresponding one of the control signals according to the buffer signal and the boost voltage to generate a corresponding one of the switching signals and output it to the corresponding one of the switching switches.

7. The automatic gain controller according to claim 6, characterized in that, Each of the voltage level shifting circuits includes: An inverter has an input for receiving the corresponding one of the control signals and an output for outputting an inverted signal; The first transistor has a first terminal, a second terminal, and a control terminal coupled to the charge pump circuit to receive the boost voltage; The second transistor has a first terminal, a second terminal, and a control terminal respectively coupled to the first terminal, the control terminal, and the second terminal of the first transistor; The third transistor has a first terminal and a second terminal coupled to the second terminal of the first transistor, and a control terminal coupled to the buffer to receive the buffer signal; The fourth transistor has a first terminal coupled to the second terminal of the second transistor, a second terminal providing the counterpart of the switching signal, and a control terminal coupled to the buffer to receive the buffer signal; The fifth transistor has a first terminal and a second terminal coupled to the second terminal of the third transistor, and a control terminal for receiving the supply voltage; The sixth transistor has a first terminal and a second terminal coupled to the second terminal of the fourth transistor, and a control terminal for receiving the supply voltage; A seventh transistor has a first terminal and a second terminal coupled to the second terminal of the fifth transistor, and a control terminal coupled to the output terminal of the inverter to receive the inverted signal; and The eighth transistor has a first terminal coupled to the second terminal of the sixth transistor, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to the input terminal of the inverter.

8. The automatic gain controller according to claim 7, characterized in that, The first to the fourth transistors are each P-type metal-oxide-semiconductor field-effect transistors, and the fifth to the eighth transistors are each N-type metal-oxide-semiconductor field-effect transistors.

9. The automatic gain controller according to claim 7, characterized in that, Each of the first to the eighth transistors is a low-dropout transistor.

10. The automatic gain controller according to claim 1, characterized in that, The audio amplifier is a Class D amplifier.

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