A comparator circuit for wide range high voltage signals

Abstract

This invention discloses a wide-range high-voltage signal comparison circuit. The key technical points of the circuit are: the comparison circuit includes a first branch and a second branch each containing a Schottky diode; a third branch and a fourth branch composed of n Schottky diodes connected in series; a first voltage divider branch; a second voltage divider branch; and a comparator. The outputs of the first and third branches are connected to form a first node, and the outputs of the second and fourth branches are connected to form a second node. The first node is connected to the first voltage divider branch, and after voltage division, it is connected to the positive input terminal of the comparator. The second node is connected to the second voltage divider branch, and after voltage division, it is connected to the negative input terminal of the comparator. The comparison circuit designed in this invention operates directly between the high-voltage power supply and global ground, which not only avoids the layout design difficulties caused by multiple power supply grounds but also effectively improves comparison accuracy.

Description

Technical Field

[0001] This invention relates to the field of high-voltage signal comparison technology in analog integrated circuits, and more specifically, to a comparison circuit for a wide range of high-voltage signals. Background Technology

[0002] The issues of frequent and slow battery charging in consumer electronics have always been a primary research topic for major manufacturers. To solve this problem, one approach is to reduce the power consumption of chips in the application and extend the charging cycle; another approach is to increase the charging voltage or current to achieve faster charging.

[0003] The commonly used PD3.0 interface standard now supplies 20V, while the PD3.1 interface standard supplies 48V. To achieve fast battery charging, high interface voltage seems unavoidable. Therefore, high-voltage current comparators are essential for the input voltage tolerance of some power management chips and the selection of input voltage in multiple power management chips. Existing technologies typically use floating power grounds to reduce the design complexity of high-voltage current comparators. However, this design makes the comparator's accuracy dependent to some extent on the choice of the floating power ground. For example, the existing technology CN120710491A provides a high-voltage power selection circuit and its control method. In this existing technology, such as... Figure 1 As shown, HVDD and HVSS are a set of floating power grounds. The potential of node A is related to the voltage value of HVDD, and the potential of node B is related to the voltage value of HVSS. The voltage difference between nodes A and B will affect the mirroring accuracy of the two sets of current mirrors NM2~NM1\NM3\NM4 and PM5~PM6, and thus affect the accuracy of the comparator. Summary of the Invention

[0004] The purpose of this invention is to provide a comparator circuit for a wide range of high-voltage signals, which solves the problem that the accuracy of existing comparators is affected by the selection of floating power supply ground.

[0005] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0006] This invention provides a comparison circuit for wide-range high-voltage signals, used to compare a first wide-range high-voltage signal and a second wide-range high-voltage signal. The comparison circuit includes a first branch with a Schottky diode, a second branch with a Schottky diode, a third branch consisting of n Schottky diodes connected in series, a fourth branch consisting of n Schottky diodes connected in series, a first voltage divider branch, a second voltage divider branch, and a comparator. The first wide-range high-voltage signal serves as the input to the first and third branches, and the second wide-range high-voltage signal serves as the input to the second and fourth branches; n is an integer greater than or equal to 2.

[0007] The output of the first branch is connected to the output of the fourth branch to form a first node, and the output of the second branch is connected to the output of the third branch to form a second node;

[0008] The first node is connected to the first voltage divider branch, and after voltage division, it is connected to the positive input terminal of the comparator. The second node is connected to the second voltage divider branch, and after voltage division, it is connected to the negative input terminal of the comparator.

[0009] In one implementation, the first voltage divider branch includes a first resistor, a second resistor, and a first current source;

[0010] The first node is connected to the positive terminal of the first current source via a first resistor in series with a second resistor, and the negative terminal of the first current source is grounded.

[0011] In one implementation, the comparator circuit further includes a fifth resistor; one end of the fifth resistor is connected to the midpoint between the first resistor and the second resistor, and the other end is connected to the positive input of the comparator.

[0012] In one implementation, the second voltage divider branch includes a third resistor, a fourth resistor, and a second current source;

[0013] The second node is connected to the positive terminal of the second current source via a third resistor in series with a fourth resistor, and the negative terminal of the second current source is grounded.

[0014] In one implementation, the comparator circuit further includes a sixth resistor; one end of the sixth resistor is connected to the midpoint between the third and fourth resistors, and the other end is connected to the negative input of the comparator.

[0015] In one implementation, the comparator includes:

[0016] The judgment component is used to determine the voltage difference between the first node and the second node;

[0017] An isolation protection device is used to isolate and protect the judgment component to prevent overpressure from occurring in the judgment component;

[0018] A switching component for controlling the switching of the comparator in response to an enable control signal in the low-voltage signal domain;

[0019] A third current source is used to provide bias current to the comparator;

[0020] A current mirror assembly is used to convert a dual-output signal into a single-output signal; and

[0021] A Schmitt trigger is used to shape a single output signal and output the comparison result of two wide-range high-voltage signals.

[0022] In one implementation, the determining component includes a first low-voltage PMOS transistor, a second low-voltage PMOS transistor, and a third low-voltage PMOS transistor;

[0023] The isolation protection device includes a first high-voltage P-type LDMOS device, a second high-voltage P-type LDMOS device, a third high-voltage P-type LDMOS device, and a seventh resistor;

[0024] The switching assembly includes a first high-voltage N-type LDMOS device, a second high-voltage N-type LDMOS device, and a third high-voltage N-type LDMOS device; wherein, the gate input of the first high-voltage N-type LDMOS device, the second high-voltage N-type LDMOS device, and the third high-voltage N-type LDMOS device is an enable control signal;

[0025] The current mirror assembly includes a first low-voltage NMOS transistor and a second low-voltage NMOS transistor;

[0026] The sources of the first and second low-voltage PMOS transistors are connected to the positive input terminal, and the source of the third low-voltage PMOS transistor is connected to the negative input terminal.

[0027] The drain of the first low-voltage PMOS transistor is connected to the source of the first high-voltage P-type LDMOS device, the drain of the second low-voltage PMOS transistor is connected to the source of the second high-voltage P-type LDMOS device, and the drain of the third low-voltage PMOS transistor is connected to the source of the third high-voltage P-type LDMOS device. The gates of the first, second, and third low-voltage PMOS transistors and the drain of the first high-voltage P-type LDMOS device are connected to one end of the seventh resistor, and the gates of the first, second, and third high-voltage P-type LDMOS devices are connected to the other end of the seventh resistor. The other end of the seventh resistor is also connected to the drain of the first high-voltage N-type LDMOS device, and the source of the first high-voltage N-type LDMOS device is connected to the positive terminal of the third current source, and the negative terminal of the third current source is grounded.

[0028] The drain of the third high-voltage P-type LDMOS device and the drain of the third high-voltage N-type LDMOS device are connected. The source of the third high-voltage N-type LDMOS device and the drain of the second low-voltage NMOS transistor are connected and then connected to the input terminal of the Schmitt trigger.

[0029] The drain of the second high-voltage P-type LDMOS device is connected to the drain of the second high-voltage N-type LDMOS device, the source of the second high-voltage N-type LDMOS device is connected to the drain and gate of the first low-voltage NMOS transistor, and the gate of the second low-voltage NMOS transistor is connected. The sources of the first low-voltage NMOS transistor and the second low-voltage NMOS transistor are grounded.

[0030] In one implementation, the comparison circuit further includes a control component connected in parallel with each Schottky diode in the third and fourth branches, which can be controlled by a switching signal, for controlling the on and off states of each Schottky diode.

[0031] In one implementation, the number of Schottky diodes in the third and fourth branches is determined by the voltage difference between the positive and negative input terminals of the comparator.

[0032] In one implementation, the comparator is a high-voltage current comparator.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] This invention compares two high-voltage signals with a wide input range. It uses a combination of Schottky diodes to form four branches for capturing the voltage range, which can then be compared using a high-voltage current comparator with a narrow input range. This allows for accurate comparison of high-voltage signals with a wide input range without generating additional floating power supply ground combinations. The comparator circuit designed in this invention operates directly between the high-voltage power supply and global ground, avoiding the layout design difficulties caused by multiple power supply grounds and effectively improving comparison accuracy. The comparator circuit provided by this invention can be used for selecting multiple power supply inputs and can also be used to prevent reverse power supply from the output to the input of the power chip. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0036] Figure 1 A schematic diagram of a high-voltage power supply height selection circuit provided for the prior art;

[0037] Figure 2 A schematic diagram of a wide-range high-voltage signal comparison circuit provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the voltage signal difference provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the high-voltage current comparator provided in an embodiment of the present invention.

[0040] Figure labels and figure descriptions:

[0041] VINP, First wide-range high-voltage signal; VINN, Second wide-range high-voltage signal; D0, Schottky diode of the first branch; D1, First Schottky diode of the third branch; D2, First Schottky diode of the fourth branch; D5, Schottky diode of the second branch; Dn, nth Schottky diode of the third branch; Dn' represents the nth Schottky diode of the fourth branch; VPP, First node; VNN, Second node; R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; R5, Fifth resistor; R6, Sixth resistor; R7, Seventh resistor; IC1, First current source; IC2 IC1, second current source; IC2, third current source; I1, comparator; VP, positive input terminal; VN, negative input terminal; P0, first low-voltage PMOS transistor; P1, second low-voltage PMOS transistor; P2, third low-voltage PMOS transistor; PD0, first high-voltage P-type LDMOS device; PD1, second high-voltage P-type LDMOS device; PD2, third high-voltage P-type LDMOS device; ND0, first high-voltage N-type LDMOS device; ND1, second high-voltage N-type LDMOS device; ND2, third high-voltage N-type LDMOS device; N1, first low-voltage NMOS transistor; N2, second low-voltage NMOS transistor; I2, Schmitt trigger. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0043] It should be noted that the terms "comprising" or "may include" used in the various embodiments of this application indicate the presence of the claimed function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in the various embodiments of this application, the terms "comprising," "having," and their cognates are intended only to indicate a specific feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or adding one or more combinations of the foregoing.

[0044] It should be understood that terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0045] The commonly used PD3.0 interface standard now supplies 20V, while the PD3.1 interface standard supplies 48V. To achieve fast battery charging, high interface voltage seems unavoidable. Therefore, high-voltage current comparators are essential for the input voltage tolerance of some power management chips and the selection of input voltage in multiple power management chips. Existing technologies typically use floating ground to reduce the design complexity of high-voltage current comparators; however, this design makes the accuracy of comparator I1 dependent to some extent on the choice of floating ground.

[0046] For example, the prior art CN120710491A provides a high-voltage power supply selection circuit and its control method. In this prior art, such as Figure 1 As shown, HVDD and HVSS are a set of floating power grounds. The potential of node A is related to the voltage value of HVDD, and the potential of node B is related to the voltage value of HVSS. The voltage difference between nodes A and B will affect the mirroring accuracy of the two sets of current mirrors NM2~NM1\NM3\NM4 and PM5~PM6, and thus affect the accuracy of comparator I1.

[0047] Therefore, in the existing technology, floating power supply ground is usually used to reduce the design difficulty of high-voltage current comparators. However, such a design makes the accuracy of comparator I1 depend to some extent on the selection of floating power supply ground. To address this issue, the comparator circuit designed in this invention operates directly between the high-voltage power supply and global ground. This not only avoids the layout design difficulty caused by multiple power supply grounds, but also effectively improves the accuracy of the comparison results.

[0048] like Figure 2As shown, this embodiment of the invention provides a comparison circuit for a wide-range high-voltage signal, used to compare a first wide-range high-voltage signal VINP and a second wide-range high-voltage signal VINN. The comparison circuit includes a first branch with a Schottky diode, a second branch with a Schottky diode, a third branch consisting of n Schottky diodes connected in series, a fourth branch consisting of n Schottky diodes connected in series, a first voltage divider branch, a second voltage divider branch, and a comparator I1. The first wide-range high-voltage signal VINP serves as the input to the first and third branches, and the second wide-range high-voltage signal VINN serves as the input to the second and fourth branches; n is an integer greater than or equal to 2.

[0049] The output of the first branch is connected to the output of the fourth branch to form the first node VPP, and the output of the second branch is connected to the output of the third branch to form the second node VNN.

[0050] The first node VPP is connected to the first voltage divider branch and then connected to the positive input terminal VP of the comparator I1 after voltage division. The second node VNN is connected to the second voltage divider branch and then connected to the negative input terminal VN of the comparator I1 after voltage division.

[0051] The working principle of the comparator circuit provided in this embodiment of the invention is as follows: Figure 2 In this circuit, VINP and VINN are two wide-range high-voltage signals. They are bridged by the Schottky diode D0 of the first branch, the first Schottky diode D1 of the third branch, the first Schottky diode D2 of the fourth branch, the nth Schottky diode Dn of the third branch, the nth Schottky diode Dn' of the fourth branch, and the Schottky diode D5 of the second branch. They are also connected by the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4. The voltage divider of the first current source IC1 and the second current source IC2 enables the first node VPP / the second node VNN to capture the wide input range of the first wide-range high-voltage signal VINP and the second wide-range high-voltage signal VINN. In other words, the voltage of the first node VPP is equal to the higher of the first wide-range high-voltage signal VINP-VthD (VthD represents the forward voltage drop of a Schottky diode) and the fourth wide-range high-voltage signal VINN-n*VthD; the voltage of the second node VNN is equal to the higher of the second wide-range high-voltage signal VINN-VthD (the voltage drop of a Schottky diode) and the third wide-range high-voltage signal VINP-n*VthD.

[0052] For example, condition 1): VINP > VINN + n * VthD: VPP = VINP - VthD, VNN = VINP - 2VthD;

[0053] Condition 2): VINN+n*VthD>VINP>VINN-n*VthD; VPP=VINP-VthD, VNN=VINN-VthD;

[0054] Condition 3): VINP <VINN-n*VthD;VPP=VINN-n*VthD,VNN=VINN-VthD。

[0055] Figure 3 The simulation verification was performed using Cadence simulation software. Figure 3 The waveform diagram shows that, under condition 2), the voltage difference between the first node VPP and the second node VNN, when VINP and VINN are close, is exactly equal to the difference between the first wide-range high-voltage signal VINP and the second wide-range high-voltage signal VINN. This yields a set of equivalent signals that reflect the magnitude relationship between the first wide-range high-voltage signal VINP and the second wide-range high-voltage signal VINN. The difference between the first node VPP and the second node VNN will not exceed n*VthD, where n is the number of Schottky diodes and VthD is the forward voltage drop of the Schottky diodes. Therefore, the required voltage withstand range of the devices is reduced when determining the magnitude relationship between the first node VPP and the second node VNN, which effectively saves costs. Figure 2 As shown, the voltages of VPP and VNN are further divided by the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4. The first resistor R1 and the third resistor R3 are not necessary. By adjusting the common-mode input of comparator I1, the first resistor R1 and the third resistor R3 can also be omitted. Since the first current source IC1 and the second current source IC2 have already limited the current of these two paths, the power consumption of the comparator circuit provided by this invention is also reduced.

[0056] Therefore, the comparator circuit provided in this embodiment of the invention forms four branches for intercepting the voltage range through a combination of Schottky diodes. Then, it can be compared by a high-voltage current comparator with a narrow input range. It can complete the accurate comparison of high-voltage signals with a wide input range without generating additional floating power supply ground combinations. The comparator circuit designed in this invention operates directly between the high-voltage power supply and global ground, avoiding the layout design difficulties caused by multiple power supply grounds, and can also effectively improve the comparison accuracy. The comparator circuit provided in this invention can be used to select multiple power supply inputs, and can also be used to prevent reverse power supply from the output to the input of the power chip.

[0057] Specifically, the first voltage divider branch includes a first resistor R1, a second resistor R2, and a first current source IC1; the first node VPP is connected to the positive terminal of the first current source IC1 via the first resistor R1 in series with the second resistor R2, and the negative terminal of the first current source IC1 is grounded.

[0058] Specifically, the comparator circuit further includes a fifth resistor R5; one end of the fifth resistor R5 is connected to the midpoint between the first resistor R1 and the second resistor R2, and the other end is connected to the positive input of the comparator I1.

[0059] Specifically, the second voltage divider branch includes a third resistor R3, a fourth resistor R4, and a second current source IC2; the second node VNN is connected to the positive terminal of the second current source IC2 via the third resistor R3 in series with the fourth resistor R4, and the negative terminal of the second current source IC2 is grounded.

[0060] Specifically, the comparator circuit further includes a sixth resistor R6; one end of the sixth resistor R6 is connected to the midpoint between the third resistor R3 and the fourth resistor R4, and the other end is connected to the negative input of the comparator I1.

[0061] Specifically, comparator I1 includes:

[0062] The judgment component is used to determine the voltage difference between the first node VPP and the second node VNN.

[0063] An isolation protection device is used to isolate and protect the judgment component to prevent overpressure from occurring in the judgment component;

[0064] A switching assembly for controlling the switching of comparator I1 in response to an enable control signal in the low-voltage signal domain;

[0065] The third current source IC3 is used to provide bias current for the comparator I1;

[0066] A current mirror assembly is used to convert a dual-output signal into a single-output signal; and

[0067] The Schmitt trigger I2 is used to shape a single output signal and output the comparison result of two wide-range high-voltage signals.

[0068] In one example, the decision component includes a first low-voltage PMOS transistor P0, a second low-voltage PMOS transistor P1, and a third low-voltage PMOS transistor P2; the isolation protection device includes a first high-voltage P-type LDMOS device PD0, a second high-voltage P-type LDMOS device PD1, a third high-voltage P-type LDMOS device PD2, and a seventh resistor R7; the switching component includes a first high-voltage N-type LDMOS device ND0, a second high-voltage N-type LDMOS device ND1, and a third high-voltage N-type LDMOS device ND2; wherein, the gate inputs of the first high-voltage N-type LDMOS device ND0, the second high-voltage N-type LDMOS device ND1, and the third high-voltage N-type LDMOS device ND2 are enable control signals; the current mirror component includes a first low-voltage NMOS transistor N1 and a second low-voltage NMOS transistor N2;

[0069] The sources of the first low-voltage PMOS transistor P0 and the second low-voltage PMOS transistor P1 are connected to the positive input terminal VP, and the source of the third low-voltage PMOS transistor P2 is connected to the negative input terminal VN.

[0070] The drain of the first low-voltage PMOS transistor P0 is connected to the source of the first high-voltage P-type LDMOS device PD0; the drain of the second low-voltage PMOS transistor P1 is connected to the source of the second high-voltage P-type LDMOS device PD1; and the drain of the third low-voltage PMOS transistor P2 is connected to the source of the third high-voltage P-type LDMOS device PD2. The gates of the first low-voltage PMOS transistor P0, the second low-voltage PMOS transistor P1, and the third low-voltage PMOS transistor P2, and the drain of the first high-voltage P-type LDMOS device PD0, are connected to one end of the seventh resistor R7. The gates of the first high-voltage P-type LDMOS device PD0, the second high-voltage P-type LDMOS device PD1, and the third high-voltage P-type LDMOS device PD2 are connected to the other end of the seventh resistor R7. The other end of the seventh resistor R7 is also connected to the drain of the first high-voltage N-type LDMOS device ND0. The source of the first high-voltage N-type LDMOS device ND0 is connected to the positive terminal of the third current source IC3, and the negative terminal of the third current source IC3 is grounded.

[0071] The drain of the third high-voltage P-type LDMOS device PD2 is connected to the drain of the third high-voltage N-type LDMOS device ND2. The source of the third high-voltage N-type LDMOS device is connected to the drain of the second low-voltage NMOS transistor N2 and then connected to the input terminal of the Schmitt trigger I2.

[0072] The drain of the second high-voltage P-type LDMOS device PD1 is connected to the drain of the second high-voltage N-type LDMOS device ND1. The source of the second high-voltage N-type LDMOS device ND1 is connected to the drain and gate of the first low-voltage NMOS transistor N1 and the gate of the second low-voltage NMOS transistor N2. The sources of the first low-voltage NMOS transistor N1 and the second low-voltage NMOS transistor N2 are grounded.

[0073] Specifically, such as Figure 4The diagram shows the structure of comparator I1 with source-level input. Resistors R5 and R6 adjust the threshold of comparator I1. Hysteresis is generated by utilizing the voltage difference across R5 / R6. P0-P2 are low-voltage PMOS transistors. Because low-voltage devices have significantly better matching performance and smaller area, they are used to match the current flowing into comparator I1 from the first node VPP and the second node VNN, thus determining the voltage difference between VPP and VNN. PD0-PD3 are high-voltage P-type LDMOS devices, isolating and protecting the low-voltage PMOS transistors to prevent overvoltage issues. Resistor R7 is the self-bias generator for the high-voltage P-type LDMOS devices. ND0-ND2 are high-voltage N-type LDMOS devices, controlled by the enable signal EN in the low-voltage signal domain, which controls the switching of comparator I1, effectively saving current consumption in the off state. The third current source IC3 provides bias current to comparator I1. The first low-voltage NMOS transistor N1 forms a current mirror structure to convert the double-ended output into a single-ended output. Then, the output signal is shaped and output through the Schmitt trigger I2 in the low-voltage domain, so that the comparison result of the two wide-range high-voltage signals can be obtained.

[0074] In some embodiments, the comparison circuit provided by the present invention further includes: a control component controllable by a switching signal connected in parallel with each Schottky diode in the third and fourth branches, for controlling the conduction and turn-off of each Schottky diode, wherein the number of Schottky diodes in the third and fourth branches is determined by the voltage difference between the positive input terminal VP and the negative input terminal VN of the comparator I1.

[0075] The number of Schottky diodes in the third and fourth branches are both n, where n is an integer greater than 2. However, based on current common manufacturing processes, the gate oxide withstand voltage of these devices is typically around 5V. Therefore, to ensure the advantages of this invention, n must generally be (n-1)*VthD < 5V, where VthD is the forward voltage drop of the Schottky diode, typically around 0.3V~0.4V, so n must be an integer less than 13. In summary, in practical applications, the value of n is a positive integer greater than 2 and less than 13. The voltage range of VINP and VINN can be 0~V. DMAX (V) DMAX (This refers to the maximum operating voltage of the Schottky diode). Depending on the manufacturing process, there are usually different Schottky diodes that support around 10V, 20V, and 80V. You can select the appropriate type of Schottky diode based on the range of VINP and VINN signals that need to be processed.

[0076] Conventional high-voltage current comparators can compare two high-voltage signals with a voltage difference not exceeding 5V. This is achieved by drawing current from each of the two high-voltage signals with a voltage difference not exceeding 5V using an internal current source. However, due to the low gate oxide withstand voltage of MOS devices in conventional manufacturing processes, the voltage difference between the two input circuits must not exceed 5V. Therefore, directly using this comparator cannot perform direct comparison of high-voltage signals with a wide input range. This invention utilizes a diode combination to preprocess the high-voltage signals with a wide input range before employing a high-voltage current comparator to complete the comparison of the high-voltage signals with a wide input range.

[0077] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A comparison circuit of wide-range high-voltage signals for performing comparison of a first wide-range high-voltage signal and a second wide-range high-voltage signal, characterized by, The comparator circuit includes a first branch with a Schottky diode, a second branch with a Schottky diode, a third branch consisting of n Schottky diodes connected in series, a fourth branch consisting of n Schottky diodes connected in series, a first voltage divider branch, a second voltage divider branch, and a comparator; wherein, the first wide-range high-voltage signal is used as the input to the first and third branches, and the second wide-range high-voltage signal is used as the input to the second and fourth branches; n is an integer greater than or equal to 2; The output of the first branch is connected to the output of the fourth branch to form a first node, and the output of the second branch is connected to the output of the third branch to form a second node; The first node is connected to the first voltage divider branch, and after voltage division, it is connected to the positive input terminal of the comparator. The second node is connected to the second voltage divider branch, and after voltage division, it is connected to the negative input terminal of the comparator.

2. The comparator circuit of claim 1, wherein, The first voltage divider branch includes a first resistor, a second resistor, and a first current source; The first node is connected to the positive terminal of the first current source via a first resistor in series with a second resistor, and the negative terminal of the first current source is grounded.

3. The comparison circuit for a wide-range high-voltage signal according to claim 2, characterized in that, The comparator circuit further includes a fifth resistor; one end of the fifth resistor is connected to the midpoint between the first resistor and the second resistor, and the other end is connected to the positive input of the comparator.

4. The comparison circuit for a wide-range high-voltage signal according to claim 1, characterized in that, The second voltage divider branch includes a third resistor, a fourth resistor, and a second current source; The second node is connected to the positive terminal of the second current source via a third resistor in series with a fourth resistor, and the negative terminal of the second current source is grounded.

5. The comparison circuit for a wide-range high-voltage signal according to claim 4, characterized in that, The comparator circuit further includes a sixth resistor; one end of the sixth resistor is connected to the midpoint between the third and fourth resistors, and the other end is connected to the negative input of the comparator.

6. The comparison circuit for a wide-range high-voltage signal according to claim 1, characterized in that, The comparator includes: The judgment component is used to determine the voltage difference between the first node and the second node; An isolation protection device is used to isolate and protect the judgment component to prevent overpressure from occurring in the judgment component; A switching component for controlling the switching of the comparator in response to an enable control signal in the low-voltage signal domain; A third current source is used to provide bias current to the comparator; A current mirror assembly is used to convert a dual-output signal into a single-output signal; and A Schmitt trigger is used to shape a single output signal and output the comparison result of two wide-range high-voltage signals.

7. The comparison circuit for a wide-range high-voltage signal according to claim 6, characterized in that, The determination component includes a first low-voltage PMOS transistor, a second low-voltage PMOS transistor, and a third low-voltage PMOS transistor; The isolation protection device includes a first high-voltage P-type LDMOS device, a second high-voltage P-type LDMOS device, a third high-voltage P-type LDMOS device, and a seventh resistor; The switching assembly includes a first high-voltage N-type LDMOS device, a second high-voltage N-type LDMOS device, and a third high-voltage N-type LDMOS device; wherein, the gate input of the first high-voltage N-type LDMOS device, the second high-voltage N-type LDMOS device, and the third high-voltage N-type LDMOS device is an enable control signal; The current mirror assembly includes a first low-voltage NMOS transistor and a second low-voltage NMOS transistor; The sources of the first and second low-voltage PMOS transistors are connected to the positive input terminal, and the source of the third low-voltage PMOS transistor is connected to the negative input terminal. The drain of the first low-voltage PMOS transistor is connected to the source of the first high-voltage P-type LDMOS device, the drain of the second low-voltage PMOS transistor is connected to the source of the second high-voltage P-type LDMOS device, and the drain of the third low-voltage PMOS transistor is connected to the source of the third high-voltage P-type LDMOS device. The gates of the first, second, and third low-voltage PMOS transistors and the drain of the first high-voltage P-type LDMOS device are connected to one end of the seventh resistor, and the gates of the first, second, and third high-voltage P-type LDMOS devices are connected to the other end of the seventh resistor. The other end of the seventh resistor is also connected to the drain of the first high-voltage N-type LDMOS device, and the source of the first high-voltage N-type LDMOS device is connected to the positive terminal of the third current source, and the negative terminal of the third current source is grounded. The drain of the third high-voltage P-type LDMOS device and the drain of the third high-voltage N-type LDMOS device are connected. The source of the third high-voltage N-type LDMOS device and the drain of the second low-voltage NMOS transistor are connected and then connected to the input terminal of the Schmitt trigger. The drain of the second high-voltage P-type LDMOS device is connected to the drain of the second high-voltage N-type LDMOS device, the source of the second high-voltage N-type LDMOS device is connected to the drain and gate of the first low-voltage NMOS transistor, and the gate of the second low-voltage NMOS transistor is connected. The sources of the first low-voltage NMOS transistor and the second low-voltage NMOS transistor are grounded.

8. The comparison circuit for a wide-range high-voltage signal according to claim 1, characterized in that, The comparison circuit further includes a control component connected in parallel with each Schottky diode in the third and fourth branches, which can be controlled by a switching signal, for controlling the on and off states of each Schottky diode.

9. The comparison circuit for a wide-range high-voltage signal according to claim 8, characterized in that, The number of Schottky diodes in the third and fourth branches is determined by the voltage difference between the positive and negative input terminals of the comparator.

10. The comparison circuit for a wide-range high-voltage signal according to claim 1, characterized in that, The comparator is a high-voltage current comparator.

Images