A high-speed zero-current level conversion circuit suitable for wide voltage

Abstract

This invention discloses a high-speed zero-current level conversion circuit suitable for a wide voltage range, comprising a low-voltage to high-voltage circuit and a high-voltage to low-voltage circuit. The low-voltage to high-voltage circuit includes a high-voltage level shifting module, a high-voltage level converter, and a high-voltage latching module. The high-voltage to low-voltage circuit includes a low-voltage level shifting module, a low-voltage level converter, and a low-voltage latching module. This invention adapts to both high-voltage and low-voltage operation with zero quiescent current and exhibits low transmission delay.

Description

Technical Field

[0001] This invention relates to a level conversion circuit, and more particularly to a high-speed zero-current level conversion circuit suitable for wide voltage ranges, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Chinese Patent Publication No. CN121055946A discloses a high-speed level conversion circuit, including an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module, and an output module. The input signal processing module converts a low-voltage input signal into a complementary logic signal pair. The voltage boosting module uses a charge pump principle to increase the voltage amplitude of the complementary logic signal. The boosted signal drives the thick-gate transistor in the differential signal generation module to generate a differential signal. The signal amplification module uses a cross-coupling structure to rapidly amplify the differential signal. Finally, the output module outputs a high-voltage domain signal inverted. This invention introduces voltage bootstrapping before gate driving, increasing the overdrive voltage of the core switching transistor. Without increasing device size or static power consumption, it effectively solves the problem of slow conversion speed in traditional level conversion circuits, achieving high-speed and high-efficiency level conversion.

[0003] This invention is limited by the characteristics of charge pumps, which require charging and have limited voltage boosting capabilities. The first drawback is that the input signal needs to wait for VDD to charge the capacitor before it can effectively pump a high voltage, thus achieving low-latency low-level to high-level transitions. If the input signal frequency is extremely high, the capacitor may not have enough time to charge, causing the charge pump's boosting function to disappear and the function to fail. Furthermore, the continuous charging and discharging of the capacitor also leads to significant energy loss. The second drawback is that the charge pump can only boost the input signal to twice the voltage of VDD, making it only suitable for applications where VDD is converted to twice VDD. This severely limits its application scenarios; for example, in applications requiring a conversion from 0-5V to 15-20V, this invention is ineffective.

[0004] Chinese Patent Publication No. CN120223049A discloses a low-delay, low-power level shifting circuit, including a low-power level shifting circuit, a fast falling edge capture circuit, a fast rising edge capture circuit, and an RS flip-flop. The low-power level shifting circuit is connected to the input terminals of both the fast falling edge capture circuit and the fast rising edge capture circuit. The output terminals of both the fast falling edge capture circuit and the fast rising edge capture circuit are connected to the RS flip-flop. This invention achieves nanosecond-level delay and nanoampere-level static power consumption while converting a low-voltage domain signal within a specific range to a high-voltage domain signal within a preset range.

[0005] This invention also cannot operate in environments with low VDDH (e.g., 2V) because the threshold voltages of its HPM1 and HPM2 will result in insufficient voltage margin for the MOSFETs in the latch section to operate. Additionally, this level shifter has a static power consumption in the hundreds of nA range.

[0006] Chinese Patent Publication No. CN120320763A discloses a level conversion circuit and a DC / DC converter, comprising: a current bias module configured to output a bias current; a control module configured to output a control current based on the bias current under the control of an input signal located in a low voltage domain; and a level conversion module configured to output an output signal located in a high voltage domain based on the control current, wherein the logic level of the output signal is the same as the logic level of the input signal. This invention can achieve fast level conversion and effectively resist interference from high voltage domain power supplies.

[0007] This invention employs a current mirror for level conversion. When signal conversion is required, a one-shot signal is activated to provide a large current path and reduce transmission delay. Due to its current mirror structure, this invention can operate at low voltages. However, the current mirror must be maintained continuously; otherwise, the output voltage state cannot be guaranteed, resulting in considerable static power consumption. Furthermore, the one-shot duration also limits the frequency of the input signal: the period of the input signal must be much longer than the duration of the one-shot.

[0008] In summary, for DC-DC converters or driver circuits with significant VIN variations, such as from 2V to 20V, the control signals need to be transmitted from the low-voltage domain to the high-voltage domain. Similarly, logic signals from the high-voltage domain also need to be transmitted to the low-voltage domain. Given the wide range of input voltage variations, level converters that can operate at high voltages typically do not function well at low voltages. Furthermore, due to efficiency requirements, level converters should ideally have zero static power consumption. Finally, the propagation delay of the level converter is also a concern, as it affects circuit reliability. Therefore, for applications with a wide range of input voltages, a high-speed level converter with zero static power consumption is required.

[0009] Furthermore, most traditional structures can only operate at high voltages. When the input voltage is low, most traditional structures cannot achieve low propagation delays, and may even fail to function. A few structures use a current mirror as the input signal conversion medium; however, such structures require high current to achieve low propagation delays, making static power consumption unavoidable. Additionally, current technology relies on one-shot signals to improve the current capability during input signal switching, which limits the input signal frequency. Summary of the Invention

[0010] This invention provides a high-speed zero-current level conversion circuit suitable for a wide voltage range. It can adapt to high-voltage and low-voltage operation under the premise of zero quiescent current and has low transmission delay.

[0011] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0012] A high-speed zero-current level conversion circuit suitable for wide voltage range includes a low-voltage to high-voltage circuit and a high-voltage to low-voltage circuit. The low-voltage to high-voltage circuit includes a high-voltage level shifting module, a high-voltage level converter, and a high-voltage latching module. The input terminal of the high-voltage level shifting module and the first input terminal of the high-voltage level converter are connected to the low-voltage domain INL. The output terminal of the high-voltage level shifting module is connected to the second input terminal of the high-voltage level converter. The output terminal of the high-voltage level converter is connected to the input terminal of the high-voltage latching module. The output terminal of the high-voltage latching module generates the high-voltage domain OUT_L2H. The high-voltage to low-voltage circuit includes a low-voltage level shifting module, a low-voltage level converter, and a low-voltage latching module. The input terminal of the low-voltage level shifting module and the first input terminal of the low-voltage level converter are connected to the high-voltage domain INH. The output terminal of the low-voltage level shifting module is connected to the second input terminal of the low-voltage level converter. The output terminal of the low-voltage level converter is connected to the input terminal of the low-voltage latching module. The output terminal of the low-voltage latching module generates the high-voltage domain OUT_L2L.

[0013] Further, the high-voltage level converter includes PMOS transistors PM3 and PM4, high-voltage PMOS transistors DPM1 and DPM2, high-voltage NMOS transistors DNM1, DNM2, NMOS transistors NM3 and NM4. The sources of PMOS transistors PM3 and PM4 are connected to the power supply VS. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM4 and the source of high-voltage PMOS transistor DPM2, generating the signal OUTLB_PRE. The gate of PMOS transistor PM4 is connected to the drain of PMOS transistor PM3 and the source of high-voltage PMOS transistor DPM1, generating the signal OUTL_PRE. The gate of high-voltage PMOS transistor DPM1... The gate of high-voltage PMOS transistor DPM2 is connected to signal VS-5. The drain of high-voltage PMOS transistor DPM1 is connected to the drain of high-voltage NMOS transistor DNM1. The drain of high-voltage PMOS transistor DPM2 is connected to the drain of high-voltage NMOS transistor DNM2. The gates of high-voltage NMOS transistor DNM1 and DNM2 are connected to signal VDD. The source of high-voltage PMOS transistor DPM1 is connected to the drain of NMOS transistor NM3. The source of high-voltage PMOS transistor DPM2 is connected to the drain of NMOS transistor NM4. The gate of NMOS transistor NM3 is connected to the low-voltage domain INL. The gate of NMOS transistor NM4 is connected to the low-voltage domain inverted signal INLB. The sources of NMOS transistor NM3 and NMOS transistor NM4 are grounded.

[0014] Furthermore, the high-voltage level shifting module includes NMOS transistors NM6, NMOS transistors NM7, NMOS transistors NM8, NMOS transistors NM9, high-voltage PMOS transistors DPM5 and DPM6, the drain of NMOS transistor NM7 is connected to the signal OUTL_PRE, the drain of NMOS transistor NM8 is connected to the signal OUTLB_PRE, the gate of NMOS transistor NM7 is connected to the gate of NMOS transistor NM9, the drain of NMOS transistor NM6 and the source of high-voltage PMOS transistor DPM5 to generate the signal INL_L2H, and the NMOS transistor NM... The gate of transistor 8 is connected to the gate of NMOS transistor NM6, the drain of NMOS transistor NM9, and the source of high-voltage PMOS transistor DPM6 to generate the signal INLB_L2H. The gate of high-voltage PMOS transistor DPM5 is connected to the source of NMOS transistor NM6, the source of NMOS transistor NM7, the source of NMOS transistor NM8, the source of NMOS transistor NM9, and the gate of high-voltage PMOS transistor DPM6 to generate the signal VS-5. The drain of high-voltage PMOS transistor DPM5 is connected to the low-voltage domain INL, and the drain of high-voltage PMOS transistor DPM6 is connected to the low-voltage domain inverted signal INLB.

[0015] Furthermore, the high-voltage latch module includes PMOS transistors PM10 and PM11, NMOS transistors NM12 and NM13, inverters INV1 and INV2. The sources of PMOS transistors PM10 and PM11 are connected to the power supply VS. The gate of PMOS transistor PM10 is connected to the signal OUTLB_PRE, and the gate of PMOS transistor PM11 is connected to the signal OUTL_PRE. The drain of PMOS transistor PM10 is connected to the NMOS transistor... The drain of NM12 is connected to the gate of NMOS transistor NM13. The drain of PMOS transistor PM11 is connected to the drain of NMOS transistor NM13. The gate of NMOS transistor NM12 is connected to the input of inverter INV1. The source of NMOS transistor NM12 is connected to the source of NMOS transistor NM13. The output of inverter INV1 is connected to the input of inverter INV2 and generates the signal OUTB_L2H. The output of inverter INV2 generates the signal OUT_L2H.

[0016] Further, the low-voltage level converter includes PMOS transistors PM23 and PM24, high-voltage PMOS transistors DPM21 and DPM22, high-voltage NMOS transistors DNM21 and DNM22, NMOS transistors NM23 and NM24. The sources of PMOS transistors PM23 and PM24 are connected to the power supply VS. The gate of PMOS transistor PM23 is connected to the high-voltage domain INH. The gate of PMOS transistor PM24 is connected to the high-voltage domain inverted signal INHB. The gates of high-voltage PMOS transistors DPM21 and DPM22 are connected to the signal VS-5. The drain of transistor 1 is connected to the drain of high-voltage NMOS transistor DNM21. The drain of high-voltage PMOS transistor DPM22 is connected to the drain of high-voltage NMOS transistor DNM22. The gates of high-voltage NMOS transistor DNM21 and DNM22 are connected to signal VDD. The source of high-voltage PMOS transistor DPM21 is connected to the drain of NMOS transistor NM23 and the gate of NMOS transistor NM24, generating signal OUTH_PRE. The source of high-voltage PMOS transistor DPM22 is connected to the drain of NMOS transistor NM24 and the gate of NMOS transistor NM23, generating signal OUTHB_PRE. The sources of NMOS transistor NM23 and NMOS transistor NM24 are grounded.

[0017] Furthermore, the low-voltage level shifting module includes PMOS transistors PM26, PM27, PM28, and PM29, a high-voltage NMOS transistor DNM25, and a high-voltage NMOS transistor DNM26. The drain of PMOS transistor PM27 is connected to the signal OTH_PRE, and the drain of PMOS transistor PM28 is connected to the signal OUTHB_PRE. The gate of PMOS transistor PM27 is connected to the gate of PMOS transistor PM29, the drain of PMOS transistor PM26, and the source of high-voltage NMOS transistor DNM25 to generate the signal INH_H2L. The gate of transistor DNM28 is connected to the gate of PMOS transistor PM26, the drain of PMOS transistor PM29, and the source of high-voltage NMOS transistor DNM26 to generate the signal INHB_H2L. The gate of high-voltage NMOS transistor DNM25 is connected to the source of PMOS transistor PM26, the source of PMOS transistor PM27, the source of PMOS transistor PM28, the source of PMOS transistor PM29, and the gate of high-voltage NMOS transistor DNM26 to generate the signal VDD. The drain of high-voltage NMOS transistor DNM25 is connected to the high-voltage domain INH. The drain of high-voltage NMOS transistor DNM26 is connected to the high-voltage domain inverted signal INHB.

[0018] Furthermore, the low-voltage latch module includes PMOS transistors PM30 and PM31, NMOS transistors NM32 and NM33, inverters INV3 and INV4. The sources of PMOS transistors PM30 and PM31 are connected to signal VDD. The gate of PMOS transistor PM30 is connected to the drain of PMOS transistor PM31, the drain of NMOS transistor NM33, and the input of inverter INV3. The gate of PMOS transistor PM31... The drain of PMOS transistor PM30 and the drain of NMOS transistor NM32 are connected. The gate of NMOS transistor NM32 is connected to the signal OTH_PRE, and the gate of NMOS transistor NM33 is connected to the signal OUTHB_PRE. The sources of NMOS transistors NM32 and NMOS transistor NM33 are grounded. The output of inverter INV3 is connected to the input of inverter INV4 and generates the signal OUTB_H2L. The output of inverter INV4 generates the signal OUT_H2L.

[0019] Compared with existing technologies, this invention has the following advantages and effects: This invention discloses a high-speed zero-current level shifting circuit suitable for wide voltage ranges. Through a power-free level shifting technique combined with a classic high-voltage level converter structure, it achieves fast level shifting with zero static power consumption under wide voltage ranges. This power-free level shifting technique enters a dormant state when the input voltage is high, without affecting the output signal; in this case, the output relies on the classic high-voltage level converter structure. When the input voltage is low, the classic high-voltage level converter cannot operate; at this time, the input directly acts on the latch circuit through the power-free level shifting circuit, directly changing the output signal. When the input voltage is neither too high nor too low, the classic high-voltage level converter structure and the power-free level shifting circuit proposed in this invention will operate simultaneously. Therefore, under any input voltage, this invention can achieve low propagation delay and zero static power consumption. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a high-speed zero-current level conversion circuit suitable for wide voltage range according to the present invention.

[0021] Figure 2 This is a schematic diagram of the high-voltage level converter of the present invention.

[0022] Figure 3 This is a schematic diagram of the high-voltage level displacement module of the present invention.

[0023] Figure 4 This is a schematic diagram of the high-voltage latch module of the present invention.

[0024] Figure 5 This is a schematic diagram of the low-voltage level converter of the present invention.

[0025] Figure 6This is a schematic diagram of the low-voltage level displacement module of the present invention.

[0026] Figure 7 This is a schematic diagram of the low-voltage latch module of the present invention.

[0027] Figure 8 This is a simulation result diagram of the rising edge of the low-voltage to high-voltage transition under the conditions of VS=20V and VDD=5V.

[0028] Figure 9 This is a simulation result diagram of the falling edge of the low-voltage to high-voltage transition under the conditions of VS=20V and VDD=5V.

[0029] Figure 10 This is a simulation result diagram of the rising edge of the high-voltage to low-voltage transition under the conditions of VS=20V and VDD=5V.

[0030] Figure 11 This is a simulation result diagram of the falling edge of the high-voltage to low-voltage transition under the conditions of VS=20V and VDD=5V.

[0031] Figure 12 This is a simulation result diagram of the low-voltage to high-voltage rising edge of the present invention under the conditions of VS=2V and VDD=2V.

[0032] Figure 13 This is a simulation result diagram of the falling edge of the low-voltage to high-voltage transition under the conditions of VS=2V and VDD=2V.

[0033] Figure 14 This is a simulation result diagram of the rising edge of the high-voltage to low-voltage transition under the conditions of VS=2V and VDD=2V.

[0034] Figure 15 This is a simulation result diagram of the falling edge of the high-voltage to low-voltage transition under the conditions of VS=2V and VDD=2V. Detailed Implementation

[0035] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0036] like Figure 1As shown, this invention provides a high-speed zero-current level conversion circuit suitable for wide voltage ranges, comprising a low-voltage to high-voltage circuit and a high-voltage to low-voltage circuit. The low-voltage to high-voltage circuit includes a high-voltage level shifting module, a high-voltage level converter, and a high-voltage latching module. The input terminal of the high-voltage level shifting module and the first input terminal of the high-voltage level converter are connected to the low-voltage domain INL. The output terminal of the high-voltage level shifting module is connected to the second input terminal of the high-voltage level converter. The output terminal of the high-voltage level converter is connected to the input terminal of the high-voltage latching module. The output terminal of the high-voltage latching module generates the high-voltage domain OUT_L2H. The high-voltage to low-voltage circuit includes a low-voltage level shifting module, a low-voltage level converter, and a low-voltage latching module. The input terminal of the low-voltage level shifting module and the first input terminal of the low-voltage level converter are connected to the high-voltage domain INL. The output terminal of the low-voltage level shifting module is connected to the second input terminal of the low-voltage level converter. The output terminal of the low-voltage level converter is connected to the input terminal of the low-voltage latching module. The output terminal of the low-voltage latching module generates the high-voltage domain OUT_L2L.

[0037] like Figure 2 As shown, the high-voltage level converter includes PMOS transistors PM3 and PM4, high-voltage PMOS transistors DPM1 and DPM2, high-voltage NMOS transistors DNM1, DNM2, NMOS transistors NM3 and NM4. The sources of PMOS transistors PM3 and PM4 are connected to the power supply VS. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM4 and the source of high-voltage PMOS transistor DPM2, generating the signal OUTLB_PRE. The gate of PMOS transistor PM4 is connected to the drain of PMOS transistor PM3 and the source of high-voltage PMOS transistor DPM1, generating the signal OUTL_PRE. The gate of high-voltage PMOS transistor DPM1 is connected to the high-voltage PMOS transistor DPM2. The gate of high-voltage PMOS transistor DPM2 is connected to signal VS-5. The drain of high-voltage PMOS transistor DPM1 is connected to the drain of high-voltage NMOS transistor DNM1. The drain of high-voltage PMOS transistor DPM2 is connected to the drain of high-voltage NMOS transistor DNM2. The gates of high-voltage NMOS transistor DNM1 and DNM2 are connected to signal VDD. The source of high-voltage PMOS transistor DPM1 is connected to the drain of NMOS transistor NM3. The source of high-voltage PMOS transistor DPM2 is connected to the drain of NMOS transistor NM4. The gate of NMOS transistor NM3 is connected to the low-voltage domain INL. The gate of NMOS transistor NM4 is connected to the low-voltage domain inverted signal INLB. The sources of NMOS transistor NM3 and NMOS transistor NM4 are grounded.

[0038] Signal VDD is the low-voltage rail, power supply VS is the high-voltage rail, and signal VS-5 is the voltage rail that is 5V lower than power supply VS.

[0039] NMOS transistors NM3 and NM4 are low-voltage devices, located in the VDD_GND domain. PMOS transistors PM3 and PM4 are low-voltage devices, located in the VS_VS-5 domain. High-voltage PMOS transistors DPM1, DPM2, DNM1, and DNM2 are all high-voltage devices.

[0040] Considering the low-voltage domain INL turning high, when the low-voltage domain inverted signal INLB turns low, NMOS transistor NM3 is turned on, and NMOS transistor NM4 is completely turned off. Then, signal OUTL_PRE is simultaneously pulled down by NMOS transistor NM3 and pulled up by PMOS transistor PM3. Since the aspect ratio of NMOS transistor NM3 is much larger than that of PMOS transistor PM3, signal OUTL_PRE is pulled low. Due to the presence of high-voltage PMOS transistor DPM1, signal OUTL_PRE can only be at a minimum of VS-5+Vth to ensure that PMOS transistor PM4 will not be damaged. At this time, NMOS transistor NM4 is completely turned off, while PMOS transistor PM4 is turned on, and signal OUTLB_PRE will be pulled high. After the above process is completed, INL and INLB, as low-voltage domain signals, are transmitted to the high-voltage domain. At this time, signals OUTL_PRE and OUTLB_PRE are in the VS_VS-5+Vth domain and will be converted to the VS_VS-5 domain by the high-voltage latch module.

[0041] When the low-voltage domain VS is low, for example, only 2V, the signal VS-5 drops to 0V, and the signal VDD, as the internal rail, is only 2V. At this time, the signal OUTL_PRE can only drop to 0+Vth, where Vth is the threshold voltage of the high-voltage MOS DPM1, which is typically high, reaching 1.5V. Therefore, the VGS voltage of PMOS transistors PM3 and PM4 is 2-Vth, only 0.5V, and neither PMOS transistors PM3 nor PM4 can be turned on, preventing signal transmission. This problem will be solved by the level shifting module.

[0042] like Figure 3As shown, the high-voltage level shifting module includes NMOS transistors NM6, NMOS transistors NM7, NMOS transistors NM8, NMOS transistors NM9, and high-voltage PMOS transistors DPM5 and DPM6. The drain of NMOS transistor NM7 is connected to the signal OUTL_PRE, and the drain of NMOS transistor NM8 is connected to the signal OUTLB_PRE. The gate of NMOS transistor NM7 is connected to the gate of NMOS transistor NM9, and the drain of NMOS transistor NM6 is connected to the source of high-voltage PMOS transistor DPM5, generating the signal INL_L2H. The NMOS transistor NM8... The gate of the high-voltage PMOS transistor DPM5 is connected to the gate of NMOS transistor NM6, the drain of NMOS transistor NM9, and the source of high-voltage PMOS transistor DPM6 to generate the signal INLB_L2H. The gate of high-voltage PMOS transistor DPM5 is connected to the source of NMOS transistor NM6, the source of NMOS transistor NM7, the source of NMOS transistor NM8, the source of NMOS transistor NM9, and the gate of high-voltage PMOS transistor DPM6 to generate the signal VS-5. The drain of high-voltage PMOS transistor DPM5 is connected to the low-voltage domain INL, and the drain of high-voltage PMOS transistor DPM6 is connected to the low-voltage domain inverted signal INLB.

[0043] Signals INL_L2H and INLB_L2H are signals from the low-voltage domain INL and the low-voltage domain inverted signal INLB, passed through the high-voltage PMOS transistors DPM5 and DPM6. Due to the clamping effect of the high-voltage PMOS transistors DPM5 and DPM6, both INL_L2H and INLB_L2H are higher than VS-5, so there is no risk of breakdown for NMOS transistors NM6-NM9. When VS is high, since INL and INLB are much smaller than VS-5, INL_L2H and INLB_L2H will remain at VS-5-0.7, clamped by VS-5 through the body diodes of NMOS transistors NM6 and NM9. Therefore, NMOS transistors NM6-NM9 cannot be turned on and cannot affect signals OUTL_PRE and OUTLB_PRE.

[0044] When VS is low, VS-5 drops to 0. Signals INL_L2H and INLB_L2H are directly equal to INL and INLB. Considering INL going high, INL_L2H goes high, NMOS transistors NM7 and NM9 turn on. Turning on NMOS transistor NM7 pulls OUTL_PRE low, performing a level shift. Turning on NMOS transistor NM9 pulls INLB_L2H low and turns off NMOS transistor NM8, allowing OUTLB_PRE to go high. The reverse is also true.

[0045] like Figure 4As shown, the high-voltage latch module includes PMOS transistors PM10 and PM11, NMOS transistors NM12 and NM13, inverters INV1 and INV2. The sources of PMOS transistors PM10 and PM11 are connected to the power supply VS. The gate of PMOS transistor PM10 is connected to the signal OUTLB_PRE, and the gate of PMOS transistor PM11 is connected to the signal OUTL_PRE. The drain of PMOS transistor PM10 is connected to the NMOS transistor NM12. The drain of PMOS transistor PM12 is connected to the gate of NMOS transistor NM13. The drain of PMOS transistor PM11 is connected to the drain of NMOS transistor NM13. The gate of NMOS transistor NM12 is connected to the input of inverter INV1. The source of NMOS transistor NM12 is connected to the source of NMOS transistor NM13. The output of inverter INV1 is connected to the input of inverter INV2 and generates the signal OUTB_L2H. The output of inverter INV2 generates the signal OUT_L2H.

[0046] The signals OUTL_PRE and OUTLB_PRE are inverted signals. After passing through the latch circuit composed of PM10, PM11, NM12, and NM13, they generate two output signals OUT_L2H and OUTB_L2H in the VS_VS-5 domain.

[0047] Through the above three circuit components, this invention completes the low-voltage to high-voltage level conversion and can adapt to a wide range of input voltages. Since no current mirror is introduced, the static power consumption of this invention is zero. Furthermore, due to the full utilization of the input voltage, the transmission delay is very low.

[0048] like Figure 5As shown, the low-voltage level converter includes PMOS transistors PM23 and PM24, high-voltage PMOS transistors DPM21 and DPM22, high-voltage NMOS transistors DNM21 and DNM22, NMOS transistors NM23 and NM24. The sources of PMOS transistors PM23 and PM24 are connected to the power supply VS. The gate of PMOS transistor PM23 is connected to the high-voltage domain INH. The gate of PMOS transistor PM24 is connected to the high-voltage domain inverted signal INHB. The gates of high-voltage PMOS transistors DPM21 and DPM22 are connected to signal VS-5. The drain of the high-voltage NMOS transistor DNM21 is connected to the drain of the high-voltage PMOS transistor DPM22, and the drain of the high-voltage PMOS transistor DPM22 is connected to the drain of the high-voltage NMOS transistor DNM22. The gates of the high-voltage NMOS transistor DNM21 and DNM22 are connected to the signal VDD. The source of the high-voltage PMOS transistor DPM21 is connected to the drain of the NMOS transistor NM23 and the gate of the NMOS transistor NM24, generating the signal OUTH_PRE. The source of the high-voltage PMOS transistor DPM22 is connected to the drain of the NMOS transistor NM24 and the gate of the NMOS transistor NM23, generating the signal OUTHB_PRE. The sources of the NMOS transistors NM23 and NM24 are grounded.

[0049] When INH turns low and INHB turns high, PMOS transistor PM3 is turned on, and PMOS transistor PM4 is completely turned off. The signal OutH_PRE is simultaneously pulled up by PMOS transistor PM3 and pulled down by NMOS transistor NM3. Since the aspect ratio of PMOS transistor PM3 is much larger than that of NMOS transistor NM3, the signal OutH_PRE is pulled high. Due to the presence of the high-voltage NMOS transistor DNM1, the signal OutH_PRE can only reach a maximum of VDD-Vth, ensuring that NMOS transistor NM4 will not be damaged. At this time, NMOS transistor NM4 is fully turned on, while PMOS transistor PM4 is turned off, and the signal OUTHB_PRE will be pulled high. After the above process is completed, INH and INHB, as high-voltage domain signals, are transmitted to the low-voltage domain. At this time, OutH_PRE and OUTHB_PRE are signals in the VDD-Vth domain and will be converted to the VDD_GND domain by the low-voltage latch module.

[0050] When VS is low, for example, only 2V, VS-5 drops to 0V, and VDD, as the internal rail, is only 2V. At this time, OTH_PRE can only rise to a maximum of VDD-Vth, where Vth is the threshold voltage of the high-voltage PMOS transistor DPM1, which is typically large, reaching 1.5V. Therefore, the VGS voltage of PMOS transistors PM3 and PM4 is 2-Vth, only 0.5V, and NMOS transistors NM3 and NM4 cannot be turned on, preventing signal transmission. This problem will be solved by the level shifting module.

[0051] like Figure 6 As shown, the low-voltage level shifting module includes PMOS transistors PM26, PM27, PM28, and PM29, and high-voltage NMOS transistors DNM25 and DNM26. The drain of PMOS transistor PM27 is connected to the signal OTH_PRE, and the drain of PMOS transistor PM28 is connected to the signal OUTHB_PRE. The gate of PMOS transistor PM27 is connected to the gate of PMOS transistor PM29, the drain of PMOS transistor PM26, and the source of high-voltage NMOS transistor DNM25, generating the signal INH_H2L. PMOS transistor PM28... The gate of the high-voltage NMOS transistor DNM25 is connected to the gate of PMOS transistor PM26, the drain of PMOS transistor PM29, and the source of high-voltage NMOS transistor DNM26 to generate the signal INHB_H2L. The gate of the high-voltage NMOS transistor DNM25 is connected to the source of PMOS transistor PM26, the source of PMOS transistor PM27, the source of PMOS transistor PM28, the source of PMOS transistor PM29, and the gate of high-voltage NMOS transistor DNM26 to generate the signal VDD. The drain of the high-voltage NMOS transistor DNM25 is connected to the high-voltage domain INH. The drain of the high-voltage NMOS transistor DNM26 is connected to the high-voltage domain inverted signal INHB.

[0052] INH_H2L and INHB_H2L are the signals from INH and INHB through the high-voltage NMOS transistors. Due to the clamping effect of the high-voltage NMOS transistors DNM5 and DNM6, both INH_H2L and INHB_H2L are lower than VDD, so there is no risk of breakdown for PMOS transistors PM6-PM9. When VS is higher, since INH and INHB are much higher than VDD, INH_H2L and INHB_H2L will remain at VDD+0.7, clamped by VDD through the body diodes of PMOS transistors PM6 and PM9. Therefore, PMOS transistors PM6-PM9 cannot be turned on and cannot affect OUTH_PRE and OUTHB_PRE.

[0053] When VS is low, VS-5 drops to 0. INH_H2L and INHB_H2L are directly equal to INH and INHB. Considering INH turning low, INH_H2L turns low, PMOS transistors PM7 and PM9 turn on. PMOS transistor PM7 turning on can pull OUTH_PRE high, performing level conversion. PMOS transistor PM9 turning on can pull INHB_H2L low, turn off PMOS transistor PM8, and allow OUTHB_PRE to turn low. The reverse is also true.

[0054] like Figure 7 As shown, the low-voltage latch module includes PMOS transistors PM30 and PM31, NMOS transistors NM32 and NM33, inverters INV3 and INV4. The sources of PMOS transistors PM30 and PM31 are connected to signal VDD. The gate of PMOS transistor PM30 is connected to the drain of PMOS transistor PM31, the drain of NMOS transistor NM33, and the input of inverter INV3. The gate of PMOS transistor PM31 is connected to P... The drain of MOSFET PM30 is connected to the drain of NMOS transistor NM32. The gate of NMOS transistor NM32 is connected to the signal OTH_PRE. The gate of NMOS transistor NM33 is connected to the signal OUTHB_PRE. The sources of NMOS transistors NM32 and NMOS transistor NM33 are grounded. The output of inverter INV3 is connected to the input of inverter INV4 and generates the signal OUTB_H2L. The output of inverter INV4 generates the signal OUT_H2L.

[0055] OUTH_PRE and OUTHB_PRE are inverted signals. After passing through the latch circuit composed of PM10, PM11, NM12, and NM13, they generate two output signals OUT_H2L and OUTB_H2L in the VDD_GND domain.

[0056] Through the above three circuit components, this invention completes the high-voltage to low-voltage level conversion and can adapt to a wide range of input voltages. Since no current mirror is introduced, the static power consumption of this invention is zero. Furthermore, due to the full utilization of the input voltage, the transmission delay is very low.

[0057] Based on the above analysis, this invention provides a high-speed zero-current level conversion circuit design adaptable to a wide voltage range. It can achieve high-voltage to low-voltage level conversion, as well as low-voltage to high-voltage level conversion.

[0058] When VS=20V and VDD=5V, as Figure 8 , 9 To convert from low voltage to high voltage, Figure 10 , 11 It is a high-voltage to low-voltage conversion.

[0059] Figures 8 to 11The invention demonstrates that when the VS voltage is high, it can achieve a small transmission delay of less than 5nS, and the static power consumption is less than 1nA without level conversion.

[0060] When VS=VDD=2V Figure 12 , 13 To convert from low voltage to high voltage, Figure 14 , 15 It is a high-voltage to low-voltage conversion.

[0061] Figures 12 to 15 The invention demonstrates that when the VS voltage is very low, the transmission delay is around 7ns, and the static power consumption is less than 1nA without level conversion.

[0062] Based on the above images, it can be demonstrated that the present invention is adaptable to wide voltage range operation, has low latency, and extremely low static power consumption.

[0063] The invention described herein eliminates the need for a charge pump, allowing it to adapt to high-speed input frequencies without fear of failure. Furthermore, by transmitting the input signal to either a high-voltage or low-voltage domain via a high-voltage LDMOS, it can accommodate operating voltages ranging from extremely low to extremely high. This results in a wide range of applications and completely eliminates static power consumption.

[0064] This invention designs a level converter suitable for both high and low voltage. It can adapt to both high voltage (e.g., 20V or higher) and low voltage (e.g., 2V or lower). Furthermore, this invention has no static power consumption. Moreover, this invention maintains a transmission delay of several ns under both high and low voltage conditions.

[0065] The level converter proposed in this invention has no current mirror structure and can still adapt to wide voltage range operation. Because there is no current mirror structure, there is no static power consumption. Furthermore, this invention does not require a one-shot signal to accelerate transmission delay, so the frequency of the input signal is not limited.

[0066] This invention discloses a high-speed zero-current level shifting circuit suitable for wide voltage ranges. By employing a power-free level shifting technique combined with a classic high-voltage level converter structure, it achieves rapid level shifting with zero static power consumption across a wide voltage range. This power-free level shifting technique enters a dormant state when the input voltage is high, without affecting the output signal; in this case, the output relies on the classic high-voltage level converter structure. When the input voltage is low, the classic high-voltage level converter cannot operate; in this case, the input directly acts on the latch circuit through the power-free level shifting circuit, directly changing the output signal. When the input voltage is neither too high nor too low, both the classic high-voltage level converter structure and the power-free level shifting circuit proposed in this invention will function simultaneously. Therefore, this invention can achieve low propagation delay and zero static power consumption under any input voltage.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A high-speed zero-current level conversion circuit suitable for wide voltage ranges, characterized in that: It includes a low-voltage to high-voltage circuit and a high-voltage to low-voltage circuit. The low-voltage to high-voltage circuit includes a high-voltage level shifting module, a high-voltage level converter, and a high-voltage latching module. The input terminal of the high-voltage level shifting module and the first input terminal of the high-voltage level converter are connected to the low-voltage domain INL. The output terminal of the high-voltage level shifting module is connected to the second input terminal of the high-voltage level converter. The output terminal of the high-voltage level converter is connected to the input terminal of the high-voltage latching module. The output terminal of the high-voltage latching module generates the high-voltage domain OUT_L2H. The high-voltage to low-voltage circuit includes a low-voltage level shifting module, a low-voltage level converter, and a low-voltage latching module. The input terminal of the low-voltage level shifting module and the first input terminal of the low-voltage level converter are connected to the high-voltage domain INH. The output terminal of the low-voltage level shifting module is connected to the second input terminal of the low-voltage level converter. The output terminal of the low-voltage level converter is connected to the input terminal of the low-voltage latching module. The output terminal of the low-voltage latching module generates the high-voltage domain OUT_L2L.

2. The high-speed zero-current level conversion circuit suitable for wide voltage range according to claim 1, characterized in that: The high-voltage level converter includes PMOS transistors PM3 and PM4, high-voltage PMOS transistors DPM1 and DPM2, high-voltage NMOS transistors DNM1, DNM2, NMOS transistors NM3 and NM4. The sources of PMOS transistors PM3 and PM4 are connected to the power supply VS. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM4 and the source of high-voltage PMOS transistor DPM2, generating the signal OUTLB_PRE. The gate of PMOS transistor PM4 is connected to the drain of PMOS transistor PM3 and the source of high-voltage PMOS transistor DPM1, generating the signal OUTL_PRE. The gate of high-voltage PMOS transistor DPM1 is connected to the high-voltage power supply VS. The gate of PMOS transistor DPM2 is connected to signal VS-5. The drain of high-voltage PMOS transistor DPM1 is connected to the drain of high-voltage NMOS transistor DNM1. The drain of high-voltage PMOS transistor DPM2 is connected to the drain of high-voltage NMOS transistor DNM2. The gates of high-voltage NMOS transistor DNM1 and DNM2 are connected to signal VDD. The source of high-voltage PMOS transistor DPM1 is connected to the drain of NMOS transistor NM3. The source of high-voltage PMOS transistor DPM2 is connected to the drain of NMOS transistor NM4. The gate of NMOS transistor NM3 is connected to the low-voltage domain INL. The gate of NMOS transistor NM4 is connected to the low-voltage domain inverted signal INLB. The sources of NMOS transistor NM3 and NMOS transistor NM4 are grounded.

3. The high-speed zero-current level conversion circuit suitable for wide voltage range according to claim 1, characterized in that: The high-voltage level shifting module includes NMOS transistors NM6, NMOS transistors NM7, NMOS transistors NM8, NMOS transistors NM9, and high-voltage PMOS transistors DPM5 and DPM6. The drain of NMOS transistor NM7 is connected to the signal OUTL_PRE, and the drain of NMOS transistor NM8 is connected to the signal OUTLB_PRE. The gate of NMOS transistor NM7 is connected to the gate of NMOS transistor NM9, the drain of NMOS transistor NM6, and the source of high-voltage PMOS transistor DPM5, generating the signal INL_L2H. The gate of NMOS transistor NM8... The gate of high-voltage PMOS transistor DPM5 is connected to the gate of NMOS transistor NM6, the drain of NMOS transistor NM9, and the source of high-voltage PMOS transistor DPM6 to generate the signal INLB_L2H. The gate of high-voltage PMOS transistor DPM5 is connected to the source of NMOS transistor NM6, the source of NMOS transistor NM7, the source of NMOS transistor NM8, the source of NMOS transistor NM9, and the gate of high-voltage PMOS transistor DPM6 to generate the signal VS-5. The drain of high-voltage PMOS transistor DPM5 is connected to the low-voltage domain INL, and the drain of high-voltage PMOS transistor DPM6 is connected to the low-voltage domain inverted signal INLB.

4. The high-speed zero-current level conversion circuit suitable for wide voltage range according to claim 1, characterized in that: The high-voltage latch module includes PMOS transistors PM10 and PM11, NMOS transistors NM12 and NM13, inverters INV1 and INV2. The sources of PMOS transistors PM10 and PM11 are connected to the power supply VS. The gate of PMOS transistor PM10 is connected to the signal OUTLB_PRE, and the gate of PMOS transistor PM11 is connected to the signal OUTL_PRE. The drain of PMOS transistor PM10 is connected to the NMOS transistor NM13. The drain of PMOS transistor PM12 is connected to the gate of NMOS transistor NM13. The drain of PMOS transistor PM11 is connected to the drain of NMOS transistor NM13. The gate of NMOS transistor NM12 is connected to the input of inverter INV1. The source of NMOS transistor NM12 is connected to the source of NMOS transistor NM13. The output of inverter INV1 is connected to the input of inverter INV2 and generates the signal OUTB_L2H. The output of inverter INV2 generates the signal OUT_L2H.

5. A high-speed zero-current level conversion circuit suitable for wide voltage range according to claim 1, characterized in that: The low-voltage level converter includes PMOS transistors PM23 and PM24, high-voltage PMOS transistors DPM21 and DPM22, high-voltage NMOS transistors DNM21 and DNM22, NMOS transistors NM23 and NM24. The sources of PMOS transistors PM23 and PM24 are connected to the power supply VS. The gate of PMOS transistor PM23 is connected to the high-voltage domain INH. The gate of PMOS transistor PM24 is connected to the high-voltage domain inverted signal INHB. The gates of high-voltage PMOS transistors DPM21 and DPM22 are connected to the signal VS-5. The drain of high-voltage PMOS transistor DPM21... The source of high-voltage PMOS transistor DPM22 is connected to the drain of high-voltage NMOS transistor DNM21, the drain of high-voltage PMOS transistor DPM22 is connected to the drain of high-voltage NMOS transistor DNM22, the gate of high-voltage NMOS transistor DNM21 and the gate of high-voltage NMOS transistor DNM22 are connected to the signal VDD, the source of high-voltage PMOS transistor DPM21 is connected to the drain of NMOS transistor NM23 and the gate of NMOS transistor NM24 and generates the signal OUTH_PRE, the source of high-voltage PMOS transistor DPM22 is connected to the drain of NMOS transistor NM24 and the gate of NMOS transistor NM23 and generates the signal OUTHB_PRE, and the source of NMOS transistor NM23 and the source of NMOS transistor NM24 are grounded.

6. A high-speed zero-current level conversion circuit suitable for wide voltage range according to claim 1, characterized in that: The low-voltage level shifting module includes PMOS transistors PM26, PM27, PM28, and PM29, as well as a high-voltage NMOS transistor DNM25 and DNM26. The drain of PMOS transistor PM27 is connected to the signal OTH_PRE, and the drain of PMOS transistor PM28 is connected to the signal OUTHB_PRE. The gate of PMOS transistor PM27 is connected to the gate of PMOS transistor PM29, the drain of PMOS transistor PM26, and the source of high-voltage NMOS transistor DNM25, generating the signal INH_H2L. PMOS transistor PM28... The gate of the high-voltage NMOS transistor DNM25 is connected to the gate of PMOS transistor PM26, the drain of PMOS transistor PM29, and the source of high-voltage NMOS transistor DNM26 to generate the signal INHB_H2L. The gate of the high-voltage NMOS transistor DNM25 is connected to the source of PMOS transistor PM26, the source of PMOS transistor PM27, the source of PMOS transistor PM28, the source of PMOS transistor PM29, and the gate of high-voltage NMOS transistor DNM26 to generate the signal VDD. The drain of the high-voltage NMOS transistor DNM25 is connected to the high-voltage domain INH. The drain of the high-voltage NMOS transistor DNM26 is connected to the high-voltage domain inverted signal INHB.

7. A high-speed zero-current level conversion circuit suitable for wide voltage range according to claim 1, characterized in that: The low-voltage latch module includes PMOS transistors PM30 and PM31, NMOS transistors NM32 and NM33, inverters INV3 and INV4. The sources of PMOS transistors PM30 and PM31 are connected to signal VDD. The gate of PMOS transistor PM30 is connected to the drain of PMOS transistor PM31, the drain of NMOS transistor NM33, and the input of inverter INV3. The gate of PMOS transistor PM31 is connected to PM... The drain of the OS transistor PM30 is connected to the drain of the NMOS transistor NM32. The gate of the NMOS transistor NM32 is connected to the signal OTH_PRE. The gate of the NMOS transistor NM33 is connected to the signal OUTHB_PRE. The sources of the NMOS transistors NM32 and NM33 are grounded. The output of the inverter INV3 is connected to the input of the inverter INV4 and generates the signal OUTB_H2L. The output of the inverter INV4 generates the signal OUT_H2L.

Images