Process method for offsetting photolithography alignment deviation and wafer level chip package structure
By adding a connection part to the bumps of the chip unit and using a multi-exposure strategy for calibration, the problem of photolithography misalignment during packaging was solved, improving connection reliability and yield, and reducing production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI YIBU SEMICON CO LTD
- Filing Date
- 2026-02-03
- Publication Date
- 2026-06-23
AI Technical Summary
In existing technologies, the problem of photolithographic alignment misalignment between chips or between chips and external pads during the packaging process cannot be effectively solved, leading to unreliable connections and reduced yield.
By increasing the area of the connector on the bump of the chip unit and using a multi-exposure strategy for calibration, including the first exposure based on the overall position and the second exposure based on the actual position, a calibration layer and a transition bump are formed to ensure the precise alignment of the connector and the bump.
This improves the reliability of the connection between the chip and the external pads and the yield of electrical connections, reduces production costs, and enhances the overall competitiveness of the packaging.
Smart Images
Figure CN122260732A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip packaging technology, and in particular to a process method for compensating for photolithography alignment misalignment and a wafer-level chip packaging structure. Background Technology
[0002] The surface mount technology (SMT) processes used in packaging technologies such as CoWoS-L (Chip-on-Wafer-on-Substrate-Local) and InFO_LSI (Integrated Fan-out Local Silicon Interconnect) have always been plagued by placement issues. As packaging density demands continue to increase, the diameters and spacing of solder balls or pillars are shrinking, making silicon bridge misalignment an increasingly prominent problem, thus limiting the use and development of silicon bridge technology.
[0003] Therefore, how to reduce the alignment misalignment between chips or between chips and external pads during the packaging process has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] To address the aforementioned technical problems, this disclosure provides a process method and wafer-level chip packaging structure for compensating for photolithographic alignment misalignment, used to reduce alignment misalignment between chips or between a chip and an external pad during the packaging process.
[0005] This disclosure provides a process method for compensating for photolithographic alignment misalignment, comprising: a plurality of recombined first chip units, each first chip unit including a chip and a first bump, the first bump being located on one side surface of the chip; forming a connection portion on the first bump, wherein the radius of the connection portion is increased by an amount greater than or equal to 1.5 times the standard deviation of the recombination accuracy of the first chip unit; and further forming a redistribution layer on the connection portion. And / or, a calibration layer and a transition bump are formed on one side of the chip cell including the first bump, the transition bump being located on the side of the calibration layer opposite to the first bump, the calibration layer undergoing at least a first exposure and a second exposure, the first exposure being based on the overall position of the plurality of recombined first chip cells, and the second exposure being based on the actual position of a single first chip cell; Metal is injected into the pattern after the calibration layer is exposed and developed to form a connecting portion. Along a direction perpendicular to the plane where the calibration layer is located, the connecting portion overlaps with the first protrusion and also overlaps with the transition protrusion.
[0006] Optionally, the first exposure is based on the overall position of the multiple recombined first chip units, and the second exposure is based on the actual position of the bump on a single first chip unit, including: A first alignment mark is set for at least two recombined first chip units, and the first exposure is based on the first alignment mark; A second alignment mark is set for a single first chip cell, and the second exposure is based on the second alignment mark.
[0007] Optionally, forming a calibration layer on one side of the first chip cell including the first bump includes: The calibration layer is formed by first exposure and second exposure of positive photoresist, followed by development to form the pattern, and metal is deposited and electroplated inside the pattern to a preset thickness.
[0008] Optionally, the calibration layer is formed by first exposure and second exposure of positive photoresist, followed by development to form the pattern, depositing metal inside the pattern and electroplating to a preset thickness; removing the positive photoresist and using negative photoresist to continue the fabrication of the calibration layer.
[0009] Optionally, the metal includes copper.
[0010] Optionally, a second chip unit or redistribution layer is provided, the second chip unit including a chip and a second bump; the second chip unit or redistribution layer is connected to the first chip unit through the transition bump.
[0011] Optionally, the first chip unit includes a plurality of first regions, the connection portion is located at the center of the first region, the area of the connection portion is larger than the area of the first bump, and the center of the connection portion overlaps with the center of the first bump.
[0012] Optionally, a second chip unit or a redistribution layer is provided, the second chip unit including a chip and a second bump; the second chip unit or the redistribution layer is connected to the first chip unit through the connection portion.
[0013] Optionally, a first calibration layer and a first transition bump are formed on the transition bump, wherein the first transition bump is located on the side of the first calibration layer opposite to the transition bump; Metal is injected into the pattern after exposure and development of the first calibration layer to form a first connection portion, the first connection portion at least covering the first transition bump and covering the transition bump; The transition bump is located between the first bump and the first transition bump.
[0014] Based on the same inventive concept, this disclosure provides a wafer-level chip packaging structure, which is fabricated using the process method described above for compensating for photolithographic alignment misalignment. The structure includes: a reconstructed first chip unit, the first chip unit including a chip and a first bump, the first bump being located on one side of the chip; a connection portion being formed on the first bump, the radius of the connection portion being increased by a radius greater than or equal to 1.5 times the standard deviation of the reconstructing accuracy of the first chip unit; and a redistribution layer being formed on the connection portion. And / or, the first chip unit includes a connector and a transition bump, the transition bump being located on the side of the calibration layer opposite to the first bump, the calibration layer undergoing at least a first exposure and a second exposure, the first exposure being based on the overall position of the plurality of reconstituted first chip units, and the second exposure being based on the actual position of a single first chip unit; the pattern formed by the exposure and development of the calibration layer forms a connector, the connector overlapping with the first bump and the transition bump along a direction perpendicular to the plane of the calibration layer; The packaging structure further includes a second chip unit or an external pad, the second chip unit or the external pad including a second bump, and the second chip unit or the external pad being connected to the connecting portion or the transition bump; The packaging structure further includes a packaging layer that at least partially covers the second chip cell or the external pad.
[0015] The technical solution provided in this disclosure has the following advantages compared with the prior art: The process method and wafer-level chip packaging structure for compensating for photolithographic alignment misalignment provided in this disclosure include: a plurality of recombined first chip units, each first chip unit including a chip and a first bump, the first bump being located on one side surface of the chip; a connecting portion is formed on the first bump, the radius of the connecting portion being increased by a dimension greater than or equal to 1.5 times the standard deviation of the recombination accuracy of the first chip unit, and a redistribution layer is further formed on the connecting portion; and / or, a calibration layer and a transition bump are formed on one side of the first chip unit including the first bump, the transition bump being located on the side of the calibration layer away from the first bump, the calibration layer undergoing at least a first exposure and a second exposure, the first exposure being based on the overall position of the plurality of recombined first chip units, and the second exposure being based on the actual position of a single first chip unit; metal is injected into the pattern after exposure and development of the calibration layer to form a connecting portion, the connecting portion overlapping the first bump and the transition bump along a direction perpendicular to the plane of the calibration layer.
[0016] By increasing the area of the first bump or employing a multi-exposure strategy based on "expected position alignment + actual position alignment" for the calibration layer, alignment errors introduced by chip position, rotation, and deformation after the first chip unit is reassembled and mounted can be compensated. High-precision compensation and calibration of the bump positions in the first chip unit improves the connection accuracy between external pads or other chip units and the first chip unit, further enhancing the electrical connection yield and reliability of the package. This helps reduce alignment misalignment between chips or between the chip and external pads during packaging and can be widely applied in industrial production. The technical solution provided in this disclosure does not require improving the precision of the pick-and-place machine, saving equipment modification costs; the calibration layer increases the area of the metal connection, effectively improving the yield stability of the process; the calibration layer avoids stress concentration in the metal connection, preventing reliability issues such as easy breakage after long-term use; and through secondary patterned exposure and interconnection, connection reliability is enhanced, achieving a comprehensive improvement in packaging competitiveness with a low-cost solution. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 The diagram shows the alignment offset of the chip in the relevant process. Figure 2 The diagram shows the alignment offset between the chip and the external connection line in the relevant process. Figure 3 The image shown is a planar schematic diagram of the reconstituted wafer; Figure 4 The diagram shown is a comparative illustration of the bump area in a first chip unit provided in an embodiment of this disclosure; Figure 5 The diagram shown is a schematic diagram of the connection between a first chip unit and an external connection line according to an embodiment of this disclosure; Figure 6 The diagram shows the positional relationship between the first protrusion and the connecting part. Figure 7 The diagram shown illustrates the first exposure process. Figure 8 The diagram shown illustrates the second exposure process. Figure 9 The diagram shows the positional relationship between the first protrusion and the transition protrusion. Figure 10 The diagram shown illustrates the formation of the connecting part; Figure 11 The diagram shown illustrates another possible formation of the connecting part; Figure 12 The diagram shown is a schematic representation of the relative positional relationship between a first region and a protrusion according to an embodiment of this disclosure. Figure 13 The diagram shown is a schematic diagram of a wafer-level chip packaging structure provided in an embodiment of this disclosure; Figure 14 The diagram shown is a schematic diagram of another wafer-level chip packaging structure provided in an embodiment of this disclosure; Figure 15 As shown Figure 13 Flowchart of the fabrication process for a mid-wafer-level chip packaging structure. Detailed Implementation
[0020] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0021] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0022] Figure 1 The diagram shown illustrates the alignment offset of the chip in the relevant process. Figure 2 The diagram shown illustrates the alignment offset between the chip and external interconnects in the relevant process. Please refer to it. Figure 1 The unavoidable positional misalignment in the surface mount technology (SMT) process will further lead to alignment misalignment in subsequent photolithography processes. This alignment misalignment reduces the contact area between the first chip 01' and the second chip 02', potentially affecting characteristic impedance. Please refer to [reference needed]. Figure 2 The alignment misalignment caused by objective constraints leads to the failure of the connection between the first chip 01' and the external connection line, resulting in the risk of unreliable connection.
[0023] To address the aforementioned issues, this disclosure provides a process method for compensating for photolithographic alignment misalignment, which increases the contact area between the chip and external pads or other chips, thereby improving connection reliability.
[0024] Figure 3 The image shown is a planar schematic diagram of the reconstituted wafer. Figure 4 The diagram shown is a comparative illustration of the bump area in a first chip unit according to an embodiment of this disclosure. Figure 5The diagram shown is a schematic representation of the connection between a first chip unit and an external connection line according to an embodiment of this disclosure. Figure 6 The diagram shows the positional relationship between the first protrusion and the connecting part. Figure 7 The diagram shown illustrates the first exposure process. Figure 8 The diagram shown illustrates the second exposure process. Figure 9 The diagram shows the positional relationship between the first protrusion and the transition protrusion. Figure 10 The diagram shown illustrates the formation of the connecting part. Please refer to it. Figures 3 to 10 This disclosure provides a process method for compensating for photolithographic alignment misalignment, comprising: multiple reconstructed first chip units 01, each first chip unit 01 including a chip and a first bump 00, the first bump 00 being located on one side surface of the chip; forming a connection portion 31 on the first bump 00, the radius of the connection portion 31 being increased by a radius greater than or equal to 1.5 times the standard deviation of the reconstructing accuracy of the first chip unit 01; and continuing to form a redistribution layer on the connection portion 31; and / or, in the first chip unit 01 including the first bump 00... A calibration layer 30 and a transition bump 40 are formed on one side. The transition bump 40 is located on the side of the calibration layer 30 away from the first bump 00. The calibration layer 30 undergoes at least a first exposure and a second exposure. The first exposure is based on the overall position of the reconstructed multiple first chip units 01, and the second exposure is based on the actual position of a single first chip unit 01. Metal is injected into the pattern after exposure and development of the calibration layer 30 to form a connecting portion 31. Along the direction perpendicular to the plane where the calibration layer 30 is located, the connecting portion 31 overlaps with the first bump 00 and also overlaps with the transition bump.
[0025] Please refer to Figures 4 to 6 In one optional embodiment provided in this disclosure, the area of the original bump in the first chip unit 01 is M1. When the first chip unit 01 is offset during mounting, and the offset is large, a relative offset will occur between the first chip unit 01 and the redistribution layer, external pads, or other chips, resulting in adverse situations such as reduced connection area or connection failure (e.g.) Figure 2 (As shown). In this embodiment, a connecting portion 31 is provided on the first bump 00. The area of the connecting portion 31 can enlarge the area of the first bump 00. For example, the area of the connecting portion 31 in the first chip unit 01 is M2, where M2 > M1. Please refer to... Figure 5 and Figure 6 Because the larger connection portion 31 can tolerate a certain range of error offset, the first bump 00 in the first chip unit 01 can still achieve connection with the redistribution layer, external pads, or chips on other substrates, reducing open circuits or poor edge contact, thereby improving production yield and increasing the process tolerance window of the entire interconnect process. Please refer to... Figure 6A redistribution layer is formed on the connection portion 31, which can achieve precise alignment of the first chip unit 01 with other chips or redistribution layers, thereby improving production yield.
[0026] In actual manufacturing, taking the first chip unit 01 reassembly accuracy of 5μm (one standard deviation) as an example, assuming the original design of the first bump 00 radius is 5μm, when the deviation exceeds 10μm, the upper and lower layers cannot be connected at all, which is considered defective. In reality, the yield rate of the upper and lower layers being able to contact is about 95%. In this embodiment, the radius of the connecting part 31 is increased by 1.5 times the standard deviation to 7.5μm. When the deviation exceeds 15μm, the upper and lower layers cannot be connected at all, which is considered defective. This can achieve an alignment yield rate of about 99.73%. This embodiment can effectively improve the yield rate of chip reassembly and positioning.
[0027] Thus, by setting the connection part 31, the area of the connection part 31 can be relatively larger than the area of the first bump 00 without changing the original chip area. This is beneficial to allow a certain degree of alignment offset and improve the reliability of the connection between the first chip unit 01 and other chips, external pads or redistribution layers.
[0028] Please refer to Figures 7 to 9 In another optional embodiment provided in this disclosure, the first substrate 10 includes a plurality of recombined first chip units 01. This disclosure does not limit the number or arrangement of the first chip units 01 on the first substrate 10. Each first chip unit 01 includes a chip and a first bump 00. Optionally, the chip and the first bump 00 can be directly connected, or a redistribution layer may be included between the chip and the first bump 00; this disclosure does not limit this. The first bump 00 is located on one side surface of the chip. Please refer to... Figure 7 A calibration layer 30 and a transition bump 40 are formed on one side of the first chip cell 01 containing the first bump 00. The calibration layer 30 undergoes at least two exposures. The first exposure is based on the overall position of the multiple recombined first chip cells 01. For example, the first exposure may be based on the overall position of 2, 3, 4, or other numbers of first chip cells 01. Figure 7 The illustration only takes two recombined first chip units 01 as the overall reference position. This disclosure does not limit the number of first chip units 01 used as the overall reference position in the first exposure. The specific number can be set according to actual needs.
[0029] In practice, due to potential misalignment and expansion / contraction during the chip transfer process, the actual placement position of the transferred chip often deviates from the predetermined placement position. This results in the connection circuit pattern obtained by exposing according to the mask pattern not accurately aligning with the chip, thus preventing accurate connection between the chip and another chip or between the chip and external pads. This disclosure addresses this by exposing the calibration layer 30 at least twice. The first exposure uses the designed mounting positions of the two chips, which are the positions that should be obtained after calibration (i.e., the expected mounting positions). The alignment reference logic for this layer, taking two chips as an example, specifically uses the center position of the positioning points of the two chips' actual positions. In this way, the theoretical position is offset by the same distance from the actual positions of the two chips, but in opposite directions. Please refer to... Figure 8 The second exposure, based on the first exposure, further uses the actual position of a single first chip unit 01 as a reference, and can be used to individually correct the actual offset of each first chip unit 01, so as to ensure that the formed calibration layer 30 pattern (and the subsequently formed connection portion 31) can be accurately aligned with the actual position of the first bump 00 on the chip.
[0030] Please refer to Figure 10 After at least two exposures, the calibration layer 30 undergoes further development processes to obtain a calibrated pattern. Metal is first deposited on the pattern of the calibration layer 30, and then electroplated to the required thickness to form the connection portion 31. Please refer to... Figure 9 On the side of the connection portion 31 opposite to the first bump 00, a transition bump 40 is formed in accordance with the expected position of the first chip unit 01, so that the transition bump 40 can be precisely connected with other chips, external pads or redistribution layers.
[0031] Thus, by applying a multi-exposure strategy based on "expected position alignment + actual position alignment" to the calibration layer 30, the alignment error introduced by the chip position, rotation and deformation after chip mounting can be compensated. The position of the first bump 00 in the chip can be compensated and calibrated with high precision, which is beneficial to improving the connection accuracy of the first chip unit 01 with other chips, external pads or redistribution layers, and further improving the electrical connection yield and reliability of the package.
[0032] Please continue to refer to this. Figures 7 to 8The first exposure uses the overall position of multiple first chip units 01 as a reference. A first mask 11 is used to set first alignment marks 111 on at least two recombined first chip units 01. The first exposure is based on the first alignment marks 111. Optionally, the first alignment marks 111 can be set on 3, 4, 5, 6... first chip units 01. Alternatively, the first alignment marks 111 can be set on all first chip units 01 on the first substrate 10. This disclosure does not limit the number of first chip units 01 used to set the first alignment marks 111. This disclosure does not limit the number, position, or shape of the first alignment marks 111. For example, the shape of the first alignment marks 111 can be a cross, a circle, a triangle, a polygon, etc. Figure 7 The illustration only takes the first alignment mark 111 as a cross shape. For example, the first alignment mark 111 can be located at the key corner or edge of the reconstructed chip array to establish a high-precision global coordinate system, which can effectively compensate for macroscopic deformations such as global thermal expansion and contraction or warping that may occur in the first substrate 10 during processing.
[0033] Please refer to Figure 8 The second exposure uses a second mask 12 and is based on the actual position of the first bump 00 on a single first chip unit 01. This includes setting a second alignment mark 112 on the single first chip unit 01, and using the second alignment mark 112 as the reference for the second exposure. That is, the second alignment mark 112 is a unique position mark for each chip in each first chip unit 01. By using the second alignment mark 112 as a reference for the second exposure of the calibration layer 30, minor local deviations such as translation and rotation that occur during the chip mounting process can be individually corrected.
[0034] It should be noted that, Figure 7 The area of the intermediate calibration layer 30 that was exposed for the first time is S1. Figure 8 The area of the calibration layer 30 that has undergone a second exposure is S2. Because the alignment references for the first and second exposures are different, the area S2+S1 after two exposures is larger than the area S1 after only one exposure. Furthermore, the minimum connection area where the connector 31, after two exposures, development, and deposition, connects to the chip 00 is larger than the minimum connection area when an offset chip is directly connected to an external chip or pad in related technologies. Please refer to... Figure 9 This increases the pattern area of the exposure area in the calibration layer 30, resulting in a larger planar area of the connection portion 31 formed in the subsequent development and electroplating processes, and a larger contact area with the first protrusion 00, which can improve connection reliability and reduce contact resistance.
[0035] Thus, by using different levels of alignment marks in different exposures, cumulative errors can be overcome and local precise positioning can be achieved, significantly improving the connection effect between the connection part 31 and the first bump 00 in the first chip unit 01. This method is applicable to high-density interconnects and fan-out packages, and can effectively compensate for both the global deformation error of the first substrate 10 and the local mounting deviation of a single chip.
[0036] Please refer to Figure 10 The formation of a calibration layer 30 on one side of the first chip unit 01, including the first bump 00, includes: the calibration layer 30 is formed by first exposure and second exposure of positive photoresist, followed by development to form a pattern, depositing metal inside the pattern and electroplating to a preset thickness. In one optional embodiment provided in this disclosure, the calibration layer 30 is exposed using a positive photoresist. A positive photoresist is a photosensitive material that undergoes a photochemical reaction in the exposed area under ultraviolet light and dissolves in the developer. The exposed area of the positive photoresist is removed after dissolution, while the non-exposed area is retained. Positive photoresists typically have good resolution and vertical sidewall characteristics, ensuring the accuracy and shape of the pattern. Positive photoresists include phenolic resins, polymethyl methacrylate, etc. This disclosure does not limit the composition of the positive photoresist; it can be selected according to actual needs. In this embodiment, a positive photoresist is applied to the calibration layer 30. This positive photoresist is dissolved and removed in the exposure area to form a pattern, which is the pattern used to form the connector 31 in the calibration layer 30. Combined with the aforementioned at least two exposures, the pattern formed after the positive photoresist is developed can accurately correspond to the actual position of the first bump 00 on the chip. The connector 31 is formed inside the pattern through deposition, electroplating, or other methods. The connector 31 accurately corresponds to the position of the first bump 00 in the first chip unit 01, solving the problem of chip position offset. Position adjustment is achieved in the calibration layer 30, facilitating subsequent operations. A transition bump 40 is then formed on the calibration layer 30. The transition bump 40 can be set according to the expected position of the first chip unit 01 to align with the original wiring pattern on the mask.
[0037] Thus, by using positive photoresist to expose the calibration layer 30, the area exposed by the positive photoresist is the area where the connection portion 31 in the calibration layer 30 is located, which is beneficial to efficiently and accurately manufacture the connection portion 31 that is accurately aligned with the first bump 00 in the first chip unit 01; positive photoresist usually uses a neutral alkaline solution, which has a smaller impact on the environment.
[0038] Figure 10 The diagram only illustrates the exposure steps using positive photoresist. It is understood that negative photoresist can also be used to fabricate the calibration layer 30. Figure 11 The diagram shown illustrates another possible configuration of the connecting portion. Please refer to the provided text. Figure 11In one optional embodiment provided in this disclosure, the calibration layer 30 is formed by first exposure and second exposure of positive photoresist, followed by development to form a pattern, depositing metal inside the pattern and electroplating to a preset thickness; removing the positive photoresist, and continuing to complete the fabrication of the calibration layer 30 using negative photoresist.
[0039] Specifically, negative photoresist is a type of photoresist that, under ultraviolet light irradiation, undergoes a photocrosslinking reaction in the exposed areas to form an insoluble network structure. During development, the exposed areas of the negative photoresist are retained, while the unexposed areas dissolve. Negative photoresist exhibits strong adhesion and high etch resistance. Materials for negative photoresist include polycarbonate resins, epoxy resins, etc. This disclosure does not limit the materials used in negative photoresist; the specific material can be selected according to actual process requirements.
[0040] Different types of photoresists can be used to meet different photolithography requirements. In this embodiment, the area removed after exposure of the positive photoresist can be used for pattern formation in the calibration layer 30. Further metal deposition or electroplating is then used to form the connection portion 31 within the pattern. The unexposed area of the positive photoresist is then removed using an etching solution. At this point, only one metal connection portion 31, precisely aligned with the first bump 00 in the first chip unit 01, remains on the surface of the first substrate 10. Since the area exposed by the negative photoresist is retained, the aforementioned metal connection portion 31 can be precisely covered or exposed using negative photoresist to construct a complete calibration layer 30. Furthermore, when multiple calibration layers 30 exist, the positive photoresist + negative photoresist method described in this embodiment can also be used to form the calibration layer 30 as described above. Combining different photolithography requirements with different types of photoresists can provide a variety of different solutions for the formation of the calibration layer 30.
[0041] Thus, by using positive photoresist to create a high-precision alignment pattern on the basis of high-precision double exposure alignment, and using negative photoresist to construct other parts of the calibration layer 30, not only are multiple optional manufacturing processes provided for the calibration layer 30, but the isolation performance and etching resistance of the areas in the calibration layer 30 other than the connecting part 31 can also be improved by the characteristics of the negative photoresist itself.
[0042] In one optional embodiment provided in this disclosure, the metal includes copper. As previously described, after at least two exposures and developments using positive photoresist, the calibration layer 30 forms a pattern. A metal material is then deposited and electroplated to a certain thickness within the pattern to obtain a metal connection portion 31 precisely aligned with the first bump 00 in the first substrate 10. The metal used to form the connection portion 31 includes copper. Copper has low resistance; using copper as the material for the connection portion 31 can reduce the connection resistance between the connection portion and the first bump 00, and also reduce signal transmission loss and delay. Copper has high thermal conductivity; when the arrangement density of the first chip unit 01 in the first substrate 10 is high, heat concentration is easily caused. Using copper as the connection portion 31 can effectively conduct the heat generated by the first chip unit 01 in the first substrate 10 away, avoiding the accumulation of local hot spots, effectively ensuring the long-term stable operation of the chip, and enhancing the thermal reliability of the chip package. The above is merely an example; the material of the connection portion 31 can also be other metals, and this disclosure does not limit this.
[0043] Furthermore, copper is the mainstream process technology for fabricating redistribution layers and copper pillars in chip packaging. In this embodiment, the connection part 31 is formed by electroplating copper as a raw material, which can be manufactured on the existing production line without the need for additional raw materials or processes, thereby reducing production costs and facilitating industrial production.
[0044] Thus, by using copper as the raw material for the interconnect 31, an interconnect 31 with excellent electrical and thermal conductivity can be deposited and electroplated based on copper's low resistance and thermal conductivity without adding additional raw materials or processes. This significantly reduces signal loss and power consumption, facilitates industrialization, and improves the reliability of chip packaging. Using copper as the interconnect 31 is suitable for the mass production of high-density interconnects, improving yield without increasing manufacturing costs.
[0045] The process for compensating for photolithographic alignment misalignment provided in this disclosure further includes: providing a second chip unit or redistribution layer, the second chip unit including a chip and a second bump; the second chip unit or redistribution layer is connected to the first chip unit 01 through the transition bump 40.
[0046] Specifically, the first substrate 10 includes a reconstituted first chip unit 01, which includes a chip and a first bump 00. To address the photolithography misalignment problem caused by chip mounting misalignment due to objective limitations, the first chip unit 01, which may experience positional misalignment, can be precisely aligned using the calibration layer 30 and the transition bump 40 provided in this disclosure. This eliminates the need to improve the precision of the pick-and-place machine, saving equipment modification costs and making it widely applicable in industrial production.
[0047] Figure 12 The diagram shown is a schematic representation of the relative positional relationship between a first region and a protrusion according to an embodiment of this disclosure. Please refer to it. Figure 12In the process of compensating for photolithographic alignment misalignment provided in this disclosure, the first chip unit 01 includes a plurality of first regions 011, the connecting portion 31 is located at the center of the first region 011, the area of the connecting portion 31 is larger than the area of the first bump 00, and the center of the connecting portion 31 overlaps with the center of the first bump 00.
[0048] In one optional embodiment provided in this disclosure, the first chip unit 01 includes a plurality of first regions 011. It should be noted that, in this embodiment, "first region 011" refers to a virtual, artificially divided region on one side surface of the first chip unit 01 including the first bump 00. This disclosure does not limit the shape, number, arrangement, etc. of the first regions 011. Figure 12 The illustration is based on the example of the first region 011 being square and arranged in an array within the first chip unit 01.
[0049] In this embodiment, the connection portion 31 is located at the center of the first region 011 in the chip. Based on this, the area of the connection portion 31 in the first region 011 in the plane direction parallel to the first substrate 10 is further expanded, which can provide the largest possible alignment deviation tolerance for a single first bump 00 in the first chip unit 01.
[0050] Inherent errors in chip manufacturing or the deposition of the first bump 00 may cause slight local offsets in the first bump 00 within a single chip. By placing the connector 31 at the center of the first region 011 and increasing the area of the connector 31 relative to the area of the first bump 00, a certain tolerance for error can be provided, improving the reliability of the connection between the first bump 00 and other chips, external pads, or redistribution layers. Furthermore, dividing the first region 011 in the first chip unit 01 into an array arrangement, with the connector 31 located at the center of each first region 011, facilitates the standardized and mass production of the connector 31, thereby improving production efficiency.
[0051] Thus, by dividing the first chip unit 01 into multiple first regions 011, setting the connection part 31 at the center of the first region 011, and expanding the area of the connection part 31, it is beneficial to the industrialization and mass production of the connection part 31, and can optimize the process tolerance margin of each first bump 00, improve the mechanical strength and thermomechanical reliability of the first bump 00, increase the contact area between the first bump 00 and the connection part 31, thereby improving the connection strength between the two.
[0052] In one optional embodiment provided in this disclosure, a second chip unit or redistribution layer is provided, the second chip unit including a chip and a second bump; the second chip unit or redistribution layer is connected to the first chip unit 01 through a connection portion 31.
[0053] In this way, without setting a calibration layer 30 and a transition bump 40, precise alignment and connection with the second chip unit, external pads or redistribution layer can be achieved simply by increasing the area of the connection part 31, which can reduce the process flow and reduce production costs.
[0054] In one optional embodiment provided in this disclosure, a first calibration layer and a first transition bump are formed on the transition bump 40, the first transition bump being located on the side of the first calibration layer opposite to the transition bump 40; metal is injected into the pattern after exposure and development of the first calibration layer to form a first connection portion, the orthographic projection of the first connection portion on the first substrate 10 at least covers the first transition bump and covers the transition bump 40; along a direction perpendicular to the plane where the first calibration layer is located, the transition bump 40 is located between the first bump 00 and the first transition bump.
[0055] It should be noted that when the mounting offset of the first chip unit 01 is too large, or to avoid the connector 31 being too large and potentially overlapping with other bumps, the first bump 00 can be gradually adjusted from the offset position to the correction reference position of the first transition bump 60 by setting two or more calibrations. Understandably, the first calibration layer can also be formed with a larger first connector area using two or more exposures. The exposure reference of the first connector can be set according to actual needs, and this disclosure does not impose any limitations.
[0056] Figure 13 The diagram shown is a schematic representation of a wafer-level chip packaging structure provided in an embodiment of this disclosure. Figure 14 The diagram shown is a schematic of another wafer-level chip packaging structure provided in this embodiment of the present disclosure. Please refer to... Figures 3 to 14 This disclosure provides a wafer-level chip packaging structure, fabricated using the aforementioned process for compensating for photolithographic alignment misalignment, including: [Please refer to...] Figure 13 The first chip unit 01 is reassembled, comprising a chip and a first bump 00 located on one side of the chip. A connection portion 31 is formed on the first bump 00, the radius of which is increased by a radius greater than or equal to 1.5 times the standard deviation of the reassembly accuracy of the first chip unit 01. A redistribution layer 80 is further formed on the connection portion 31; and / or, please refer to... Figure 14The first chip unit 01 includes a connecting portion 31 and a transition bump 40. The transition bump 40 is located on the side of the calibration layer 30 opposite to the first bump 00. The calibration layer 30 undergoes at least a first exposure and a second exposure. The first exposure is based on the overall position of the multiple recombined first chip units 01, and the second exposure is based on the actual position of a single first chip unit 01. The pattern formed by the exposure and development of the calibration layer 30 forms the connecting portion 31. Along a direction perpendicular to the plane of the calibration layer 30, the connecting portion 31 overlaps with the first bump 00 and also overlaps with the transition bump 40. The packaging structure also includes a second chip unit 02 or an external pad. The second chip unit 02 or the external pad includes a second bump 03. The second chip unit 02 or the external pad is connected to the transition bump 40. The packaging structure also includes a packaging layer 70, which at least partially covers the second chip unit 02 or the external pad.
[0057] Please refer to Figure 13 In the wafer-level chip packaging structure provided in this embodiment, a redistribution layer 80 can be provided on the transition bump 40 to achieve the connection between the first chip unit 01 and other chips or external pads. For details on the fabrication of the packaging structure in this embodiment, please refer to [reference needed]. Figure 15 , Figure 15 As shown Figure 13 The flowchart illustrates the fabrication process of a mid-wafer-level chip packaging structure. In this embodiment, the shape of the connection portion 31 can be the same as the shape of the first bump 00, only with a certain degree of enlargement relative to the area of the first bump 00. In this embodiment, the packaging of the first chip unit 01 can be independent of the substrate, using only a temporary bonding film. After molding, the temporary bonding film can be removed, and then a redistribution layer 80 can be fabricated on the connection portion 31 to achieve the connection between the first chip unit 01 and external pads or other chips. Figure 15 This illustration only shows the case where the wafer-level chip packaging unit includes one redistribution layer 80. It is understood that the wafer-level chip packaging unit may also include other chips or multiple redistribution layers, and this disclosure is not limited thereto.
[0058] Please refer to Figure 14 In the wafer-level chip packaging structure provided in this embodiment, the alignment between the transition bump 40 formed after two exposures and the second chip unit 02 is more precise, which can realize high-density, high-performance vertical interconnection from chip to chip or from chip to redistribution layer or external pad, improve interconnection reliability, and reduce contact resistance.
[0059] Understandably, the calibration layer 30 is typically made of polymer. This disclosure does not limit the composition of the portion of the calibration layer 30 other than the connecting portion 31. To achieve electrical isolation between different connecting portions 31 or between the connecting portion 31 and the chip, the material of the calibration layer 30 must also be an insulating material, which can be used as a dielectric layer or passivation layer in the packaging structure. The wafer-level chip packaging structure fabricated using the photolithography misalignment compensation process provided in this disclosure can serve as a basic structure in advanced packaging technologies, enabling high-density, high-performance interconnection between the first substrate 10 and external pads or between the first substrate 10 and other substrates.
[0060] Please combine Figure 14 The wafer-level chip packaging structure includes a first chip unit 01 and a second chip unit 02. Optionally, the second chip unit 02 can be a chip of the same or different type as the first chip unit 01; this disclosure does not limit this. The first substrate 10 includes a plurality of recombined first chip units 01. Figure 14 The illustration is based solely on an example of a first chip unit 01 on the first substrate 10, and this disclosure is not limited thereto. The first chip unit 01 includes a chip and a first bump 00. The calibration layer 30 includes a connection portion 31 formed by development and electroplating after at least two exposures. Along a direction perpendicular to the plane of the first substrate 10, the connection portion 31 in the calibration layer 30 overlaps with the first bump 00 and also overlaps with a transition bump 40. The second chip unit 02 is located on the side of the transition bump 40 away from the first chip unit 01. The transition bump 40 and the second bump 03 in the second chip unit 02 are precisely aligned. That is, the connection portion 31 and the transition bump 40, formed after at least two exposures, bridge and interconnect the first chip unit 01 and the second chip unit 02 in the first substrate 10. Optionally, the connection between the second bump 03 and the transition bump 40 can be a solder ball connection or a copper-copper bond; this disclosure does not limit this. Figure 14 This illustration only shows the connection between the transition bump 40 and the second bump 03 and does not represent the actual connection between the first chip unit 01 and the second chip unit 02. Optionally, a redistribution layer may be included between the chip in the first chip unit 01 and the first bump 00, and a redistribution layer may be included between the chip in the second chip unit 02 and the second bump 03. This disclosure does not limit this aspect. Figure 14 The illustration is based on the example where neither the first chip unit 01 nor the second chip unit 02 includes a redistribution layer.
[0061] Thus, the wafer-level chip packaging structure provided in this embodiment allows multiple chip units from different substrates, which may be of different types (such as logic chips, memory chips, sensors, etc.), to achieve high-precision alignment of different chip units and redistribution layers in the vertical direction through a calibration layer 30 and a transition bump 40 with at least two high-precision exposures. This can improve the contact area, mechanical strength, thermal reliability, and electrical performance of the connection interfaces on both sides of the transition bump 40.
[0062] The wafer-level chip packaging structure provided in this disclosure can be further expanded into a multi-layer stacked three-dimensional packaging structure based on the connection between the first chip unit 01 and the second chip unit 02. It supports complex modular design and allows vertical integration of different functional modules such as processing, storage, and I / O. It can achieve ultra-high chip and functional density while ensuring high-precision and high-reliability connection, and greatly reduce the package size.
[0063] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A process method for compensating for photolithographic alignment misalignment, characterized in that, include: Multiple recombined first chip units, each first chip unit comprising a chip and a first bump, the first bump being located on one side surface of the chip; A connection portion is formed on the first bump, the radius of the connection portion is increased by an amount greater than or equal to 1.5 times the standard deviation of the reorganization accuracy of the first chip cell, and a redistribution layer is formed on the connection portion. And / or, a calibration layer and a transition bump are formed on one side of the first chip cell including the first bump, the transition bump being located on the side of the calibration layer opposite to the first bump, the calibration layer undergoing at least a first exposure and a second exposure, the first exposure being based on the overall position of the plurality of recombined first chip cells, and the second exposure being based on the actual position of a single first chip cell; Metal is injected into the pattern after the calibration layer is exposed and developed to form a connecting portion. Along a direction perpendicular to the plane where the calibration layer is located, the connecting portion overlaps with the first protrusion and also overlaps with the transition protrusion.
2. The process method for compensating for photolithographic alignment misalignment as described in claim 1, characterized in that, The first exposure is based on the overall position of the multiple recombined first chip units, and the second exposure is based on the actual position of a single first chip unit, including: A first alignment mark is set for at least two recombined first chip units, and the first exposure is based on the first alignment mark; A second alignment mark is set for a single first chip cell, and the second exposure is based on the second alignment mark.
3. The process method for compensating for photolithographic alignment misalignment as described in claim 1, characterized in that, The step of forming a calibration layer on one side of the first chip unit including the first bump includes: The calibration layer is formed by first exposure and second exposure of positive photoresist, followed by development to form the pattern, and metal is deposited and electroplated inside the pattern to a preset thickness.
4. The process method for compensating for photolithographic alignment misalignment as described in claim 1, characterized in that, The calibration layer is formed by first exposure and second exposure of positive photoresist, followed by development to form the pattern, and metal is deposited and electroplated inside the pattern to a preset thickness; Remove the positive photoresist and continue fabricating the calibration layer using negative photoresist.
5. The process method for compensating for photolithographic alignment misalignment as described in claim 1, characterized in that, The metal includes copper.
6. The process method for compensating for photolithographic alignment misalignment as described in claim 1, characterized in that, A second chip unit or redistribution layer is provided, the second chip unit including a chip and a second bump; the second chip unit or the redistribution layer is connected to the first chip unit through the transition bump.
7. The process method for compensating for photolithographic alignment misalignment as described in claim 6, characterized in that, The first chip unit includes multiple first regions, the connection portion is located at the center of the first region, the area of the connection portion is larger than the area of the first bump, and the center of the connection portion overlaps with the center of the first bump.
8. The process method for compensating for photolithographic alignment misalignment as described in claim 1, characterized in that, A second chip unit or redistribution layer is provided, the second chip unit including a chip and a second bump; the second chip unit or the redistribution layer is connected to the first chip unit through the connection portion.
9. The process method for compensating for photolithographic alignment misalignment as described in claim 1, characterized in that, A first calibration layer and a first transition bump are formed on the transition bump, wherein the first transition bump is located on the side of the first calibration layer opposite to the transition bump; Metal is injected into the pattern after exposure and development of the first calibration layer to form a first connection portion, the first connection portion at least covering the first transition bump and covering the transition bump; The transition bump is located between the first bump and the first transition bump.
10. A wafer-level chip packaging structure, characterized in that, Fabricated using the process method for compensating for photolithographic alignment misalignment as described in any one of claims 1-9, comprising: The first chip unit is reassembled, the first chip unit includes a chip and a first bump, the first bump is located on one side of the chip; a connection portion is formed on the first bump, the radius of the connection portion is increased by a radius dimension greater than or equal to 1.5 times the standard deviation of the reassembly accuracy of the first chip unit, and a redistribution layer is further formed on the connection portion; And / or, the first chip unit includes a connector and a transition bump, the transition bump being located on the side of the calibration layer opposite to the first bump, the calibration layer undergoing at least a first exposure and a second exposure, the first exposure being based on the overall position of the plurality of reconstituted first chip units, and the second exposure being based on the actual position of a single first chip unit; the pattern formed by the exposure and development of the calibration layer forms a connector, the connector overlapping with the first bump and the transition bump along a direction perpendicular to the plane of the calibration layer; The packaging structure further includes a second chip unit or an external pad, the second chip unit or the external pad including a second bump, and the second chip unit or the external pad being connected to the connecting portion or the transition bump; The packaging structure further includes a packaging layer that at least partially covers the second chip cell or the external pad.