Electromagnetic side-channel protection measures

Abstract

The present disclosure relates to electromagnetic side-channel countermeasures. Embodiments herein relate to countermeasures against electromagnetic (EM) probing attacks on voltage regulators (VRs) of cryptographic circuits. In one aspect, the clamping strength of a VR (e.g., a switched-capacitor VR) is dynamically and randomly modulated. The VR can include switches for transferring charge, where the switches can include multiple sub-switches in parallel, and the number of active switches is randomly changed to randomize EM emissions. In another aspect, the capacitors of a VR are formed in a metal routing layer (e.g., a top metal layer) of an integrated circuit package, where the capacitors have interdigitated electrodes that cancel current in and out of the electrodes, thereby reducing EM emissions. In another aspect, a resonant VR includes circuitry for detecting changes in current or voltage that are related to changes in its resonant frequency due to being subjected to EM probing.

Description

Technical Field

[0001] This disclosure relates to electromagnetic side-channel protection measures. Background Technology

[0002] Cryptographic circuits are used to securely store cryptographic information in computing devices. Examples of cryptographic circuits include circuits that implement symmetric-key encryption algorithms (e.g., AES (Advanced Encryption Standard)), asymmetric-key encryption algorithms (e.g., RSA (Rivest-Shamir-Adleman) or elliptic curve cryptography (ECC)), hash functions (e.g., SHA-256), and digital signature algorithms (e.g., ECDSA (Elliptic Curve Digital Signature Algorithm)). These circuits are all constructed using logic gates to perform the complex mathematical operations required for encryption and decryption processes. However, there remains a persistent need to prevent attackers from compromising cryptographic circuits. Summary of the Invention

[0003] According to one embodiment of this disclosure, an apparatus is provided, comprising: one or more switches coupled between an input node and an output node, wherein a respective switch of the one or more switches includes a plurality of sub-switches connected in parallel; one or more capacitors coupled to the one or more switches; and control circuitry coupled to a control gate of the one or more switches including the plurality of sub-switches, wherein the control circuitry includes a random number generator.

[0004] According to one embodiment of this disclosure, an apparatus is provided, comprising: a substrate including a circuit; one or more metal layers on the substrate; and a capacitor in a respective metal layer of the one or more metal layers, wherein the capacitor includes an interdigitated first electrode and a second electrode; and a via coupled between the first electrode and the second electrode and the circuit.

[0005] According to one embodiment of this disclosure, an apparatus is provided, comprising: a resonant voltage regulator (VR) including a portion of a substrate and an inductor in a metal layer above the substrate; and control circuitry coupled to the resonant voltage regulator to monitor the current of the resonant VR, wherein the control circuitry is configured to determine, based on the monitoring, whether the inductor is subjected to electromagnetic detection.

[0006] According to one embodiment of this disclosure, a method is provided, comprising: receiving an input voltage at an input node of a switched capacitor voltage regulator; and controlling a plurality of switches to transfer charge from the input node to an output node through one or more capacitors, wherein at least one respective switch of the plurality of switches comprises a plurality of sub-switches connected in parallel, and the control comprises randomly activating a different number of the plurality of sub-switches during a continuous charge-discharge cycle of the voltage regulator. Attached Figure Description

[0007] The embodiments of this disclosure will be more fully understood through the accompanying drawings, which are given below with reference to the specific embodiments and various examples of this disclosure. However, these drawings should not be construed as limiting this disclosure to the particular embodiments, but are for explanation and understanding only.

[0008] Figure 1 An example Advanced Encryption Standard (AES) accelerator circuit 100 according to various embodiments is depicted.

[0009] Figure 2 Example images depict electromagnetic (EM) probes and wafers containing cryptographic circuitry according to various embodiments.

[0010] Figure 3 A graph depicting the correlation magnitude versus the number of traces according to various embodiments is presented.

[0011] Figure 4 An example cross-sectional view of a package 400 containing cryptographic circuitry according to various embodiments is depicted.

[0012] Figure 5 An example voltage regulator (VR) 500 according to various embodiments of cryptographic circuitry is depicted, which is in the form of a charge pump configured as a voltage multiplier, wherein one or more switches include a plurality of sub-switches connected in parallel that can be controlled individually and randomly.

[0013] Figure 6 An example voltage regulator 600 of cryptographic circuitry according to various embodiments is depicted, which is in the form of a charge pump configured with a 1:1.33 ratio, wherein one or more switches include a plurality of sub-switches connected in parallel that can be controlled individually and randomly.

[0014] Figure 7A A view of a capacitor circuit 700 according to various embodiments is depicted, the capacitor circuit 700 including a capacitor 705 having interdigitated electrodes 705E1 and 705E2 in a metal wiring layer of an IC package.

[0015] Figure 7BThe yz plane at x=x0 is depicted according to various embodiments. Figure 7A A view showing the current flow direction in capacitor 705.

[0016] Figure 8 Example circuit 800, including a resonant VR 810 and a resonant frequency detector 820, is depicted according to various embodiments.

[0017] Figure 9 Depicting various embodiments Figure 8 An example implementation of the resonant VR 810 is an inductor-inductor-capacitor (LLC) resonant VR 900.

[0018] Figure 10 The use of current transformers to measure, according to various embodiments, is described. Figure 9 Example circuit 1000 of the current in VR 900.

[0019] Figure 11 Examples of components that may exist in computing system 1150 according to various embodiments for implementing the techniques described herein (e.g., operations, processes, methods, and methodologies) are shown. Detailed Implementation

[0020] As mentioned earlier, there remains a need to prevent attackers from compromising cryptographic circuits.

[0021] Attackers can use various types of attacks to obtain information such as secret keys from integrated circuits (ICs). ICs that store passwords or other secret data can be called cryptographic circuits. Cryptographic circuits can refer to digital circuits specifically designed to perform cryptographic operations (e.g., encryption or decryption), which use logic gates to manipulate data bits according to a specific cryptographic algorithm, thereby translating the mathematical steps of encryption into a hardware implementation using electronic circuits.

[0022] One type of attack is a side-channel attack, in which information such as power consumption and electromagnetic (EM) radiation is measured from the circuit while it is running. This information is called leaked information and may be related to the circuit's underlying computations or keys. For example, a timing attack can measure computation time (e.g., the time used to perform private key operations) and attempt to correlate computation time to reveal information such as a fixed Diffie-Hellman exponent, Rivest-Shamir-Adleman (RSA) factor, and other secret parameters of the cryptosystem.

[0023] Power analysis attacks involve physically measuring the current consumption of a circuit over time using external probes and attempting to correlate this current consumption with the instructions or data being processed. In a Simple Power Analysis (SPA) attack, the attacker observes the current consumption trace over time and attempts to apply it directly to the underlying cryptographic processing. Attackers use high-speed devices, such as modern digital oscilloscopes with high-speed analog-to-digital (A / D) capture capabilities, to collect a large amount of power consumption traces from thousands of encryptions. Another type of power analysis attack is Differential Power Analysis (DPA), which relies on statistical tests to isolate the signal of interest from the noisy and complex power signals on the device.

[0024] While power analysis attacks (SPA and DPA) are based on measured power consumption, electromagnetic (EM) attacks are based on measured electromagnetic signals (generated by current flowing in cryptographic circuits).

[0025] EM side-channel attacks pose a significant threat to cryptographic hardware accelerators; for example, EM radiation is directly related to the current consumption of the power supply.

[0026] One possible solution is to provide isolation between the load current characteristics and the input power supply visible to the attacker. For example, in integrated voltage regulators (IVRs), a possible solution to mitigate EM attacks includes a low-dropout (LDO) voltage regulator incorporating cryptographic hardware enhanced with arithmetic countermeasures. The LDO can transform the load current characteristics, thus providing a significant improvement in side-channel resistance against power-based SCA attacks. Arithmetic countermeasures provide uniform power consumption and EM side-channel resistance. For example, mask-based arithmetic countermeasures involve adding a pseudo-random mask to the input key, thereby breaking the correlation between data and corresponding power consumption. While this significantly improves side-channel resistance against power-based SCA attacks, the underlying load current perturbation remains visible through EM radiation, rendering these countermeasures ineffective.

[0027] The solution presented in this paper addresses the aforementioned and other shortcomings. In some aspects, the solution provides EM leakage suppression for VR, as well as EM detection and prevention utilizing top metal (TM) on-chip inductors.

[0028] In one aspect, the solution involves dynamic modulation of the clamping strength of the voltage regulator (VR). Clamping strength can refer to the VR's ability to maintain a stable output voltage despite input voltage fluctuations. In an example implementation, one or more switches of the VR comprise multiple sub-switches connected in parallel, which can be individually and randomly controlled to turn on or off. In another example implementation, the VR is a switched-capacitor charge pump, where one or more switches are used to transfer charge from the input node to the output node. Dynamic clamping strength modulation can randomize the switching times within or between switches in the VR, thereby altering the EM emissions from the circuit to make the attacker's task more difficult.

[0029] In another approach, the capacitor for the VR used in the cryptographic circuitry is formed within the metal wiring layer of the IC package (e.g., in a top metal layer above the substrate), where the capacitor has interdigitated electrodes. For example, the capacitor could be a metal-insulator-metal (MiM) capacitor. The capacitor will have currents with opposite phases, which cancel each other out and reduce EM emissions.

[0030] In another aspect, the resonant VR of the cryptographic circuit includes associated circuitry for detecting changes in the characteristics of VR (e.g., current or voltage) that are related to changes in the resonant frequency due to EM probing by an attacker. Detection of the probe can trigger an alarm and / or other actions, such as stopping the encryption process or shutting down the circuit. The resonant VR may have one or more inductors formed in a metal wiring layer that are susceptible to EM probing.

[0031] These solutions offer numerous advantages, including thwarting and detecting attackers' attempts to obtain highly sensitive security assets or other data from cryptographic circuits or other general circuits.

[0032] These and other features will be further illustrated in the following discussion.

[0033] Figure 1 An example Advanced Encryption Standard (AES) accelerator circuit 100 according to various embodiments is depicted. This circuit is a baseline unprotected 16-bit serial AES accelerator. Figure 2 A wafer probing experiment (which collected EM traces) evaluated the EM side-channel attack vulnerability of the circuit.

[0034] AES circuits operate by performing a series of multiple rounds of operations on data blocks, including substitution, permutation, and mixing with round keys. They scramble the data using a predefined lookup table (S-box), making it extremely difficult to decrypt without the correct key. The process involves a series of complex transformations applied to the data, encrypting it in a specific order, with each round adding further complexity by combining the data with a portion of the key.

[0035] Circuit 100 includes shared components, a key component, a data component, and other components. The shared components include 2:1 multiplexers 130 and 131, a MaptoField1 block 132, Sbox1 138 and Sbox2 139, and InvMap1 block 136 and InvMap2 block 137. The key component includes a 3:1 multiplexer 111 (mux), a key generator 112, and a key ordering unit 113. The data component includes a 4:1 mux 121, a MixColumns block 122, adders 123, 124, and 125, and a 2:1 mux 126. Other components include a key register 110 and a data register 120.

[0036] Multiplexer 121 receives the output from data register 120, plaintext, nextdata (output from mux 126), and the output from MixColumns block 122 on path 142, and provides a 16-bit value to data register 120. MixColumns refers to a specific operation in which each column of the state matrix is ​​multiplied with a fixed matrix using a special multiplication based on the Galois Field (GF(2^8)).

[0037] The output of data register 120 is input to adders 124 and 125. mux 130 receives the output of adder 124 and data on path 135, and provides the output to MaptoField1 block 132. Map to field refers to the process of representing data (usually multiple bytes) as elements of a specific finite field (e.g., the Galois field GF(2^8), which is the mathematical basis of the AES operation).

[0038] MaptoField1 block 132 provides output to the 2:1 mux 131 and adder 125. Mux 131 provides output to Sbox1 and Sbox2, which are the first and second lookup tables, respectively. "Sbox" stands for "Substitution Box," a component that performs non-linear transformations on 8-bit (one-byte) data blocks. It replaces each input byte with a unique, predefined output byte based on the lookup table. The outputs of Sbox1 and Sbox2 are provided to MixColumns block 122, InvMap1 block, and InvMap2 block. The outputs of InvMap1 and InvMap2 blocks are provided to key generator 112 and 2:1 mux 126.

[0039] mux 111 receives the output of key sequence 113 on path 140 and the output of the key generator on path 141, and provides the output to key register 110. The key register is a dedicated storage location used to hold the encryption key, which is then expanded into multiple round keys used during each round of the encryption process. The key register provides the output to key sequence, which in turn provides the output to adder 123 and path 140. The adder also receives data [15,14].

[0040] Figure 2 Example images of electromagnetic (EM) probes and wafers containing cryptographic circuitry according to various embodiments are depicted. EM emissions from the chip were collected using a Langer RF2 (Langer EMV-Technik GmbH, Bannewitz, Germany) and a Micro Field Analysis (MFA) probe. A high-resolution MFA probe (200µm) was used to scan the chip to locate peak EM emission locations. EM features were captured at a 100MHz clock frequency and 0.75V voltage to mitigate any process-related advantages. The features were averaged over 16 iterations with the same input to improve the signal-to-noise ratio (SNR).

[0041] Figure 3Graphs depicting the correlation magnitude versus the number of traces according to various embodiments are presented. Graph 300 depicts the case with the correct key, and combined graph 310 depicts the case with the incorrect key. Correlation EM analysis (CEMA) of an unprotected AES using the Hamming weight (HW) output by the Sbox as a power consumption model shows that the minimum number of traces to disclose (MTD) for the first extracted key byte is 10K, demonstrating the effectiveness of the EM attack. Metal layers (especially the top metal layer, see...) Figure 4 The EM probe acts as an antenna and emits EM radiation that is directly dependent on the input data. Traditional low-dropout (LDO) regulators hide load current characteristics from the input power supply, thus improving side-channel resistance to power-based SCA attacks. However, the power rails of the load power supply on higher metal layers emit EM radiation that can be picked up by the EM probe. The EM characteristics will contain information about the underlying load perturbations, which are directly dependent on the key. A CEMA attack on the resulting EM characteristics can reveal the key bytes, thereby compromising the security of the cryptographic system.

[0042] Figure 4 An example cross-sectional view of a package 400 containing cryptographic circuitry according to various embodiments is depicted. The package includes a silicon substrate 420 on which cryptographic circuitry 421, such as that of an AES accelerator, is disposed. Multiple top metal layers (also called wiring layers) are disposed on the substrate. For example, a set of metal layers 450 includes first to eighth metal layers 430-437, respectively. Layer 437 is the topmost metal layer. Metal layers typically become thicker the farther they are from the substrate, making the topmost metal layer the thickest. Furthermore, some components of the cryptographic circuitry 421, such as inductors and capacitors, can be formed in one or more metal layers. This approach saves space on the substrate and utilizes the properties of metals that are desirable for capacitors and inductors. Components in the top metal layers are vulnerable to EM probing by an attacker. The topmost metal layer 437 can be electrically coupled from above to external contacts of the package via solder balls 440 or other connectors.

[0043] In some cases, a bottom metal layer is provided beneath the substrate, typically for powering circuitry on the substrate. Theoretically, components of the cryptographic circuitry (e.g., inductors and capacitors) can be included within the bottom metal layer. The metal layers are coupled to each other and to the cryptographic circuitry 421 via vias extending vertically within the package. An example via 438 is illustrated. In one approach, vias extend between adjacent metal layers, and multiple vias can be stacked on top of each other or otherwise electrically coupled to provide a path to the substrate or between non-adjacent metal layers. In another approach, a single via can extend through multiple metal layers.

[0044] Figure 5 An example voltage regulator (VR) 500 according to various embodiments of a cryptographic circuit is depicted, which takes the form of a charge pump configured as a voltage multiplier, wherein one or more switches include multiple sub-switches connected in parallel that can be controlled individually and randomly. A charge pump converter is a direct current (DC) / DC voltage converter that uses capacitors to boost or deboost voltage.

[0045] VR includes an input node 510 that receives Vin, an output node 520 that provides Vout = 2xVin, a flying capacitor Cf, switches S1-S4, and an output capacitor Cout. Each switch may include a set of sub-switches coupled in parallel. For example, arrow 530 shows that switch S4 may include sub-switches S4a, S4b, S4c, and S4d coupled in parallel between nodes 531 and 532. In other words, switch (switch block or group) S4 represents a set of switches.

[0046] In the VR 500, capacitor Cf is charged by the input node and discharged to the output node. During the charging phase, S1 and S4 are turned on (making them conductive), while S2 and S3 are turned off (not conductive). This allows the input voltage to charge Cf. Next is the conversion phase. In this phase, S1 and S4 are turned off, while S2 and S3 are turned on, because the voltage across the capacitor does not change immediately. Cf then discharges to the output capacitor. Charging and discharging are repeated at a specified frequency in continuous charge-discharge cycles or periods, where each cycle includes both charging and discharging.

[0047] The sub-switches can be individually controlled by signals from control circuitry 540. For example, a sub-switch can be a metal-oxide-semiconductor field-effect transistor (MOSFET) with its control gate coupled to the control circuitry to receive an on / off voltage. Control circuitry 540 may include memory 542 for storing instructions and processor 541 for executing instructions to provide the functionality described herein. Control circuitry 540 may also include a random number generator 543 that generates one or more numbers for use during each charge / discharge cycle. The value of each number can range from 1 to the number of sub-switches (e.g., 4 in this example).

[0048] One factor determining the intensity of EM radiation from a cryptographic circuit is the switching time. The faster the signal switching, the stronger and more easily detected these emissions. This method uses dynamic VR clamp intensity modulation to mitigate the EM generated by VR switching. One or more switches in the charge pump each have multiple sub-switch plates controlled by their own drivers. For example, under the control of the control circuit, a set of drivers 560 can be used to drive sub-switches S4a-S4d.

[0049] Turning on fewer sub-switches results in higher resistance in the path, increasing the resistance-capacitance (RC) time constant and thus affecting charging and discharging times. As a result, the portion of the VR located in the top metal (e.g., a capacitor) will withstand a smaller current step, and the EM can be reduced. For example, the capacitor can be a metal-insulator-metal (MiM) capacitor formed in one or more metal layers. Furthermore, the switching time can be dynamically randomized in real time to prevent key information leakage. This randomization can occur within different sub-switches within a single switch and / or between different switches.

[0050] There are several ways to randomize the EM characteristics of a VR. For example, a random number can be used for each switch to be randomly controlled. For instance, if the random number is three, then for each of switches S1-S4, three sub-switches are turned on / off. That is, these sub-switches are active or selected. In one approach, one or more switches (but fewer than all switches) are randomly controlled. For example, S1 and S4 can be randomly controlled, and each includes four sub-switches, while S2 and S3 can include only a single switch without sub-switches. In another approach, different switches include different numbers of sub-switches. For example, S1 can include two sub-switches, and S2 can include four sub-switches. In yet another approach, the random number is used for two or more consecutive charge / discharge cycles, rather than changing for each charge / discharge cycle. Other variations are also possible.

[0051] The random generator is designed to cover truly random output, pseudo-random output, and / or mixed output.

[0052] A true random number generator (TRNG) uses unpredictable physical phenomena to generate random numbers. It is nondeterministic; its output depends on the physical process, ensuring true randomness. Examples of physical phenomena used include thermal noise (e.g., resistor or diode noise), radioactive decay, photon emission or scattering, and jitter in an oscillator (e.g., variability in a clock signal). Example implementations include amplifiers with noise as input (e.g., using a Zener diode as a noise source), oscillator sampling with jitter (e.g., sampling a high-frequency oscillator with a slower clock), and entropy collection circuitry. Entropy collection circuitry is a specialized electronic circuit designed to capture and transform the natural randomness from physical phenomena (e.g., thermal noise, clock jitter, or other unpredictable fluctuations) to generate a usable stream of random bits, thereby essentially collecting the entropy (disorder) present in the environment to generate truly random numbers.

[0053] A pseudo-random number generator (PRNG) uses a deterministic algorithm to generate seemingly random sequences of numbers. Its output depends on the initial seed value and is reproducible if the seed and algorithm are known. This approach can be used in applications requiring high speed and repeatability. Example implementations use linear feedback shift registers (LFSRs), cellular automata, and algorithmic methods such as linear congruence generators and the Mersenne Twister algorithm.

[0054] Hybrid random number generators combine TRNGs and PRNGs to enhance performance and randomness. In one approach, the TRNG is used to provide entropy or a seed for the PRNG.

[0055] Figure 6An example voltage regulator 600 according to various embodiments of a cryptographic circuit is depicted, which takes the form of a charge pump configured with a 1:1.33 ratio, wherein one or more switches include multiple sub-switches connected in parallel that can be controlled individually and randomly. VR includes an input node 601 and an output node 602, which provides Vout = Vin x 1.33. Multiple switches S10-S19 are depicted, each of which includes multiple sub-switches. For example, S10 includes sub-switches S10a, S10b, and S10c, which are controlled by their respective drivers 609. S10 is between nodes 601 and 603, and S11 is between nodes 603 and 602. Path 604 extends from node 603 to multiple grounded sub-paths. Path 604 includes S21 and C4. The first sub-path includes C1 and S13, the second sub-path includes S15 (coupled to the first path via S14), C2 and S16, and the third sub-path includes S20 (coupled to the second path via S17), C3 and S18. S12 and S19 can be coupled to power nodes 616 and 656, respectively, to receive the power supply voltage Vdd. In operation, charge is transferred from the input node to capacitor C4 and the capacitor below it, and from C4 to the output node 602.

[0056] Figure 5 and Figure 6 These are just two examples of VR that can use randomized switches. Generally, any type of switch-based VR can be used.

[0057] Figure 7A A view of a capacitor circuit 700 according to various embodiments is depicted, comprising a capacitor 705 having interdigitated electrodes 705E1 and 705E2 in a metal wiring layer of an IC package. Physical isolation is another effective method to reduce EM emissions used by attackers. However, metal shielding or protection is not applicable when no available metal layer is located above the top metal layer. This figure illustrates a phase array layout strategy for preventing or reducing EM emissions. The MiM capacitor formed in the top metal layer is arranged with top and bottom plates / electrodes adjacent to each other. During operation of the circuit including this capacitor, current flows from the lower metal layer through a first set of via rows to the first electrode of the capacitor, and then as a displacement current flows from the first electrode to the second electrode, and then through a second set of via rows to the lower metal layer. As a result, adjacent currents are 180 degrees out of phase, and the magnetic fields they generate can interfere destructively.

[0058] In the example implementation, the electrodes are located in a single wiring layer, such as the top wiring layer. The first electrode 705E1 includes a base 710 and a plurality of fingers 711, 712, 713, and 714 extending perpendicularly to the base 710. Similarly, the second electrode 705E2 includes a base 720 and a plurality of fingers 721, 722, 723, and 724 extending perpendicularly to the base 720. The fingers of the electrodes may extend parallel to each other and are separated by an insulating material.

[0059] Capacitor 705 can be considered as a single capacitor, which consists of different individual capacitors formed by adjacent fingers. Capacitor 705 is Figure 5 or Figure 6 An example of one of the capacitors in a VR or other switched capacitor VR or other circuits.

[0060] Capacitor circuit 700 extends in the xy plane, parallel to the substrate including other portions of the cryptographic circuit. Vias extend in the z-direction to couple conductive paths extending in the x-direction to capacitor fingers. For example, conductive paths 751, 752, 753, and 754 are coupled to fingers 711, 712, 713, and 714 via a first set of via rows 731, 732, 733, and 734, respectively, and conductive paths 761, 762, 763, and 764 are coupled to fingers 721, 722, 723, and 724 via a second set of via rows 741, 742, 743, and 744, respectively.

[0061] In the example implementation, conductive paths 751, 752, 753, and 754 are coupled to each other via path 770, and conductive paths 761, 762, 763, and 764 are coupled to each other via path 780. The conductive paths can be on the substrate or on a metal wiring layer lower than the metal wiring layer that includes the capacitor.

[0062] The upward or downward arrows on the vias indicate example directions of current flow into / out of the capacitor electrodes during operation of the circuit (e.g., VR). For example, the upward arrows on vias 731, 732, 733, and 734 indicate current flowing towards the fingers of electrode 705E1, and the downward arrows on vias 741, 742, 743, and 744 indicate current leaving the fingers of electrode 705E2. Current reaching the fingers of electrode 705E1 from conductive paths 751, 752, 753, and 754 can be displaced by displacement current (indicated by curved dashed arrows) to the adjacent fingers of electrode 705E2 and back to conductive paths 761, 762, 763, and 764.

[0063] The first and second electrodes can have the same number of fingers, for example, four in this example.

[0064] Figure 7B The yz plane at x=x0 is depicted according to various embodiments. Figure 7A A view showing the current flow in capacitor 705. For clarity, the fingers 711, 712, 713, and 714 of the first electrode 705E1 are depicted with a cross-shaded pattern, and the fingers 721, 722, 723, and 724 of the second electrode 705E2 are undiagrammed. Dashed arrows depict the displacement current that occurs when the capacitor is charging or discharging. Displacement current occurs between adjacent fingers. For example, displacement occurs from fingers 711 and 712 to finger 721. Displacement occurs from fingers 712 and 713 to finger 722. Displacement occurs from fingers 713 and 714 to finger 723. Displacement occurs from finger 714 to finger 724.

[0065] The fingers are spaced apart and separated by an insulator (e.g., example insulator 790 between fingers 714 and 724). The fingers may be spaced at equal intervals.

[0066] Figure 8 Example circuits 800, including a resonant VR 810 and a resonant frequency detector 820, are depicted according to various embodiments. A resonant VR is a power regulation device that uses the principle of resonance in an electrical circuit to regulate the output voltage. It typically involves components such as inductors, capacitors, and transformers arranged in a resonant circuit to provide a stable output voltage even in the presence of input voltage fluctuations or varying load conditions.

[0067] Resonant circuits (VRs) operate based on the phenomenon of resonance. At a specific frequency (resonant frequency), the inductive and capacitive reactances in the circuit cancel each other out, thereby minimizing impedance and allowing maximum power transfer. By maintaining the circuit's operation at or near its resonant frequency, the output voltage is stabilized. An example of a resonant VR is an inductor-inductor-capacitor (LLC) VR. Other types of resonant circuits include, for example, LC circuits, LLCC circuits, and so on.

[0068] The resonant VR 810 receives Vin and provides a voltage Vout through the example inductor L1. In the example implementation, arrow 805 indicates that L1 can be formed by a spiral metal path in a metal wiring layer. Vias 806 and 807 can be coupled to opposite ends of the inductor to couple the inductor to the rest of the circuitry on the substrate. An attacker can place an EM probe 830 close to the inductor to detect its EM emissions. The probe generates a recorded magnetic field vector (H) 831 and an unrecorded vertical magnetic field vector 832.

[0069] In the example implementation, frequency detector 820 is used to detect changes in the characteristics of the VR (e.g., current and / or voltage), which indicate changes in the VR's resonant frequency. This change can then indicate an EM probe of the VR. Appropriate actions can be performed, such as triggering an alarm and / or shutting down the VR.

[0070] The resonant VR provides efficiency improvements and protection against EM probing. An inductor at the output node (which can be implemented using the top metal layer) can be used for resonant operation within the VR. The VR operates at a resonant frequency Fres = 1 / (2π√LC), which is related to the topological equivalent RC of the VR. In the example implementation, a resonant frequency detector / calculator is added to the VR to monitor Fres. Due to magnetic coupling, an attacker placing an RF probe near the top metal will alter the inductor's value. As a result, Fres changes, and the detector / calculator can detect the frequency shift. An alert can be issued to trigger actions, such as stopping the encryption process or implementing countermeasures.

[0071] Figure 9 Depicting various embodiments Figure 8 An example implementation of the resonant VR 810 is an inductor-inductor-capacitor (LLC) resonant VR 900. VR includes an input node 901, an output node 902, and a ground node 903, and consists of four blocks. The first block 910 includes power switches S90 and S91, which are driven by a gate driver 911. The second block 920 is a resonant cavity including a series resonant inductor Lr, a parallel inductor Lm, and a series resonant capacitor Cs. The third block 930 is a transformer including inductors L9, L10, and L11 with an n:1 winding ratio. The fourth block 940 is a diode rectifier including diodes D1 and D2 and an output capacitor Cout. The load at the output node is described by a resistor Rload.

[0072] In operation, the MOSFET power switch converts the input DC voltage into a high-frequency square wave. This square wave then enters a resonant cavity, which eliminates harmonics and outputs a fundamental frequency sine wave. The sine wave is transmitted to the secondary side of the transformer via a high-frequency current transformer, which proportionally increases or decreases the voltage depending on the application. Finally, a diode rectifier converts the sine wave into a stable DC output.

[0073] Example VR is a half-bridge converter with a full-wave rectifier. Another example of a resonant VR is a full-bridge converter with a bridge rectifier.

[0074] Typically, VR can have two different resonant frequencies. The first fixed resonant frequency is fr = 1 / [2]. (Cr*Lr)]. The second resonant frequency (which varies with the load) is fm=1 / 2 [Cr*(Lr+Lm)] .

[0075] Control circuitry 960 can communicate with VR 900, for example, to monitor input and output voltages, control the gate driver, and monitor characteristics of VR (e.g., current and / or voltage) indicating changes in the resonant frequencies (fr and / or fm) of VR. The control circuitry may include memory 962 storing instructions that will be executed by processor 961 to provide the features described herein. The control circuitry may include measurement circuitry 963 for measuring characteristics of VR, such as current and / or voltage.

[0076] For example, three techniques for measuring current include: using a power resistor with small tolerances; using a current transformer; and directly using a current probe to measure the resonant cavity current.

[0077] A power resistor with small tolerances refers to a resistor designed to handle high power levels while also having a very precise resistance value. This method involves connecting the resistor (Rp) in series with other components in the resonant loop (e.g., Lr, Lm, and / or Cr in the resonant cavity). The resistor should have high resolution and good temperature performance. Typically, one terminal of the resonant loop is connected to ground, which reduces common-mode noise during measurement. This method provides a direct way to measure the resonant cavity current, but it has drawbacks, such as increased power losses, especially at high currents. Furthermore, it alters the resonant parameters and causes operation to deviate from the original design.

[0078] The use of current transformers will be discussed next.

[0079] Figure 10 The use of current transformers to measure, according to various embodiments, is described. Figure 9 Example circuit 1000 for current in VR 900. This circuit can be placed in Figure 9The circuit is located at the dashed line 950. It includes path 1001 with a capacitance Cp (representing the parasitic capacitance on the primary side) and a current Ipr. Cp is connected in series with current transformer 1010 and Cs (the parasitic capacitance on the secondary side). The current transformer provides the current isr through a leakage inductance lleak, and a sampling resistor R is located between nodes 902 and 903. Because the secondary leakage inductance is much larger than the primary leakage inductance, the leakage inductance is located on the secondary side. The parasitic capacitance between the primary and secondary turns is represented by Cps1 coupled between path 1001 and node 1002, and Cps2 coupled between path 1001 and node 1003.

[0080] In this method, the primary side is connected in series in the resonant loop. Compared to using a power resistor, this method has lower resistance and lower power loss. Furthermore, the magnetizing inductance of the current transformer is very small and negligible compared to Lr and Lm of the resonant loop. However, the current transformer method has drawbacks due to parasitic parameters.

[0081] The third technique for measuring current in the VR 900 is to measure the resonant cavity current directly using a galvanometer connected in series with other components in the resonant loop.

[0082] In one approach, the VR is tested during the manufacturing phase to determine one or more characteristics related to its resonant frequency. The determined characteristics can be stored in control circuitry 960 for subsequent use when the device reaches the end user. At this point, the control circuitry can detect one or more characteristics during VR operation and compare them to the stored characteristics. If a deviation indicating that the VR is being probed by an EM (Eye Monitoring System) is detected, action can be taken.

[0083] Figure 11 Examples of components that may exist in computing system 1150 for implementing the techniques described herein (e.g., operations, processes, methods, and methodologies) are shown.

[0084] Computing system 1150 may include any combination of the hardware or logic components mentioned herein. These components may be implemented as ICs, portions thereof, discrete electronics, or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or combinations thereof adapted within computing system 1150, or as components otherwise included within the chassis of a larger system. In an example implementation, voltage regulator 1100 represents one or more VRs discussed herein, and other circuitry may represent one or more load dies, including cryptographic circuitry powered by VRs. In one approach, all or part of computing system 1150 may be provided as a SoP, System in Package (SiP), or System on Chip (SoC).

[0085] A voltage regulator can provide a voltage Vout to one or more components of the computing system 1150. Memory circuitry 1154 can store instructions, and processor circuitry 1152 can execute these instructions to perform the functions described herein.

[0086] System 1150 includes processor circuitry in the form of one or more processors 1152. Processor circuitry 1152 includes, but is not limited to, circuitry such as (but not limited to): one or more processor cores and one or more of the following: cache memory, low drop-out (LDO) voltage regulator, interrupt controller, serial interface such as SPI, I2C, or general-purpose programmable serial interface circuitry, real-time clock (RTC), timer-counters including interval and watchdog timers, general-purpose I / O, memory card controller such as secure digital / multi-media card (SD / MMC) or similar interfaces, mobile industrial processor interface (MIPI) interface, and Joint Test Access Group (JTAG) test access port. In some implementations, processor circuitry 1152 may include one or more hardware accelerators (e.g., the same as or similar to acceleration circuitry 1164), which may be microprocessors, programmable processing devices (e.g., FPGAs, ASICs, etc.), etc. The one or more accelerators may include, for example, computer vision and / or deep learning accelerators. In some implementations, processor circuitry 1152 may include on-chip memory circuitry, which may include any suitable volatile and / or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0087] Processor circuitry 1152 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFICs), one or more microprocessors or controllers, multi-core processors, multi-threaded processors, ultra-low voltage processors, embedded processors, or any other known processing element, or any suitable combination thereof. Processor (or core) 1152 may be coupled to or may include a memory / storage device and may be configured to execute instructions stored in the memory / storage device to enable various applications or operating systems to run on platform 1150. Processor (or core) 1152 is configured to operate application software to provide specific services to users of platform 1150. In some embodiments, processor(s) 1152 may be one or more dedicated processors / controllers configured (or configurable to) operate according to various embodiments herein.

[0088] As an example, processor(s) 1152 may include Intel® Core™ architecture-based processors, such as i3, i5, i7, i9-based processors; Intel® microcontroller-based processors, such as Quark™, ​​Atom™, or other MCU-based processors; Pentium® processors, Xeon® processors, or other such processors available from Intel® Inc., Santa Clara, California. However, any number of other processors may also be used, such as one or more of the following: Zen® architecture from Advanced Micro Devices (AMD), such as one or more Ryzen® or EPYC® processors, Accelerated Processing Units (APUs), MxGPUs, one or more Epyc® processors, etc.; one or more A5-A12 and / or S1-S4 processors from Apple®, one or more Snapdragon™ or Centriq™ processors from Qualcomm® Technologies, one or more Open Multimedia Applications Platform (OMAP)™ processors from Texas Instruments, Inc.; MIPS-based designs from MIPS Technologies, such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings, such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; ThunderX2® from Cavium™, etc. In some implementations, the processor(s) 1152 may be part of a system-on-a-chip (SoC), a system-in-package (SiP), a multi-chip package (MCP), etc., in which the processor(s) 1152 and other components are formed as a single integrated circuit or a single package, such as an Edison™ or Galileo™ SoC board from Intel® Corporation. Other examples of the processor(s) 1152 are mentioned elsewhere in this disclosure.

[0089] System 1150 may include or be coupled to acceleration circuitry 1164, which may be implemented by one or more AI / ML accelerators, neural computation sticks, neuromorphic hardware, FPGAs, GPUs, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, application-specific integrated circuits (including programmable ASICs), PLDs (such as complex PLDs (CPLDs) or high complexity PLDs (HCPLDs)), and / or other specialized processors or circuits designed to perform one or more specialized tasks. These tasks may include AI / ML processing (e.g., including training, inference, and classification operations), visual data processing, network data processing, object detection, rule analysis, and so on. In an FPGA-based implementation, acceleration circuitry 1164 may include logic blocks or logic architectures and other interconnected resources that may be programmed (configured) to perform various functions, such as the processes, methods, functions, and so on of the various embodiments discussed herein. In such an implementation, the acceleration circuit 1164 may also include memory cells (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, antifuse, etc.)) for storing logic blocks, logic architectures, data, etc. in LUTs, etc.

[0090] In some implementations, processor circuitry 1152 and / or acceleration circuitry 1164 may include hardware elements specifically tailored for machine learning and / or artificial intelligence (AI) functions. In these implementations, processor circuitry 1152 and / or acceleration circuitry 1164 may be or may include an AI engine chip, which, once loaded with appropriately weighted and trained code, can run many different types of AI instruction sets. Additionally or alternatively, processor circuitry 1152 and / or acceleration circuitry 1164 may be or may include one or more AI accelerators, which may be one or more of the aforementioned hardware accelerators designed for hardware acceleration of AI applications. As an example, these processors or accelerators could be clusters of the following: artificial intelligence (AI) GPUs, tensor processing units (TPUs) developed by Google®, real AI processors (RAP™) provided by AlphaICs®, neural network processors (NNPs) provided by Intel®, vision processing units (VPUs) of Intel® Movidius™ Myriad™ X, GPUs based on NVIDIA® PX™, NM500 chips provided by General Vision®, hardware 3 provided by Tesla®, processors based on Epiphany™ provided by Adapteva®, and so on. In some embodiments, the processor circuitry 1152 and / or the acceleration circuitry 1164 and / or the hardware accelerator circuitry can be implemented as one or more AI acceleration coprocessors, such as the Hexagon 685 DSP from Qualcomm®, the PowerVR 2NX Neural Net Accelerator (NNA) from Imagination Technologies Limited®, the Neural Engine core within the Apple® A11 or A12 Bionic SoC, the Neural Processing Unit (NPU) within the HiSilicon Kirin from Huawei®, and so on. In some hardware-based implementations, individual subsystems of system 1150 can be operated by various AI acceleration coprocessors, AI GPUs, TPUs, or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), etc., configured with appropriate logic blocks, bitstreams, etc., to perform their respective functions.

[0091] System 1150 also includes system memory circuitry 1154. Any number of memory devices can be used to provide a fixed amount of system memory. As an example, memory 1154 may be or may include volatile memory, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other desired type of volatile memory device. Additionally or alternatively, memory 1154 may be or may include non-volatile memory, such as read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable (EEPROM), flash memory, non-volatile RAM, ferroelectric RAM, phase-change memory (PCM), and / or any other desired type of non-volatile memory device. Access to memory 1154 is controlled by a memory controller. Individual memory devices can have any number of different package types, such as single die package (SDP), dual die package (DDP), or quad die package (Q17P). Any number of other memory implementations can be used, such as different types of dual inline memory modules (DIMMs), including but not limited to microDIMMs or MiniDIMMs.

[0092] Storage circuitry 1158 provides persistent storage for information such as data, applications, operating systems, and so on. In one example, storage circuitry 1158 may be implemented via a solid-state disk drive (SSDD) and / or high-speed electrically erasable memory (commonly referred to as "flash memory"). Other devices that can be used with storage circuitry 1158 include flash memory cards, such as SD cards, microSD cards, XD picture cards, and so on, as well as USB flash drives. In one example, the memory device may be or may include memory devices using chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) incorporating memristor technology, phase change RAM (PRAM), resistive memory including metal oxide substrates, oxygen vacancy substrates, and conductive bridge random access memory (CB-RAM), or spin transfer torque (STT)-MRAM, devices based on spintronic magnetic junction memory, devices based on magnetic tunneling junction (MTJ), devices based on domain wall (DW) and spin orbit transfer (SOT), memory devices based on semiconductor thyristors, and hard disk drives. The memory 1154 and / or the storage circuitry 1158 may also contain three-dimensional (3D) crosspoint (XPOINT) memory from Intel® and Micron®.

[0093] Memory circuitry 1154 and / or storage circuitry 1158 are configured to store computational logic 1183 in the form of software, firmware, microcode, or hardware-level instructions to implement the techniques described herein. Computational logic 1183 may be used to store working copies and / or permanent copies of programming instructions, or data for creating programming instructions, for use by various components of operating system 1150 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), the operating system of system 1150, one or more applications, and / or for implementing the embodiments discussed herein. Computational logic 1183 may be stored or loaded into memory circuitry 1154 as instructions 1182 or data for creating instructions 1182, and then accessed by processor circuitry 1152 for execution to implement the functions described herein. Processor circuitry 1152 and / or acceleration circuitry 1164 access memory circuitry 1154 and / or storage circuitry 1158 via interconnect (IX) 1156. Instruction 1182 directs processor circuitry 1152 to execute specific sequences of actions or processes, for example, as described with reference to one or more flowcharts and block diagrams of operation and function previously depicted. Various elements may be implemented using assembly instructions or high-level languages ​​supported by processor circuitry 1152, which may be compiled into instruction 1188, or used to create data for execution by processor circuitry 1152. A permanent copy of the programming instructions may be placed into persistent storage devices of the storage circuitry 1158 at the factory or in the field via, for example, a distribution medium (not shown), a communication interface (e.g., from a distribution server (not shown)), over-the-air (OTA), or any combination thereof.

[0094] IX 1156 couples processor 1152 to communication circuitry 1166 for communication with other devices, such as remote servers (not shown), etc. Communication circuitry 1166 is a hardware element, or a collection of hardware elements, for communicating via one or more networks 1163 and / or with other devices. In one example, communication circuitry 1166 is or includes transceiver circuitry configured to implement wireless communication using any number of frequencies and protocols, such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 (and / or variations thereof), IEEE 802.23.4, Bluetooth® and / or Bluetooth® Low Energy (BLE), ZigBee®, LoRaWAN™ (Long Range Wide Area Network), cellular protocols such as 3GPP LTE and / or Fifth Generation (5G) / New Radio (NR), etc. Additionally or alternatively, the communication circuit 1166 is or includes one or more network interface controllers (NICs) to enable wired communication using, for example, the following: Ethernet connection, Controller Area Network (CAN), Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway+, or PROFINET, etc.

[0095] IX 1156 also couples processor 1152 to interface circuitry 1170, which connects system 1150 to one or more external devices 1172. External devices 1172 may include, for example, sensors, actuators, positioning circuitry (e.g., global navigation satellite system (GNSS) / global positioning system (GPS) circuitry), client devices, servers, network appliances (e.g., switches, hubs, routers, etc.), integrated photonics devices (e.g., integrated circuits (ICs) of optical neural networks (ONNs), and / or other similar devices.

[0096] In some optional examples, various input / output (I / O) devices may be present within or connected to system 1150, referred to as input circuitry 1186 and output circuitry 1184. Input circuitry 1186 and output circuitry 1184 include one or more user interfaces designed to enable a user to interact with platform 1150, and / or peripheral component interfaces designed to enable peripheral components to interact with platform 1150. Input circuitry 1186 may include any physical or virtual device for accepting input, particularly including one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, a keypad, a mouse, a touchpad, a touchscreen, a microphone, a scanner, a headset, etc. Output circuitry 1184 may be included to display or otherwise convey information, such as sensor readings, actuator(s) position, or other similar information. Data and / or graphics may be displayed on one or more user interface components of output circuitry 1184. Output circuitry 1184 may include any number and / or combination of audio or visual displays, particularly including one or more simple visual outputs / indicators (e.g., binary status indicators (e.g., light-emitting diodes, LEDs)) and multi-character visual outputs, or more complex outputs such as display devices or touchscreens (e.g., liquid crystal displays). Output circuitry 1184 may include speakers and / or other audio emitting devices, one or more printers, etc. Additionally or alternatively, one or more sensors may be used as output circuitry 1184 (e.g., image capture devices, motion capture devices, etc.) and one or more actuators may be used as output device circuitry 1184 (e.g., actuators to provide haptic feedback, etc.). Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, USB ports, audio jacks, power supply interfaces, etc. In some embodiments, within the context of this system, display or console hardware may be used to provide output and receive input from the edge computing system; manage components or services of the edge computing system; identify the status of edge computing components or services; or perform any other number of management or administrative functions or service use cases.

[0097] Components of System 1150 can communicate via IX 1156. IX 1156 can include any number of technologies, including ISA, Extended ISA, I2C, SPI, Point-to-Point Interface, Power Management Bus (PMBus), PCI, PCIe, PCIx, Intel® UPI, Intel® Accelerator Link, Intel® CXL, CAPI, OpenCAPI, Intel® QPI, UPI, Intel® OPA IX, RapidIO™ System IX, CCIX, Gen-Z Alliance IX, HyperTransport Interconnect, NVLink provided by NVIDIA®, Time-Trigger Protocol (TTP) System, FlexRay System, PROFIBUS, and / or any number of other IX technologies. IX 1156 can be a proprietary bus, for example, used in SoC-based systems.

[0098] The number, capabilities, and / or capacity of the elements of system 1150 may vary depending on whether computing system 1150 is used as a fixed computing device (e.g., a server computer, workstation, desktop computer, etc. in a data center) or a mobile computing device (e.g., a smartphone, tablet computing device, laptop computer, game console, IoT device, etc.). In various implementations, computing device system 1150 may include one or more components of a data center, desktop computers, workstations, laptop computers, smartphones, tablet devices, digital cameras, smart appliances, smart home hubs, network appliances, and / or any other data processing devices / systems.

[0099] The techniques described herein can be executed, in whole or in part, by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions for implementing any other processes discussed herein). Instructions associated with and executed to implement embodiments of the disclosed subject matter can be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of instructions.

[0100] Storage media can be tangible, non-transitory, machine-readable media, such as read-only memory (ROM), random access memory (RAM), flash memory devices, floppy disks and other removable disks, magnetic storage media, optical storage media (e.g., compact disk read-only memory (CD ROMs), digital versatile disks (DVDs)), and so on.

[0101] Storage media can be included in, for example, communication devices, computing devices, network devices, personal digital assistants, manufacturing tools, mobile communication devices, cellular phones, laptops, tablets, game consoles, set-top boxes, embedded systems, TVs, or personal desktop computers.

[0102] The following are some non-limiting examples of various embodiments.

[0103] Example 1 includes an apparatus comprising: one or more switches coupled between an input node and an output node, wherein a respective switch among the one or more switches includes a plurality of sub-switches connected in parallel; one or more capacitors coupled to the one or more switches; and control circuitry coupled to a control gate of the one or more switches including the plurality of sub-switches, wherein the control circuitry includes a random number generator.

[0104] Example 2 includes the apparatus of Example 1, wherein the control circuit is configured to control the number of active sub-switches in the respective switches based on a random number generator.

[0105] Example 3 includes the apparatus of Example 1 or 2, wherein the control circuit is configured to turn on different numbers of sub-switches in the corresponding switches during different charge and discharge cycles based on a random number generator.

[0106] Example 4 includes an apparatus of any one of Examples 1-3, wherein the apparatus includes a switched capacitor voltage regulator.

[0107] Example 5 includes an apparatus of any one of Examples 1-4, wherein control circuitry is coupled to the control gates of different sub-switches among a plurality of sub-switches.

[0108] Example 6 includes an apparatus of any one of Examples 1-5, wherein the random number generator is configured to indicate the number of sub-switches among a plurality of sub-switches to be turned on in different charge-discharge cycles.

[0109] Example 7 includes an apparatus of any one of Examples 1-6, wherein: a respective switch in one or more switches each includes a plurality of sub-switches connected in parallel; and a control circuit is configured to activate different numbers of sub-switches in different switches in the respective switches during the same charge-discharge cycle based on a random number generator.

[0110] Example 8 includes the means of any one of Examples 1-7, wherein the means is provided in at least one of an integrated circuit, a system-on-a-chip, a system-in-package, or a computing device.

[0111] Example 9 includes an apparatus comprising: a substrate including a circuit; one or more metal layers on the substrate; and a capacitor in a respective metal layer of the one or more metal layers, wherein the capacitor includes interdigitated first and second electrodes; and a via coupled between the first and second electrodes and the circuit.

[0112] Example 10 includes the apparatus of Example 9, wherein: a first electrode includes fingers coupled to a corresponding base; a second electrode includes fingers coupled to a corresponding base; a first set of corresponding through-hole rows are coupled to corresponding fingers of the first electrode; and a second set of corresponding through-hole rows are coupled to corresponding fingers of the second electrode.

[0113] Example 11 includes the apparatus of Example 10, wherein rows in the first set of corresponding rows are alternately arranged with rows in the second set of corresponding rows.

[0114] Example 12 includes the apparatus of Example 10 or 11, wherein a first set of corresponding through-hole rows are coupled together, and a second set of corresponding through-hole rows are coupled together.

[0115] Example 13 includes an apparatus of any of Examples 9-12, wherein adjacent fingers of the first and second electrodes are separated by an insulator.

[0116] Example 14 includes the apparatus of any of Examples 9-13, wherein the capacitor is a switched capacitor of a voltage regulator.

[0117] Example 15 includes a system comprising: a processor; a resonant voltage regulator (VR) coupled to the processor, the resonant VR including a portion of a substrate and an inductor in a metal layer above the substrate; and control circuitry coupled to the resonant voltage regulator to monitor the current of the resonant VR, wherein the control circuitry is configured to determine, based on the monitoring, whether the inductor is electromagnetically probed.

[0118] Example 16 includes the system of Example 15, wherein: the resonant VR includes an inductor-inductor-capacitor (LLC) resonant VR, the LLC resonant VR including a power switch, a resonant cavity, a transformer, and a diode rectifier, the resonant cavity including a series resonant inductor, a parallel inductor, and a series resonant capacitor; and the control circuit is configured to monitor the current in a resistor connected in series with at least one of the series resonant inductor, the parallel inductor, or the series resonant capacitor.

[0119] Example 17 includes the system of Example 15 or 16, wherein: the resonant VR includes a resonant cavity comprising a series resonant inductor, a parallel inductor, and a series resonant capacitor; and control circuitry is configured to monitor the current in the resonant cavity.

[0120] Example 18 includes a system of any one of Examples 15-17, wherein: the resonant VR includes an inductor-inductor-capacitor (LLC) resonant VR, the LLC resonant VR including a power switch, a resonant cavity, a transformer, and a diode rectifier, the resonant cavity including a series resonant inductor, a parallel inductor, and a series resonant capacitor; and control circuitry is configured to monitor the current in the resonant cavity.

[0121] Example 19 includes a system of any one of Examples 15-18, wherein the resonant VR includes a current transformer and the control circuit is configured to monitor the current in the current transformer.

[0122] Example 20 includes a system of any of Examples 15-19, wherein the control circuitry is configured to trigger an alarm when monitoring indicates that the inductor is being electromagnetically probed.

[0123] Example 21 includes a method comprising: receiving an input voltage at an input node of a switched capacitor voltage regulator; and controlling a plurality of switches to transfer charge from the input node to an output node through one or more capacitors, wherein at least one of the plurality of switches comprises a plurality of sub-switches connected in parallel, and the control comprises randomly activating a different number of the plurality of sub-switches during a continuous charge-discharge cycle of the voltage regulator.

[0124] Example 22 includes an apparatus including means for performing the method of Example 21.

[0125] Example 23 includes a machine-readable storage medium including machine-readable instructions that, when executed, cause a computer to implement the method of Example 21.

[0126] Example 24 includes a computer program that includes instructions that, when executed by a computer, cause the computer to perform the method of Example 21.

[0127] Example 25 includes a method comprising: receiving an input voltage at an input node of a resonant voltage regulator (VR); converting the input voltage to an output voltage at an output node; monitoring the current of the resonant VR; and determining, based on the monitoring, whether the resonant VR is subject to electromagnetic probe.

[0128] Example 26 includes the method of Example 25, wherein: the resonant VR includes a resonant cavity comprising a series resonant inductor, a parallel inductor, and a series resonant capacitor; and the monitored current is the current in the resonant cavity.

[0129] Example 27 includes the method of Example 25, wherein the resonant VR includes a current transformer, and the monitored current is the current in the current transformer.

[0130] Example 28 includes an apparatus comprising means for performing the method of any one of Examples 25-27.

[0131] Example 29 includes a machine-readable storage medium including machine-readable instructions that, when executed, cause a computer to perform a method according to any one of Examples 25-27.

[0132] Example 30 includes a computer program that includes instructions that, when executed by a computer, cause the computer to perform a method according to any one of Examples 25-27.

[0133] Various operations can be described sequentially as a plurality of discrete actions or operations in a manner most helpful for understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from that described in the embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0134] The terms “basically,” “near,” “roughly,” “approximately,” and “about” generally refer to within + / - 10% of the target value. Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third,” etc., to describe common objects merely indicates that different instances of similar objects are being referenced, and is not intended to imply that the objects described in this way must be in a given sequence in time, space, ranking, or any other way.

[0135] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0136] The description may use the phrases "in one embodiment" or "in an embodiment," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in connection with embodiments of this disclosure are synonymous.

[0137] As used herein, the term "circuit" can refer to, is part of, or includes: an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or grouped), combinational logic circuitry, and / or other suitable hardware components that provide the described functionality. As used herein, "computer-implemented method" can refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet device, a laptop computer, a set-top box, a game console, and the like.

[0138] This document uses the terms “coupling,” “communicationally coupled,” and their derivatives. The term “coupling” can mean two or more elements in direct physical or electrical contact with each other, can mean two or more elements in indirect contact with each other but still cooperating or interacting with each other, and / or can mean one or more other elements coupled or connected between the elements allegedly coupled to each other. The term “direct coupling” can mean two or more elements in direct contact with each other. The term “communicationally coupled” can mean two or more elements in contact with each other through communication means, including through wires or other interconnections, through wireless communication channels or links, etc.

[0139] The use of terms such as "an embodiment," "one embodiment," "some embodiments," or "other embodiments" in the specification means that a specific feature, structure, or characteristic described in connection with these embodiments is included in at least some embodiments, but not necessarily in all embodiments. Various appearances of "an embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," it is not mandatory to include that particular component, feature, structure, or characteristic. If the specification or claims refer to the element "a," it does not mean that there is only one such element. If the specification or claims refer to the element "an additional," it does not exclude the possibility of having more than one such additional element.

[0140] Furthermore, specific features, structures, functions, or characteristics can be combined in any suitable manner in one or more embodiments. For example, a first embodiment can be combined with a second embodiment wherever specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0141] While this disclosure has been described in conjunction with specific embodiments thereof, those skilled in the art will recognize from the foregoing description many alternatives, modifications, and variations of such embodiments. The embodiments of this disclosure are intended to encompass all such alternatives, modifications, and variations falling within the broad scope of the appended claims.

[0142] Furthermore, for the sake of simplicity in illustration and discussion, and to avoid obscuring this disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the accompanying drawings. Additionally, arrangements may be shown in block diagram form to avoid obscuring this disclosure, also taking into account the fact that the specific details of the implementation of such block diagram arrangements are highly dependent on the platform in which this disclosure is to be implemented (i.e., such specific details should be entirely within the view of someone skilled in the art). In the context of setting forth specific details (e.g., circuits) to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that this disclosure can be implemented without these specific details, or using variations thereof. Therefore, this specification should be considered illustrative rather than restrictive.

[0143] An abstract is provided to allow the reader to determine the nature and spirit of this technical disclosure. The abstract is submitted with the understanding that it is not intended to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim serving as an independent, separate embodiment.

Claims

1. An apparatus comprising: One or more switches are coupled between an input node and an output node, wherein a respective switch in the one or more switches comprises a plurality of sub-switches connected in parallel; One or more capacitors, coupled to the one or more switches; and A control circuit coupled to the control gate of one or more switches including the plurality of sub-switches, wherein the control circuit includes a random number generator.

2. The apparatus of claim 1, wherein, The control circuit is configured to control the number of active sub-switches in the corresponding switches based on the random number generator.

3. The apparatus of claim 1 or 2, wherein, The control circuit is configured to activate different numbers of sub-switches in the corresponding switches during different charge / discharge cycles, based on the random number generator.

4. The apparatus of claim 1 or 2, wherein, The device includes a switched capacitor voltage regulator.

5. The apparatus of claim 1 or 2, wherein, The control circuit is coupled to the control gate of different sub-switches among the plurality of sub-switches.

6. The apparatus of claim 1 or 2, wherein, The random number generator is configured to indicate the number of sub-switches among the plurality of sub-switches to be turned on in different charge-discharge cycles.

7. The apparatus according to claim 1 or 2, wherein: Each of the one or more switches comprises a plurality of sub-switches connected in parallel; and The control circuit is configured to activate different numbers of sub-switches among different switches in the corresponding switches during the same charge / discharge cycle based on the random number generator.

8. The apparatus of claim 1 or 2, wherein, The device is provided in at least one of an integrated circuit, a system-on-a-chip, a system-in-package, or a computing device.

9. An apparatus comprising: Substrate, including circuitry; One or more metal layers are disposed on the substrate; as well as A capacitor, in a respective metal layer of one or more metal layers, wherein the capacitor includes an interdigitated first electrode and a second electrode; A through-hole is coupled between the first and second electrodes and the circuit.

10. The apparatus according to claim 9, wherein: The first electrode includes a finger coupled to the corresponding base; The second electrode includes a finger coupled to the corresponding base; The first set of corresponding through-hole rows are coupled to the corresponding fingers of the first electrode; and The second set of corresponding through-hole rows are coupled to the corresponding fingers of the second electrode.

11. The apparatus of claim 10, wherein, The rows in the first group of corresponding rows are arranged alternately with the rows in the second group of corresponding rows.

12. The apparatus according to claim 10 or 11, wherein, The first group of corresponding through-hole rows are coupled together, and the second group of corresponding through-hole rows are coupled together.

13. The apparatus according to claim 9 or 10, wherein, The adjacent fingers of the first electrode and the second electrode are separated by an insulator.

14. The apparatus according to claim 9 or 10, wherein, The capacitor in question is a switched capacitor of a voltage regulator.

15. An apparatus comprising: A resonant voltage regulator (VR) includes a portion of a substrate and an inductor in a metal layer above the substrate; as well as A control circuit, coupled to the resonant voltage regulator, monitors the current of the resonant VR, wherein the control circuit is configured to determine, based on the monitoring, whether the inductor is subjected to electromagnetic detection.

16. The apparatus according to claim 15, wherein: The resonant VR includes an inductor-inductor-capacitor (LLC) resonant VR, which includes a power switch, a resonant cavity, a transformer, and a diode rectifier. The resonant cavity includes a series resonant inductor, a parallel inductor, and a series resonant capacitor. The control circuit is configured to monitor the current in a resistor connected in series with at least one of the series resonant inductor, the parallel inductor, or the series resonant capacitor.

17. The apparatus according to claim 15 or 16, wherein: The resonant VR includes a resonant cavity, which comprises a series resonant inductor, a parallel inductor, and a series resonant capacitor; and The control circuit is configured to monitor the current in the resonant cavity.

18. The apparatus according to claim 15 or 16, wherein: The resonant VR includes an inductor-inductor-capacitor (LLC) resonant VR, which includes a power switch, a resonant cavity, a transformer, and a diode rectifier. The resonant cavity includes a series resonant inductor, a parallel inductor, and a series resonant capacitor. The control circuit is configured to monitor the current in the resonant cavity.

19. The apparatus according to claim 15 or 16, wherein, The resonant VR includes a current transformer, and the control circuit is configured to monitor the current in the current transformer.

20. The apparatus according to claim 15 or 16, wherein, The control circuit is configured to trigger an alarm if the monitoring indicates that the inductor is being electromagnetically detected.

21. A method comprising: The input voltage is received at the input node of the switched capacitor voltage regulator; as well as Controlling multiple switches to transfer charge from the input node to the output node via one or more capacitors, wherein at least one of the multiple switches comprises a plurality of sub-switches connected in parallel, and the control comprises randomly activating a different number of the plurality of sub-switches during a continuous charge-discharge cycle of the voltage regulator.

22. The method according to claim 21, wherein, The random activation is based on a random number generator.

23. An apparatus comprising means for performing the method according to claim 21 or 22.

24. A machine-readable storage medium comprising machine-readable instructions that, when executed, cause a computer to perform the method according to claim 21 or 22.

25. A computer program product comprising instructions that, when executed by a computer, cause the computer to perform the method according to claim 21 or 22.

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