A direct current component adaptive suppression system for optical storage direct flexible bidirectional converter

Abstract

This invention provides an adaptive DC component suppression system and method for photovoltaic-storage DC-flexible bidirectional converters. The system combines a two-stage negative feedback conditioning circuit in hardware with a dual-path adaptive compensation logic in software to accurately suppress the DC component during bidirectional power transfer in the photovoltaic-storage DC-flexible system. The hardware architecture employs a first-stage voltage parallel negative feedback integrator circuit and a second-stage voltage series negative feedback proportional amplifier circuit, along with a voltage clamping circuit, to provide a stable and safe sampling voltage for the processor. In software, the processor synchronously acquires the raw AC current and the rectified detection current at the output of the bidirectional converter, dynamically adjusts the compensation weights based on the system's steady-state or transient operating conditions using an intelligent weighted fusion algorithm, and achieves closed-loop suppression of DC offset through a PR controller and SVPWM modulation. This invention effectively solves the problems of sensor temperature drift and DC injection caused by complex DC microgrid switching conditions, significantly improving the reliability of system operation.

Description

Technical Field

[0001] This invention relates to the field of optical-storage DC-flexible bidirectional converter technology, specifically to a DC component suppression system and method based on a two-stage conditioning circuit and a dual-path compensation algorithm. Background Technology

[0002] In photovoltaic-storage-DC-flexible (PEDF) systems, bidirectional converters or DC microgrids, especially under complex operating conditions such as energy storage system charge / discharge switching and electric vehicle integration, exhibit highly transient dynamic fluctuations in the DC component. Existing solutions often struggle to achieve high-precision suppression due to unstable sampling signals or sluggish compensation algorithm responses, and lack overvoltage protection for processor pins, making it difficult to meet the stringent requirements of flexible distribution networks for safe operation and power quality. Summary of the Invention

[0003] The purpose of this invention is to design a bidirectional converter with a two-stage conditioning circuit. By combining the two-stage amplification of "integral + proportional" on the hardware side with the dual-path compensation logic of "raw AC + rectified DC" on the software side, a stable voltage signal is output and the DC component is accurately suppressed.

[0004] To achieve the above objectives, this invention employs a technical solution of hardware and software collaboration and dual-path cross-validation: 1. Hardware level: Design a two-stage conditioning circuit. The first stage uses a voltage parallel negative feedback integrator circuit to achieve IV conversion and suppress high-frequency noise; the second stage uses a voltage series negative feedback non-inverting amplifier circuit to provide accurate linear gain.

[0005] 2. Software level: Synchronously acquire the raw inverter AC current at the output of the bidirectional converter. i inv and the DC bias current after rectification and filtering i DCI The processor uses an intelligent weighted fusion algorithm (such as dynamically adjusting weight allocation based on the steady-state or transient state of the system's charging and discharging conditions) to generate a comprehensive DC compensation amount. Id comp Inject reference instructions.

[0006] Beneficial effects: This invention enhances signal stability through a hardware conditioning architecture, and at the same time, it improves suppression accuracy and robustness without significantly increasing hardware costs by using a dual-path compensation algorithm that combines fast and slow methods, effectively solving the problem of DC injection caused by complex DC operating condition switching. Attached Figure Description

[0007] Figure 1 This is the overall control block diagram of the DC component adaptive suppression system for the optical-storage DC-flexible bidirectional converter in this embodiment of the invention; Figure 2This is a schematic diagram of the dual-path sampling circuit in an embodiment of the present invention; Figure 3 This is a schematic diagram of the first conditioning circuit (first amplifier circuit) of the present invention; Figure 4 This is a schematic diagram of the second conditioning circuit (second amplifier circuit) of the present invention; Figure 5 The schematic diagram of the hardware topology of the bidirectional converter for the photovoltaic-storage DC-flexible system provided in the embodiment of the present invention shows the complete bidirectional energy conversion path from the DC microgrid power branch to the AC grid. Figure 6 The voltage outer loop control dynamic model diagram provided in the embodiment of the present invention illustrates the compensation relationship of the small-signal model in the feedforward control logic. Detailed Implementation

[0008] 1. Explanation of basic system principles and terminology: Clark and Park transforms are used to decouple coupled variables in a three-phase system of an optical-storage DC-flexible bidirectional converter into independently controllable axis components. The SVPWM modulation algorithm generates pulse width modulation waves with specific switching modes to control the duty cycle of the bidirectional converter's IGBTs, making the output current approach an ideal sine wave.

[0009] A specific embodiment of the present invention provides a DC component suppression process based on dual-path sampling.

[0010] It should be noted that, Figure 1 In the control block diagram shown, the inverter bridge within the dashed box only schematically illustrates a single-phase bridge arm structure; the three-phase full-bridge topology is not fully shown in the diagram. This invention specifically targets a three-phase photovoltaic-storage DC-flexible bidirectional converter, and the system employs three-phase current... i abc Coordinate decoupling is achieved through Clark and Park transformations, which are specifically designed for three-phase systems. For single-phase applications, the Clark transformation can be omitted, and single-phase current can be directly acquired for subsequent processing. The scope of this invention covers both single-phase and three-phase implementations.

[0011] Please see Figure 1 The system collects the grid-connected current at the output of the LCL filter. i 2. Simultaneously acquire the first inverter AC current at the output terminal of the switching transistor (IGBT). i inv and the second DC bias current obtained after rectification and filtering. i DCI In this embodiment, the processor first retrieves data from... i inv and i DCI Extract the DC compensation component Id 1 and Id 2 Subsequently, the system calculates the average current after compensation for both paths and compares this average current with the grid-connected current. i The difference between 2 and 3 is fed into the PR controller for adjustment after Clark and Park transformations. Finally, the SVPWM modulation algorithm generates the switching control signal, achieving precise control of the IGBT duty cycle and thus suppressing the DC component in the grid-connected current. To complete closed-loop control, the system also collects grid voltage data from the grid side. U g The inverter voltage U is sampled from the IGBT output terminal. in And collect the DC voltage U from the output of the DC boost circuit. dc Reference DC voltage with U dc The difference is input to the outer voltage loop regulator (such as a PI controller) for processing. Grid-connected current i 2. After tracking the grid phase via a phase-locked loop (PLL), the components in the rotating coordinate system are obtained through Clark and Park transformations. It is used for inner loop current tracking.

[0012] It should be noted that the above scheme for calculating the average current i is mathematically equivalent to using the first compensation amount Id 1 With the second compensation amount Id 2 Take the arithmetic mean as the comprehensive DC compensation amount, and take it from the reference current. i ∗ This is subtracted all at once. This is a specific implementation of the linear combination operation (i.e., the mean operation) in the fusion operation described in this invention.

[0013] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0014] 2. Hardware Sampling and Signal Conditioning: Please refer to [link / reference]. Figure 3 and Figure 4In the complex electromagnetic environment of a DC microgrid, the current signal sampled by the bus circuit first enters the first conditioning circuit 21. The current signal input terminal of the first amplifier circuit 211 has two parallel resistors, R1 and R2, forming a differential input structure. Specifically, R1 and R2 receive positive and negative differential signals from the two ends of the current sampling element (such as a Hall sensor or sampling resistor), respectively, and are acquired differentially by the inverting input terminal of the first operational amplifier 21111, thereby effectively suppressing common-mode interference. In the complex electromagnetic environment of the optical-storage DC-flexible system, the DC bus, the high-frequency switching action of the switching transistors, and the flexible load all introduce strong common-mode noise into the sampling line; the differential input structure can reduce the impact of common-mode noise on sampling accuracy by more than 40dB, significantly improving the signal-to-noise ratio, thereby ensuring the accuracy of subsequent DC component detection. The first amplifier circuit 211 uses the first operational amplifier 21111 to form an integral operation circuit (voltage parallel negative feedback), converting the current signal into a preliminary voltage signal and filtering out high-frequency harmonic noise generated by the flexible load. Specifically, in the first amplifier circuit 211, the feedback network consists of a resistor R3 and a capacitor C1 connected in parallel, with a low-pass cutoff angular frequency of ω_c1 = 1 / (R3·C1). To ensure effective filtering of high-frequency ripple generated by the switching frequency (typically 10kHz to 20kHz) while retaining the DC component and low-order harmonics (50Hz and its lower harmonics), the typical design values ​​of R3 and C1 should ensure that the cutoff frequency f_c1 = ω_c1 / (2π) satisfies: 50Hz ≪ f_c1 ≪ f_sw, meaning the cutoff frequency is much higher than the power frequency (50Hz) and much lower than the switching frequency (f_sw). In a typical embodiment, R3 = 100kΩ and C1 = 10nF, resulting in f_c1 ≈ 159Hz, which meets the above design requirements. Those skilled in the art can adjust R3 and C1 proportionally according to the actual switching frequency and accuracy requirements.

[0015] Then it enters the second amplifier circuit 221 ( Figure 4 The second operational amplifier 22121 is used for in-phase proportional amplification (voltage series negative feedback), with a proportional gain G = 1 + R6 / R7. In the specific application scenario of the DC component suppression system of this invention, the value of gain G needs to take into account the following constraints: First, if the gain is too small (G < 1.5), the amplitude of the DC component signal will be too low, exceeding the effective quantization range of the subsequent ADC; second, if the gain is too large (G > 5), the operational amplifier will saturate when there is DC bias, compressing the dynamic range. Therefore, in a typical embodiment, R6 = 400kΩ and R7 = 200kΩ are selected, corresponding to G = 3, satisfying the above constraints, so that the amplitude of the conditioned signal is optimally matched with the input range of the processor ADC (typical value 0~3.3V), realizing high-precision DC component acquisition. The input terminal of the second amplifier circuit 221 is also provided with multiple bypass decoupling capacitors ( Figure 4The capacitors (labeled as capacitor banks) are connected in parallel to ground to filter out high-frequency interference transmitted between stages, ensuring the stability of the input signal of the second operational amplifier 22121. The decoupling capacitors are engineering implementation details of the signal conditioning link; their number and capacitance values ​​are determined by specific EMC design requirements and do not affect the establishment of the core gain feature G=1+R6 / R7 of this invention. Each stage is equipped with a voltage follower and clamping circuit to ensure that the voltage signal input to the processor is stable and limited.

[0016] 3. Dual-path adaptive DC detection and compensation: Please refer to [link / reference needed]. Figure 1 The processor synchronously acquires data at the output of the bidirectional converter. i inv and i DCI .

[0017] Path 1: To i inv The DC component is extracted by digital low-pass filtering and then used to generate the first compensation value via a PI regulator. Id 1 This approach focuses on steady-state, high-precision suppression.

[0018] Path 2: i DCI The signal, after being processed by the rectifier branch, directly reflects the DC offset, and a second compensation value is generated by the PI regulator. Id 2 This approach focuses on rapid transient response.

[0019] 4. Intelligent Fusion: Processor to Id 1 and Id 2 Perform fusion operations to generate Id comp The fusion operation includes, but is not limited to, linear combination operations. In a preferred embodiment, a weighted fusion operation is used, according to the formula... Id comp = k 1 ⋅Id 1 +k 2 ⋅Id 2 (Equation I) Calculate the comprehensive compensation amount. In another embodiment, the fusion calculation can be performed using the mean value calculation, i.e. Id comp =( Id 1 + Id 2 ) / 2. This is equivalent to the scheme described in the aforementioned specific implementation where each current is compensated separately and then averaged. The total DC compensation amount... Id comp The current control loop is injected in a feedforward manner, through Figure 1 The subtraction points shown are used to correct the reference command in real time, thereby offsetting the DC bias in the grid-connected current. (Continue referencing...) Figure 1 Compensation module 1 and compensation module 2 essentially constitute a weighted fusion unit within the processor. This unit adjusts the weights in real time according to the system operating conditions (steady-state / transient), and synthesizes the two compensation values. Id comp Then the reference instructions are revised. For example... Figure 1 As shown, the DC suppression program inside the processor does not simply output two independent compensation values, but rather dynamically allocates weights through a weighted fusion unit. The two compensation branches in the diagram correspond to... Id comp The two weighted terms in the formula enable distributed compensation in the control loop.

[0020] Control structure description: such as Figure 1 As shown in the figure, compensation module 1 and compensation module 2 constitute a weighted fusion unit inside the processor, with two compensation values. k 1 ⋅Id 1 and k 2 ⋅Id 2 First, the weighted fusion calculation is performed inside the processor to generate the comprehensive DC compensation amount. Id comp = k 1 ⋅Id 1 + k 2 ⋅Id 2 Then, the reference command subtraction node of the current control loop is uniformly injected in the feedforward manner to correct the reference current i* in one go. Figure 1 The diagrammatic representation of the two subtraction nodes is schematic; their essential meaning is: comprehensive compensation amount. Id comp The feedforward superposition is completed during the reference current generation stage (i.e., before entering the inner current loop PR controller), and there is no structure within the control loop where multiple independent integrators process the two compensation values ​​separately. By adopting a unified feedforward injection method, the single integral path characteristic of the control loop can be ensured, avoiding the steady-state error coupling problem introduced by multiple integrators in parallel, thereby ensuring high-precision steady-state suppression of the DC component.

[0021] 5. Voltage feedforward control and small-signal stability design:

[0022] This invention, through the introduction of a voltage feedforward control strategy, further optimizes the voltage outer loop to improve the system's robustness during grid connection. For example... Figure 6 As shown, its detailed control logic is as follows: (1) Small-signal model establishment: The processor is designed for the peak value of the injected grid current and the voltage of the power supply branch in the αβ coordinate system. V PV The relationship between the DC bus voltages was used to establish a small-signal model as shown in Equation II:

[0023] V grid_OP The operating point of the power grid voltage. I PV For photovoltaic output current, ω 0 =I PV / (V PV ⋅C PV ) This is the critical compensation pole of the system.

[0024] (2) Dynamic compensation principle: In the voltage loop, the processor simulates the current control loop as a first-order low-pass transfer function. To achieve stable operation, the voltage loop's crossover frequency... ωCv Designed to be below the current loop crossover frequency ωCi However, it must be higher than the maximum value of the extreme point. ω 0_max (Right now I PV / ( V PV_min ⋅C PV )).

[0025] It should be further noted that the transfer function shown in Equation II contains a right-half-plane zero (s=ω0), indicating that the transfer function has a non-minimum phase characteristic. The right-half-plane zero introduces additional phase lag near the crossover frequency, threatening the phase margin of the outer voltage loop. To ensure stable system operation, the following design constraints must be met: First, the crossover frequency design constraint: the voltage outer loop crossover frequency ωCv must satisfy... ωCv ≤ / 5, meaning the crossover frequency does not exceed 1 / 5 of the frequency of the zero point in the right half-plane, to ensure that the phase lag introduced by the zero point in the right half-plane at the crossover frequency does not exceed about 11°, so that the system phase margin is maintained at a safety margin of more than 45°.

[0026] Secondly, DC bus capacitor design constraints: from ω0=I PV / (VPV ·C PV It can be seen that increasing C PV Can reduce This shifts the zero point in the right half-plane to lower frequencies, thus creating a crossover frequency. ωCv The setting allows for a larger margin. In a typical embodiment, take... That is, satisfying ≥5 ωCv The minimum capacitance. Taking typical parameters as an example: if I PV_max =10A, V PV_min =200V, ωCv =2π×20rad / s, then C PV ≥10 / (200×2π×100)≈79.6μF, C is taken in engineering. PV ≥100μF.

[0027] Thirdly, when C PV When the above minimum constraint is met, the DC bus can fully utilize its energy buffering function, ensuring that the impact of grid voltage fluctuations on the injected current satisfies i. L2_αβ / v grid_αβ ≪1, thereby ensuring the stability margin of the outer voltage loop while effectively suppressing the DC component of the grid-connected current.

[0028] (3) Feedforward compensation implementation: when the frequency is close to ωCv At that time, the PI controller passes through the pole in the open-loop state. ω 0 Compensate for this first-order low-pass transfer function. If the DC bus capacitance C... PV Sufficiently high, the DC bus can act as an energy buffer between the photovoltaic power source and the inverter, thus minimizing the impact of grid voltage fluctuations on the injected current (satisfying i). L2_αβ / v grid_αβ ≪1).

[0029] The processor calculates the reference voltage based on the output power of the MPPT module. and compared with actual measurements V PV Comparison. The difference is determined via... Figure 6 After processing by the voltage control loop Gv(s) shown, a reference value for the peak grid-connected current is obtained. This serves as the input command for the subsequent inner current loop.

[0030] During this instruction generation process, the processor utilizes the small-signal model established by Equation II to cross the frequency... ωCv Near the pole ω 0 The phase lag caused by the first-order low-pass transfer function of the compensation current loop. When the DC bus capacitance C... PVWhen set at a preset high level, the DC bus can act as an energy buffer between the power supply branch and the converter, ensuring that the injected current is minimally affected by grid voltage fluctuations (satisfying i). L2_αβ / v grid_αβ ≪1), thereby ensuring the robustness of the outer voltage loop and the secondary stability of suppressing DC components while generating instructions.

[0031] Furthermore, in a practical photovoltaic-storage DC-flexible system, the photovoltaic side voltage V PV Due to the dynamic tracking effect of the MPPT algorithm, real-time fluctuations occur near the maximum power point (typical fluctuation range is ±5% to ±15% of the rated operating voltage). PV The fluctuations will lead to the compensation pole ω0=I PV / (V PV ·C PV This results in corresponding changes, thus affecting the accuracy of feedforward compensation. To ensure the robustness of the system during the MPPT dynamic process, the present invention adopts the following measures: (a) Real-time pole frequency update: In each control cycle, the processor updates the pole frequency based on the real-time acquired V. PV and I PV The current ω0 is dynamically calculated, and the pole parameters of the feedforward compensation transfer function are updated so that the compensation always matches the current operating point. (b) Worst-case stability guarantee: at V PV Take the lowest operating voltage V PV_min (Corresponding to ω0 taking the maximum value ω0_max=I) PV_max / (V PV_min ·C PV When the crossover frequency constraint ωCv≤ω0_max / 5 in clause (2) above is still satisfied, the system can remain stable at any MPPT operating point. This constraint has been passed through the DC bus capacitor C. PV The selection of (see section (2)) is guaranteed during the system design phase, therefore the feedforward compensation scheme proposed in this invention ensures the performance of photovoltaic V. PV The dynamic changes are inherently robust and do not require additional gain scheduling mechanisms.

[0032] This invention further achieves dynamic optimization of the compensation logic through a built-in intelligent weighting unit in the processor. This unit adjusts the first DC compensation value in real time according to the system operating conditions (such as grid-connected steady state or load switching transient). Id 1 With the second DC compensation value Id 2 The weighting ratio is determined by the AC path. Under steady-state conditions, the focus is on utilizing the high-precision filtering characteristics of the AC path; under transient conditions, the focus is on utilizing the extremely fast response characteristics of the rectifier path, thereby maintaining an extremely low DC injection level under different power grid conditions.

[0033] 6. Control Execution and Closed-Loop: The calculated comprehensive DC compensation amount Id comp ,according to Figure 1 The logic feedforward injection current control loop is shown. According to the aforementioned series equivalent description, this process, in its algorithmic implementation, manifests as the flexible power reference command i, which characterizes bidirectional energy flow, being initiated from... ∗ Intermediate deduction k 1 ⋅Id 1 and k 2 ⋅Id 2 .

[0034] Example: For weighting coefficient adjustment under different power grid operating conditions, please refer to [link / reference]. Figure 1 In this embodiment, the processor outputs current through the coupling point. i The rate of change of 2 is used to determine the system operating condition, and the weighting coefficients are dynamically adjusted accordingly. k 1 and k 2 (satisfy k 1 + k 2 =1), calculate the comprehensive compensation amount. Id comp = k 1 ⋅Id 1 +k 2 ⋅Id 2 .

[0035] This embodiment uses weighted fusion operation as an example for explanation. When other fusion operations (such as mean operation) are used, the adjustment logic can be changed accordingly.

[0036] 1. Steady-state operating conditions (such as stable discharge of energy storage): When the grid-connected current... i When the rate of change of voltage 2 is lower than a preset threshold (e.g., 1% / ms) and the DC bus voltage fluctuation is stable, the system is determined to be in a steady state. At this time, the processor sets the weighting coefficients. k 1 =0.8, k 2 =0.2. This configuration focuses on utilizing the first inverter AC current. i inv The path extracts high-precision DC component values ​​through deep digital filtering. Id 1 It is designed to precisely offset the zero-point residual caused by temperature drift of the Hall sensor, ensuring the sinusoidal nature of the grid-connected current.

[0037] 2. Transient operating conditions (such as flexible load shedding or energy storage charging / discharging switching): When grid-connected current is detected... i When the rate of change of 2 exceeds 10% / ms (e.g., due to sudden load changes or instantaneous power grid fluctuations), the system automatically switches to transient protection logic. At this time, the processor adjusts the weighting coefficient to... k 1 =0.3, k 2 =0.7. Due to the second DC current i DCI The path is extracted via a hardware rectified branch, eliminating the need for complex digital low-pass filtering algorithms and exhibiting extremely high dynamic response speed (compensation can typically be completed within 5ms). By increasing... k 2 With the right weighting, the system can quickly suppress DC injection during transient processes and prevent transformer magnetic saturation.

[0038] 3. Compensation Execution: The final generated comprehensive DC compensation amount Id comp according to Figure 1 The logic feedforward is shown in the reference current command. According to the aforementioned series equivalence description, this process, in its algorithmic implementation, manifests as feeding the flexible power reference command i, which characterizes bidirectional energy flow, forward. ∗ By cascading down k1⋅Id1 and k2⋅Id2, real-time closed-loop suppression of the DC component is achieved.

[0039] Although the present invention has been described in detail above with general descriptions, specific embodiments, and experiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A DC component adaptive suppression system for optical-storage DC-flexible bidirectional converters, characterized in that, It includes a bus circuit, a two-stage negative feedback conditioning circuit, and a processor that executes a DC suppression program; the conditioning circuit is connected between the bus sampling point and the processor, and is used to perform two-stage amplification and voltage clamping processing on the original current sampling signal; the processor is configured to extract the first DC compensation value based on the conditioned high-precision signal using a dual-path detection algorithm. Id 1 Second DC compensation value Id 2 And generate a comprehensive DC compensation amount based on the fusion calculation. Id comp Inject current into the inner loop reference command to control the duty cycle of the bidirectional converter switching transistors.

2. The system as described in claim 1, characterized in that, The two-stage negative feedback conditioning circuit includes: First-stage conditioning circuit: A voltage parallel negative feedback integral operation circuit is used to convert the input current signal into a preliminary voltage signal and suppress high-frequency noise using the first operational amplifier (21111). The second-stage conditioning circuit is connected in series after the first stage. It uses a voltage-series negative feedback in-phase amplifier circuit and utilizes the second operational amplifier (22121) for linear amplification.

3. The system as described in claim 2, characterized in that, The proportional gain G of the second-stage conditioning circuit satisfies: G = 1 + R6 / R7; wherein each stage of the conditioning circuit has a voltage follower and a clamping protection circuit at its output to limit the voltage range input to the processor.

4. The system as described in claim 1, characterized in that, The processor acquires two signals: the first path directly acquires the first inverter AC current output by the converter. i inv The second path obtains the second DC bias current via the rectifier and filter branch. i DCI ; The method for the processor to extract DC compensation values ​​includes: right i inv Low-pass filtering is performed to extract the DC component, which is then generated by the first proportional-integral (PI) regulator. Id 1 ; After conditioning i DCI The signal is directly processed by the second PI regulator to generate Id 2 .

5. The system as described in claim 1, characterized in that, The fusion operation is performed on the first DC compensation value. Id 1 and the second DC compensation value Id 2 Perform linear combination operations.

6. The system as described in claim 5, characterized in that, The linear combination operation is a weighted fusion operation, and the comprehensive DC compensation amount Id comp The calculation formula is: Id comp = k 1 ⋅Id 1 +k 2 ⋅Id 2 ； in k 1 and k 2 The weighting coefficients and k 1 + k 2 =1; The processor detects the grid-connected current in real time. i 2 rate of change d i 2 / d t Compare it with the preset rate of change threshold Δ I _th comparison: when d i 2 / d t <Δ I When _th, the system is determined to be in steady-state condition, and the following settings are made: k 1 > k 2 When d i 2 / d t ≥Δ I When _th, the system is determined to be in a transient condition, and the settings are... k 2 > k 1 The processor dynamically switches the weights of the two compensation values ​​in real time based on the above judgment results, and the rate of change threshold Δ I _th is pre-calibrated based on the system's rated current and response time requirements.

7. The system as described in claim 5, characterized in that, The linear combination operation is a mean operation, and the comprehensive DC compensation amount Id comp for Id 1 and Id 2 The arithmetic mean.

8. The system as described in claim 1, characterized in that, The processor also executes voltage feedforward control logic by acquiring the DC distribution bus voltage or the power supply branch voltage (or DC bus voltage). V PV Establish a small-signal model, with the frequency close to the crossover frequency. ωCv When, passing through the pole ω 0 =I PV / (V PV ⋅C PV ) Compensation transfer function.

9. The system as described in claim 1, characterized in that, The system includes a phase-locked loop (PLL) for tracking the phase of the AC voltage at the grid or microgrid point. θ The processor converts and injects the grid-connected current through Clark. Id comp The reference command is compared with the result, and the difference is adjusted by the PR controller and then modulated by SVPWM to generate the switching transistor drive signal; the switching transistor of the bidirectional converter adopts an insulated gate bipolar transistor (IGBT).

10. A method for suppressing DC component, applied to the optical-storage DC-flexible system according to any one of claims 1-9, characterized in that, Includes the following steps: Acquisition Steps: Synchronously acquire the first inverter AC current i inv and the second DC bias current obtained after rectification and filtering i DCI ; Calculation steps: based on the above i inv and i DCI Calculate the first DC compensation value Id 1 Second DC compensation value Id 2 ; Fusion Steps: Based on the converter's operating conditions, perform fusion calculations to fuse the... Id 1 and Id 2 Generate integrated DC compensation quantity Id comp ; Compensation steps: [The following is a list of steps, not a direct translation] Id comp The reference current command fed forward to the current control loop is used to suppress the DC component of the grid-connected current.

Images