operational amplifier
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 3PEAK INC
- Filing Date
- 2026-04-28
- Publication Date
- 2026-06-23
Smart Images
Figure CN122268280A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to an operational amplifier. Background Technology
[0002] With the increasing popularity of portable electronic devices, higher demands are being placed on the low power consumption and low voltage operation of integrated circuits. Therefore, operational amplifiers with low voltage and low power consumption characteristics have become an important development direction in the field of analog integrated circuit design.
[0003] However, existing operational amplifiers typically exhibit high quiescent power consumption when their output voltage is 0V. In applications where power consumption is extremely sensitive, such as portable devices, the increased quiescent power consumption at 0V severely restricts the performance and application range of operational amplifiers. Summary of the Invention
[0004] In view of the above problems, the purpose of this application is to provide an operational amplifier that can reduce the static power consumption of the operational amplifier.
[0005] According to one aspect of this application, an operational amplifier is provided, wherein the output stage of the operational amplifier includes: a first output transistor and a second output transistor connected in series, the common node of which provides the output voltage of the operational amplifier; a first mirror transistor of the first output transistor; a first current limiting structure for limiting a first mirror current flowing through the first mirror transistor; a second mirror transistor of the second output transistor; and a second current limiting structure for limiting a second mirror current flowing through the second mirror transistor.
[0006] Optionally, the magnitudes of the first mirror current and the second mirror current are equal.
[0007] Optionally, the first current limiting structure includes: a first current source, wherein the first mirror transistor and the first current source are connected in series between a first power supply terminal and a second power supply terminal, and the first current source is used to provide a first source current; and a first shunt module, wherein a first end is connected to the first power supply terminal and a second end is connected to the second end of the first mirror transistor, and the first shunt module is used to provide a first shunt current. The second current limiting structure includes: a second current source, which is connected in series with the second mirror transistor between the first power supply terminal and the second power supply terminal, and the second current source is used to provide a second source current; and a second shunt module, wherein a first end is connected to the first end of the first mirror transistor and a second end is connected to the second power supply terminal, and the second shunt module is used to provide a second shunt current, wherein the first source current and the second source current are equal in magnitude, and the first shunt current and the second shunt current are equal in magnitude.
[0008] Optionally, the operational amplifier further includes: an input stage for providing a differential current based on a differential input signal; a gain stage for providing a first drive signal to the control terminals of the first output transistor and the first mirror transistor, and a second drive signal to the control terminals of the second output transistor and the second mirror transistor, based on the differential current; and a bias signal generation circuit for providing corresponding bias voltages to the input stage, the gain stage, and the output stage.
[0009] Optionally, the first mirror structure of the bias signal generation circuit is used to provide a first bias voltage and a second bias voltage. The first mirror structure includes: a fifteenth transistor and a reference current source connected in series between a first power supply terminal and a second power supply terminal, wherein the control terminal of the fifteenth transistor is connected to the second terminal and provides the first bias voltage; and a sixteenth transistor and a seventeenth transistor connected in series between the first power supply terminal and the second power supply terminal, wherein the control terminal of the sixteenth transistor is connected to the control terminal of the fifteenth transistor, and the control terminal of the seventeenth transistor is connected to the first terminal and provides the second bias voltage. The first current source and the second current source are transistor current sources, wherein the first current source provides a first source current according to the first bias voltage, and the second current source provides a second source current according to the second bias voltage.
[0010] Optionally, the bias signal generation circuit further includes: a second mirror structure for providing a third bias voltage based on the second bias voltage; and a third mirror structure for providing a fourth bias voltage based on the first bias voltage. The second mirror structure includes: a first control voltage generation module and a third current source connected in series between the first power supply terminal and the second power supply terminal, the first control voltage generation module being used to generate a first control voltage based on the branch current provided by the third current source; an eighteenth transistor, a nineteenth transistor, and a fourth current source connected in series between the first power supply terminal and the second power supply terminal, the control terminal of the eighteenth transistor being connected to the second terminal of the nineteenth transistor, and the control terminal of the nineteenth transistor being connected to the first control voltage; and a twentieth transistor and a fifth current source connected in series between the second terminal of the eighteenth transistor and the second power supply terminal, the control terminal of the twentieth transistor being connected to the second terminal and providing the third bias voltage. The third mirror structure includes: a first control voltage generation module and a third current source connected in series between the first power supply terminal and the second power supply terminal; and a second control voltage generation module and a third current source connected in series between the second terminal of the eighteenth transistor and the second power supply terminal, the control terminal of the twentieth transistor being connected to the second terminal and providing the third bias voltage. The system comprises a sixth current source and a second control voltage generating module between the first power supply terminal and the second power supply terminal. The second control voltage generating module generates a second control voltage based on the branch current provided by the sixth current source. A seventh current source, a twenty-first transistor, and a twenty-second transistor are connected in series between the first power supply terminal and the second power supply terminal. The first terminal of the twenty-first transistor is connected to the control terminal of the twenty-second transistor, and the control terminal of the twenty-first transistor is connected to the second control voltage. An eighth current source and a twenty-third transistor are also connected in series between the first power supply terminal and the second power supply terminal. The first terminal of the twenty-third transistor is connected to the control terminal and provides the fourth bias voltage. The third to eighth current sources are transistor current sources. The third to fifth current sources provide branch current to their respective branches based on the second bias voltage, and the sixth to eighth current sources provide branch current to their respective branches based on the first bias voltage.
[0011] Optionally, the first control voltage generating module includes a first resistor connected between the first power supply terminal and the third current source, and the second control voltage generating module includes a second resistor connected between the sixth current source and the second power supply terminal.
[0012] Optionally, the gain stage includes: a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series between the first power supply terminal and the second power supply terminal, wherein the first terminal of the fourth transistor is connected to one of the differential currents; a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series between the first power supply terminal and the second power supply terminal, wherein the first terminal of the eighth transistor is connected to the other of the differential currents, and the intermediate node between the sixth transistor and the seventh transistor provides the first drive signal; and a ninth transistor and a tenth transistor connected in series, wherein the first terminal of the ninth transistor is connected to the first terminal of the sixth transistor, the second terminal of the tenth transistor is connected to the second terminal of the seventh transistor, and the intermediate node between the ninth transistor and the tenth transistor provides the second drive signal, wherein the control terminal of the second transistor is connected to the control terminal of the sixth transistor and connected to the third bias voltage, the control terminals of the third transistor and the tenth transistor are connected to the fourth bias voltage, the control terminals of the fourth transistor and the eighth transistor are connected to the second bias voltage, the control terminal of the ninth transistor is connected to the second terminal of the first mirror transistor, and the control terminal of the seventh transistor is connected to the first terminal of the second mirror transistor.
[0013] Optionally, the gain stage further includes: an eleventh transistor connected in series between the first transistor and the second transistor; a twelfth transistor connected in series between the third transistor and the fourth transistor; a thirteenth transistor connected in series between the fifth transistor and the sixth transistor; and a fourteenth transistor connected in series between the seventh transistor and the eighth transistor. The control terminals of the eleventh transistor and the thirteenth transistor are connected to a fifth bias voltage, and the control terminals of the twelfth transistor and the fourteenth transistor are connected to a sixth bias voltage. When the gain stage includes the eleventh transistor and the thirteenth transistor, the control terminals of the first transistor and the fifth transistor are connected to each other and connected to the second terminal of the eleventh transistor; conversely, the control terminals of the first transistor and the fifth transistor are connected to each other and connected to the second terminal of the second transistor.
[0014] Optionally, the first control voltage generating module further includes: a third resistor and a second fourteenth transistor connected in series between the first power supply terminal and the first resistor, the control terminal of the second fourteenth transistor being connected to the second terminal and providing the fifth bias voltage; the second control voltage generating module further includes: a twenty-fifth transistor and a fourth resistor connected in series between the second resistor and the second power supply terminal, the control terminal of the second fifteenth transistor being connected to the first terminal and providing the sixth bias voltage.
[0015] Optionally, the first shunt module provides the first shunt current by clamping the second terminal voltage of the first mirror transistor to the third bias voltage, and the second shunt module provides a second shunt current equal to the first shunt current by clamping the first terminal voltage of the second mirror transistor to the fourth bias voltage.
[0016] Optionally, the first shunt module includes: a ninth current source and a twenty-sixth transistor connected in series between the first power supply terminal and the second power supply terminal, the control terminal of the twenty-sixth transistor being connected to a first control voltage; and a twenty-seventh transistor, the first terminal of which is connected to the first terminal of the twenty-sixth transistor, and the second terminal of which is connected to the control terminal and connected to the second terminal of the first mirror transistor. The second shunt module includes: a twenty-eighth transistor and a tenth current source connected in series between the first power supply terminal and the second power supply terminal, the control terminal of the twenty-eighth transistor being connected to the second control voltage; and a twenty-ninth transistor, the first terminal of which is connected to the control terminal and connected to the first terminal of the second mirror transistor, and the second terminal of which is connected to the second terminal of the twenty-eighth transistor, wherein the twenty-seventh transistor and the twenty-ninth transistor are both low threshold voltage devices.
[0017] Optionally, the first shunt module is the same as the first control voltage generating module; the second shunt module is the same as the second control voltage generating module.
[0018] Optionally, the second transistor, the third transistor, the sixth transistor, the seventh transistor, the ninth transistor, the tenth transistor, the twentieth transistor, and the twentieth transistor are low threshold voltage transistors.
[0019] Optionally, the voltage division of the fourth resistor is greater than the overdrive voltage of the eighth transistor, the voltage division of the second resistor is greater than the overdrive voltage of the fourteenth transistor, the negative of the voltage division of the third resistor is less than the overdrive voltage of the fifth transistor, and the negative of the voltage division of the first resistor is less than the overdrive voltage of the thirteenth transistor.
[0020] According to the operational amplifier provided in this application, by setting a first current limiting structure and a second current limiting structure to limit the current of the first mirror transistor and the second mirror transistor, the static current of the output transistor can be limited, thereby effectively suppressing the abnormal increase of the static current in the output transistor and helping to reduce the static power consumption of the operational amplifier. Attached Figure Description
[0021] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0022] Figure 1 A schematic structural diagram of an operational amplifier according to an embodiment of this application is shown;
[0023] Figure 2A Schematic circuit diagrams of the gain stage and output stage in some embodiments of this application are shown;
[0024] Figure 2B Schematic circuit diagrams of the gain stage and output stage are shown in some embodiments of this application;
[0025] Figure 3 A schematic circuit diagram of the bias signal generation circuit in some embodiments of this application is shown;
[0026] Figure 4 Schematic circuit diagrams of a first shunt module and a second shunt module are shown in some embodiments of this application;
[0027] Figure 5 Schematic circuit diagrams of a first shunt module and a second shunt module are shown in some embodiments of this application. Detailed Implementation
[0028] Various embodiments of the present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0029] Certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This specification and claims do not use differences in name to distinguish components.
[0030] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0031] Furthermore, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0032] Furthermore, it should be noted that in the following description, the transistor has a first terminal, a second terminal, and a control terminal. When the transistor is turned on, current flows from the first terminal to the second terminal. For an NMOS transistor, the first terminal is the drain, the second terminal is the source, and the control terminal is the gate; for a PMOS transistor, the first terminal is the source, the second terminal is the drain, and the control terminal is the gate.
[0033] Figure 1 A schematic structural diagram of an operational amplifier according to an embodiment of this application is shown. (Reference) Figure 1 The operational amplifier 10 includes a main circuit and an output stage 300. The main circuit provides a drive signal based on the input signal, and the output stage 300 provides an output voltage based on the drive signal.
[0034] exist Figure 1 In the example, the main circuit includes: input stage 100, gain stage 200, and bias signal generation circuit 400.
[0035] Input stage 100 is used to provide differential current based on the differential input signal.
[0036] In some embodiments, the input stage 100 includes a differential input pair and a tail current source. The tail current source provides a bias current to the differential input pair so that the differential input pair provides a differential current according to the differential input signal.
[0037] exist Figure 1 In the illustrated embodiment, the tail current source is a transistor current source, specifically including a tail current source transistor MIW. The differential input pair includes a first input transistor MIN1 and a second input transistor MIN2. Wherein, Figure 1 In the example, the tail current source transistor MIW, the first input transistor MIN1, and the second input transistor MIN2 are all PMOS transistors.
[0038] More specifically, the control terminal of the tail current source transistor MIW receives a first bias voltage VB1, which is connected to the first power supply terminal VDD. The second terminal provides a bias current. The control terminal of the first input transistor MIN1 receives one of the differential input signals, for example, a positive signal INN. The first terminal of the first input transistor MIN1 is connected to the bias current, which is also connected to the second terminal of the tail current source transistor MIW. The second terminal of the first input transistor MIN1 provides one of the differential currents, for example, current I1. The control terminal of the second input transistor MIN2 receives the other differential input signal, for example, a negative signal INP. The first terminal of the second input transistor MIN2 is also connected to the second terminal of the tail current source transistor MIW. The second terminal of the second input transistor MIN2 provides the other differential current, for example, current I2.
[0039] However, it should be understood that input level 100 is not limited to this, but can include any relevant structure.
[0040] Gain stage 200 provides drive signals VD1 and VD2 based on differential currents I1 and I2. Output stage 300 provides output voltage VOUT based on drive signals VD1 and VD2. Bias signal generation circuit 400 provides corresponding bias voltages for input stage 100, gain stage 200, and output stage 300.
[0041] The gain stage 200, output stage 300, and bias signal generation circuit 400 described above will be explained in detail below with reference to the corresponding circuit diagrams.
[0042] Figure 2A Schematic circuit diagrams of gain stage 200 and output stage 300 in some embodiments of this application are shown. The gain stage 200 is illustrated as an example of a gain stage 200a with a two-stage sleeve structure.
[0043] refer to Figure 2AGain stage 200a includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4 connected in series between a first power supply terminal VDD and a second power supply terminal VSS; a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8 connected in series between the first power supply terminal VDD and the second power supply terminal VSS; and a ninth transistor M9 and a tenth transistor M10 connected in series. The first input transistor MIN1 and the second input transistor MIN2 are both PMOS transistors. In the first power supply voltage VDD and the second power supply voltage VSS, the first power supply voltage VDD is high, and the second power supply voltage VSS is low (e.g., ground). The first terminal of the fourth transistor M4 is connected to one of the differential currents, for example, current I1, and the first terminal of the eighth transistor M8 is connected to the other differential current, for example, current I2. The intermediate node between the sixth transistor M6 and the seventh transistor M7 provides a first drive signal VD1, and the intermediate node between the ninth transistor M9 and the tenth transistor M10 provides a second drive signal VD2.
[0044] exist Figure 2A In the example, transistors M1, M2, M5, M6, and M9 are PMOS transistors, while M3, M4, M7, M8, and M10 are NMOS transistors. Specifically, the first terminal of transistor M1 is connected to the first power supply terminal VDD, and its second terminal is connected to the first terminal of transistor M2. The second terminal of transistor M2 is connected to the first terminal of transistor M3, the second terminal of transistor M3 is connected to the first terminal of transistor M4, and the second terminal of transistor M4 is connected to the second power supply terminal VSS. The first terminal of transistor M5 is connected to the first power supply terminal VDD, and its second terminal is connected to the first terminal of transistor M6. The second terminal of transistor M6 is connected to the first terminal of transistor M7, the second terminal of transistor M7 is connected to the first terminal of transistor M8, and the second terminal of transistor M8 is connected to the second power supply terminal VSS. The first terminal of transistor M9 is connected to the first terminal of transistor M6, and its second terminal is connected to the first terminal of transistor M10. The second terminal of transistor M10 is connected to the second terminal of transistor M7. The control terminals of the first transistor M1 and the fifth transistor M5 are connected to the second terminal of the second transistor M2. The control terminal of the second transistor M2 is connected to the control terminal of the sixth transistor M6 and is connected to the third bias voltage VB3. The control terminal of the third transistor M3 is connected to the control terminal of the tenth transistor M10 and is connected to the fourth bias voltage VB4. The control terminal of the fourth transistor M4 is connected to the control terminal of the eighth transistor M8 and is connected to the second bias voltage VB2.
[0045] refer toFigure 2A The output stage 300 includes a first output transistor MO1 and a second output transistor MO2 connected in series between the first power supply terminal VDD and the second power supply terminal VSS.
[0046] exist Figure 2A In the example, the first output transistor MO1 is a PMOS transistor, and the second output transistor MO2 is an NMOS transistor. Specifically, the first terminal of the first output transistor MO1 is connected to the first power supply terminal VDD, and the second terminal is connected to the first terminal of the second output transistor MO2, providing the output voltage VOUT. The second terminal of the second output transistor MO2 is connected to the second power supply terminal VSS.
[0047] The control terminal of the first output transistor MO1 receives the first drive signal VD1, and the control terminal of the second output transistor MO2 receives the second drive signal VD2. Through the complementary driving of VD1 and VD2, the first output transistor MO1 and the second output transistor MO2 are alternately turned on, thereby providing a stable output voltage VOUT while reducing the static power consumption of the operational amplifier.
[0048] Continue to refer to Figure 2A The output stage 300 also includes a first mirror transistor MM1 of the first output transistor MO1, a first current limiting structure 310, a second mirror transistor MM2 of the second output transistor MO2, and a second current limiting structure 320. The first current limiting structure 310 is used to limit the first mirror current IM1 flowing through the first mirror transistor MM1, and the second current limiting structure 320 is used to limit the second mirror current IM2 flowing through the second mirror transistor MM2.
[0049] By coordinating the adjustment of the first current-limiting structure 310 and the second current-limiting structure 320, the current values of the first mirror current IM1 and the second mirror current IM2 are made equal. This ensures that the pull-up current provided by the first output transistor MO1 is equal to the pull-down current provided by the second output transistor MO2, thereby controlling the quiescent current in the output transistors and reducing the quiescent power consumption of the operational amplifier 10. This is especially effective when the output voltage VOUT is 0V.
[0050] The first current-limiting structure 310 may include a first current source and a first shunt module 311. The first current source is connected in series with the first mirror transistor MM1 between the first power supply terminal VDD and the second power supply terminal VSS to provide a first source current IS1. The first terminal of the first shunt module 311 is connected to the first power supply terminal VDD, and the second terminal is connected to the second terminal of the first mirror transistor MM1. The first shunt module 311 provides a first shunt current IF1. Based on the shunt effect of the first shunt current IF1, the first mirror current IM1 = IS1 − IF1.
[0051] Similarly, the second current-limiting structure 320 includes a second current source and a second shunt module 321. The second mirror transistor MM2 is connected in series with the second current source between the first power supply terminal VDD and the second power supply terminal VSS to provide a second source current IS2. The first terminal of the second shunt module 321 is connected to the first terminal of the second transistor MM2, and the second terminal is connected to the second power supply terminal VSS. The second shunt module 321 provides a second shunt current IF2. Based on the shunt effect of the second shunt current IF2, the second mirror current IM2 = IS2 − IF2.
[0052] exist Figure 2A In the example, the first current source and the second current source are transistor current sources. Specifically, the first current source includes a first current source transistor MI1, and the second current source includes a second current source transistor MI2.
[0053] The first terminal of the first mirror transistor MM1 is connected to the first power supply terminal VDD, and the second terminal is connected to the first terminal of the first current source transistor MI1. The second terminal of the first current source transistor MI1 is connected to the second power supply terminal VSS. The control terminal of the first mirror transistor MM1 is connected to the control terminal of the first output transistor MO1 and to the first drive signal VD1. The control terminal of the first current source transistor MI1 is connected to the second bias voltage VB2. The first shunt module 311 is connected between the first power supply terminal VDD and the second terminal of the first mirror transistor MM1. The second terminal of the first mirror transistor MM1 is also connected to the control terminal of the ninth transistor M9.
[0054] The first terminal of the second current source transistor MI2 is connected to the first power supply terminal VDD, and the second terminal is connected to the first terminal of the second mirror transistor MM2. The second terminal of the second mirror transistor MM2 is connected to the second power supply terminal VSS. The control terminal of the second mirror transistor MM2 is connected to the control terminal of the second output transistor MO2 and is also connected to the second drive signal VD2. The control terminal of the second current source transistor MI2 is connected to the first bias voltage VB1. The second shunt module 321 is connected between the first terminal of the second mirror transistor MM2 and the second power supply terminal VSS. The first terminal of the second mirror transistor MM2 is also connected to the control terminal of the seventh transistor M7.
[0055] Among them, Figure 2A In the illustrated embodiment, the first mirror transistor MM1 and the second current source transistor MI2 are, for example, PMOS transistors, and the second mirror transistor MM2 and the first current source transistor MI1 are, for example, NMOS transistors.
[0056] A first source current IS1 and a second source current IS2 of equal magnitude are provided based on a first bias voltage VB1 and a second bias voltage VB2. A first shunt current IF1 and a second shunt current IF2 of equal magnitude are provided by a first shunt module 311 and a second shunt module 321, thereby achieving the limitation of static power consumption.
[0057] In some embodiments, such as Figure 2A The output stage 300 also includes a compensation module 330. The compensation module 330 includes a first capacitor C1 connected between the control terminal and the second terminal of the first output transistor MO1; and a second capacitor C2 connected between the control terminal and the first terminal of the second output transistor MO2. The first capacitor C1 and the second capacitor C2 together constitute a Miller compensation structure, effectively improving the loop phase margin and suppressing high-frequency oscillations.
[0058] Figure 2B Schematic circuit diagrams of gain stages and output stages in some embodiments of this application are shown. Gain stage 200 is illustrated as an example of gain stage 200b with a three-stage sleeve structure. This gain stage 200b, through its three-stage sleeve structure, can effectively improve the open-loop gain of the operational amplifier.
[0059] exist Figure 2B In the three-stage sleeve structure, the gain stage 200b further includes: an eleventh transistor M11 connected in series between the first transistor M1 and the second transistor M2; a twelfth transistor M12 connected in series between the third transistor M3 and the fourth transistor M4; a thirteenth transistor M13 connected in series between the fifth transistor M5 and the sixth transistor M6; and a fourteenth transistor M14 connected in series between the seventh transistor M7 and the eighth transistor M8. Figure 2B In the example, the eleventh transistor M11 and the thirteenth transistor M13 are PMOS transistors, and the twelfth transistor M12 and the fourteenth transistor M14 are NMOS transistors.
[0060] Specifically, the first terminal of the eleventh transistor M11 is connected to the second terminal of the first transistor M1, and the second terminal is connected to the first terminal of the second transistor M2. The first terminal of the twelfth transistor M12 is connected to the second terminal of the third transistor M3, and the second terminal is connected to the first terminal of the fourth transistor M4. The first terminal of the thirteenth transistor M13 is connected to the second terminal of the fifth transistor M5, and the second terminal is connected to the first terminal of the sixth transistor M6. The first terminal of the fourteenth transistor M14 is connected to the second terminal of the seventh transistor M7, and the second terminal is connected to the first terminal of the eighth transistor M8. The control terminals of the eleventh transistor M11 and the thirteenth transistor M13 are connected to the fifth bias voltage VB5. The control terminals of the twelfth transistor M12 and the fourteenth transistor M14 are connected to the sixth bias voltage VB6. Furthermore, due to the arrangement of the eleventh transistor M11 and the thirteenth transistor M13, the control terminal of the first transistor M1 connected to the fifth transistor M5 is connected to the second terminal of the eleventh transistor M11.
[0061] exist Figure 2B In the above, the first transistor M1 to the tenth transistor M10 in the gain stage 200b, the output stage 300 and its included first output transistor MO1, second output transistor MO2, first mirror transistor MM1, second mirror transistor MM2, first current limiting structure 310, second current limiting structure 320, first current source transistor MI1, second current source transistor MI2, first shunt module 311, second shunt module 321, compensation module 330, first capacitor C1, second capacitor C2, and first bias voltage VB1 to fourth bias voltage VB4 can all be referred to for comparison. Figure 2A The relevant description in the document.
[0062] Figure 3 A schematic circuit diagram of a bias signal generation circuit 400 in some embodiments of this application is shown. (See reference...) Figure 3 The bias signal generation circuit 400 includes a first mirror structure 410, a second mirror structure 420, and a third mirror structure 430.
[0063] The first mirror structure 410 is used to generate a first bias voltage VB1 and a second bias voltage VB2. Figure 3 In the example, the first mirror structure 410 includes a fifteenth transistor M15 and a reference current source I0 connected in series between the first power supply terminal VDD and the second power supply terminal VSS; and a sixteenth transistor M16 and a seventeenth transistor M17 connected in series between the first power supply terminal VDD and the second power supply terminal VSS. The fifteenth transistor M15 and the sixteenth transistor M16 are, for example, PMOS transistors, and the seventeenth transistor M17 is, for example, an NMOS transistor.
[0064] Specifically, the first terminal of the fifteenth transistor M15 is connected to the first power supply terminal VDD, and the second terminal is grounded via the reference current source I0. The control terminal of the fifteenth transistor M15 is connected to its second terminal and provides a first bias voltage VB1. The first terminal of the sixteenth transistor M16 is connected to the first power supply terminal VDD, the second terminal is connected to the first terminal of the seventeenth transistor M17, and its control terminal is connected to the control terminal of the fifteenth transistor M15. The control terminal of the seventeenth transistor M17 is connected to its first terminal and provides a second bias voltage VB2, and its second terminal is connected to the second power supply terminal VSS.
[0065] The second mirror structure 420 is used to generate a third bias voltage VB3 based on the second bias voltage VB2. Figure 3 In the example, the second mirror structure 420 includes a first control voltage generating module 421 and a third current source connected in series between the first power supply terminal VDD and the second power supply terminal VSS; an eighteenth transistor M18, a nineteenth transistor M19 and a fourth current source connected in series between the first power supply terminal VDD and the second power supply terminal VSS; and a twentieth transistor and a fifth current source connected in series between the second terminal of the eighteenth transistor M18 and the second power supply terminal VSS.
[0066] exist Figure 3 In the example, the third, fourth, and fifth current sources are, for example, mirror current sources, to provide the same branch current to their respective connected transistors according to the second bias voltage VB2. Specifically, the third current source includes a third current source transistor MI3, the fourth current source includes a fourth current source transistor MI4, and the fifth current source includes a fifth current source transistor MI5; MI3, MI4, and MI5 are of the same size, and their control terminals are all connected to the second bias voltage VB2, thereby providing equal branch current to their respective branches.
[0067] The first control voltage generation module 421 is used to provide a first control voltage VC1 according to the branch current of its branch. In some embodiments, such as when the gain stage 200 is a two-stage sleeve structure, the first control voltage generation module 421 includes a first resistor R1. The first resistor R1 is connected between the first power supply terminal VDD and the third current source, that is, the first terminal of the third current source transistor MI3, and the second terminal of the third current source transistor MI3 is connected to the second power supply terminal VSS.
[0068] The first terminal of the eighteenth transistor M18 is connected to the first power supply terminal VDD, and the second terminal is connected to the first terminal of the nineteenth transistor M19. The control terminal is connected to the second terminal of the nineteenth transistor M19. The second terminal of the nineteenth transistor M19 is also connected to the second power supply terminal VSS via a fourth current source. That is, the second terminal of the nineteenth transistor M18 is connected to the first terminal of the fourth current source transistor MI4, and the second terminal of the fourth current source transistor MI4 is connected to the second power supply terminal VSS. The control terminal of the nineteenth transistor M19 is connected to the first control voltage VC1.
[0069] The first terminal of the twentieth transistor M20 is connected to the second terminal of the eighteenth transistor M18, and the second terminal is connected to the second power supply terminal VSS via the fifth current source. That is, the second terminal of the twentieth transistor M20 is connected to the first terminal of the fifth current source transistor MI5, and the second terminal of MI5 is connected to the second power supply terminal VSS. The control terminal of the twentieth transistor M20 is connected to the second terminal and provides a third bias voltage VB3.
[0070] In some embodiments, when the gain stage 200 is a three-stage sleeve structure, the second mirror structure 420 is also used to generate a fifth bias voltage VB5. Accordingly, the first control voltage generation module 421 also includes a third resistor R3 and a twenty-fourth transistor M24 connected between the first power supply terminal VDD and the first resistor R1.
[0071] Specifically, the first terminal of the twenty-fourth transistor M24 is connected to the first power supply terminal VDD via the third resistor R3, the second terminal is connected to the first resistor R1, and the control terminal and the second terminal are connected to provide a fifth bias voltage VB5. In some embodiments, the twenty-fourth transistor M24 and the nineteenth transistor M19 have the same dimensions.
[0072] The third mirror structure 430 is used to generate a fourth bias voltage VB4 based on the first bias voltage VB1. Figure 3 In the example, the third mirror structure 430 includes a sixth current source and a second control voltage generation module 431 connected in series between the first power supply terminal VDD and the second power supply terminal VSS; a seventh current source, a twenty-first transistor M21 and a twenty-second transistor M22 connected in series between the first power supply terminal VDD and the second power supply terminal VSS; and an eighth current source and a twenty-third transistor M23 connected in series between the first power supply terminal VDD and the second terminal of the twenty-first transistor M21.
[0073] exist Figure 3In the example, the sixth, seventh, and eighth current sources are, for example, mirror current sources, to provide the same branch current to their respective connected transistors according to the first bias voltage VB1. Specifically, the sixth current source includes a sixth current source transistor MI6, the seventh current source includes a seventh current source transistor MI7, and the eighth current source includes an eighth current source transistor MI8; MI6, MI7, and MI8 are of the same size, and their control terminals are all connected to the first bias voltage VB1, thereby providing equal branch current to their respective branches.
[0074] The second control voltage generation module 431 is used to provide a second control voltage VC2 based on the branch current of its branch. In some embodiments, such as when the gain stage 200 is a two-stage sleeve structure, the second control voltage generation module 431 includes a second resistor R2. The first terminal of the sixth current source transistor MI6 is connected to the first power supply terminal VDD, and the second terminal is connected to the second power supply terminal VSS via the second resistor R2. The intermediate node between the sixth current source transistor MI6 and the second resistor R2 provides the second control voltage VC2.
[0075] The first terminal of the seventh current source transistor MI7 is connected to the first power supply terminal VDD, and the second terminal is connected to the first terminal of the twenty-first transistor M21. The second terminal of the twenty-first transistor M21 is connected to the first terminal of the twenty-second transistor M22, and the second terminal of the twenty-second transistor M22 is connected to the second power supply terminal VSS. The control terminal of the twenty-first transistor M21 is connected to the second control voltage VC2. The control terminal of the twenty-second transistor M22 is connected to the first terminal of the twenty-first transistor M21.
[0076] The first terminal of the eighth current source transistor MI8 is connected to the first power supply terminal VDD, and the second terminal is connected to the first terminal of the twenty-third transistor M23. The second terminal of M23 is connected to the second terminal of the twenty-first transistor M21. The control terminal of the twenty-third transistor M23 is connected to its first terminal and provides the fourth bias voltage VB4.
[0077] In some embodiments, when the gain stage 200 is a three-stage sleeve structure, the third mirror structure 430 is also used to generate a sixth bias voltage VB6. Correspondingly, the second control voltage generation module 431 also includes a twenty-fifth transistor M25 and a fourth resistor R4 connected between the second resistor R2 and the second power supply terminal VSS. In some embodiments, the twenty-first transistor M21 and the twenty-fifth transistor M25 have the same dimensions.
[0078] Specifically, the first terminal of the twenty-fifth transistor M25 is connected to the second resistor R2, the second terminal is connected to the second power supply terminal VSS via the fourth resistor R4, and the control terminal is connected to the first terminal and provides the sixth bias voltage VB6.
[0079] exist Figure 3In the embodiment, the sixth current source transistor MI6, the seventh current source transistor MI7, the eighth current source transistor MI8, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20 and the twenty-fourth transistor M24 are all PMOS transistors, and the third current source transistor MI3, the fourth current source transistor MI4, the fifth current source transistor MI5, the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23 and the twenty-fifth transistor M25 are all NMOS transistors, as an example for explanation.
[0080] In some embodiments, to reduce the minimum operating voltage of operational amplifier 10 and increase its gain, the second transistor M2, third transistor M3, sixth transistor M6, seventh transistor M7, ninth transistor M9, tenth transistor M10, twentieth transistor M20, and twenty-third transistor M23 are all low threshold voltage transistors, while the remaining transistors are standard threshold voltage transistors. The low threshold voltage transistors have the same threshold voltage, and the standard threshold voltage transistors have the same threshold voltage. The threshold voltage of the low threshold voltage transistor is lower than the threshold voltage of the standard threshold voltage transistor. That is, the threshold voltages of the second transistor M2, third transistor M3, sixth transistor M6, seventh transistor M7, ninth transistor M9, tenth transistor M10, twentieth transistor M20, and twenty-third transistor M23 are equal and lower than any of the remaining transistors.
[0081] Below, we will take the gain stage of a three-stage sleeve as an example, combined with... Figure 2B and Figure 3 This explains the working principle of the operational amplifier 10 of this application.
[0082] refer to Figure 3 The sixth current source transistor MI6 generates the sixth source current IS6, which flows through the second resistor R2, the twenty-fifth transistor M25, and the fourth resistor R4. The seventh current source transistor MI7 generates the seventh source current IS7, which flows through the twenty-first transistor M21 and the twenty-second transistor M22. The eighth current source transistor MI8 generates the eighth source current IS8, which flows through the twenty-third transistor M23 and the twenty-second transistor M22.
[0083] Under the condition that MI6, MI7, and MI8 have the same size, the sixth source current IS6, the seventh source current IS7, and the eighth source current IS8 are equal and are all counted as IN1.
[0084] Therefore, the control terminal voltage of the 25th transistor M25 is:
[0085] (1),
[0086] The control terminal voltage of the twenty-first transistor M21, also known as the second control voltage VC2, is:
[0087] (2),
[0088] The voltage at the second terminal of the twenty-first transistor M21, i.e., the voltage VP at node P, is:
[0089] (3),
[0090] The fourth bias voltage VB4 is:
[0091] (4),
[0092] In other words, under the condition that the twenty-first transistor M21 and the twenty-fifth transistor M25 have the same size, due to and If they are equal, then equation (4) above can be simplified to:
[0093] (5),
[0094] Combination Figure 2B In the above and and equal, and Under equal conditions, the voltages at the first terminals of the fourth transistor M4 and the eighth transistor M8 are:
[0095] (6),
[0096] Under the condition that the second supply voltage VSS is regarded as the ground voltage, the voltage at the first terminal of the fourth transistor M4 and the eighth transistor M8 is also the voltage difference between the first and second terminals of the fourth transistor M4 and the eighth transistor M8.
[0097] Under the condition that the voltage drop across the fourth resistor is greater than the overdrive voltage of the eighth transistor M8, the eighth transistor M8 can be guaranteed to operate in the saturation region. Similarly, the fourth transistor M4 also operates in the saturation region.
[0098] In the aforementioned twenty-third transistor M23 and tenth transistor M10, which are low threshold voltage devices, and and Under equal conditions, the voltages at the first terminals of the twelfth transistor M12 and the fourteenth transistor M14 are:
[0099] (7),
[0100] The voltage difference between the first and second terminals of the twelfth transistor M12 and the fourteenth transistor M14 is IN1 × R2, which is the voltage drop across the second resistor R2. As long as the voltage drop across the second resistor is greater than the overdrive voltage of the fourteenth transistor M14, the fourteenth transistor M14 can operate in the saturation region. Similarly, the twelfth transistor M12 also operates in the saturation region.
[0101] refer to Figure 3 The third current source transistor MI3 generates a third source current IS3 that flows through the third resistor R3, the twenty-fourth transistor M24, and the first resistor R1. The fourth current source transistor MI4 generates a fourth source current IS4 that flows through the eighteenth transistor M18 and the nineteenth transistor M19. The fifth current source transistor MI5 generates a fifth source current IS5 that flows through the eighteenth transistor M18 and the twentieth transistor M20.
[0102] Under the condition that the third current source transistor MI3, the fourth current source transistor MI4, and the fifth current source transistor MI5 have the same size, the third source current IS3, the fourth source current IS4, and the fifth source current IS5 are equal, and all are counted as IP1.
[0103] Therefore, the control terminal voltage of the 24th transistor M24 is:
[0104] (8),
[0105] The control terminal voltage of the nineteenth transistor M19, also known as the first control voltage VC1, is:
[0106] (9),
[0107] The voltage at the second terminal of the eighteenth transistor M18, i.e., the voltage VQ at node Q, is:
[0108] (10)
[0109] Therefore, given that the nineteenth transistor M19 and the twenty-fourth transistor M24 have the same dimensions, since and Equal to each other, the third bias voltage VB3 is:
[0110] (11),
[0111] Combination Figure 2B In the above and and equal, and Under equal conditions, the voltages at the second terminals of the first transistor M1 and the fifth transistor M5 are:
[0112] (12),
[0113] The voltage at the second terminal of the thirteenth transistor M13 is:
[0114] (13)
[0115] As long as the negative of the voltage division of the third resistor is less than the overdrive voltage of the fifth transistor M5, the fifth transistor M5 can be guaranteed to operate in the saturation region. Similarly, the first transistor M1 also operates in the saturation region.
[0116] In the twentieth transistor M20 and the sixth transistor M6, both are low threshold voltage devices, and and Under equal conditions, the voltages at the second terminals of the thirteenth transistor M13 and the eleventh transistor M11 are:
[0117] (14)
[0118] If the negative of the voltage division of the first resistor is less than the overdrive voltage of the thirteenth transistor M13, the thirteenth transistor M13 can be guaranteed to operate in the saturation region.
[0119] Among the formulas mentioned above, This is the control terminal voltage of transistor Mx. This represents the gate-source voltage of transistor Mx. Ry is the drain voltage of transistor Mx, where 1 ≤ x ≤ 25; Ry is the resistance of the y-th resistor, where 1 ≤ y ≤ 4; and VDD is the supply voltage at the first power supply terminal. Further explanations will not be repeated below.
[0120] When operational amplifier 10 is operating stably, under the conditions that the first shunt current IF1 and the second shunt current IF2 are equal, and the first source current IS1 and the second source current IS2 are equal, the first mirror current IM1 flowing through the first mirror transistor MM1 and the current IM2 flowing through the second mirror transistor MM2 are equal. Therefore, under the condition that the current flowing through the first output transistor MO1 is m times IM1 and the current flowing through the second output transistor MO2 is m times IM2, the current configurations of the first output transistor MO1 and the second output transistor MO2 are equal, thereby achieving effective control of static power consumption.
[0121] Further analysis reveals that when the voltage at node B increases, the current flowing through the seventh transistor M7 increases, while the current flowing through the tenth transistor M10 decreases. This strengthens the pull-down capability of the second mirror transistor MM2, thereby reducing the voltage at node B through feedback regulation. Similarly, when the voltage at node A increases, the current flowing through the ninth transistor M9 decreases, while the current flowing through the sixth transistor M6 increases. This weakens the pull-up capability of the first mirror transistor MM1, thus reducing the voltage at node A through feedback regulation.
[0122] The above two adjustment modes can effectively control the quiescent current of the output transistor, thereby achieving effective control of the quiescent power consumption of the operational amplifier 10.
[0123] In some embodiments, the first shunt module 311 provides a first shunt current IF1 by clamping the second terminal voltage of the first mirror transistor MM1 to a third bias voltage VB3. The second shunt module 321 provides a second shunt current IF2 equal in magnitude to the first shunt current IF1 by clamping the first terminal voltage of the second mirror transistor MM2 to a fourth bias voltage VB4.
[0124] Figure 4 Schematic circuit diagrams of the first shunt module 311 and the second shunt module 321 in some embodiments of this application are shown. Among them, (a) is a schematic circuit diagram of the first shunt module and (b) is a schematic circuit diagram of the second shunt module.
[0125] refer to Figure 4 In Figure (a), in some embodiments, the first shunt module 311 includes: a ninth current source I1 and a second sixteenth transistor M26 connected in series between the first power supply terminal VDD and the second power supply terminal VSS; and a twenty-seventh transistor connected between the first terminal of the second sixteenth transistor M26 and node A. Node A is also the second terminal of the first mirror transistor MM1.
[0126] Taking the twenty-sixth transistor M26 and the twenty-seventh transistor M27 as PMOS transistors as an example. Specifically, the first terminal of the twenty-sixth transistor M26 is connected to the first power supply terminal VDD via the ninth current source I1, the second terminal is connected to the second power supply terminal VSS, and the control terminal is connected to the first control voltage VC1. The first terminal of the twenty-seventh transistor M27 is connected to the first terminal of the twenty-sixth transistor M26, the second terminal is connected to the control terminal, and connected to node A.
[0127] Wherein, the voltage VA at node A is:
[0128] (15)
[0129] Substituting equation (9) into equation (15), it can be seen that under the condition that the twenty-seventh transistor M27 and the twentieth transistor M20 are both low threshold voltage devices and the remaining transistors are standard threshold voltage devices, the voltage VA of node A is the third bias voltage VB3.
[0130] refer to Figure 4 In Figure (b) of the diagram, in some embodiments, the second shunt module 321 includes: a twenty-eighth transistor M28 and a tenth current source I2 connected in series between the first power supply terminal VDD and the second power supply terminal VSS; and a twenty-ninth transistor M29 connected between node B and the second terminal of the twenty-eighth transistor M28. Node B is also the first terminal of the second mirror transistor MM2.
[0131] Taking the 28th transistor M28 and the 29th transistor M29 as NMOS transistors as examples. Specifically, the first terminal of the 28th transistor M28 is connected to the first power supply terminal VDD, and the second terminal is connected to the second power supply terminal VSS via the tenth current source I2. The control terminal is connected to the second control voltage VC2. The first terminal of the 29th transistor M29 is connected to the control terminal and connected to node B, and the second terminal is connected to the second terminal of the 28th transistor M28.
[0132] The voltage VB at node B is:
[0133] (16)
[0134] Substituting equation (2) into equation (17), we can see that when the twenty-ninth transistor M29 and the twenty-third transistor M23 are both low threshold voltage devices, and the remaining transistors are standard threshold voltage devices, the voltage VB at node B is the fourth bias voltage VB4. At this time, the first shunt current IF1 and the second shunt current IF2 are equal.
[0135] Figure 5 Schematic circuit diagrams of a first shunt module and a second shunt module are shown in some embodiments of this application. (a) is a schematic circuit diagram of the first shunt module, and (b) is a schematic circuit diagram of the second shunt module.
[0136] refer to Figure 5 In some embodiments, the structure of the first shunt module 311 is the same as that of the first control voltage generating module 421, that is, the components, component parameters, and connection relationships between the components are the same. The structure of the second shunt module 321 is the same as that of the second control voltage generating module 431, that is, the components, component parameters, and connection relationships between the components are the same.
[0137] Specifically, the first shunt module 311 includes resistors R3' and R1' and transistor M24'. The first terminal of transistor M24' is connected to the first power supply terminal VDD via resistor R3', and the second terminal is connected to the control terminal and then connected to node A via resistor R1'. Node A is also the second terminal of the first mirror transistor MM1. Resistor R3' is the same as the third resistor R3, resistor R1' is the same as the first resistor R1, and transistor M24' is the same as the twenty-fourth transistor M24.
[0138] The second shunt module 321 includes resistors R2' and R4' and transistor M25'. The first terminal of transistor M25' is connected to the control terminal and then connected to node B via resistor R2'. Node B is also the first terminal of the second mirror transistor MM2. The second terminal of transistor M25' is connected to the second power supply terminal VSS via resistor R4'. Resistor R2' is the same as the second resistor R2, resistor R4' is the same as the fourth resistor R4, and transistor M25' is the same as the twenty-fifth transistor M25.
[0139] At this point, the first shunt current IF1 and the second shunt current IF2 are equal.
[0140] According to the operational amplifier provided in this application, by setting a first current limiting structure and a second current limiting structure to limit the current of the first mirror transistor and the second mirror transistor, the static current of the output transistor can be limited, thereby effectively suppressing the abnormal increase of the static current in the output transistor and helping to reduce the static power consumption of the operational amplifier.
[0141] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit this application to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. The scope of protection of this application should be determined by the scope defined in the claims of this application.
Claims
1. An operational amplifier, wherein, The output stage of the operational amplifier includes: A first output transistor and a second output transistor are connected in series, and their common node provides the output voltage of the operational amplifier; The first mirror transistor of the first output transistor; A first current-limiting structure is used to limit the first mirror current flowing through the first mirror transistor; The second output transistor's second mirror transistor; and The second current-limiting structure is used to limit the second mirror current flowing through the second mirror transistor.
2. The operational amplifier according to claim 1, wherein, The magnitudes of the first mirror current and the second mirror current are equal.
3. The operational amplifier according to claim 2, wherein, The first current limiting structure includes: A first current source, wherein the first mirror transistor and the first current source are connected in series between a first power supply terminal and a second power supply terminal, and the first current source is used to provide a first source current; and The first shunt module has a first terminal connected to the first power supply terminal and a second terminal connected to the second terminal of the first mirror transistor. The first shunt module is used to provide a first shunt current. The second current limiting structure includes: A second current source, connected in series with the second mirror transistor between the first power supply terminal and the second power supply terminal, is used to provide a second source current; and The second shunt module has a first terminal connected to the first terminal of the first mirror transistor and a second terminal connected to the second power supply terminal. This second shunt module is used to provide a second shunt current. Wherein, the first source current and the second source current are equal in magnitude, and the first shunt current and the second shunt current are equal in magnitude.
4. The operational amplifier according to claim 3, wherein, The operational amplifier also includes: The input stage is used to provide differential current based on the differential input signal; A gain stage is configured to provide a first drive signal to the control terminals of the first output transistor and the first mirror transistor according to the differential current, and to provide a second drive signal to the control terminals of the second output transistor and the second mirror transistor; and A bias signal generation circuit is used to provide corresponding bias voltages for the input stage, the gain stage, and the output stage.
5. The operational amplifier according to claim 4, wherein, The first mirror structure of the bias signal generation circuit is used to provide a first bias voltage and a second bias voltage. The first mirror structure includes: A fifteenth transistor and a reference current source are connected in series between the first and second power supply terminals. The control terminal of the fifteenth transistor is connected to the second terminal and provides the first bias voltage. A sixteenth transistor and a seventeenth transistor are connected in series between the first power supply terminal and the second power supply terminal. The control terminal of the sixteenth transistor is connected to the control terminal of the fifteenth transistor, and the control terminal of the seventeenth transistor is connected to the first terminal and provides the second bias voltage. Wherein, the first current source and the second current source are transistor current sources, the first current source provides the first source current according to the first bias voltage, and the second current source provides the second source current according to the second bias voltage.
6. The operational amplifier according to claim 5, wherein, The bias signal generation circuit further includes: A second mirror structure is used to provide a third bias voltage based on the second bias voltage; and The third mirror structure is used to provide a fourth bias voltage based on the first bias voltage. The second mirror structure includes: A first control voltage generating module and a third current source are connected in series between the first power supply terminal and the second power supply terminal. The first control voltage generating module is used to generate a first control voltage according to the branch current provided by the third current source. An eighteenth transistor, a nineteenth transistor, and a fourth current source are connected in series between the first power supply terminal and the second power supply terminal. The control terminal of the eighteenth transistor is connected to the second terminal of the nineteenth transistor, and the control terminal of the nineteenth transistor is connected to the first control voltage. A twentieth transistor and a fifth current source are connected in series between the second terminal of the eighteenth transistor and the second power supply terminal. The control terminal of the twentieth transistor is connected to the second terminal and provides the third bias voltage. The third mirror structure includes: A sixth current source and a second control voltage generating module are connected in series between the first power supply terminal and the second power supply terminal. The second control voltage generating module is used to generate a second control voltage based on the branch current provided by the sixth current source. A seventh current source, a twenty-first transistor, and a twenty-second transistor are connected in series between the first power supply terminal and the second power supply terminal. The first terminal of the twenty-first transistor is connected to the control terminal of the twenty-second transistor, and the control terminal of the twenty-first transistor is connected to the second control voltage. An eighth current source and a twenty-third transistor are connected in series between the first power supply terminal and the second power supply terminal. The first terminal of the twenty-third transistor is connected to the control terminal and provides the fourth bias voltage. Wherein, the third to the eighth current sources are transistor current sources, the third to the fifth current sources provide branch current to their respective branches according to the second bias voltage, and the sixth to the eighth current sources provide branch current to their respective branches according to the first bias voltage.
7. The operational amplifier according to claim 6, wherein, The first control voltage generation module includes: A first resistor is connected between the first power supply terminal and the third current source. The second control voltage generation module includes: The second resistor is connected between the sixth current source and the second power supply terminal.
8. The operational amplifier according to claim 7, wherein, The gain stage includes: A first transistor, a second transistor, a third transistor, and a fourth transistor are connected in series between the first power supply terminal and the second power supply terminal, wherein the first terminal of the fourth transistor is connected to one of the differential currents; A fifth, sixth, seventh, and eighth transistor are connected in series between the first power supply terminal and the second power supply terminal. The first terminal of the eighth transistor is connected to another of the differential currents. The intermediate node between the sixth and seventh transistors provides the first drive signal. A ninth and tenth transistor are connected in series, with the first terminal of the ninth transistor connected to the first terminal of the sixth transistor, and the second terminal of the tenth transistor connected to the second terminal of the seventh transistor. The intermediate node between the ninth and tenth transistors provides the second drive signal. Wherein, the control terminal of the second transistor is connected to the control terminal of the sixth transistor and connected to the third bias voltage; the control terminal of the third transistor is connected to the control terminal of the tenth transistor and connected to the fourth bias voltage; the control terminal of the fourth transistor is connected to the control terminal of the eighth transistor and connected to the second bias voltage; the control terminal of the ninth transistor is connected to the second terminal of the first mirror transistor; and the control terminal of the seventh transistor is connected to the first terminal of the second mirror transistor.
9. The operational amplifier according to claim 8, wherein, The gain stage also includes: An eleventh transistor connected in series between the first transistor and the second transistor; A twelfth transistor connected in series between the third transistor and the fourth transistor; A thirteenth transistor connected in series between the fifth transistor and the sixth transistor; The fourteenth transistor is connected in series between the seventh transistor and the eighth transistor. The control terminals of the eleventh and thirteenth transistors are connected to a fifth bias voltage, and the control terminals of the twelfth and fourteenth transistors are connected to a sixth bias voltage. When the gain stage includes the eleventh transistor and the thirteenth transistor, the control terminals of the first transistor and the fifth transistor are connected and connected to the second terminal of the eleventh transistor; conversely, the control terminals of the first transistor and the fifth transistor are connected and connected to the second terminal of the second transistor.
10. The operational amplifier according to claim 9, wherein, The first control voltage generation module further includes: A third resistor and a second fourteenth transistor are connected in series between the first power supply terminal and the first resistor. The control terminal and the second terminal of the second fourteenth transistor are connected to provide the fifth bias voltage. The second control voltage generation module also includes: A 25th transistor and a 4th resistor are connected in series between the second resistor and the second power supply terminal. The control terminal of the 25th transistor is connected to the first terminal and provides the 6th bias voltage.
11. The operational amplifier according to any one of claims 7-10, wherein, The first shunt module provides the first shunt current by clamping the voltage at the second terminal of the first mirror transistor to the third bias voltage. The second shunt module clamps the first terminal voltage of the second mirror transistor to the fourth bias voltage to provide a second shunt current equal to the first shunt current.
12. The operational amplifier according to claim 11, wherein, The first splitting module includes: A ninth current source and a second sixteenth transistor are connected in series between the first power supply terminal and the second power supply terminal, and the control terminal of the second sixteenth transistor is connected to a first control voltage; and The twenty-seventh transistor has its first terminal connected to the first terminal of the twenty-sixth transistor, and its second terminal connected to the control terminal and also connected to the second terminal of the first mirror transistor. The second splitting module includes: A twenty-eighth transistor and a tenth current source are connected in series between the first power supply terminal and the second power supply terminal; the control terminal of the twenty-eighth transistor is connected to the second control voltage; and The twenty-ninth transistor has its first terminal connected to the control terminal and also connected to the first terminal of the second mirror transistor, and its second terminal connected to the second terminal of the twenty-eighth transistor. Both the 27th transistor and the 29th transistor are low threshold voltage devices.
13. The operational amplifier according to claim 11, wherein, The first shunt module is the same as the first control voltage generating module; The second shunt module and the second control voltage produce the same result.
14. The operational amplifier according to claim 9 or 10, wherein, The second transistor, the third transistor, the sixth transistor, the seventh transistor, the ninth transistor, the tenth transistor, the twentieth transistor, and the twenty-third transistor are low threshold voltage transistors.
15. The operational amplifier according to claim 10, wherein, The voltage division of the fourth resistor is greater than the overdrive voltage of the eighth transistor, the voltage division of the second resistor is greater than the overdrive voltage of the fourteenth transistor, the negative number of the voltage division of the third resistor is less than the overdrive voltage of the fifth transistor, and the negative number of the voltage division of the first resistor is less than the overdrive voltage of the thirteenth transistor.