Digital notch filter, digital low pass filter and design method, medium and electronic device

Abstract

The application relates to a digital wave trap, a digital low-pass filter and a design method, a medium and an electronic device. The digital wave trap comprises a wave limit boundary anchoring unit and a wave limit zero point modulation unit which are cascaded in sequence, the wave limit boundary anchoring unit adopts a cascaded integral comb filter structure and is used for generating a first attenuation zero point at a boundary frequency of a target wave trap frequency band; the wave limit zero point modulation unit adopts a finite-length unit impulse response filter structure and is used for generating at least one second attenuation zero point in the target wave trap frequency band; and a continuous suppression band for the target wave trap frequency band is formed in the amplitude-frequency response of an output signal of the wave limit zero point modulation unit by the first attenuation zero point and the at least one second attenuation zero point. By using the digital wave trap provided by the application, a digital low-pass filter which can deeply and widely suppress power frequency interference and maintain strict linear phase and excellent low-pass characteristics can be designed without significantly increasing hardware resources and power consumption.

Description

Technical Field

[0001] This application relates to the fields of digital signal processing and mixed-signal integrated circuit design technology, and in particular to a digital notch filter, a digital low-pass filter and its design method, dielectric and electronic equipment. Background Technology

[0002] With the development of mixed-signal integrated circuit technology, high-precision analog-to-digital converters (ADCs) have been widely used in precision measurement, industrial control, and environmental monitoring for artificial intelligence chips. These applications typically operate in complex electromagnetic environments, where 50Hz or 60Hz power frequency interference from electrical facilities can easily couple into the chip system. Effectively addressing this interference in complex electromagnetic environments has become a key challenge in improving the measurement accuracy of chip systems. To ensure signal quality, the back-end of the ADC usually needs to be equipped with a digital filter capable of simultaneously filtering out quantization noise and out-of-band interference.

[0003] Currently, relevant technical solutions mainly employ linear-phase finite-impulse-response (FIR) band-stop filters or infinite-impulse-response (IIR) notch filters to achieve power frequency suppression. In multi-rate systems, cascaded integrator-comb (CIC) filters are commonly used for signal decimation, followed by FIR filters for waveform shaping. However, these technical solutions have significant shortcomings in simultaneously meeting the requirements for deep power frequency suppression and efficient low-pass filtering. First, traditional linear-phase FIR band-stop filters require extremely high filter orders to achieve sufficient notch depth, consuming substantial hardware resources. This necessitates not only a large chip area but also high power consumption, making them unsuitable for resource-constrained hardware platforms. Second, conventional notch filter designs often focus only on the attenuation of the notch point, easily compromising the overall low-pass characteristics and affecting DC measurement accuracy. Furthermore, high-order filters introduce significant group delays, limiting the system's real-time response capability. These shortcomings limit the applicability of existing technologies in resource-constrained on-chip systems and low-power applications.

[0004] Designing a digital filter structure that can perform deep broadband suppression of 50Hz or 60Hz power frequency interference while maintaining strict linear phase and excellent low-pass characteristics without significantly increasing hardware resources and power consumption has become a key design challenge. Summary of the Invention

[0005] To address the technical problems of complex design and high resource consumption in existing digital low-pass filters due to the pursuit of deep suppression of power frequency interference, strict linear phase, and excellent low-pass characteristics, this invention provides a digital notch filter, a digital low-pass filter, a design method, a dielectric material, and an electronic device. The digital notch filter provided in this application significantly reduces hardware complexity and achieves high-performance notch characteristics through the collaborative design of a notch boundary anchoring unit and a notch zero modulation unit. Specifically, this application utilizes the simple structure and multiplication-free nature of a cascaded integrator comb filter to accurately anchor the notch boundary at extremely low cost. Combined with the flexible zero-point configuration advantage of a finite-length unit impulse response filter, the characteristics within the notch band are efficiently sculpted. Together, these elements form a deep, continuous suppression band. The digital notch filter provided in this application fundamentally avoids the problem of drastically increased resource consumption caused by traditional high-order finite-length unit impulse response notch filters in pursuit of equivalent performance, while maintaining linear phase characteristics. This provides key technical support for achieving high-precision power frequency interference suppression in resource-constrained chip systems.

[0006] To achieve the above objectives, a first aspect of the present invention provides a digital notch filter, comprising: a limiting boundary anchoring unit and a limiting zero modulation unit cascaded sequentially in the signal flow direction. The limited-wave boundary anchoring unit adopts a cascaded integrator comb filter structure to generate a first attenuation zero at the boundary frequency of the target notch band. The first attenuation zero is related to the delay length and decimation factor of the comb filter. The limited-wave null modulation unit adopts a finite-length unit impulse response filter structure to generate at least one second attenuation zero in the target notch band. The second attenuation zero is related to the number of conjugate zero pairs arranged on the unit circle of the finite-length unit impulse response filter and the angular frequency of each pair of zeros. The first attenuation zero and the at least one second attenuation zero constitute a continuous suppression band for the target notch frequency band in the amplitude-frequency response of the output signal of the limit zero modulation unit.

[0007] In one possible implementation of the first aspect, the zero-point modulation unit is further configured to configure equalization zeros in a frequency band higher than the target notch band, the equalization zeros being configured to make the DC gain of the digital notch filter at zero frequency greater than the gain of the digital notch filter at any frequency point between zero frequency and the folding frequency of the zero-point modulation unit, wherein the equalization zeros are conjugate zero pairs, and the equalization zeros are configured near a point symmetrical about π / 2 of the lower limit of the target notch band, or near a frequency point of the folding frequency of the zero-point modulation unit.

[0008] In one possible implementation of the first aspect, the system function of the digital notch filter is calculated as follows:

[0009] in, This is the system function of the digital notch filter; Let z be the z-variable of the wave-limited boundary anchoring unit. ; Let z be the z-variable of the limited-wave null modulation unit. ; The ratio of the input sampling frequencies of the wave-limiting boundary anchoring unit to the wave-limiting null modulation unit is given by Fs, where Fs is the input sampling frequency of the wave-limiting null modulation unit, and nFs is the input sampling frequency of the wave-limiting boundary anchoring unit. The delay length of the comb filter in the wave-limiting boundary anchoring unit; The number of unit circle conjugate zero pairs configured for the limited-wave zero modulation unit.

[0010] In one possible implementation of the first aspect, the group delay of the digital notch filter is calculated as follows:

[0011] in, The group delay of the digital notch filter.

[0012] In one possible implementation of the first aspect, the number of conjugate zero pairs on the unit circle of the finite-length unit impulse response filter and the angular frequency of each pair of zeros are programmable.

[0013] In a second aspect, this application provides a digital low-pass filter, including a digital notch filter and a low-pass shaping filter unit cascaded in sequence, as described in the first aspect and any possible implementation of the first aspect. The digital notch filter is used to filter the input signal and form a suppression band in the target notch frequency band; The low-pass shaping filter unit is used to perform low-pass filtering and shaping on the signal processed by the digital notch filter.

[0014] In one possible implementation of the second aspect, the digital low-pass filter is a multi-rate system, and the digital low-pass filter further includes a pre-stage sampling rate conversion unit disposed before the digital notch filter. The pre-stage sampling rate conversion unit is used to downsample the input signal, and the decimation factor of the pre-stage sampling rate conversion unit is greater than the decimation factor of the limiting boundary anchoring unit in the digital notch filter.

[0015] In one possible implementation of the second aspect, the input sampling frequency of the digital notch filter is 2 to 15 times the upper limit frequency of the target notch band.

[0016] In one possible implementation of the second aspect, the folding frequency of the limiting null modulation unit is greater than the upper limit frequency of the target notch band.

[0017] In one possible implementation of the second aspect, the digital low-pass filter is a single-rate system, and the decimation factor of the limiting boundary anchoring unit in the digital notch filter is configured to 1.

[0018] In one possible implementation of the second aspect, the low-pass shaping filter unit is a finite-length unit impulse response filter or a half-band finite-length unit impulse response filter.

[0019] In one possible implementation of the second aspect, the target notch band is a power frequency interference band of 50 Hz to 60 Hz.

[0020] Thirdly, this application provides a design method for a digital low-pass filter, applicable to digital low-pass filters as described in the second aspect and any possible implementation thereof, the method comprising: Obtain target technical indicators, including notch depth, target notch bandwidth, passband cutoff frequency, stopband boundary frequency, maximum passband attenuation, and minimum stopband attenuation; Based on the target technical specifications, the system type of the digital low-pass filter to be designed is determined, and the system type includes multi-rate system and single-rate system; Select the appropriate filter configuration and cascade path based on the system type.

[0021] In one possible implementation of the third aspect, when the system type is determined to be a multi-rate system, the method includes: Determine the number of stages and the decimation factor of the preceding sampling rate conversion unit; Configure the front-end sampling rate conversion unit and the rear-end low-pass shaping filter unit; Configure a digital notch filter and cascade the digital notch filter between the front-end sampling rate conversion unit and the low-pass shaping filter unit.

[0022] In one possible implementation of the third aspect, when the system type is determined to be a single-rate system, the method includes: Configure the digital notch filter to single-rate mode and configure the decimation factor of the limiting boundary anchoring unit in the digital notch filter to 1. The digital notch filter, configured in single-rate mode, is used as a pre-stage and cascaded with a low-pass shaping filter unit as a post-stage.

[0023] In one possible implementation of the third aspect, configuring the digital notch filter includes: Configure cascaded beam-limiting boundary anchoring units and beam-limiting null modulation units; Based on the boundary frequency of the target notch band, the delay length and decimation factor of the comb filter of the limiting boundary anchoring unit are configured to generate the first attenuation zero point. Based on the target notch band, configure the number and angular frequency of the conjugate zero pairs on the unit circle of the limited-wave null modulation unit to generate at least one second attenuation zero. The first attenuation zero point and the at least one second attenuation zero point constitute a suppression band for the target notch band.

[0024] In one possible implementation of the third aspect, the configuration of the limited-wave null modulation unit further includes: Equalization nulls are configured in a frequency band higher than the target notch band. The equalization nulls are conjugate pairs and are configured near the symmetrical point of the lower limit of the target notch band about π / 2, or near the frequency point of the folding frequency of the notch null modulation unit. The equalization zero is used to make the DC gain of the digital notch filter at zero frequency greater than the gain of the digital notch filter at any frequency between zero frequency and the folding frequency of the limiting zero modulation unit.

[0025] Fourthly, this application provides an electronic device including a memory and a processor, wherein the memory is used to store a computer program executable by the processor; the processor is used to execute the computer program in the memory to implement a design method for a digital low-pass filter as described in the third aspect and any possible implementation thereof.

[0026] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein when the executable computer program in the storage medium is executed by a processor, it is capable of implementing the design method of a digital low-pass filter as described in the third aspect and any possible implementation thereof.

[0027] Compared with the prior art, the beneficial effects of this application are as follows: 1. By employing a cascaded integrator comb filter structure as the boundary anchoring unit for the notch filter, and utilizing its comb filter delay length and decimation factor to generate the first attenuation zero point at the target notch band boundary frequency, the problem of excessive hardware resource consumption caused by relying on high-order filters for boundary positioning in the prior art is solved. This effectively improves the resource efficiency of the notch filter implementation and achieves the technical effect of accurately anchoring the notch band boundary at low cost.

[0028] 2. By employing a finite-length unit impulse response filter structure as the limiting zero-point modulation unit, the inherent phase nonlinearity problem of traditional IIR-type notch filters is solved. Structurally, this ensures that the digital notch filter has a constant group delay, effectively improving the phase fidelity of the signal after passing through the notch filter. By generating at least one second attenuation zero within the target notch band based on the number and angular frequency of conjugate zero pairs configured on its unit circle, the problem of difficulty in balancing notch depth, width, and filter order in traditional schemes is solved. This effectively improves the flexibility and accuracy of notch shaping, achieving the technical effect of efficiently and accurately constructing the internal characteristics of the notch band with a small number of zeros.

[0029] 3. By combining the first attenuation zero point generated by the wave-limiting boundary anchoring unit with at least one second attenuation zero point generated by the wave-limiting zero-point modulation unit, a continuous suppression band is formed in the amplitude-frequency response. This solves the systemic problem that it is difficult to coordinate the optimization of notch filter boundary control and in-band suppression characteristics, effectively improves the overall performance of the notch band, and achieves a broadband notch effect with depth, flatness and clear boundaries.

[0030] 4. By constructing a digital notch filter using cascaded, functionally defined limiting boundary anchoring units and limiting zero-point modulation units in the signal flow direction, the problems of insufficient design flexibility and low modularity of complex filtering systems are solved, effectively improving the reusability and integration convenience of the digital notch filter as a core functional module. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 According to some embodiments of this application, a structural block diagram of a digital notch filter is shown; Figure 2 According to some embodiments of this application, a block diagram of a multi-rate digital low-pass filter structure is shown; Figure 3 According to some embodiments of this application, a block diagram of a single-rate digital low-pass filter structure is shown; Figure 4 According to some embodiments of this application, a flowchart of a design method for a digital low-pass filter is shown; Figure 5 According to some embodiments of this application, another more specific flowchart of a design method for a digital low-pass filter is shown; Figure 6 According to some embodiments of this application, a structural block diagram of a digital low-pass filter applied to a Σ-Δ ADC is shown; Figure 7 According to some embodiments of this application, a structural block diagram of an electronic device is shown. Detailed Implementation

[0033] The illustrative embodiments of this application include, but are not limited to, a digital notch filter, a digital low-pass filter and design methods, media and electronic devices.

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0035] As mentioned earlier, existing digital low-pass filters are complex in design and have high resource consumption due to their pursuit of deep suppression of power frequency interference, strict linear phase, and excellent low-pass characteristics.

[0036] In view of this, the digital notch filter provided in this application significantly reduces hardware complexity and achieves high-performance notch characteristics through the collaborative design of a notch-limiting boundary anchoring unit and a notch-limiting zero-point modulation unit. Specifically, this application utilizes the simple structure and multiplication-free nature of a cascaded integrator comb filter to accurately anchor the notch boundary at extremely low cost. Combined with the flexible zero-point configuration advantage of a finite-length unit impulse response filter, the characteristics within the notch band are efficiently sculpted. Together, these elements form a deep, continuous suppression band. The digital notch filter provided in this application fundamentally avoids the problem of drastically increased resource consumption caused by traditional high-order finite-length unit impulse response notch filters in pursuit of equivalent performance, while maintaining linear phase characteristics. This allows for high-precision power frequency interference suppression even in resource-constrained chip systems.

[0037] refer to Figure 1The present invention provides a digital notch filter 11, comprising: a limiting boundary anchoring unit 111 and a limiting zero modulation unit 112 cascaded in the signal flow direction. The limiting boundary anchoring unit 111 adopts a cascaded integrator comb filter structure to generate a first attenuation zero at the boundary frequency of the target notch band. The first attenuation zero is related to the delay length and decimation factor of the comb filter. The limiting zero modulation unit 112 adopts a finite-length unit impulse response filter structure to generate at least one second attenuation zero within the target notch band. The second attenuation zero is related to the number of conjugate zero pairs arranged on the unit circle of the finite-length unit impulse response filter and the angular frequency of each pair of zeros. The first attenuation zero and at least one second attenuation zero constitute a continuous suppression band for the target notch band in the amplitude-frequency response of the output signal of the limiting zero modulation unit 112. The target notch band includes, but is not limited to, the power frequency interference band from 50Hz to 60Hz.

[0038] Specifically, the frequency configuration of the first attenuation zero point in the limiting boundary anchoring unit 111 follows the principle of setting the frequency of the first attenuation zero point at the boundary frequency of the target notch band to anchor the start or end position of the notch band. For example, when the target notch band is a power frequency interference band of 50Hz to 60Hz, the first attenuation zero point is precisely set at 50Hz or 60Hz. By adjusting the decimation factor of the limiting boundary anchoring unit 111 and the delay length of the comb filter, precise control of the position of the first attenuation zero point can be achieved.

[0039] The configuration of the second attenuation zero in the notch modulation unit 112 follows these principles: within the target notch band, conjugate zero pairs are configured on the unit circle according to a predetermined pattern to generate at least one second attenuation zero. The number of conjugate zero pairs and the angular frequency of each pair are used together to control the bandwidth and depth of the notch band. The conjugate zero pairs can be equally or unequally spaced along the frequency axis to meet different notch shape design objectives.

[0040] In this way, by setting the first attenuation zero frequency of the limiting boundary anchoring unit 111 at the boundary position of the power frequency interference band, i.e., the start or end position, and in conjunction with the conjugate zeros configured on the unit circle by the limiting zero modulation unit 112, a deep notch region within 50Hz to 60Hz or a specified frequency band is formed. The notch range, depth, and position can be flexibly controlled. Compared with FIR bandstop filters of the same order, it has a deeper notch depth and a more easily adjustable design process. Furthermore, the digital notch filter 11 provided in this application has lower hardware complexity and power consumption, facilitating chip-level integration.

[0041] In some embodiments, the number of conjugate zero pairs on the unit circle of the finite-length unit impulse response filter and the angular frequency of each pair of zeros are programmable. This enables flexible online adjustment of the notch depth, notch bandwidth, and notch center frequency of the target notch band. This solves the problem that traditional fixed-parameter notch filters cannot adapt to different power frequency environments or cope with power frequency fluctuations. The digital notch filter 11 provided in this application can quickly and accurately adapt to different interference spectra through software instructions, thereby improving the adaptability and reliability of the digital notch filter 11 in complex electromagnetic environments, while avoiding the cost and cycle overhead of redesigning and manufacturing hardware to cope with different scenarios.

[0042] In some embodiments, the selection of the order and decimation factor of the limiting boundary anchoring unit 111 affects the overall performance of the digital notch filter 11. A higher order of the limiting boundary anchoring unit 111 results in greater attenuation within the target notch band and a deeper notch depth; a smaller decimation factor results in a greater achievable notch depth; and a larger decimation factor results in stronger overall stopband attenuation of the digital notch filter 11, while also reducing the design complexity of the equalization section in the limiting zero-point modulation unit 112. By comprehensively adjusting the order, decimation factor, and zero-point distribution of the limiting zero-point modulation unit 112, a digital notch filter 11 can be obtained that meets the requirements for deep power frequency notch filtering while minimizing the impact on the system's low-pass characteristics.

[0043] In some embodiments, to optimize amplitude-frequency characteristics, the zero-point modulation unit 112 is further configured with equalization zeros in a frequency band higher than the target notch band. The equalization zeros are used to ensure that the DC gain of the digital notch filter 11 at zero frequency is greater than the gain of the digital notch filter 11 at any frequency point between zero frequency and the folding frequency of the zero-point modulation unit 112. The equalization zeros are conjugate zero pairs, and are configured near the symmetrical point of the lower limit of the target notch band about π / 2, or near the folding frequency of the zero-point modulation unit 112. By configuring equalization zeros, the minimum stopband attenuation can be improved, the DC gain can be kept approximately 1, and the negative impact of the digital notch filter 11 on the system's low-pass characteristics can be reduced, thereby constructing a single-sided passband characteristic on the DC side. While meeting the notch depth and bandwidth requirements, the negative impact on the system's stopband and low-pass characteristics can also be reduced, making it particularly suitable for low-pass filtering scenarios.

[0044] In some embodiments, the system function of the digital notch filter 11 is calculated using the following formula:

[0045] in, For the system functions of digital notch filter 11; For the z-variable of the wave-limited boundary anchoring element 111, ; For the z-variable of the finite-wave null modulation unit 112, ; The ratio of the input sampling frequencies of the wave-limited boundary anchoring unit 111 to the wave-limited null modulation unit 112 is given by Fs, where Fs is the input sampling frequency of the wave-limited null modulation unit 112, and nFs is the input sampling frequency of the wave-limited boundary anchoring unit 111. The delay length of the comb filter in the wave-limited boundary anchoring unit 111; The number of unit circle conjugate zero pairs configured for the wave-limited zero modulation unit 112.

[0046] It should be understood that the z-variable mentioned above refers to the complex frequency variable in the Z-transform.

[0047] In some embodiments, the group delay of the digital notch filter 11 is calculated using the following formula:

[0048] in, This is the group delay of the digital notch filter 11. It is easy to see that this group delay... Since the phase is a constant, the digital notch filter 11 provided in this application is essentially a linear-phase FIR filter, which can guarantee the overall linear phase characteristics. Compared with traditional FIR band-stop filters, the digital notch filter 11 provided in this invention introduces a CIC filter structure, which makes the hardware implementation complexity of the digital notch filter 11 provided in this application lower and the notch performance easier to meet the requirements.

[0049] In summary, the digital notch filter provided in this application, by employing a cascaded integrator comb filter structure as the boundary anchoring unit, and utilizing the comb filter delay length and decimation factor to generate a first attenuation zero at the target notch band boundary frequency, solves the problem of excessive hardware resource consumption caused by relying on high-order filters for boundary positioning in existing technologies. This effectively improves the resource efficiency of the notch filter implementation and achieves the technical effect of accurately anchoring the notch band boundary at low cost. Utilizing a finite-length unit impulse response filter structure as the boundary zero modulation unit solves the inherent phase nonlinearity problem of traditional IIR-type notch filters, structurally ensuring a constant group delay for the digital notch filter and effectively improving the phase fidelity of the signal after passing through the notch filter. By generating at least one second attenuation zero within the target notch band based on the number and angular frequency of conjugate zero pairs configured on its unit circle, the problem of difficulty in balancing notch depth, width, and filter order in traditional schemes is solved, effectively improving the flexibility and accuracy of notch shaping and achieving the technical effect of efficiently and accurately constructing the internal characteristics of the notch band with a small number of zeros. By coordinating the first attenuation zero generated by the limiting boundary anchoring unit with at least one second attenuation zero generated by the limiting zero modulation unit, a continuous suppression band is formed in the amplitude-frequency response. This solves the systemic problem of the difficulty in coordinating the optimization of notch filter boundary control and in-band suppression characteristics, effectively improving the overall performance of the notch band and achieving a deep, flat, and clearly defined broadband notch effect. Furthermore, by constructing a digital notch filter using cascaded, functionally defined limiting boundary anchoring units and limiting zero modulation units along the signal flow direction, the design flexibility and modularity of complex filtering systems are addressed, effectively improving the reusability and integration convenience of the digital notch filter as a core functional module.

[0050] This application also provides a digital low-pass filter, which uses the aforementioned digital notch filter 11 as its core component and cascades it with a low-pass shaping filter unit 12. This digital low-pass filter is compatible with both single-rate and multi-rate operating modes, thus flexibly adapting to different application scenarios. By embedding the digital notch filter 11 provided in this application into the digital low-pass filter, the digital low-pass filter provided in this application achieves both deep power frequency notch filtering and high-quality low-pass filtering, ultimately providing a complete solution for high-precision Σ-Δ ADCs and various signal processing requiring high purity.

[0051] This application provides a digital low-pass filter comprising a digital notch filter 11 and a low-pass shaping filter unit 12 cascaded together. The digital notch filter 11 is used to filter the input signal and form a suppression band in the target notch frequency band; the low-pass shaping filter unit 12 is used to perform low-pass filtering and shaping on the signal processed by the digital notch filter 11.

[0052] In some embodiments, the digital low-pass filter is a multi-rate system, hereinafter referred to as a multi-rate digital low-pass filter 10, such as... Figure 2 As shown, the multi-rate digital low-pass filter 10 includes not only a cascaded digital notch filter 11 and a low-pass shaping filter unit 12, but also a pre-stage sampling rate conversion unit 13 positioned before the digital notch filter 11. The pre-stage sampling rate conversion unit 13 performs downsampling processing on the input signal, and its decimation factor is greater than that of the thresholding boundary anchoring unit 111 in the digital notch filter 11. By setting the pre-stage sampling rate conversion unit 13 and ensuring its decimation factor is greater than that of the thresholding boundary anchoring unit 111 in the digital notch filter 11, the multi-rate digital low-pass filter 10 achieves efficient, step-by-step reduction of the signal data stream. This allows the digital notch filter 11 and the low-pass shaping filter unit 12 to operate at a lower sampling rate, optimizing the overall hardware resources and power consumption of the digital low-pass filter.

[0053] In some embodiments, the input sampling frequency of the multi-rate digital low-pass filter 10 is 2 to 15 times the upper limit frequency of the target notch band. This avoids notch band distortion caused by insufficient sampling frequency and ensures that the digital notch filter 11 can form an effective and clear suppression band within the target frequency band.

[0054] In some embodiments, the folding frequency of the zero-point modulation unit 112 in the multi-rate digital low-pass filter 10 is greater than the upper limit frequency of the target notch band. This avoids spectral aliasing of the notch band signal during downsampling and ensures that the notch filtering effect of the digital notch filter 11 is not distorted.

[0055] In some embodiments, the digital low-pass filter is a single-rate system, hereinafter referred to as a single-rate digital low-pass filter 20, such as... Figure 3 As shown, the single-rate digital low-pass filter 20 includes a digital notch filter 11 and a low-pass shaping filter unit 12 cascaded in sequence. The decimation factor of the limiting boundary anchoring unit 111 in the single-rate digital low-pass filter 20 is configured to 1. By configuring the decimation factor of the limiting boundary anchoring unit 111 in the digital notch filter 11 to 1 and directly cascading the digital notch filter 11 and the low-pass shaping filter unit 12, the single-rate digital low-pass filter 20 provided in this application forms a simple two-stage processing architecture. This reduces control complexity and achieves low latency and high integration.

[0056] In some embodiments, the low-pass shaping filter unit 12 is a finite-length unit impulse response filter or a half-band finite-length unit impulse response filter to ensure high quality of the output signal of the digital low-pass filter.

[0057] The digital low-pass filter provided in this application combines high-performance power frequency notch filtering with high-quality low-pass shaping performance by cascading a digital notch filter as the core functional module with a low-pass shaping filter unit. This digital low-pass filter is compatible with both single-rate and multi-rate operating modes, allowing for flexible adaptation to different application scenarios and technical specifications.

[0058] In multi-rate system mode, by introducing a pre-stage sampling rate conversion unit and optimizing its cascaded path and parameter configuration with the digital notch filter and low-pass shaping filter unit, the signal data flow is progressively reduced. This allows subsequent processing units to operate at lower sampling rates, effectively optimizing overall hardware resource consumption and power consumption, making it suitable for applications with high input sampling rates and power sensitivity. Simultaneously, by constraining the relationship between the digital notch filter's operating sampling frequency and its notch bandwidth, spectral aliasing caused by insufficient sampling frequency is avoided.

[0059] In single-rate system mode, by configuring the digital notch filter to single-rate mode and directly cascading it with the low-pass shaping filter unit to form a two-stage processing architecture, it helps to reduce system control complexity and signal processing delay, achieves fast response and high integration, and is suitable for fixed sampling rate scenarios with high real-time requirements.

[0060] In summary, the digital low-pass filter provided in this application embeds a digital notch filter with deep notch filtering, linear phase, and low resource consumption characteristics, effectively solving the technical problem that traditional digital low-pass filters cannot simultaneously achieve deep power frequency suppression and excellent low-pass characteristics. It provides a solution for high-precision Σ-Δ ADCs and systems requiring high-purity signal processing that can simultaneously achieve high-performance notch filtering and high-quality low-pass filtering.

[0061] Furthermore, this application also provides a design method for a digital low-pass filter, applicable to digital low-pass filters as described in any of the foregoing embodiments, referencing... Figure 4 The design method of a digital low-pass filter provided in this application includes the following steps S11~S13: Step S11: Obtain the target technical specifications, which include notch depth, target notch band, passband cutoff frequency, stopband boundary frequency, maximum passband attenuation, and minimum stopband attenuation.

[0062] Step S12: Determine the system type of the digital low-pass filter to be designed based on the target technical specifications. The system type includes multi-rate system and single-rate system.

[0063] In some embodiments, the system type of the digital low-pass filter to be designed is determined based on the target technical specifications. The judgment logic is as follows: When the passband cutoff frequency and stopband boundary frequency in the target technical specifications are much lower than the input signal sampling frequency, and there are strict constraints on hardware resources and power consumption, the system type is determined to be a multi-rate system. The basis for this judgment is that the multi-rate system uses the pre-stage sampling rate conversion unit 13 for downsampling, which enables the subsequent digital notch filter 11 and low-pass shaping filter unit 12 to operate at a lower sampling rate, thereby reducing the overall computational complexity and power consumption to meet the resource constraint indicators. When the system has high requirements for single-cycle setup response speed, or the system itself operates at a single sampling frequency, the system type is determined to be a single-rate system. The basis for this judgment is that the single-rate system adopts a two-stage architecture of directly cascading the digital notch filter 11 and the low-pass shaping filter unit 12, avoiding the processing delay caused by sampling rate conversion in the multi-rate system, which is conducive to achieving a faster signal response speed.

[0064] Step S13: Select the appropriate filter configuration and cascade path according to the system type.

[0065] Here, filter configuration can refer to the relevant configuration of each functional unit in the digital low-pass filter to be designed; cascade path can refer to the connection order of each functional unit in the signal flow direction in the digital low-pass filter to be designed.

[0066] In some embodiments, when the system type is determined to be a multi-rate system, the design method of a digital low-pass filter provided in this application further includes: determining the number of stages and the decimation factor of the pre-stage sampling rate conversion unit 13; configuring the pre-stage sampling rate conversion unit 13 and the subsequent low-pass shaping filter unit 12; configuring a digital notch filter 11, and cascading the digital notch filter 11 between the pre-stage sampling rate conversion unit 13 and the low-pass shaping filter unit 12.

[0067] In some embodiments, when the system type is determined to be a single-rate system, the design method of a digital low-pass filter provided in this application includes: configuring the digital notch filter 11 in single-rate mode, configuring the decimation factor of the limiting boundary anchoring unit 111 in the digital notch filter 11 to 1; and cascading the digital notch filter 11 configured in single-rate mode as a front stage with the low-pass shaping filter unit 12 as a rear stage.

[0068] In some embodiments, configuring the digital notch filter 11 includes: configuring a cascaded limiting boundary anchoring unit 111 and a limiting null modulation unit 112; configuring the comb filter delay length and decimation factor of the limiting boundary anchoring unit 111 based on the boundary frequency of the target notch band to generate a first attenuation null; configuring the number and angular frequency of the conjugate null pairs on the unit circle of the limiting null modulation unit 112 based on the target notch band to generate at least one second attenuation null; and the first attenuation null and at least one second attenuation null constitute a suppression band for the target notch band.

[0069] In some embodiments, configuring the zero-point modulation unit 112 further includes: configuring equalization zeros in a frequency band higher than the target notch band, wherein the equalization zeros are conjugate zero pairs and are configured near the symmetrical point of the lower limit of the target notch band about π / 2, or near the frequency point of the folding frequency of the zero-point modulation unit 112; the equalization zeros are used to make the DC gain of the digital notch filter 11 at zero frequency greater than the gain of the digital notch filter 11 at any frequency point between zero frequency and the folding frequency of the zero-point modulation unit 112.

[0070] It is understood that the execution order of steps S11 to S13 above is only an illustration. In other embodiments, other execution orders may be used, and some steps may be split or combined. This is not limited here.

[0071] The following will combine Figure 5 The flowcharts shown below provide a detailed explanation of how to design a multi-rate digital low-pass filter 10 and a single-rate digital low-pass filter 20.

[0072] The design process for the multi-rate digital low-pass filter 10 is roughly as follows: First, the total upsampling / downsampling factor is determined based on the input sampling frequency and the target output data rate. Based on the total upsampling / downsampling factor and the resource efficiency optimization objective, the number of filter stages and their specific distribution are determined. A multi-stage cascaded structure is typically used, such as a 3-stage or 5-stage cascaded structure. Based on the passband cutoff frequency, stopband boundary frequency, and minimum stopband attenuation obtained in step S11, the pre-stage sampling rate conversion unit 13 is designed. This unit is implemented using a cascaded integrator-comb filter. By configuring its number of stages, the comb filter delay length, and the decimation factor of each stage, it achieves significant downsampling and a reduced data rate while providing initial stopband attenuation, thus reducing the burden on subsequent processing units.

[0073] Based on the notch depth, target notch band, and other notch-related technical specifications obtained in step S11, a digital notch filter 11 is designed. Specifically, the digital notch filter 11 is set to multi-rate mode. Based on the system architecture, the input sampling frequency Fs of the notch-limiting null modulation unit 112 is determined. The target notch band is set, for example, the target notch band is [50Hz, 60Hz]. The notch-limiting boundary anchoring unit 111 is configured: by adjusting its comb filter delay length M and decimation factor, the first attenuation zero point it generates is precisely set at the boundary of the target notch band, for example, at 50Hz or 60Hz. The notch-limiting null modulation unit 112 is configured: within the target notch band, a certain number of conjugate zero pairs are configured on the unit circle to generate a second attenuation zero point. The number of zeros and the angular frequency are used to control the notch bandwidth and depth. Constraints are determined, such as the folding frequency of the notch-limiting null modulation unit 112 being greater than the upper limit frequency of the target notch band, to avoid spectral aliasing. The input sampling frequency Fs of the wave-limiting zero-point modulation unit 112 is configured to be 2 to 15 times that of f_max. Parameter comprehensive adjustment: The number of stages and decimation factor of the wave-limiting boundary anchoring unit 111 and the zero-point distribution of the wave-limiting zero-point modulation unit 112 need to be jointly optimized to meet the requirements of notch depth, width and overall resource consumption.

[0074] Then, the location and parameters of the notch filter are determined. Specifically, considering the amplitude-frequency characteristics of the currently designed front-end sampling rate conversion unit 13, the digital notch filter 11, and the subsequent low-pass shaping filter unit 12, the precise location of the digital notch filter 11 in the cascaded link is determined. For example, the digital notch filter 11 is placed in an intermediate stage, and its parameters are fine-tuned. This step requires comprehensive consideration of system setup response, hardware resources, power consumption, and disturbances to low-pass characteristics. The optimal solution is obtained by adjusting the notch filter location or its internal parameters, such as by adjusting the CIC stage and the number of zero-log configurations of the zero-limiting modulation unit 112.

[0075] Next, a low-pass shaping filter unit 12 is designed and cascaded. Specifically, the low-pass shaping filter unit 12 is designed based on the final output data rate and strict low-pass technical specifications. This unit may be a finite-length unit impulse response filter or a half-band finite-length unit impulse response filter. Finally, according to the determined architecture, the preceding sampling rate conversion unit 13, the digital notch filter 11, and the low-pass shaping filter unit 12 are cascaded sequentially to complete the design of the entire multi-rate digital low-pass filter 10. Based on the final design, the hardware complexity can be further reduced by utilizing the coefficient symmetry of the linear phase FIR filter, etc.

[0076] The design process for a single-rate digital low-pass filter 20 is roughly as follows: First, the core functional units are designed. Specifically, based on the target technical specifications obtained in step S11, a low-pass shaping filter unit 12 and a digital notch filter 11 are designed. For the low-pass shaping filter unit 12, a finite-length unit impulse response filter is designed as the low-pass shaping filter unit 12 using methods such as the window function method, based on the relevant technical specifications of the passband and stopband. For the digital notch filter 11, it is specifically set to single-rate mode, and the decimation factor of its internal limiting boundary anchoring unit 111 is configured to 1. Based on the notch filter-related technical specifications, the target notch frequency band is set. The limiting boundary anchoring unit 111 is configured so that its first attenuation zero is located at the notch band boundary. The limiting zero modulation unit 112 is configured, arranging conjugate zero pairs within the notch band. To ensure the DC-side single-sided passband characteristics, an equalization zero is also configured near the folding frequency of the limiting zero modulation unit 112. Next, a two-stage cascaded architecture was determined: the digital notch filter 11 configured in single-rate mode was used as the first stage, and the designed low-pass shaping filter unit 12 was used as the second stage, with the two directly cascaded. This structure facilitates direct suppression of power frequency interference in the front stage, reducing the design burden of the subsequent filter, thereby completing the design of the single-rate digital low-pass filter 20.

[0077] The following example uses a typical multi-rate implementation of a Σ-Δ analog-to-digital converter (ADC) as a case study, combined with... Figure 6 This section briefly introduces the implementation process of a specific multi-rate digital low-pass filter.

[0078] Figure 6 This paper presents a specific implementation example of a digital low-pass filter applied to a multi-rate Σ-Δ ADC system. The system uses the output of a high-precision Σ-Δ modulator as input, assumes a sampling frequency of 32kHz, and designs three output data rate levels: 20sps, 10sps, and 5sps per second. The entire digital low-pass filter employs a multi-stage, multi-rate cascaded architecture to achieve deep power frequency notch filtering and high-quality low-pass filtering while efficiently reducing the data rate.

[0079] Specifically, taking the 20sps output level as an example, the digital low-pass filter includes three cascaded processing units.

[0080] The first stage is the front-end sampling rate conversion unit 13, corresponding to Figure 6The CIC_1 unit is configured as a CIC filter with a decimation factor of 40. This configuration allows the pre-amplifier sampling rate conversion unit 13 to provide initial stopband attenuation while significantly reducing the data rate from 32kHz to 800Hz, thereby reducing the design burden on subsequent processing units. Its stopband cutoff frequency can be configured to be 1 to 4 times the decimated folding frequency, and the number of stages can be adjusted according to the stopband attenuation requirements; in this embodiment, a single stage is optional.

[0081] The second stage is a digital notch filter 11, which serves as the core module for power frequency suppression and is inserted after the preceding sampling rate conversion unit 13. Its specific configuration is as follows: the built-in limiting boundary anchoring unit 111 corresponds to CIC_2 in the figure, is configured in multi-rate mode, its decimation factor is set to 4, and the CIC filter delay length is set to 8. Through this parameter configuration, the precise frequency of the first attenuation zero point generated by the limiting boundary anchoring unit 111 is located at 50Hz, thereby anchoring a boundary of the target notch band [50Hz, 60Hz]. The limiting zero-point modulation unit 112 corresponds to... Figure 6 In the NMZ of the target notch band, conjugate zero pairs are configured on the unit circle. In this embodiment, one or more pairs of conjugate zeros are constructed at 55Hz and 60Hz. Thus, the first attenuation zero at 50Hz and the second attenuation zeros at 55Hz and 60Hz work together to form a continuous suppression band for the [50Hz, 60Hz] frequency band in the amplitude-frequency response of the output signal of the limiting zero modulation unit 112. With this configuration, the digital notch filter 11 achieves excellent notch performance. Testing shows that its minimum notch depth can reach approximately -65dB, fully meeting the requirements of high-precision measurement systems for power frequency interference suppression. Simultaneously, since the target notch band is approximately located between half the folding frequency of the limiting zero modulation unit 112 and the folding frequency, the digital notch filter 11 has a DC-side single-sided passband characteristic, i.e., it obtains unity gain at DC, and the DC gain is greater than the gain at other frequencies within its passband, while the stopband attenuation meets system requirements.

[0082] The third stage is the low-pass shaping filter unit 12, corresponding to Figure 6 The FIR filter is used in this unit. Its design is based on an output data rate of 20 sps, using a folding frequency consistent with this rate for the low-pass filter design. This low-pass shaping filter unit 12 strictly meets the system's requirements for low-pass technical specifications such as passband ripple, transition bandwidth, and stopband attenuation. It can be designed using methods such as the window function method, and is used for the final waveform shaping and out-of-band noise suppression of the signal after notch filtering.

[0083] For the 10sps and 5sps levels, the digital low-pass filter is implemented by cascading an additional half-band finite-length unit impulse response filter and a 2x decimator on top of the 20sps output. Specifically, to achieve the 10sps level, a half-band finite-length unit impulse response filter (corresponding to...) is cascaded after the 20sps output. Figure 6 The output consists of a Half-band FIR_1 filter and a 2x decimator. To achieve the 5sps setting, a half-band finite-length unit impulse response filter (corresponding to...) is cascaded after the 10sps output. Figure 6 The Half-band FIR_2) and a 2x extractor.

[0084] In the aforementioned architectures with output speeds of 20sps, 10sps, and 5sps, the digital notch filter 11 is fixedly configured in the intermediate stage between the pre-amplitude sampling rate conversion unit 13 and the low-pass shaping filter unit 12. This design ensures that the entire digital low-pass filter maintains consistent and sufficient suppression capability for power frequency noise in the 50Hz–60Hz range at different output data rates. Furthermore, through multi-rate hierarchical processing, it achieves efficient utilization of hardware resources and optimization of system power consumption.

[0085] In addition, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein when the executable computer program in the storage medium is executed by a processor, it can implement a design method for a digital low-pass filter as described in any of the foregoing embodiments.

[0086] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements a design method for a digital low-pass filter as described in any of the foregoing embodiments.

[0087] Embodiments of this application also provide an electronic device 700, such as... Figure 7 As shown, the electronic device 700 includes a memory 701 and a processor 702. The memory 701 is used to store computer programs executable by the processor 702; the processor 702 is used to execute the computer programs in the memory 701 to implement a design method for a digital low-pass filter in any of the above embodiments.

[0088] Figure 7 The illustrated electronic device 700 also includes a communication interface 703. The processor 702, memory 701, and communication interface 703 are connected via a communication bus and communicate with each other.

[0089] The processor 702 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the above scheme.

[0090] The communication interface 703 is used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.

[0091] The memory 701 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0092] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0093] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0094] It should be noted that in the examples and description of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0095] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A digital notch filter, characterized in that, include: The wave-limiting boundary anchoring unit and the wave-limiting zero-point modulation unit are cascaded in sequence along the signal flow direction. The limited-wave boundary anchoring unit adopts a cascaded integrator comb filter structure to generate a first attenuation zero at the boundary frequency of the target notch band. The first attenuation zero is related to the delay length and decimation factor of the comb filter. The limited-wave null modulation unit adopts a finite-length unit impulse response filter structure to generate at least one second attenuation zero in the target notch band. The second attenuation zero is related to the number of conjugate zero pairs arranged on the unit circle of the finite-length unit impulse response filter and the angular frequency of each pair of zeros. The first attenuation zero and the at least one second attenuation zero constitute a continuous suppression band for the target notch frequency band in the amplitude-frequency response of the output signal of the limit zero modulation unit.

2. The digital notch filter according to claim 1, characterized in that, The zero-point modulation unit is further configured to configure equalization zeros in a frequency band higher than the target notch band. The equalization zeros are configured to make the DC gain of the digital notch filter at zero frequency greater than the gain of the digital notch filter at any frequency point between zero frequency and the folding frequency of the zero-point modulation unit. The equalization zeros are conjugate zero pairs, and the equalization zeros are configured near the symmetrical point of the lower limit of the target notch band about π / 2, or near the folding frequency of the zero-point modulation unit.

3. The digital notch filter according to claim 1 or 2, characterized in that, The system function of the digital notch filter is calculated using the following formula: in, This is the system function of the digital notch filter; Let z be the z-variable of the wave-limited boundary anchoring unit. ; Let z be the z-variable of the limited-wave null modulation unit. ; The ratio of the input sampling frequencies of the wave-limiting boundary anchoring unit to the wave-limiting null modulation unit is given by Fs, where Fs is the input sampling frequency of the wave-limiting null modulation unit, and nFs is the input sampling frequency of the wave-limiting boundary anchoring unit. The delay length of the comb filter in the wave-limiting boundary anchoring unit; The number of unit circle conjugate zero pairs configured for the limited-wave zero modulation unit.

4. The digital notch filter according to claim 3, characterized in that, The formula for calculating the group delay of the digital notch filter is as follows: in, The group delay of the digital notch filter.

5. The digital notch filter according to claim 1, characterized in that, The number of conjugate zero pairs on the unit circle and the angular frequency of each pair of zeros of the finite-length unit impulse response filter are programmable.

6. A digital low-pass filter, characterized in that, Includes a digital notch filter and a low-pass shaping filter unit as described in any one of claims 1 to 5, cascaded in sequence; The digital notch filter is used to filter the input signal and form a suppression band in the target notch frequency band; The low-pass shaping filter unit is used to perform low-pass filtering and shaping on the signal processed by the digital notch filter.

7. The digital low-pass filter according to claim 6, characterized in that, The digital low-pass filter is a multi-rate system. The digital low-pass filter also includes a pre-stage sampling rate conversion unit disposed before the digital notch filter. The pre-stage sampling rate conversion unit is used to downsample the input signal. The decimation factor of the pre-stage sampling rate conversion unit is greater than the decimation factor of the limiting boundary anchoring unit in the digital notch filter.

8. The digital low-pass filter according to claim 7, characterized in that, The input sampling frequency of the digital notch filter is 2 to 15 times the upper limit frequency of the target notch band.

9. The digital low-pass filter according to claim 8, characterized in that, The folding frequency of the zero-point modulation unit is greater than the upper limit frequency of the target notch band.

10. The digital low-pass filter according to claim 6, characterized in that, The digital low-pass filter is a single-rate system, and the decimation factor of the limiting boundary anchoring unit in the digital notch filter is configured to be 1.

11. The digital low-pass filter according to claim 6, characterized in that, The low-pass shaping filter unit is a finite-length unit impulse response filter or a half-band finite-length unit impulse response filter.

12. The digital low-pass filter according to claim 6, characterized in that, The target notch band is the 50Hz to 60Hz power frequency interference band.

13. A design method for a digital low-pass filter, applicable to the digital low-pass filter as described in any one of claims 6 to 12, characterized in that, The method includes: Obtain target technical indicators, including notch depth, target notch bandwidth, passband cutoff frequency, stopband boundary frequency, maximum passband attenuation, and minimum stopband attenuation; Based on the target technical specifications, the system type of the digital low-pass filter to be designed is determined, and the system type includes multi-rate system and single-rate system; Select the appropriate filter configuration and cascade path based on the system type.

14. The design method according to claim 13, characterized in that, When the system type is determined to be a multi-rate system, the method includes: Determine the number of stages and the decimation factor of the preceding sampling rate conversion unit; Configure the front-end sampling rate conversion unit and the rear-end low-pass shaping filter unit; Configure a digital notch filter and cascade the digital notch filter between the front-end sampling rate conversion unit and the low-pass shaping filter unit.

15. The design method according to claim 13, characterized in that, When the system type is determined to be a single-rate system, the method includes: Configure the digital notch filter to single-rate mode and configure the decimation factor of the limiting boundary anchoring unit in the digital notch filter to 1. The digital notch filter, configured in single-rate mode, is used as a pre-stage and cascaded with a low-pass shaping filter unit as a post-stage.

16. The design method according to claim 13, characterized in that, The configuration of the digital notch filter includes: Configure cascaded beam-limiting boundary anchoring units and beam-limiting null modulation units; Based on the boundary frequency of the target notch band, the delay length and decimation factor of the comb filter of the limiting boundary anchoring unit are configured to generate the first attenuation zero point. Based on the target notch band, configure the number and angular frequency of the conjugate zero pairs on the unit circle of the limited-wave null modulation unit to generate at least one second attenuation zero. The first attenuation zero point and the at least one second attenuation zero point constitute a suppression band for the target notch band.

17. The design method according to claim 16, characterized in that, The configuration of the wave-limiting null modulation unit further includes: Equalization nulls are configured in a frequency band higher than the target notch band. The equalization nulls are conjugate pairs and are configured near the symmetrical point of the lower limit of the target notch band about π / 2, or near the frequency point of the folding frequency of the notch null modulation unit. The equalization zero is used to make the DC gain of the digital notch filter at zero frequency greater than the gain of the digital notch filter at any frequency between zero frequency and the folding frequency of the limiting zero modulation unit.

18. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program executable by the processor; and the processor executes the computer program in the memory to implement the design method of the digital low-pass filter as described in any one of claims 13 to 17.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the executable computer program in the storage medium is executed by a processor, the design method of the digital low-pass filter as described in any one of claims 13 to 17 can be implemented.

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