A clock distribution circuit and apparatus suitable for use in a multi-channel radio frequency link

Abstract

The application discloses a clock branching circuit and device suitable for a multi-channel radio frequency link, comprising a clock conditioning module, a power division module, a multi-path shunt module, a differential conversion module, a clock generation module and an impedance matching module, the clock conditioning module outputs a conditioned clock signal based on an original clock signal; the power division module outputs a plurality of branched clock signals of the same source based on the conditioned clock signal; the multi-path shunt module divides the branched clock signal into a first clock signal and at least one second clock signal and then outputs them respectively based on the branched clock signal; the differential conversion module outputs a differential reference clock signal after differential conversion processing based on the first clock signal; the clock generation module outputs a plurality of differential sampling clock signals and a plurality of single-ended sampling clock signals based on the differential reference clock signal; and the impedance matching module outputs a reference clock signal to a radio frequency receiving chip based on the second clock signal. The application improves the synchronization accuracy of the multi-channel radio frequency link and effectively reduces the cost.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a clock splitter circuit and apparatus suitable for multi-channel radio frequency links. Background Technology

[0002] In electronic devices such as satellite navigation receivers, multimode wireless communications, and general-purpose software radios, multi-channel RF links are the structure for signal reception, processing, and synchronization. There are two main clock supply schemes for multi-channel RF links: one is to use multiple independent clock sources, with a separate clock generation module configured for each RF channel. This has the disadvantages of high hardware cost, high power consumption, and complex layout. Moreover, frequency deviation and phase shift are easy to occur between multiple clock sources, making it impossible to guarantee the homogeneity of the clocks of each channel and making it difficult to meet the synchronization requirements of high-precision multi-channel RF links. The other is to use a single clock source with a simple power divider. The clock signal output from the single clock source is directly split by the power divider and supplied to each device. However, the clock signal is prone to amplitude attenuation, high-frequency noise interference, and waveform distortion after splitting. Summary of the Invention

[0003] One object of this application is to provide a clock splitter circuit suitable for multi-channel RF links. Another object of this application is to provide a clock splitter device suitable for multi-channel RF links.

[0004] To achieve the above objectives, this application discloses a clock splitter circuit suitable for multi-channel RF links, comprising: The clock conditioning module connects to an external clock source module to receive and process the raw clock signal and output the conditioned clock signal. The power divider module is connected to the output of the clock conditioning module and is used to convert the conditioned clock signal into multiple shared clock signals from the same source and output them. A multi-channel splitter module is connected to the output terminal of the power splitter module and is used to receive the splitter clock signal, split it into a first clock signal and at least one second clock signal, and then output them respectively. A differential conversion module is connected to the first output terminal of the multi-channel splitter module, and is used to receive the first clock signal and perform differential conversion processing to output a differential reference clock signal. A clock generation module, connected to the output of the differential conversion module, is used to receive the differential reference clock signal and generate and output multiple differential sampling clock signals and multiple single-ended sampling clock signals. An impedance matching module is connected to the second output terminal of the multi-channel shunt module. It is used to receive the second clock signal and perform impedance matching processing, and output a reference clock signal to the RF receiver chip.

[0005] Optionally, the clock conditioning module includes a power amplifier submodule and a low-pass filter submodule connected in sequence; The power amplifier submodule is used to amplify the power of the original clock signal. The low-pass filter submodule is used to perform low-pass filtering on the power-amplified clock signal to obtain the conditioned clock signal and output it.

[0006] Optionally, the power amplifier submodule adopts a low-noise amplifier circuit structure built with operational amplifiers.

[0007] Optionally, the low-pass filter submodule is a multi-stage low-pass filter built with a passive LC structure.

[0008] Optionally, the differential conversion module includes a signal attenuation submodule, a differential drive submodule, and a signal conditioning submodule connected in sequence; The signal attenuation submodule is used to attenuate the first clock signal; The differential drive submodule is used to convert the attenuated single-ended clock signal into a differential clock signal. The signal conditioning submodule is used to perform AC coupling and DC biasing processing on the differential clock signal and output the differential reference clock signal.

[0009] Optionally, the clock generation module includes a clock generation chip and a peripheral loop filter; The clock generation chip is used to control the voltage-controlled oscillator to work stably and to process and generate the multi-channel differential sampling clock signal and the multi-channel single-ended sampling clock signal. The peripheral loop filter is used to adjust the locking time of the phase-locked loop.

[0010] Optionally, the peripheral loop filter adopts a third-order passive filter structure.

[0011] Optionally, the impedance matching module is configured with adjustable impedance matching parameters.

[0012] Optionally, the reference clock signal output by the impedance matching module is a cutting sine wave clock signal.

[0013] Another aspect of this application discloses a clock splitter device suitable for multi-channel RF links, including the clock splitter circuit and clock source module described above for multi-channel RF links.

[0014] The beneficial effects of this application are as follows: This application discloses a clock splitter circuit suitable for multi-channel RF links. Through the coordinated operation of a clock conditioning module, a power splitter module, and a multi-path splitter module, all output reference clock signals and sampling clock signals originate from the same original clock signal. This solves the problems of asynchronous sampling, inconsistent signal processing, and decreased positioning accuracy caused by different clock sources in existing multi-clock source solutions. The clock conditioning module's power amplification and low-pass filtering effectively compensate for the insertion loss of the power splitter module, suppressing high-frequency noise and spurious interference, and outputting a stable conditioning clock. A differential conversion module converts the single-ended clock to a differential clock, improving anti-interference capability. An impedance matching module achieves impedance matching with the RF receiver chip, reducing signal reflection loss and significantly improving signal processing accuracy. Furthermore, modular deployment reduces the number of active components, lowers costs, and simplifies layout. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This diagram shows an overall structural diagram of a clock splitter circuit suitable for multi-channel RF links according to an embodiment of this application; Figure 2 This diagram illustrates the structure of a clock conditioning module for a clock splitter circuit applicable to a multi-channel RF link according to an embodiment of this application. Figure 3 This illustration shows a structural diagram of a third-order passive filter for a clock splitter circuit suitable for a multi-channel RF link, according to an embodiment of this application. Figure 4 This diagram illustrates a structural diagram of a clock test environment for a clock splitter circuit suitable for a multi-channel RF link, according to an embodiment of this application. Figure 5 This diagram illustrates the structure of a differential drive submodule of a clock splitter circuit suitable for multi-channel RF links according to an embodiment of this application. Attached image description: 100. Clock source module; 200. Clock conditioning module; 300. Power divider module; 400. Multi-channel splitter module; 500. Impedance matching module; 600. RF receiver chip; 700. Differential conversion module; 800. Clock generation module; 910. Multi-channel differential sampling clock signal; 920. Multi-channel single-ended sampling clock signal. Detailed Implementation

[0016] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0017] It should be understood that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0018] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0019] In order to solve at least one of the problems existing in the prior art, according to one aspect of this application, such as Figure 1As shown, this embodiment discloses a clock splitter circuit suitable for multi-channel RF links, including a clock conditioning module 200, a power splitter module 300, a multi-channel splitter module 400, a differential conversion module 700, a clock generation module 800, and an impedance matching module 500. The clock conditioning module 200 is connected to an external clock source module 100 and is used to receive and process the original clock signal and output a conditioned clock signal. The power splitter module 300 is connected to the output terminal of the clock conditioning module 200 and is used to convert the conditioned clock signal into multiple shared clock signals and output them. The multi-channel splitter module 400 is connected to the output terminal of the power splitter module 300 and is used to receive the split clock signals and split them into multiple channels. A clock signal and at least one second clock signal are output separately; a differential conversion module 700 is connected to the first output terminal of the multi-channel splitter module 400, and is used to receive the first clock signal and perform differential conversion processing to output a differential reference clock signal; a clock generation module 800 is connected to the output terminal of the differential conversion module 700, and is used to receive the differential reference clock signal and generate and output multiple differential sampling clock signals 910 and multiple single-ended sampling clock signals 920; an impedance matching module 500 is connected to the second output terminal of the multi-channel splitter module 400, and is used to receive the second clock signal and perform impedance matching processing to output a reference clock signal to the RF receiver chip 600.

[0020] The input terminal of the clock conditioning module 200 is electrically connected to the external clock source module 100 to receive the raw clock signal output by the clock source module 100. The output terminal of the clock conditioning module 200 is electrically connected to the input terminal of the power divider module 300 to transmit the conditioned clock signal to the power divider module 300. The output terminal of the power divider module 300 is electrically connected to the input terminal of the multi-channel splitter module 400 to realize the conversion and transmission of a single-channel conditioned clock signal to multiple channels of the same source splitter clock signal. The multi-channel splitter module 400 has at least two output terminals, of which the first output terminal is electrically connected to the input terminal of the differential conversion module 700 to transmit the first clock signal to the differential conversion module 700, and the remaining second output terminal... The second clock signal is transmitted to the impedance matching module 500 via an electrical connection to the input terminal of the differential conversion module 700. The output terminal of the differential conversion module 700 is electrically connected to the input terminal of the clock generation module 800 via an electrical connection to the clock generation module 800 via a electrical connection to the clock generation module 800 via a electrical connection to the clock generation module 800 via a electrical connection to the clock generation module 800 via a electrical connection to the clock input terminal of the RF link and the clock generation module 800 via a electrical connection to the clock generation module 600 via a electrical connection to the clock input terminal of the RF receiver chip 600 via a electrical connection to the clock generation module 600 via a electrical connection to the clock generation module 700 via a electrical connection to the clock generation module 8 ...700 via a electrical connection to the clock generation module 700 via a electrical connection to the clock generation module 700 via a electrical connection to

[0021] In a specific embodiment, a 12-channel RF link is used. The multi-channel splitter module 400 adopts a 1-to-4 signal splitting structure, that is, the first output terminal is 1 channel, used to transmit the first clock signal to the differential conversion module 700, and the second output terminal is 3 channels, used to transmit 3 second clock signals to the impedance matching module 500, respectively adapting to the clock input requirements of the 3 RX3701 RF receiver chips 600; the clock generation module 800 is configured to output 1 62MHz differential sampling clock signal of LVPECL level and 4 62MHz single-ended sampling clock signals of LVCMOS level. Among them, 3 single-ended sampling clock signals are electrically connected to the synchronous sampling terminals of the 3 RX3701 RF receiver chips 600, and 1 single-ended sampling clock signal and 1 differential sampling clock signal are electrically connected to the synchronous sampling terminal of the baseband processing module, realizing the whole system clock synchronization between the RF link and the baseband processing module.

[0022] The layout of each module on the PCB follows the principle of the shortest path for signal transmission. The clock conditioning module 200, power divider module 300, and multi-channel splitter module 400 are concentrated near the output of the clock source module 100 to reduce transmission loss of the original clock signal and the conditioned clock signal. The differential conversion module 700 is located adjacent to the first output of the multi-channel splitter module 400 and the input of the clock generation module 800 to shorten the transmission distance from the single-ended clock signal to the differential reference clock signal and reduce signal interference. The clock generation module 800 is located between the RF link and the baseband processing module to facilitate the split transmission of multiple sampled clock signals. The impedance matching module 500 is located adjacent to the second output of the multi-channel splitter module 400 and the clock input of each RF receiver chip 600, respectively, to achieve local matching processing of each second clock signal, improving the accuracy of impedance matching and signal transmission efficiency. Meanwhile, electromagnetic shielding isolation zones are set between all analog clock signal processing modules and digital circuit modules to avoid electromagnetic interference from digital circuits to analog clock signals, ensuring that the phase noise and jitter of the clock signals meet the requirements of the radio frequency system.

[0023] Specifically, the power divider module 300 performs the initial conversion from a single-channel conditioned clock signal to multiple co-source split clock signals. The splitter module 400 performs a directional secondary split of the power-divided clock signal, transmitting it to the differential conversion module 700 and the impedance matching module 500 respectively. In a specific example, the power divider module 300 uses a 1-to-4 power divider. The input of the power divider is electrically connected to the output of the clock conditioning module 200 to receive the conditioned clock signal; the output is electrically connected to the input of the splitter module 400 to output four co-source split clock signals.

[0024] In an optional implementation, the clock conditioning module 200 includes a power amplification submodule and a low-pass filter submodule connected in sequence; the power amplification submodule is used to amplify the original clock signal; the low-pass filter submodule is used to perform low-pass filtering on the amplified clock signal to obtain the conditioned clock signal and output it.

[0025] Specifically, the clock conditioning module 200 includes a power amplification submodule and a low-pass filter submodule connected in sequence. The input terminal of the power amplification submodule is electrically connected to the external clock source module 100 as the input terminal of the clock conditioning module 200, and the output terminal of the low-pass filter submodule is electrically connected to the input terminal of the power divider module 300 as the output terminal of the clock conditioning module 200. The core function of the power amplification submodule is to amplify the original clock signal, compensate for the signal insertion loss introduced by the subsequent power divider module 300, and ensure that the amplitude of the clock signal at the input terminal of the power divider module 300 meets the operating requirements. The core function of the low-pass filter submodule is to perform low-pass filtering on the amplified clock signal, suppress out-of-band noise and spurious interference introduced during the power amplification process, eliminate signal aliasing in the circuit, and output a stable conditioned clock signal.

[0026] In specific examples, such as Figure 2 The diagram shows the structure of the clock conditioning module 200. The power amplifier submodule, centered on an operational amplifier, receives a 10MHz, 0.4V amplitude sine wave original clock signal from the input source. After amplification by the operational amplifier, the output is matched using resistor R5, effectively compensating for insertion loss in subsequent power dividers and filtering stages, ensuring stable clock signal amplitude. The low-pass filter submodule, composed of cascaded inductors L1 and L2 and capacitors C1 and C2, performs low-pass filtering on the amplified clock signal, effectively suppressing high-frequency noise and spurious interference introduced by the power amplifier. The filtered signal is then split into multiple co-source signals by the power divider. The outputs are AC-coupled via capacitors C3 and C4, and impedance matched using resistors R1 and R2, before being output to the subsequent multi-channel splitter module 400, ensuring consistent amplitude and phase synchronization of the clock signals in each branch. This front-end circuit has been verified through transient simulation; within a 1000ns simulation period, the clock signal shows no significant distortion, and the phase noise and jitter parameters meet the requirements of a multi-channel RF link.

[0027] In an optional implementation, the power amplifier submodule adopts a low-noise amplifier circuit structure built with operational amplifiers.

[0028] Specifically, the power amplifier submodule adopts a low-noise amplifier circuit structure built with operational amplifiers. In this embodiment, the Maxim Integrated MAX4012EUK operational amplifier is selected as the core component. This operational amplifier is a low-noise, high-speed, wideband operational amplifier whose bandwidth characteristics can completely cover the frequency range of the 10MHz basic clock signal commonly used in satellite navigation receivers. It also has a low noise figure, effectively avoiding the introduction of additional phase noise during amplification and ensuring the purity of the clock signal. The low-noise amplifier circuit built with the MAX4012EUK is a non-inverting amplifier circuit structure, including the operational amplifier itself, gain adjustment resistors, load impedance adjustment resistors, power supply filter capacitors, and other peripheral components. The gain adjustment resistors include feedback resistors. and grounding resistance The load impedance adjustment resistor includes the output matching resistor. and terminating resistor Power supply filter capacitors are connected in parallel between the positive and negative power supply inputs of the operational amplifier and ground to filter out ripple noise in the power supply and prevent power supply noise from coupling into the clock signal. Those skilled in the art can choose the appropriate capacitors according to actual needs; this application does not impose any limitations on this selection.

[0029] In an optional implementation, the low-pass filter submodule is a multi-stage low-pass filter built with a passive LC structure.

[0030] Specifically, the low-pass filter submodule employs a multi-order low-pass filter built with a passive LC structure. In this embodiment, it is a fourth-order passive LC low-pass filter. Compared to traditional first-order and second-order low-pass filters, the fourth-order structure has a steeper amplitude-frequency characteristic, enabling higher out-of-band rejection while ensuring low-loss in-band signal transmission. This effectively suppresses high-frequency noise introduced by the power amplifier submodule and external electromagnetic interference, and eliminates aliasing effects of the clock signal in subsequent processing. The passive LC low-pass filter is composed of inductors and capacitors connected in alternating series and parallel connections. It has no active components or external power supply, thus avoiding the introduction of additional power supply noise and component noise. Furthermore, it is low in cost, low in power consumption, and highly stable.

[0031] In this specific example, the clock signal frequency is 10MHz, the filter cutoff frequency is 12MHz, the in-band insertion loss is controlled within 1dB, the out-of-band rejection ratio is above 30dB after 20MHz, and the LC low-pass filter cutoff frequency is... Where L is the inductance and C is the capacitance. The VSWR formula for an LC filter is: Where μ = wL / R, w is the angular frequency, and R is the resistance. The loss of the LC filter is... Based on the above formula, the corresponding circuit design can be derived by changing the values ​​of capacitance and inductance.

[0032] It should be noted that the above design is for a 10MHz sine wave clock signal. For different frequency points and different amplitude requirements, those skilled in the art only need to change the corresponding parameter values ​​according to the calculation. The clock splitter circuit of this application can meet the clock requirements of most RF receiver chips 600.

[0033] In an optional implementation, the differential conversion module 700 includes a signal attenuation submodule, a differential drive submodule, and a signal conditioning submodule connected in sequence; the signal attenuation submodule is used to attenuate the first clock signal; the differential drive submodule is used to convert the attenuated single-ended clock signal into a differential clock signal; and the signal conditioning submodule is used to perform AC coupling and DC bias processing on the differential clock signal to output the differential reference clock signal.

[0034] Specifically, the differential conversion module 700 includes a signal attenuation submodule, a differential drive submodule, and a signal conditioning submodule connected in sequence. The input terminal of the signal attenuation submodule is electrically connected to the first output terminal of the multiplexer module 400, serving as the input terminal of the differential conversion module 700. The output terminal of the signal conditioning submodule is electrically connected to the input terminal of the clock generation module 800, serving as the output terminal of the differential conversion module 700. The differential conversion module 700 converts the single-ended first-channel clock signal output from the multiplexer module 400 into a differential reference clock signal, improving the clock signal's anti-interference capability and transmission distance.

[0035] In this specific example, the differential driver submodule is built using ADI's AD8352 as the main component. Because the AD8352 has drive and amplification capabilities, the signal is first attenuated by a 6dBπ attenuation submodule. Then, the AD8352 converts the 10MHz single-ended signal into a differential signal. Next, the signal conditioning submodule performs AC coupling and DC biasing on the differential clock signal output from the differential driver submodule to eliminate the DC component before outputting it to the clock generation module 800. The signal conditioning submodule includes AC coupling capacitors and a DC bias circuit.

[0036] In an optional implementation, the clock generation module 800 includes a clock generation chip and an external loop filter; the clock generation chip is used to control the voltage-controlled oscillator to operate stably and to process and generate the multi-channel differential sampling clock signal 910 and the multi-channel single-ended sampling clock signal 920; the external loop filter is used to adjust the lock-in time of the phase-locked loop.

[0037] Specifically, the input terminal of the clock generation chip is electrically connected to the output terminal of the differential conversion module 700, serving as the input terminal of the clock generation module 800, to receive the differential reference clock signal. The output terminal of the clock generation chip is also electrically connected to the synchronous sampling terminals of the RF link and the baseband processing module, respectively, outputting multiple differential sampling clock signals 910 and multiple single-ended sampling clock signals 920. The peripheral loop filter is electrically connected to the phase-locked loop (PLL) loop port of the clock generation chip to adjust the PLL's locking time. The clock generation module 800 uses the differential reference clock signal output by the differential conversion module 700 as a reference, and performs frequency multiplication and division processing through its internal PLL and voltage-controlled oscillator to generate multiple sampling clock signals with different level standards and amplitudes. These signals satisfy the synchronous sampling requirements of the RF receiver chip 600 and the baseband processing module, and all generated sampling clock signals originate from the same source as the original clock signal. In this specific example, the clock generation chip selected is the Analog Devices AD9517-4ABCPZ. This chip is a high-performance, multi-output clock generator that integrates a low-phase-noise phase-locked loop and a voltage-controlled oscillator. It supports eight high-precision clock outputs, exhibits excellent jitter performance with sub-picosecond jitter levels, and can meet the high accuracy requirements of satellite navigation receivers for sampling clock signals. Furthermore, the AD9517-4ABCPZ's VCO operates in the 1.45GHz~1.8GHz frequency range and can be flexibly configured via registers for frequency multiplication and division, enabling the generation of clock signals at various frequencies to adapt to the sampling clock requirements of different RF systems. In an optional implementation, the peripheral loop filter adopts a third-order passive filter structure.

[0038] In this embodiment, by adjusting the parameters of the third-order passive filter, the locking time of the phase-locked loop is controlled, enabling the clock generation chip to quickly and stably lock the reference clock signal and generate a high-precision sampling clock signal.

[0039] In specific examples, such as Figure 3 As shown, in this embodiment, the peripheral loop filter of the clock generation module 800 is a third-order passive filter designed to adapt to the AD9517-4 chip. This third-order passive filter can effectively suppress the high-frequency ripple and spurious interference output by the phase detector by precisely configuring the resistor and capacitor parameters.

[0040] In an optional implementation, the impedance matching module 500 is configured with adjustable impedance matching parameters.

[0041] In an optional implementation, the reference clock signal output by the impedance matching module 500 is a cutting sine wave clock signal.

[0042] Specifically, the input terminal of the impedance matching module 500 is electrically connected to the second output terminal of the multiplexer module 400 to receive the second clock signal; its output terminal is electrically connected to the clock input terminal of the RF receiver chip 600 to output a compatible reference clock signal. The impedance matching module 500 is designed to adapt the clock signal to the RF receiver chip 600. Its functions include two aspects: first, performing impedance matching processing on the second clock signal output from the multiplexer module 400 to ensure that the output impedance of the clock signal is perfectly matched to the clock input impedance of the RF receiver chip 600, achieving reflection-free signal transmission, improving signal transmission efficiency, and reducing signal loss and distortion; second, conditioning the waveform of the clock signal, converting the sine wave clock signal into a cut sine wave clock signal required by the RF receiver chip 600, and simultaneously calibrating the signal amplitude to ensure that the signal amplitude falls within the clock input amplitude range of the RF receiver chip 600, guaranteeing the normal operation of the RF receiver chip 600.

[0043] In a specific example, this embodiment provides a clock splitter circuit suitable for multi-channel RF links, applied to a 12-channel satellite navigation receiver RF link. It provides three 62MHz (CMOS) sampling clocks for three RX3701 RF receiver chips 600, and simultaneously outputs one 62MHz (CMOS) reference clock and one 62MHz (LVPECL) reference clock. The clock generation chip is an AD9517-4, whose PLL circuit consists of four registers: a prescaler P, a counter A, a counter B, and a divider R. The relationship between the VCO operating frequency and each register satisfies the formula... In this embodiment, the input reference clock frequency fREF = 10MHz. To ensure the VCO operates stably at 1.488GHz, the registers are configured with prescaler P = 32, counter B = 23, counter A = 8, and divider R = 5. The AD9517-4 internally sets up a VCO divider DV and a phase delay divider D0. The relationship between the output clock frequency and the VCO operating frequency satisfies the following formula: In this embodiment, a 62MHz sampling clock needs to be output. Combined with the VCO frequency of 1.488GHz, a 24-fold frequency division is required. The VCO divider DV=6, the phase delay divider D0=4, and channel 0 of the AD9517-4 is configured to LVPECL level, outputting one 62MHz differential sampling clock. Channels 6 and 7 are both configured to LVCMOS level, each outputting one 62MHz single-ended sampling clock, totaling three 62MHz CMOS sampling clocks to meet the sampling clock requirements of three RX3701 RF receiver chips 600. The peripheral loop filter adopts a third-order passive filter structure and is electrically connected to the PLL circuit of the AD9517-4 to adjust the lock-in time of the phase-locked loop.

[0044] In specific examples, such as Figure 4As shown, a clock testing environment is configured, using an N6705B modular power supply as the test power supply and raw clock signal source. This provides low-noise DC power to the power amplification submodule of the clock conditioning module 200, the differential drive submodule of the differential conversion module 700, and the clock generation chip of the clock generation module 800, and outputs a 10MHz standard sine wave raw clock signal. At the differential reference clock output of the differential conversion module 700 and the multi-channel differential sampling clock output of the clock generation module 800, signals are acquired using a P7360A high-frequency differential probe and connected to a DSA70604 high-performance spectrum analyzer to test the phase noise, jitter, harmonic suppression, and other indicators of the differential clock signal. At the reference clock output of the impedance matching module 500, the signal is directly connected to the single-ended input of the DSA70604 spectrum analyzer to test the amplitude, waveform distortion, and reflection loss of the cut sine wave clock signal of the adapted RF receiver chip 600. The clock splitter circuit in this embodiment can achieve multi-channel clock synchronization from the same source, meeting the high-precision synchronization requirements of multi-channel RF links such as satellite navigation receivers.

[0045] like Figure 5 As shown, in this embodiment, the differential driver submodule of the differential conversion module 700 is built using the AD8352 chip. The circuit is divided into a 6dB π-type attenuation submodule, a DC bias submodule, and a 6dB gain differential driver submodule. The single-ended clock input signal on the left undergoes two stages of filtering and a resistor attenuation network to achieve 6dB amplitude attenuation and impedance matching. The DC component is then isolated by capacitive coupling, in conjunction with the DC bias submodule consisting of a resistor voltage divider and a capacitor filter. The AD8352 differential driver chip in the middle receives the processed single-ended clock signal and converts it from single-ended to differential signal, outputting a differential clock signal with low jitter and high common-mode rejection ratio. The output terminal forms a matching network through resistors and capacitors, ultimately achieving an anti-interference, long-distance transmission differential clock signal output. This differential driver circuit can convert a single-ended clock signal into a differential signal with low jitter and high common-mode rejection ratio, effectively improving the anti-interference capability and transmission distance of the clock signal.

[0046] Another aspect of this application discloses a clock splitter device suitable for multi-channel RF links, including the clock splitter circuit and clock source module 100 described above.

[0047] Since the principle by which this device solves the problem is similar to that of the circuit described above, the implementation of this device can be found in the circuit implementation, and will not be repeated here.

[0048] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A clock splitter circuit suitable for multi-channel RF links, characterized in that, include: The clock conditioning module connects to an external clock source module to receive and process the raw clock signal and output the conditioned clock signal. The power divider module is connected to the output of the clock conditioning module and is used to convert the conditioned clock signal into multiple shared clock signals from the same source and output them. A multi-channel splitter module is connected to the output terminal of the power splitter module and is used to receive the splitter clock signal, split it into a first clock signal and at least one second clock signal, and then output them respectively. A differential conversion module is connected to the first output terminal of the multi-channel splitter module, and is used to receive the first clock signal and perform differential conversion processing to output a differential reference clock signal. A clock generation module, connected to the output of the differential conversion module, is used to receive the differential reference clock signal and generate and output multiple differential sampling clock signals and multiple single-ended sampling clock signals. An impedance matching module is connected to the second output terminal of the multi-channel shunt module. It is used to receive the second clock signal and perform impedance matching processing, and output a reference clock signal to the RF receiver chip.

2. The clock splitter circuit for multi-channel RF links according to claim 1, characterized in that, The clock conditioning module includes a power amplifier submodule and a low-pass filter submodule connected in sequence. The power amplifier submodule is used to amplify the power of the original clock signal. The low-pass filter submodule is used to perform low-pass filtering on the power-amplified clock signal to obtain the conditioned clock signal and output it.

3. The clock splitter circuit for multi-channel RF links according to claim 2, characterized in that, The power amplifier submodule adopts a low-noise amplifier circuit structure built with operational amplifiers.

4. The clock splitter circuit for multi-channel RF links according to claim 2, characterized in that, The low-pass filter submodule is a multi-stage low-pass filter built with a passive LC structure.

5. The clock splitter circuit for multi-channel RF links according to claim 1, characterized in that, The differential conversion module includes a signal attenuation submodule, a differential drive submodule, and a signal conditioning submodule connected in sequence. The signal attenuation submodule is used to attenuate the first clock signal; The differential drive submodule is used to convert the attenuated single-ended clock signal into a differential clock signal. The signal conditioning submodule is used to perform AC coupling and DC biasing processing on the differential clock signal and output the differential reference clock signal.

6. The clock splitter circuit for multi-channel RF links according to claim 1, characterized in that, The clock generation module includes a clock generation chip and an external loop filter; The clock generation chip is used to control the voltage-controlled oscillator to work stably and to process and generate the multi-channel differential sampling clock signal and the multi-channel single-ended sampling clock signal. The peripheral loop filter is used to adjust the locking time of the phase-locked loop.

7. The clock splitter circuit for multi-channel RF links according to claim 6, characterized in that, The peripheral loop filter adopts a third-order passive filter structure.

8. The clock splitter circuit for multi-channel RF links according to claim 1, characterized in that, The impedance matching module is configured with adjustable impedance matching parameters.

9. The clock splitter circuit for multi-channel RF links according to claim 1, characterized in that, The reference clock signal output by the impedance matching module is a cutting sine wave clock signal.

10. A clock splitter device suitable for multi-channel radio frequency links, characterized in that, Includes the clock splitter circuit and clock source module for multi-channel RF links as described in any one of claims 1-9.

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