A structure of a SiC embedded PCB with reinforced heat dissipation and insulation and a preparation method thereof

Abstract

The application relates to a structure of a SiC embedded PCB with reinforced heat dissipation and insulation and a preparation method thereof. The application comprises, from top to bottom, a PCB upper layer circuit and a functional layer, a SiC chip embedding unit, a diamond reinforced insulation heat dissipation functional layer and a bottom layer heat dissipation and connection layer; the SiC chip embedding unit comprises a SiC power chip arranged in a PCB cavity, a silver sintering layer arranged on the back of the SiC power chip and a functional copper layer connected with the silver sintering layer; the functional copper layer is connected with the diamond reinforced insulation heat dissipation functional layer through a vertical interconnection copper via; the diamond reinforced insulation heat dissipation functional layer comprises a CVD diamond film layer, the CVD diamond film layer independently constitutes a main insulation heat dissipation layer, or the CVD diamond film layer and an AMB ceramic layer are combined to constitute a composite insulation heat dissipation layer. The problems of insufficient insulation, accelerated thermal aging and high long-term failure risk of the existing SiC embedded PCB structure under the high-voltage and high-heat-flow working condition of 800V and above are solved, and the high-voltage insulation performance and service life are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor packaging technology, and in particular to a structure and preparation method of a SiC embedded PCB (printed circuit board) with enhanced heat dissipation and insulation. Background Technology

[0002] With the rapid upgrade of new energy vehicles, energy storage, rail transit, industrial power supplies, and other fields to 800V and above high-voltage platforms, silicon carbide (SiC) power devices, with their core advantages of high frequency, high efficiency, high temperature resistance, and low switching losses, have become the core component choice for high-voltage, high-power power electronic systems. To fully leverage the performance potential of SiC wide-bandgap devices and further improve the power density of power modules, reduce parasitic parameters, enhance heat dissipation capabilities, and improve long-term reliability, SiC chip embedded PCB packaging has become the mainstream technology for next-generation power modules.

[0003] Currently, mainstream SiC chip embedded PCB technologies worldwide (such as the Smartp Pack solution based on S-Cell jointly developed by Infineon and Schweizer, the embedded SiC MOSFET packaging solution from Fraunhofer IZM, and the automotive-grade embedded technology solution from Würth Elektronik) generally employ SiC chips and copper layers sintered with high temperature and silver to achieve low-resistance, high-reliability connections. The core structure beneath is an AMB (Active Metal Brazing) ceramic substrate (silicon nitride / aluminum nitride / alumina system) that provides electrical insulation and heat dissipation. Among these, the AMB silicon nitride ceramic substrate, with its insulation breakdown strength of 15–20kV / mm and thermal conductivity of 80–170W / m・K, has replaced traditional organic dielectrics such as FR-4 in medium- and high-voltage scenarios, significantly improving the module's heat dissipation and withstand voltage capabilities, and has become the mainstream insulation support solution for current SiC embedded PCB packaging.

[0004] However, under actual operating conditions of continuous high voltage of 800V and above and heat flux density of not less than 200W / cm², the existing SiC embedded PCB structure with AMB ceramic insulation and sintered copper layer still faces the following three insurmountable technical bottlenecks: 1. Insufficient high-voltage insulation margin and poor long-term reliability: Under strong electric field and high-temperature coupling conditions, the existing AMB ceramic insulation layer is prone to partial discharge, increased dielectric loss and material aging. Especially under automotive-grade wide temperature range cycling conditions of -40℃ to 175℃, microcracks in the ceramic layer will further accelerate insulation failure, which cannot meet the long-term safe operation requirements of 3.3kV and above high-voltage platforms.

[0005] 2. Significant thermal conductivity bottleneck, limiting device performance: The thermal conductivity of existing AMB silicon nitride ceramics is approximately 80 W / m·K, significantly lower than that of SiC chips (approximately 490 W / m·K) and copper layers (approximately 380 W / m·K). In the vertical heat conduction path, the ceramic layer becomes the primary source of thermal resistance, making it difficult to efficiently and promptly remove hotspots from the chip. This not only limits the performance of SiC chips under high-frequency, high-current conditions but also further exacerbates the thermal aging problem of the insulating layer.

[0006] 3. Severe thermal expansion mismatch and insufficient interface reliability: The coefficient of thermal expansion of SiC chips is approximately 2.5 ppm / K, copper layers are approximately 17 ppm / K, and silicon nitride ceramics are approximately 3.0 ppm / K, resulting in a significant thermal expansion mismatch among the three. During long-term power and temperature cycling, this can easily lead to failure phenomena such as interface fatigue, interlayer delamination, and sintered layer cracking, making it difficult to meet the long-life requirements of automotive-grade applications, which require at least 10,000 power cycles.

[0007] To overcome these bottlenecks, existing solutions in the industry mostly improve upon these issues by optimizing the ceramic layer thickness, enhancing sintering process quality, and increasing the number of heat dissipation vias. However, these improvements are limited by the inherent performance limits of the ceramic materials themselves, preventing a simultaneous leap forward in both heat dissipation and insulation performance. Therefore, developing a new SiC chip-embedded PCB structure that can simultaneously address the three major challenges of insulation, heat dissipation, and thermal matching has become a core technical problem that the industry urgently needs to solve. Summary of the Invention

[0008] Therefore, this invention provides a structure and preparation method of a SiC embedded PCB with enhanced heat dissipation and insulation, which solves the problems of insufficient insulation, accelerated thermal aging, and high risk of long-term failure of existing SiC embedded PCB structures under high voltage and high heat flow conditions of 800V and above, and significantly improves high voltage insulation performance and lifespan.

[0009] To solve the above technical problems, the present invention provides a SiC embedded PCB structure with enhanced heat dissipation and insulation, comprising: a PCB upper layer circuit and functional layer, a SiC chip embedded unit, a diamond-enhanced insulation and heat dissipation functional layer, and a bottom heat dissipation and connection layer arranged sequentially from top to bottom; The SiC chip embedding unit includes a SiC power chip disposed inside the PCB cavity, a silver sintered layer disposed on the back of the SiC power chip, and a functional copper layer connected to the silver sintered layer. The functional copper layer is connected to the diamond-reinforced insulating and heat-dissipating functional layer through vertical interconnect copper vias; the front side of the SiC power chip is electrically connected to the upper circuitry and functional layer of the PCB through vertical interconnect copper vias. The diamond-reinforced insulating and heat-dissipating functional layer includes a CVD diamond thin film layer, which alone constitutes the main insulating and heat-dissipating layer, or is combined with an AMB ceramic layer to form a composite insulating and heat-dissipating layer.

[0010] In one embodiment of the present invention, the diamond-reinforced insulating and heat-dissipating functional layer includes a CVD diamond thin film layer and an AMB ceramic layer; The CVD diamond film layer is disposed on the upper surface of the AMB ceramic layer, and the thickness of the CVD diamond film layer is 10μm~100μm. The upper and lower surfaces of the CVD diamond film layer are connected to the transition copper layer by metallurgical bonding. The AMB ceramic layer is a silicon nitride, aluminum nitride, or alumina ceramic layer with a thickness of 200μm to 400μm.

[0011] In one embodiment of the present invention, the diamond-reinforced insulating and heat-dissipating functional layer includes, from top to bottom, an upper interface transition copper layer, a CVD diamond thin film layer, a lower interface transition copper layer, and an AMB ceramic layer. The thickness of the CVD diamond film layer is 100μm~300μm; The AMB ceramic layer is a high thermal conductivity silicon nitride or aluminum nitride ceramic layer with a thickness of 50μm~150μm.

[0012] In one embodiment of the present invention, the upper and lower surfaces of the SiC chip are connected to the functional copper layer through a silver sintering layer, and CVD diamond thin film insulating heat dissipation layers are symmetrically arranged on the upper and lower sides of the SiC chip. PCB circuit layers and heat sinks are arranged at both the upper and lower ends of the structure to form a double-sided heat dissipation path.

[0013] In one embodiment of the present invention, the SiC power chip is a SiC MOSFET or a SiC IGBT die.

[0014] In one embodiment of the present invention, the upper layer of the PCB circuitry and functional layer includes a top copper foil circuitry, a driver IC, and a local DC bus capacitor. The driver IC is arranged adjacent to the SiC power chip to form a low parasitic switching circuit.

[0015] In one embodiment of the present invention, the bottom heat dissipation and connection layer includes a bottom copper layer, a system solder layer, and a copper heat sink, wherein the bottom copper layer is connected to the copper heat sink through the system solder layer.

[0016] In one embodiment of the present invention, the copper heat sink has a thickness of 3mm to 10mm and a heat transfer coefficient at the cooling end of ≥10000W / (m²·K).

[0017] This invention also provides a method for fabricating a SiC embedded PCB structure that enhances heat dissipation and insulation, comprising: S1. Pre-fabrication of diamond-reinforced insulating and heat-dissipating functional layer: A CVD diamond thin film layer is prepared using CVD technology. Both sides of the CVD diamond thin film layer are ground, polished, and surface metallized. A Ti / Cu seed layer is formed by magnetron sputtering, and a transition copper layer is electroplated on the Ti / Cu seed layer. The CVD diamond thin film layer alone constitutes the main insulating and heat-dissipating layer, or it can be combined with an AMB ceramic layer to form a composite insulating and heat-dissipating layer, thereby forming the diamond-reinforced insulating and heat-dissipating functional layer. S2. Prefabrication of SiC chip embedded unit: The back side of the SiC power chip is metallized, and the SiC power chip is fixed on the functional copper layer by silver sintering process to form a SiC chip embedded unit including the SiC power chip, the silver sintering layer and the functional copper layer. S3, PCB Embedding and Lamination: A cavity matching the SiC chip embedding unit is opened on the PCB substrate, the SiC chip embedding unit is embedded in the cavity, and the resin filling and multi-layer PCB stacking are completed by lamination process to form the structural basis of the upper layer circuit and functional layer of PCB. S4. Vertical interconnect forming: Vertical interconnect copper vias are formed by laser drilling, and copper interconnects are formed by electroplating filling process, so that the functional copper layer is connected to the diamond-reinforced insulation and heat dissipation functional layer through the vertical interconnect copper vias, and the front side of the SiC power chip is electrically connected to the upper circuit and functional layer of the PCB through the vertical interconnect copper vias. S5. Formation of the bottom heat dissipation and connection layer: A bottom copper layer is formed below the diamond-reinforced insulating heat dissipation functional layer, and the bottom copper layer is connected to the copper heat sink through the system solder layer to form the bottom heat dissipation and connection layer. S6. Component mounting and post-processing: Mount driver ICs and passive components on the upper circuit and functional layers of the PCB, and complete electrical connections, module assembly and testing.

[0018] In one embodiment of the present invention, in step S1, the surface metallization treatment of the CVD diamond thin film layer is carried out by double-sided magnetron sputtering to sequentially form a Ti layer with a thickness of 50-200 nm and a Cu layer with a thickness of 100 nm-500 nm, and a transition copper layer with a thickness of 3 μm-10 μm is electroplated on its surface.

[0019] The technical solution of the present invention has the following advantages compared with the prior art: The present invention discloses a structure and fabrication method for a SiC embedded PCB with enhanced heat dissipation and insulation. Compared with existing SiC embedded PCB structures, the present invention provides a diamond-enhanced insulation and heat dissipation functional layer below the SiC chip embedded unit, and coordinates it with the upper circuit and functional layers and the lower heat dissipation and connection layer of the PCB, which has the following beneficial effects: 1. Significantly improved thermal performance. Due to the high thermal conductivity of the CVD diamond thin film layer, it can significantly reduce the thermal resistance in the downward heat transfer path of the SiC power chip, reduce the interface thermal resistance and the overall thermal resistance, thereby effectively reducing the chip junction temperature and improving the module power density and continuous output capability.

[0020] 2. Enhanced insulation performance and long-term reliability. By using the CVD diamond film layer as the main insulating and heat dissipation layer on its own, or by combining it with the AMB ceramic layer to form a composite insulating and heat dissipation layer, it is possible to improve the insulation stability under high-voltage conditions while enhancing the withstand voltage capability, and reduce the risk of failure caused by long-term thermal aging and partial discharge.

[0021] 3. Improved interface reliability. The CVD diamond thin film layer has a better thermal expansion matching relationship with the SiC power chip, which helps to reduce interlayer stress caused by thermal expansion mismatch, reduce failure problems such as delamination, cracking and interface fatigue, thereby improving power cycle life and long-term service reliability.

[0022] 4. System-level performance optimization. By placing the driver IC close to the SiC power chip and using vertical interconnect copper vias to achieve short-path electrical connections, parasitic parameters in the power circuit can be significantly reduced, voltage spikes and parasitic oscillations can be suppressed, switching losses can be reduced, and system operational stability can be improved. Attached Figure Description

[0023] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0024] Figure 1 This is a schematic diagram of the SiC embedded PCB structure of the present invention, which enhances heat dissipation and insulation.

[0025] Explanation of reference numerals on the accompanying drawings: 1. PCB upper circuitry and functional layers; 11. PCB cavity; 12. SiC power chip; 13. Silver sintered layer; 14. Functional copper layer; 15. Vertical interconnect copper vias; 2. SiC chip embedded unit; 3. Diamond-reinforced insulating and heat-dissipating functional layer; 31. CVD diamond thin film layer; 32. AMB ceramic layer; 33. Transition copper layer; 33a. Upper interface transition copper layer; 33b. Lower interface transition copper layer; 4. Bottom heat dissipation and connection layer; 41. Bottom copper layer; 42. System solder layer; 43. Copper heat sink. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0027] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0028] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0029] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0030] Example 1 Reference Figure 1 As shown, the structure of a SiC embedded PCB with enhanced heat dissipation and insulation in this embodiment includes: a PCB upper layer circuit and functional layer 1, a SiC chip embedded unit 2, a diamond-enhanced insulation and heat dissipation functional layer 3, and a bottom heat dissipation and connection layer 4 arranged sequentially from top to bottom. The SiC chip embedding unit 2 includes a SiC power chip 12 disposed inside the PCB cavity 11, a silver sintered layer 13 disposed on the back of the SiC power chip 12, and a functional copper layer 14 connected to the silver sintered layer 13. The functional copper layer 14 is connected to the diamond-reinforced insulating and heat-dissipating functional layer 3 through vertical interconnect copper vias 15; the front side of the SiC power chip 12 is electrically connected to the upper PCB circuitry and functional layer 1 through vertical interconnect copper vias 15. The diamond-reinforced insulating and heat-dissipating functional layer 3 includes a CVD diamond thin film layer 31, which alone constitutes the main insulating and heat-dissipating layer, or is combined with the AMB ceramic layer 32 to form a composite insulating and heat-dissipating layer.

[0031] Specifically, the SiC power chip 12 is a SiC MOSFET or SiC IGBT die.

[0032] Specifically, the upper layer circuitry and functional layer 1 of the PCB includes a top copper foil circuitry, a driver IC, and a local DC bus capacitor. The driver IC is arranged adjacent to the SiC power chip 12 to form a low parasitic switching circuit.

[0033] Specifically, the bottom heat dissipation and connection layer 4 includes a bottom copper layer 41, a system solder layer 42, and a copper heat sink 43. The bottom copper layer 41 is connected to the copper heat sink 43 through the system solder layer 42.

[0034] Specifically, the copper radiator 43 has a thickness of 3mm to 10mm and a heat transfer coefficient at the cooling end of ≥10000W / (m²·K).

[0035] The above settings solve the problems of insufficient insulation, accelerated thermal aging, and high risk of long-term failure of existing SiC embedded PCB structures under high voltage and high heat flux conditions of 800V and above, and significantly improve high voltage insulation performance and lifespan. Breaking through the thermal conduction bottleneck of existing AMB ceramic substrates, significantly reducing the interface thermal resistance and overall thermal resistance from the chip to the heat dissipation end, quickly dissipating chip hot spots, and fully releasing the high current and high frequency performance potential of SiC devices; Improve the matching of thermal expansion coefficients between SiC chips, metal layers and insulating layers, suppress interface delamination and cracking during temperature cycling and power cycling, and meet automotive and industrial-grade long-life reliability requirements. With an ultra-thin structure, it simultaneously achieves extreme heat dissipation, high insulation withstand voltage, and low parasitic parameters, significantly improving the power density of the power module and adapting to the miniaturization and high integration requirements of scenarios such as new energy vehicles and AI high-power power supplies.

[0036] Example 2 This embodiment provides a method for fabricating a SiC embedded PCB structure that enhances heat dissipation and insulation, including: S1. Pre-fabrication of diamond-reinforced insulating and heat-dissipating functional layer 3: A CVD diamond thin film layer 31 is prepared using CVD technology. Both sides of the CVD diamond thin film layer 31 are ground, polished, and surface metallized. A Ti / Cu seed layer is formed by magnetron sputtering, and a transition copper layer 33 is electroplated on the Ti / Cu seed layer. The CVD diamond thin film layer 31 alone constitutes the main insulating and heat-dissipating layer, or it can be combined with the AMB ceramic layer 32 to form a composite insulating and heat-dissipating layer, thereby forming the diamond-reinforced insulating and heat-dissipating functional layer 3. S2, Pre-fabrication of SiC chip embedded unit 2: The back side of the SiC power chip 12 is metallized, and the SiC power chip 12 is fixed on the functional copper layer 14 by silver sintering process to form a SiC chip embedded unit 2 including the SiC power chip 12, the silver sintering layer 13 and the functional copper layer 14. S3, PCB embedding and lamination: A cavity matching the SiC chip embedding unit 2 is opened on the PCB substrate, the SiC chip embedding unit 2 is embedded in the cavity, and the resin filling and multi-layer PCB stacking are completed by lamination process to form the structural basis of the upper PCB circuit and functional layer 1. S4. Vertical interconnect forming: Vertical interconnect copper vias 15 are formed by laser drilling, and copper interconnects are formed by electroplating filling process, so that the functional copper layer 14 is connected to the diamond-reinforced insulation and heat dissipation functional layer 3 through the vertical interconnect copper vias 15, and the front side of the SiC power chip 12 is electrically connected to the upper circuit and functional layer 1 of the PCB through the vertical interconnect copper vias 15. S5. Formation of the bottom heat dissipation and connection layer 4: A bottom copper layer 41 is formed below the diamond-reinforced insulating heat dissipation functional layer 3, and the bottom copper layer 41 is connected to the copper heat sink 43 through the system solder layer 42 to form the bottom heat dissipation and connection layer 4. S6. Component mounting and post-processing: Mount driver ICs and passive components on the upper circuitry and functional layer 1 of the PCB, and complete electrical connections, module assembly and testing.

[0037] In step S1, the surface metallization treatment of the CVD diamond thin film layer 31 is carried out by double-sided magnetron sputtering to sequentially form a Ti layer with a thickness of 50-200 nm and a Cu layer with a thickness of 100 nm-500 nm, and a transition copper layer 33 with a thickness of 3 μm-10 μm is electroplated on its surface.

[0038] Example 3 This embodiment features an enhanced structure with a CVD diamond thin film layer 31 on the surface of the AMB ceramic layer 32, suitable for 800V–1200V automotive platforms. This implementation scheme is a basic improvement scheme, introducing a CVD diamond thin film layer 31 to form a diamond-reinforced insulating and heat-dissipating functional layer 3 based on the existing AMB ceramic substrate process. It is compatible with existing mature mass production processes, facilitating engineering and industrial applications.

[0039] The layered structure of this implementation scheme, from top to bottom, includes: The PCB upper layer circuit and functional layer 1 includes a top copper foil circuit, a driver IC and a local DC bus capacitor. The thickness of the top copper foil circuit is 105μm. The PCB substrate layer is made of FR-4 or high Tg epoxy material, with a thickness of 200μm, and has a PCB cavity 11 inside for accommodating the SiC chip embedded unit 2. SiC chip embedding unit 2 is disposed inside the PCB cavity 11. The SiC chip embedding unit 2 includes a SiC power chip 12, a silver sintered layer 13 disposed on the back of the SiC power chip 12, and a functional copper layer 14 connected to the silver sintered layer 13. The SiC power chip 12 is a 1200V bare die with a size of 5mm×5mm. The silver sintered layer 13 has a thickness of 20μm, and the functional copper layer 14 has a thickness of 300μm. The diamond-reinforced insulating and heat-dissipating functional layer 3 includes a CVD diamond thin film layer 31 and an AMB ceramic layer 32. The CVD diamond thin film layer 31 is disposed on the upper surface of the AMB ceramic layer 32. The thickness of the CVD diamond thin film layer 31 is 10μm to 100μm, and the thermal conductivity is 800W / m·K to 2000W / m·K. It is metallurgically bonded to the upper and lower transition copper layers 33 through surface metallization treatment. The AMB ceramic layer 32 is an AMB silicon nitride ceramic layer with a thickness of 320μm, a thermal conductivity of 80W / m·K, and a breakdown field strength of 15kV / mm. The bottom heat dissipation and connection layer 4 includes a bottom copper layer 41, a system solder layer 42, and a copper heat sink 43. The bottom copper layer 41 is disposed below the AMB ceramic layer 32. The system solder layer 42 has a thickness of 200 μm, the copper heat sink 43 has a thickness of 5 mm, and the heat transfer coefficient at the cooling end is 20000 W / (m²·K).

[0040] In this embodiment, the functional copper layer 14 is connected to the diamond-enhanced insulation and heat dissipation functional layer 3 through vertical interconnect copper vias 15, and the front side of the SiC power chip 12 is electrically connected to the upper PCB circuit and functional layer 1 through vertical interconnect copper vias 15, thereby forming a SiC embedded PCB structure that takes into account low parasitic parameters, enhanced heat dissipation and insulation reliability.

[0041] Example 4 This embodiment features a diamond-ceramic composite main insulation layer structure, suitable for 1200V–3.3kV industrial platforms or energy storage platforms. This implementation uses a CVD diamond thin film layer 31 as the core insulating and heat-dissipating layer, combined with an AMB ceramic layer 32 to form a composite insulating and heat-dissipating structure. This improves insulation withstand voltage while further reducing thermal resistance, making it suitable for medium- and high-voltage, high-power applications.

[0042] The layered structure of this implementation scheme, from top to bottom, includes: The PCB upper layer circuit and functional layer 1 includes a top copper foil circuit, driving devices and passive devices, and the thickness of the top copper foil circuit is 105μm. The PCB substrate layer is made of high Tg epoxy material and has a thickness of 150μm. A PCB cavity 11 is formed inside to accommodate the SiC chip embedded unit 2. The SiC chip embedding unit 2 includes a SiC power chip 12 disposed inside the PCB cavity 11, a silver sintered layer 13 disposed on the back of the SiC power chip 12, and a functional copper layer 14 connected to the silver sintered layer 13. The SiC power chip 12 is a 1200V or 3300V SiC MOSFET die, the silver sintered layer 13 has a thickness of 20μm, and the functional copper layer 14 has a thickness of 300μm. The diamond-reinforced insulating and heat-dissipating functional layer 3 comprises, from top to bottom, an upper interface transition copper layer 33a, a CVD diamond thin film layer 31, a lower interface transition copper layer 33b, and an AMB ceramic layer 32. The upper interface transition copper layer 33a has a thickness of 5 μm, the CVD diamond thin film layer 31 has a thickness of 100 μm to 300 μm, a thermal conductivity of 800 W / m·K to 2200 W / m·K, and a breakdown field strength greater than 10 MV / cm, the lower interface transition copper layer 33b has a thickness of 5 μm, and the AMB ceramic layer 32 is a high thermal conductivity silicon nitride ceramic layer or a high thermal conductivity aluminum nitride ceramic layer with a thickness of 100 μm, used to provide insulation redundancy and structural support. The bottom heat dissipation and connection layer 4 includes a bottom copper layer 41, a system solder layer 42, and a copper heat sink 43. The bottom copper layer 41 has a thickness of 300 μm, the system solder layer 42 has a thickness of 200 μm, and the copper heat sink 43 has a thickness of 5 mm.

[0043] In this embodiment, the CVD diamond thin film layer 31 and the AMB ceramic layer 32 together constitute a composite insulating and heat dissipation layer, which can simultaneously improve the insulation withstand voltage and vertical heat conduction capacity, thereby meeting the comprehensive requirements of high insulation margin, high heat dissipation efficiency and high long-term reliability under medium and high voltage and high power conditions.

[0044] Example 5 This embodiment employs a symmetrical structure design with double-sided embedding and double-sided CVD diamond thin film, constructing insulating heat dissipation pathways on both the top and bottom sides of the SiC chip to achieve double-sided heat dissipation. Compared to a single-sided heat dissipation structure, this solution can further reduce the overall thermal resistance and parasitic parameters of the module, and significantly improve the thermal expansion matching between different materials. Therefore, it is particularly suitable for power module packaging structures under ultra-high voltage and ultra-high power density conditions.

[0045] Its stacked structure is a symmetrical design, and the core includes: a SiC chip embedded unit 2 set in the center. The upper and lower surfaces of the SiC chip are connected to the functional copper layer 14 through a silver sintering layer 13. CVD diamond thin film insulating heat dissipation layers are set on both the upper and lower sides of the SiC chip to form a symmetrical vertical heat conduction path. PCB circuit layers and copper heat sinks 43 are set on both the upper and lower sides of the structure to form a double-sided heat dissipation path. At the same time, the overall structure adopts a bonding wire-free interconnection method and achieves electrical interconnection through vertical copper vias set at the top and bottom, thereby reducing the stray inductance of the power circuit to within 0.5nH.

[0046] Example 6 This embodiment provides a method for fabricating a SiC embedded PCB structure that enhances heat dissipation and insulation, including the following steps: S1. Pre-fabrication of diamond-reinforced insulating and heat-dissipating functional layer 3: A CVD diamond thin film layer 31 is prepared using CVD technology. The CVD diamond thin film layer 31 is ground, polished, and surface metallized on both sides. A Ti / Cu seed layer is formed by magnetron sputtering, and a transition copper layer 33 is electroplated on its surface. The surface metallization treatment of the CVD diamond thin film layer 31 is carried out by double-sided magnetron sputtering to sequentially form a Ti layer with a thickness of 50nm to 200nm and a Cu layer with a thickness of 100nm to 500nm, and a transition copper layer 33 with a thickness of 3μm to 10μm is electroplated on its surface. The CVD diamond thin film layer 31 alone constitutes the main insulating and heat-dissipating layer, or it can be combined with the AMB ceramic layer 32 to form a composite insulating and heat-dissipating layer to form the diamond-reinforced insulating and heat-dissipating functional layer 3. S2, Pre-fabrication of SiC chip embedded unit 2: The back side of the SiC power chip 12 is metallized, and the SiC power chip 12 is fixed on the functional copper layer 14 by silver sintering process to form a SiC chip embedded unit 2 including the SiC power chip 12, the silver sintering layer 13 and the functional copper layer 14. S3, PCB embedding and lamination: A PCB cavity 11 matching the SiC chip embedding unit 2 is formed on the PCB substrate, the SiC chip embedding unit 2 is embedded inside the PCB cavity 11, and resin filling and multi-layer PCB stacking are completed by lamination process. S4. Vertical interconnect forming: Vertical interconnect copper vias 15 are formed by laser drilling, and copper interconnects are formed by electroplating filling process, so that the functional copper layer 14 is connected to the diamond-reinforced insulation and heat dissipation functional layer 3 through the vertical interconnect copper vias 15, and the front side of the SiC power chip 12 is electrically connected to the upper circuit and functional layer 1 of the PCB through the vertical interconnect copper vias 15. S5. Formation of the bottom heat dissipation and connection layer 4: A bottom copper layer 41 is formed below the diamond-reinforced insulating heat dissipation functional layer 3, and the bottom copper layer 41 is connected to the copper heat sink 43 through the system solder layer 42 to form the bottom heat dissipation and connection layer 4. S6. Component mounting and post-processing: Mount driver ICs and passive components on the upper circuitry and functional layer 1 of the PCB, and complete electrical connections, module assembly and testing.

[0047] Example 7 This embodiment provides a SiC embedded PCB structure for enhanced heat dissipation and insulation suitable for 800V vehicle-mounted main inverters.

[0048] Its structural parameters are as follows: In the SiC chip embedding unit 2, the SiC power chip 12 adopts Infineon 1200V CoolSiC™ Gen2p bare die, and four chips are connected in parallel to form a half-bridge switching unit. The size of a single SiC power chip 12 is 5mm×5mm; the silver sintering layer 13 has a thickness of 20μm, a sintering temperature of 250℃, and a sintering pressure of 10MPa; the functional copper layer 14 adopts a high conductivity copper layer with a thickness of 300μm.

[0049] In the diamond-reinforced insulating and heat dissipation functional layer 3, the CVD diamond thin film layer 31 has a thickness of 50μm and a thermal conductivity of 1800W / m·K, and is electroplated to form a 5μm thick transition copper layer 33 after double-sided surface metallization treatment. The AMB ceramic layer 32 is a 320μm thick silicon nitride ceramic layer with 300μm thick copper layers on the top and bottom sides. The thermal conductivity of the ceramic layer is 80W / m·K, and the breakdown field strength is 15kV / mm.

[0050] The PCB substrate corresponding to the upper layer circuit of the PCB and the functional layer 1 is made of high Tg FR-4 substrate with a thickness of 200μm, and the size of the PCB cavity 11 is matched with the half-bridge switching unit.

[0051] In the bottom heat dissipation and connection layer 4, the copper heat sink 43 has a thickness of 5mm and a heat transfer coefficient of 20000W / (m²·K) at the cooling end.

[0052] Its preparation process includes: Step 1: A 50 μm thick CVD diamond film layer 31 is prepared using microwave plasma CVD process, and the CVD diamond film layer 31 is ground and polished on both sides to make the surface roughness Ra less than 10 nm; after forming a Ti / Cu seed layer by magnetron sputtering, a 5 μm thick transition copper layer 33 is electroplated on its surface to complete the prefabrication of the diamond-reinforced insulating heat dissipation functional layer 3; Step 2: The CVD diamond thin film layer 31 and the AMB ceramic layer 32 are metallurgically bonded together by vacuum brazing to form a composite insulating and heat dissipation layer. Step 3: Perform backside metallization on the SiC power chip 12, and fix the four SiC power chips 12 onto the functional copper layer 14 by silver sintering process to form the SiC chip embedded unit 2. Step 4: A PCB cavity 11 matching the SiC chip embedding unit 2 is formed on the PCB substrate, the SiC chip embedding unit 2 is embedded inside the PCB cavity 11, and the resin filling and PCB stacking are completed by vacuum lamination process. Step 5: Vertical interconnect copper vias 15 are prepared by laser drilling, and copper interconnects are formed by electroplating. Then, the top and bottom circuits are fabricated by patterned etching. Step 6: Mount the driver IC and local DC bus capacitor on the upper circuit and functional layer 1 of the PCB, and complete the electrical connection through reflow soldering. The bottom layer is attached to the copper heat sink 43 through the system solder layer 42 to complete the module assembly.

[0053] Example 8 This embodiment provides a SiC embedded PCB structure for enhanced heat dissipation and insulation suitable for 3.3kV energy storage converters.

[0054] It is applied to the output scenarios of energy storage converters from 500kW to 1MW, using CVD diamond thin film layer 31 as the core insulating heat dissipation layer, and forming a composite insulating heat dissipation structure in conjunction with AMB ceramic layer 32.

[0055] Its structural parameters are as follows: In the SiC chip embedded unit 2, the SiC power chip 12 adopts a 3300V SiC MOSFET bare die, and 6 chips are connected in parallel to form a three-phase full-bridge switching unit. The size of a single SiC power chip 12 is 6mm×6mm, and both the front and back sides of the SiC power chip 12 are metallized. The silver sintered layer 13 has a thickness of 20μm, a sintering temperature of 260℃, and a sintering pressure of 15MPa. The functional copper layer 14 is connected to the silver sintered layer 13 to realize thermal and electrical integrated connection.

[0056] In the diamond-reinforced insulating and heat-dissipating functional layer 3, the upper interface transition copper layer 33a has a thickness of 5 μm; the CVD diamond thin film layer 31 has a thickness of 150 μm, a thermal conductivity of 2000 W / m·K, a breakdown field strength greater than 10 MV / cm, and a volume resistivity greater than 10 Ω·cm. 15 Ω·cm; the thickness of the lower interface transition copper layer 33b is 5μm; the AMB ceramic layer 32 is a 100μm thick high thermal conductivity aluminum nitride ceramic layer with a thermal conductivity of 170W / m·K; the thickness of the bottom copper layer 41 is 300μm.

[0057] The PCB substrate is made of high Tg epoxy material with a thickness of 150μm. A PCB cavity 11 matching the shape of the SiC chip embedded unit 2 is formed inside the substrate, with a dimensional tolerance of ±5μm.

[0058] In the bottom heat dissipation and connection layer 4, the copper heat sink 43 has a thickness of 8mm, a heat transfer coefficient of 25000W / (m²·K) at the cooling end, and a system solder layer 42 has a thickness of 200μm.

[0059] Its preparation process includes: Step 1: A 150 μm thick CVD diamond film layer 31 is prepared using microwave plasma CVD process, and its double sides are polished at the nanoscale to make the surface roughness Ra less than 5 nm; Ti / Cu seed layer is formed on both sides of the CVD diamond film layer 31 by magnetron sputtering, and a 5 μm thick transition copper layer 33 is formed on its surface by electroplating. Step 2: The CVD diamond thin film layer 31 and the 100μm thick AMB ceramic layer 32 are metallurgically bonded together by vacuum brazing to form a composite insulating and heat dissipation layer, with a porosity of less than 0.3% at the brazing interface; Step 3: Perform backside metallization on the 3300V SiC MOSFET die, and fix six SiC power chips 12 onto the functional copper layer 14 by silver sintering process to form SiC chip embedded unit 2. Step 4: Create a PCB cavity 11 on a high Tg epoxy material that matches the SiC chip embedding unit 2, accurately embed the SiC chip embedding unit 2 into the PCB cavity 11, and use a vacuum lamination process to complete resin filling and multilayer PCB stacking. Step 5: A vertical interconnect copper via 15 is formed by laser drilling to connect the front side of the SiC power chip 12 with the upper circuit and functional layer 1 of the PCB. The copper interconnect is achieved by electroplating and filling the via. Then, the top and bottom circuits of the PCB are fabricated by patterned etching. Step 6: The driver IC and passive components are mounted on the upper circuit and functional layer 1 of the PCB, and the electrical connection is completed by reflow soldering; the bottom layer is bonded to the copper heat sink 43 through the system solder layer 42 to complete the module assembly, high voltage insulation test and reliability screening.

[0060] In summary, compared with existing mainstream SiC embedded PCB structures, this invention achieves significant improvements in heat dissipation, insulation performance, interface reliability, and system-level integration performance, bringing substantial technological advancements and beneficial effects. Specifically: Significantly improved thermal performance (1) The interfacial thermal resistance is significantly reduced.

[0061] In implementation scheme one, the interfacial thermal resistance Rth(jc) between the chip and the substrate can be reduced from 0.02 to 0.03 K·cm² / W in the existing structure to 0.008 to 0.012 K·cm² / W, a reduction of 60% to 70%.

[0062] (2) The overall thermal resistance is significantly reduced.

[0063] The overall junction-to-shell thermal resistance Rth(jh) of the module can be reduced from 0.12–0.15 K·cm² / W in the existing structure to 0.08–0.10 K·cm² / W, a reduction of 30%–40%.

[0064] (3) The junction temperature is reduced and the power density is increased.

[0065] Under the condition of power loss of 200W / cm², the chip junction temperature can be reduced by 15℃~25℃; while keeping the chip junction temperature basically unchanged, the power density allowed by the module can be increased by 40%~50%, thereby more fully releasing the performance potential of the SiC chip.

[0066] The insulation performance and long-term reliability are significantly enhanced.

[0067] (1) The insulation withstand voltage capability is significantly improved.

[0068] With CVD diamond thin film layer 31 as the main insulating layer, the overall insulation breakdown field strength can be increased from 15kV / mm of the existing ceramic structure to the order of 10MV / cm, which increases the insulation margin of the 800V platform by more than 10 times and can be stably adapted to the 3.3kV and above high voltage platform.

[0069] (2) The aging rate slows down significantly over the long term.

[0070] Because the chip junction temperature is significantly reduced, the actual operating temperature of the insulating material decreases accordingly, its thermal aging rate can be reduced by more than 50%, and the partial discharge initiation voltage (PDIV) can be increased by more than 30%, thereby significantly extending the service life of the module under high voltage conditions.

[0071] (3) The reliability of the interface is significantly improved.

[0072] The coefficient of thermal expansion (CTE) of the CVD diamond thin film layer 31 is 0.8–2.0 ppm / K, which is closer to the CTE of 2.5 ppm / K of the SiC chip. This can reduce the interlayer thermal expansion mismatch stress by more than 70%, thereby increasing the power cycle life from 10,000 cycles in the existing structure to more than 30,000 cycles, which can meet the requirements of automotive-grade long-life applications.

[0073] System-level performance has been further optimized.

[0074] (1) Parasitic parameters are further reduced.

[0075] The stacked structure of this invention enables the near-end arrangement of the driver IC and the SiC chip, and combined with the bonding wire-free vertical copper interconnect, the stray inductance of the power circuit is reduced to less than 1nH, thereby effectively suppressing voltage spikes and parasitic oscillations during SiC switching and reducing switching losses.

[0076] (2) Power density and integration are further improved.

[0077] The CVD diamond thin film layer 31 can achieve both high insulation performance and high thermal conductivity under relatively thin conditions, and the overall thickness of the module can be reduced by more than 30%. Combined with the embedded integrated design, the module power density can reach more than 100W / cm³, which is significantly better than the existing structure level of about 60W / cm³.

[0078] (3) The total system cost has been further optimized.

[0079] This invention improves the heat dissipation performance and insulation reliability of the module, while also enabling SiC chips to operate at lower junction temperatures, thereby reducing chip derating design requirements and simplifying the heat dissipation system design, ultimately reducing the total system cost by 15% to 20%.

[0080] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A structure for a SiC embedded PCB that enhances heat dissipation and insulation, characterized in that, include: The PCB upper layer circuit and functional layer (1), SiC chip embedded unit (2), diamond reinforced insulation and heat dissipation functional layer (3), and bottom heat dissipation and connection layer (4) are arranged from top to bottom. The SiC chip embedding unit (2) includes a SiC power chip (12) disposed inside the PCB cavity (11), a silver sintered layer (13) disposed on the back of the SiC power chip (12), and a functional copper layer (14) connected to the silver sintered layer (13). The functional copper layer (14) is connected to the diamond-reinforced insulating and heat dissipation functional layer (3) through vertical interconnect copper vias (15); the front side of the SiC power chip (12) is electrically connected to the upper circuit and functional layer (1) of the PCB through vertical interconnect copper vias (15). The diamond-reinforced insulating and heat-dissipating functional layer (3) includes a CVD diamond film layer (31), which alone constitutes the main insulating and heat-dissipating layer, or is combined with the AMB ceramic layer (32) to form a composite insulating and heat-dissipating layer.

2. The structure of a SiC embedded PCB with enhanced heat dissipation and insulation according to claim 1, characterized in that, The diamond-reinforced insulating and heat-dissipating functional layer (3) includes a CVD diamond thin film layer (31) and an AMB ceramic layer (32). The CVD diamond film layer (31) is disposed on the upper surface of the AMB ceramic layer (32). The thickness of the CVD diamond film layer (31) is 10μm~100μm. The upper and lower surfaces of the CVD diamond film layer (31) are connected to the transition copper layer (33) by metallurgical bonding. The AMB ceramic layer (32) is a silicon nitride, aluminum nitride, or aluminum oxide ceramic layer with a thickness of 200μm~400μm.

3. The structure of a SiC embedded PCB with enhanced heat dissipation and insulation according to claim 1, characterized in that, The diamond-reinforced insulating and heat-dissipating functional layer (3) includes, from top to bottom, an upper interface transition copper layer (33a), a CVD diamond thin film layer (31), a lower interface transition copper layer (33b), and an AMB ceramic layer (32). The thickness of the CVD diamond thin film layer (31) is 100μm~300μm; The AMB ceramic layer (32) is a high thermal conductivity silicon nitride or aluminum nitride ceramic layer with a thickness of 50μm~150μm.

4. The structure of a SiC embedded PCB with enhanced heat dissipation and insulation according to claim 1, characterized in that, The upper and lower surfaces of the SiC chip are connected to the functional copper layer (14) through a silver sintering layer (13), and CVD diamond thin film insulating heat dissipation layers are symmetrically arranged on the upper and lower sides of the SiC chip. PCB circuit layers and heat sinks are arranged at both the upper and lower ends of the structure to form a double-sided heat dissipation path.

5. The structure of a SiC embedded PCB with enhanced heat dissipation and insulation according to claim 1, characterized in that, The SiC power chip (12) is a SiC MOSFET or SiC IGBT die.

6. The structure of a SiC embedded PCB with enhanced heat dissipation and insulation according to claim 1, characterized in that, The upper circuit and functional layer (1) of the PCB includes a top copper foil circuit, a driver IC and a local DC bus capacitor. The driver IC is arranged adjacent to the SiC power chip (12) to form a low parasitic switching circuit.

7. The structure of a SiC embedded PCB with enhanced heat dissipation and insulation according to claim 1, characterized in that, The bottom heat dissipation and connection layer (4) includes a bottom copper layer (41), a system solder layer (42), and a copper heat sink (43). The bottom copper layer (41) is connected to the copper heat sink (43) through the system solder layer (42).

8. The structure of a SiC embedded PCB with enhanced heat dissipation and insulation according to claim 7, characterized in that, The copper radiator (43) has a thickness of 3mm to 10mm and a heat transfer coefficient at the cooling end of ≥10000W / (m²·K).

9. A method for fabricating a SiC embedded PCB structure with enhanced heat dissipation and insulation, characterized in that, include: S1. Pre-fabrication of diamond-reinforced insulating and heat-dissipating functional layer (3): A CVD diamond thin film layer (31) is prepared by CVD process. The two sides of the CVD diamond thin film layer (31) are ground, polished and surface metallized. A Ti / Cu seed layer is formed by magnetron sputtering, and a transition copper layer (33) is electroplated on the Ti / Cu seed layer. The CVD diamond thin film layer (31) alone constitutes the main insulating and heat-dissipating layer, or it is combined with the AMB ceramic layer (32) to form a composite insulating and heat-dissipating layer, so as to form the diamond-reinforced insulating and heat-dissipating functional layer (3). S2, SiC chip embedding unit (2) prefabrication: The back side of the SiC power chip (12) is metallized and the SiC power chip (12) is fixed on the functional copper layer (14) by silver sintering process to form a SiC chip embedding unit (2) including the SiC power chip (12), the silver sintering layer (13) and the functional copper layer (14). S3, PCB embedding and lamination: A cavity matching the SiC chip embedding unit (2) is opened on the PCB substrate, the SiC chip embedding unit (2) is embedded in the cavity, and the resin filling and multi-layer PCB stacking are completed by lamination process to form the structural basis of the upper PCB circuit and functional layer (1). S4, Vertical interconnect forming: Vertical interconnect copper vias (15) are formed by laser drilling, and copper interconnects are formed by electroplating filling process, so that the functional copper layer (14) is connected to the diamond reinforced insulation and heat dissipation functional layer (3) through the vertical interconnect copper vias (15), and the front side of the SiC power chip (12) is electrically connected to the upper circuit and functional layer (1) of the PCB through the vertical interconnect copper vias (15). S5. Formation of the bottom heat dissipation and connection layer (4): A bottom copper layer (41) is formed below the diamond-reinforced insulating heat dissipation functional layer (3), and the bottom copper layer (41) is connected to the copper heat sink (43) through the system solder layer (42) to form the bottom heat dissipation and connection layer (4). S6. Component mounting and post-processing: Mount driver ICs and passive components on the upper circuit and functional layer (1) of the PCB, and complete electrical connections, module assembly and testing.

10. A method for fabricating a SiC embedded PCB structure with enhanced heat dissipation and insulation according to claim 9, characterized in that, In step S1, the surface metallization treatment of the CVD diamond thin film layer (31) is carried out by double-sided magnetron sputtering to sequentially form a Ti layer with a thickness of 50-200 nm and a Cu layer with a thickness of 100 nm-500 nm, and a transition copper layer (33) with a thickness of 3 μm-10 μm is electroplated on its surface.

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