Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate having a plurality of active regions, wherein each of the plurality of active regions extends longitudinally in a first direction; and an isolation film disposed on the substrate and defining each of the plurality of active regions. Each of the plurality of active regions includes: a first extension and a second extension, opposite to each other in the first direction; and a connection portion connecting the first extension and the second extension, and having a varying width in a second direction perpendicular to the first direction. The maximum width of each of the first extension and the second extension in the second direction is greater than the minimum width of the connection portion in the second direction.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0194327, filed with the Korean Intellectual Property Office on December 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor memory devices. Background Technology

[0004] As semiconductor devices become increasingly integrated, individual circuit patterns are also miniaturized, allowing for a greater number of semiconductor devices to be implemented within the same area. With the increasing integration density of semiconductor devices, the design rules for semiconductor device components are also simplified.

[0005] In highly scaled semiconductor devices, the process of forming multiple wirings and multiple buried contacts (BCs) between the wirings is becoming increasingly complex and challenging. Summary of the Invention

[0006] The purpose of this disclosure is to provide semiconductor memory devices that can improve reliability and performance.

[0007] The purposes of this disclosure are not limited to those described above, and other purposes not expressly stated will be clearly understood by those skilled in the art based on the following description.

[0008] According to one aspect of this disclosure, a semiconductor memory device includes: a substrate having a plurality of active regions, wherein each of the plurality of active regions extends longitudinally in a first direction; and an isolation film disposed on the substrate and defining each of the plurality of active regions. Each of the plurality of active regions includes: a first extension and a second extension, opposite to each other in the first direction; and a connecting portion connecting the first extension and the second extension, and having a varying width in a second direction perpendicular to the first direction. The maximum width of each of the first extension and the second extension in the second direction is greater than the minimum width of the connecting portion in the second direction.

[0009] According to one aspect of this disclosure, a semiconductor memory device includes: a substrate having a plurality of active regions, wherein each of the plurality of active regions extends longitudinally in a first direction. Each of the plurality of active regions includes: a first extension and a second extension, opposite to each other in the first direction; and a connecting portion connecting the first extension to the second extension, and having a varying width in a second direction perpendicular to the first direction. The connecting portion includes a first portion connected to the first extension, a second portion connected to the second extension, and a third portion between the first portion and the second portion. The width of the third portion in the second direction is greater than the width of each of the first portion and the second portion.

[0010] According to one aspect of this disclosure, a semiconductor memory device includes: a substrate having a plurality of active regions, wherein each of the plurality of active regions has a long axis in a first direction and a short axis in a second direction perpendicular to the first direction; an isolation film disposed on the substrate and defining each of the plurality of active regions; a plurality of word lines disposed within the substrate and extending in a third direction; a plurality of bit lines disposed on the substrate and extending in a fourth direction perpendicular to the third direction; and a plurality of data storage patterns on the substrate. Each of the plurality of active regions includes: a first extension and a second extension, opposite to each other in the first direction; and a connection portion connecting the first extension to the second extension and having a varying width in the second direction. When viewed in a plan view, each of the first extension and the second extension has a semicircle. At the boundary between the first extension and the connection portion, the width of the first extension in the second direction is greater than the width of the connection portion in the second direction. At the boundary between the second extension and the connection portion, the width of the second extension in the second direction is greater than the width of the connection portion in the second direction. For the first active region among multiple active regions, two corresponding data storage patterns among multiple data storage patterns are electrically connected to the first extension and the second extension of the first active region.

[0011] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will become apparent from the following description. Attached Figure Description

[0012] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1 It is a layout diagram of a semiconductor memory device according to some embodiments;

[0014] Figure 2 It shows Figure 1 The layout diagram of the active region, the first isolation membrane, and the second isolation membrane in the diagram;

[0015] Figure 3 It is along Figure 1 A cross-sectional view taken from line AA;

[0016] Figure 4 It is along Figure 1 A cross-sectional view of line BB;

[0017] Figure 5 It is a layout diagram of a semiconductor memory device according to some embodiments;

[0018] Figure 6 It is along Figure 5 A cross-sectional view of line BB;

[0019] Figures 7 to 18 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to some embodiments;

[0020] Figures 19 to 21 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0021] Figure 1 This is a layout diagram of a semiconductor memory device according to some embodiments. Figure 2 It shows Figure 1 The layout diagram of the active region, the first isolation membrane, and the second isolation membrane. Figure 3 It is along Figure 1 The cross-sectional view taken from line AA. Figure 4 It is along Figure 1 The cross-sectional view of line BB.

[0022] The accompanying drawings of some embodiments of semiconductor memory devices have been described using dynamic random access memory (DRAM) as an example, but this disclosure is not limited thereto.

[0023] refer to Figure 1 and Figure 2 According to some embodiments, a semiconductor memory device includes an active region 10 and isolation films (105 and 106).

[0024] Figure 3 and Figure 4 The substrate 100 may have an active region 10, which may be defined by isolation films 105 and 106. Isolation films 105 and 106 may be formed on... Figure 3 and Figure 4The active region 10 is located within the substrate 100. In an embodiment, the active region 10 may include active fins. The active fins may be formed by partially etching the substrate 100, or epitaxially formed from the substrate 100. As the design rules of semiconductor memory devices according to some embodiments decrease, as shown, the active regions 10 may be arranged diagonally or in a stripe shape. For example, the active regions 10 may extend longitudinally in a first direction D1. The active regions 10 may be spaced apart from each other.

[0025] The fourth direction D4 can be orthogonal to the third direction D3. The second direction D2 can be orthogonal to the first direction D1. The first direction D1 can be the direction between the third direction D3 and the fourth direction D4. The fifth direction D5 can be orthogonal to the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4. The fifth direction D5 can be perpendicular to the upper surface of the substrate 100. The upper and lower surfaces can be defined based on the fifth direction D5. For example, the first directions D1 to the fourth direction D4 can be in the same plane, and the fifth direction D5 can be perpendicular to that plane.

[0026] Each active region in the active region 10 includes a first extension 31, a second extension 32, and a connecting part 20 connected sequentially along the first direction D1.

[0027] The first extension portion 31 and the second extension portion 32 are opposite ends of the corresponding active region 10 in the first direction D1. The first extension portion 31 and the second extension portion 32 may be convex in the first direction D1. From a planar viewpoint (e.g., from the viewpoint of a plane including the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4) (i.e., when viewed from a plan view), the first extension portion 31 and the second extension portion 32 may be semi-circular. For example, when viewed from a plan view, the circumferential surface of the first extension portion 31 may be connected to the isolation membrane 105 (i.e., the first pair of first isolation membranes 105A) and may be semi-circular. Similarly, when viewed from a plan view, the circumferential surface of the second extension portion 32 may be connected to the isolation membrane 105 (i.e., the second pair of first isolation membranes 105B) and may be semi-circular.

[0028] The connecting portion 20 connects the first extension portion 31 and the second extension portion 32. At the boundary between the connecting portion 20 and the first extension portion 31, the width of the first extension portion 31 in the second direction D2 is greater than the width of the connecting portion 20 in the second direction D2. Similarly, at the boundary between the connecting portion 20 and the second extension portion 32, the width of the second extension portion 32 in the second direction D2 is greater than the width of the connecting portion 20 in the second direction D2.

[0029] The connecting part 20 may include a main body 26, a first extension 27, and a second extension 28.

[0030] The main body 26 may extend in a first direction D1. The main body 26 may have a stripe extending longitudinally in the first direction D1. The main body 26 may have an elongated island shape, including a major axis and a minor axis. The main body 26 may have an inclined shape, forming an angle of less than 90 degrees with the letter line WL extending in a third direction D3. The major axis of the main body 26 may extend in the first direction D1, and the minor axis of the main body 26 may extend in a second direction D2.

[0031] The first extension 31 can be connected to the first end of the main body 26 in the first direction D1, and the second extension 32 can be connected to the second end of the main body 26 opposite to the first end in the first direction D1.

[0032] The first extension 27 may extend along at least a portion of a first side of the body 26 in the second direction D2. The second extension 28 may extend along at least a portion of a second side of the body 26 (opposite to the first side) in the second direction D2. The first extension 27 and the second extension 28 may be spaced apart from the first extension 31 and the second extension 32. A portion of the first extension 27 may overlap with a portion of the second extension 28 in the second direction D2. The first extension 27 may include a portion that overlaps with the second extension 28 in the second direction D2, and a portion that does not overlap with the second extension 28 in the second direction D2. The second extension 28 may include a portion that overlaps with the first extension 27 in the second direction D2, and a portion that does not overlap with the first extension 27 in the second direction D2.

[0033] The opposite sides of each of the first extension 27 and the second extension 28 in the first direction D1 may be circular. The width of each of the first extension 27 and the second extension 28 in the first direction D1 may increase as it moves away from the main body 26.

[0034] The connecting portion 20 includes a first portion 21, a second portion 22, a third portion 23, a fourth portion 24, and a fifth portion 25. The first portion 21 can be connected to the first extension portion 31. For example, the first portion 21 may correspond to the portion of the connecting portion 20 between the first pair of first insulating membranes 105A in the second direction D2. The second portion 22 can be connected to the second extension portion 32. For example, the second portion 22 may correspond to the portion of the connecting portion 20 between the second pair of first insulating membranes 105B in the second direction D2. The third portion 23 may be disposed between the first extension portion 31 and the second extension portion 32. The fourth portion 24 can connect the first portion 21 and the third portion 23. The fifth portion 25 can connect the second portion 22 and the third portion 23. The first pair of first insulating membranes 105A may include a first first insulating membrane 105A1 and a second first insulating membrane 105A2. The fourth portion 24 may correspond to the portion of the connecting portion 20 in the second direction D2 between the first first isolation membrane 105A1 and the second isolation membrane 106 (e.g., the second second isolation membrane 106B, which will be described below). The second pair of isolation membranes 105B may include the first second isolation membrane 105B1 and the second second isolation membrane 105B2. The fifth portion 25 may correspond to the portion of the connecting portion 20 in the second direction D2 between the first second isolation membrane 105B1 and the second isolation membrane 106 (e.g., the fourth second isolation membrane 106D, which will be described below). The third portion 23 disposed in the first direction D1 between the fourth portion 24 and the fifth portion 25 may correspond to the portion of the connecting portion 20 in the second direction D2 between the two opposing portions of the second isolation membrane 106 (e.g., the second second isolation membrane 106B and the fourth second isolation membrane 106D).

[0035] That is, the first part 21, the fourth part 24, the third part 23, the fifth part 25, and the second part 22 can be connected sequentially along the first direction D1. The first part 21 and the second part 22 can form the first part and the second part of the main body 26. The third part 23 can include the third part of the main body 26, the first part of the first extension 27, and the first part of the second extension 28. The first part of the first extension 27 and the first part of the second extension 28 can overlap each other in the second direction D2. The fourth part 24 can include the fourth part of the main body 26 and the second part of the second extension 28, which overlap each other in the second direction D2. The fifth part 25 can include the fifth part of the main body 26 and the second part of the first extension 27, which overlap each other in the second direction D2.

[0036] In the second direction D2, the maximum width W21 of the first extension 31 and the maximum width W22 of the second extension 32 are greater than the width W11 of the first portion 21 and the width W12 of the second portion 22. In the second direction D2, the width W13 of the third portion 23 is greater than the widths W11 and W12 of the first portion 21 and the second portion 22. In the second direction D2, the width W13 of the third portion 23 is also greater than the widths W14 of the fourth portion 24 and W15 of the fifth portion 25. In the second direction D2, the widths W14 and W15 of the fourth portion 24 and the fifth portion 25 are greater than the widths W11 and W12 of the first portion 21 and the second portion 22. Additionally, in the second direction D2, the maximum widths W21 and W22 of the first extension 31 and the second extension 32 are greater than the minimum width of the connecting portion 20 (e.g., W11 and / or W12).

[0037] Isolation films (105 and 106) can be formed within the substrate 100. Isolation films (105 and 106) can have a shallow trench isolation (STI) structure, which can provide excellent device isolation characteristics. Isolation films (105 and 106) can define an active region 10 within the memory cell region.

[0038] The isolation membranes (105 and 106) may include a first isolation membrane 105 and a second isolation membrane 106. For example, each active region may be defined by four first isolation membranes 105 and four second isolation membranes 106. Each of the four first isolation membranes 105 and each of the four second isolation membranes 106 may be alternately connected in a counterclockwise direction to define the active region. For each active region, the four first isolation membranes 105 may include a first first isolation membrane 105A1, a second first isolation membrane 105A2, a first second isolation membrane 105B1, and a second second isolation membrane 105B2 arranged in a counterclockwise direction; and the four second isolation membranes 106 may include a first second isolation membrane 106A, a second second isolation membrane 106B, a third second isolation membrane 106C, and a fourth second isolation membrane 106D arranged in a counterclockwise direction. In an embodiment, the first first isolation membrane 105A1 and the first second isolation membrane 105B1 may have the same shape, and the second first isolation membrane 105A2 and the second second isolation membrane 105B2 may have the same shape. The length of each of the first isolation membrane 105A1 and the first second isolation membrane 105B1 in the first direction D1 may be greater than the length of each of the second first isolation membrane 105A2 and the second second isolation membrane 105B2 in the first direction D1. In an embodiment, the first second isolation membrane 106A, the second second isolation membrane 106B, the third second isolation membrane 106C, and the fourth second isolation membrane 106D may have the same shape. Each of the first second isolation membrane 106A, the second second isolation membrane 106B, the third second isolation membrane 106C, and the fourth second isolation membrane 106D may be shared by four adjacent active regions, and therefore can be interchanged depending on which of the four active regions is referenced. For example, the second second isolation membrane 106B of a particular active region may be referred to as the first second isolation membrane 106 of the active region adjacent to it and sharing the first second isolation membrane 105B1.

[0039] The first separator 105 may include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second separator 106 may include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In embodiments, the first separator 105 and the second separator 106 may be formed of the same insulating material. For example, the first separator 105 and the second separator 106 may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. This disclosure is not limited thereto. For example, the insulating material of the first separator 105 may be different from the insulating material of the second separator 106. In some embodiments, each of the second separators 106 may be a single layer. This disclosure is not limited thereto. In embodiments, each of the second separators 106 may include two or more layers, such as... Figure 5 As shown, this will be described later.

[0040] The opposing side surfaces of the main body 26 of the active region 10 in the second direction D2 may be defined by a first isolation membrane 105. For example, a first pair of first isolation membranes 105A and a second pair of first isolation membranes 105B may protrude into the interior of the active region 10. The side surfaces of the first isolation membrane 105A1 extending in the first direction D1, the side surfaces of the second isolation membrane 105B2 extending in the first direction D1, and a first imaginary line connecting the side surfaces of the first isolation membrane 105A1 and the side surfaces of the second isolation membrane 105B2 and extending in the first direction D1 may constitute the first side surface of the main body 26. In an embodiment, the first imaginary line, the side surfaces of the first isolation membrane 105A1 and the second isolation membrane 105B2 may be aligned along a straight line extending in the first direction D1. The side surface of the second first isolation membrane 105A2 extending in the first direction D1, the side surface of the first second isolation membrane 105B1 extending in the first direction D1, and a second imaginary line connecting the side surfaces of the second first isolation membrane 105A2 and the first second isolation membrane 105B1 and extending in the first direction D1 can constitute the second side surface of the body 26, which is opposite to the first side surface of the body 26 in the second direction D2. In an embodiment, the second imaginary line, the side surface of the second first isolation membrane 105A2, and the side surface of the first second isolation membrane 105B1 can be aligned along a straight line extending in the first direction. The opposing side surfaces of the first extension 27 of the active region 10 in the first direction D1 can be defined by the first isolation membrane 105 (e.g., the first first isolation membrane 105A1 and the second second isolation membrane 105B2). The opposing side surfaces of the second extension 28 of the active region 10 in the first direction D1 may also be defined by a first isolation membrane 105 (e.g., a second first isolation membrane 105A2 and a first second isolation membrane 105B1). The side surfaces of the first extension 27 of the active region 10 in the second direction D2 and the side surfaces of the second extension 28 of the active region 10 in the second direction D2 may be defined by a second isolation membrane 106. For example, in each active region 10, the side surface of the first extension 27 may be defined by a second isolation membrane 106 (e.g., a fourth second isolation membrane 106D), and the side surface of the second extension 28 may be defined by a second isolation membrane 106 (e.g., a second second isolation membrane 106B). The first extension 31 and the second extension 32 of the active region 10 may be defined by a first isolation membrane 105 and a second isolation membrane 106. In each active region 10, the first extension 31 may be defined by a first second isolation membrane 106A and a first pair of first isolation membranes 105A, and the second extension 32 may be defined by a third second isolation membrane 106C and a second pair of first isolation membranes 105B.

[0041] Multiple gate electrodes can be provided extending through the active region 10 in the third direction D3. These gate electrodes can extend parallel to each other. For example, the multiple gate electrodes can correspond to multiple word lines WL. The word lines WL can be arranged at regular intervals along the fourth direction D4. The width of the word lines WL and the spacing between them can be determined according to design rules. From a planar perspective (e.g., from a plane including the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4), the word lines WL can be spaced apart from the first extension 31 and the second extension 32 of the active region 10.

[0042] Each active region 10 can be divided into three parts by two word lines WL extending on the third direction D3. Each active region 10 can include a memory connection region and a bit line connection region. The bit line connection region can be located at the central portion of the corresponding active region 10, while the memory connection regions can be located at opposite ends of the corresponding active region 10. The bit line connection region can include at least a portion of the third portion 23 and / or the fourth portion 24 of the corresponding active region 10, and at least a portion of the fifth portion 25 of the corresponding active region 10; while the memory connection region can include at least a portion of the first extension 31 and / or the first portion 21 of the corresponding active region 10, and at least a portion of the second extension 32 and / or the second portion 22 of the corresponding active region 10.

[0043] For example, a bit line connection area can correspond to a region connected to a bit line BL, while a storage connection area can correspond to a region connected to a data storage pattern ( Figure 3 and Figure 4 The bit line connection region corresponds to the common drain region, and the memory connection region corresponds to the source region. Each word line WL and its adjacent bit line connection region and memory connection region can form a transistor.

[0044] Multiple bit lines BL can be set above the word line WL, extending in a fourth direction D4 perpendicular to the word line WL. The bit lines BL can extend parallel to each other. The bit lines BL can be arranged at regular intervals along a third direction D3. The width of the bit lines BL and the spacing between the bit lines BL can be determined according to design rules.

[0045] According to some embodiments, a semiconductor memory device may include various contact arrangements formed on an active region 10. These various contact arrangements may include, for example, direct contacts DC, buried contacts BC, and bonding pads LP.

[0046] The direct contact DC can refer to the contact that electrically connects the active region 10 to the bit line BL. The buried contact BC can refer to the contact that connects the active region 10 to the lower electrode of the data storage pattern 190. Figure 3The contact portion BC is buried. Due to the arrangement of the contact portion BC and the active region 10, the contact area between them may be small. Accordingly, a conductive bonding pad LP can be introduced to increase the contact area between the active region 10 and the lower electrode 191 of the data storage pattern 190.

[0047] The bonding pad LP can be disposed between the active region 10 and the buried contact BC, or between the buried contact BC and the lower electrode 191 of the data storage pattern 190. In a semiconductor memory device according to some embodiments, the bonding pad LP can be disposed between the buried contact BC and the lower electrode 191 of the data storage pattern 190. By introducing the bonding pad LP, the contact area can be increased and the contact resistance between the active region 10 and the lower electrode of the capacitor can be reduced.

[0048] The direct contact DC can be connected to the bit line connection area of ​​the active region 10. The buried contact BC can be connected to the memory connection area of ​​the active region 10. Since the buried contact BC is located at opposite ends of the active region 10 (e.g., the first extension 31 and / or the first portion 21, and the second extension 32 and / or the second portion 22), the bonding pad LP can be located near opposite ends of the active region 10 and partially overlap with the buried contact BC. The buried contact BC can overlap with the active region 10 and the isolation films (105 and 106) between adjacent word lines WL and between adjacent bit lines BL.

[0049] In a semiconductor memory device according to some embodiments, a buried contact BC may be connected to a relatively wide first extension 31 and second extension 32 of the active region 10. For example, the first extension 31 and the second extension 32 may include opposite ends of a conventional active region and additional regions epitaxially grown from opposite ends of the conventional active region, which will refer to... Figure 13 The following discussion will be conducted. Compared to a conventional active region, the first extension 31 and the second extension 32 can provide a larger contact area for the buried contact portion BC. Compared to a conventional active region, the buried contact portion BC can contact the relatively wide first extension 31 and second extension 32 of the active region 10. Therefore, the contact area between the buried contact portion BC and the active region 10 can be increased, thereby providing a storage device with improved reliability.

[0050] The word line WL can be formed to be buried within the substrate 100. The word line WL can extend through the active region 10 between the direct contacts DC, or it can extend through the active region 10 between the buried contacts BC. As shown, two word lines WL can extend through a single active region 10. Since the active region 10 extends in the first direction D1, the word line WL can form an angle of less than 90 degrees with the active region 10.

[0051] The direct contact portion DC and the buried contact portion BC can be arranged symmetrically. Therefore, the direct contact portion DC and the buried contact portion BC can be arranged in a straight line extending along the third direction D3 and the fourth direction D4. Conversely, the bonding pad LP can be arranged in a zigzag pattern along the fourth direction D4 extending along the bit line BL. Additionally, along the third direction D3 extending along the word line WL, the bonding pad LP can overlap with the same side of the corresponding bit line BL.

[0052] For example, the first row of contact pads LP can overlap with the left side of the corresponding bit line BL, while the second row of contact pads LP can overlap with the right side of the corresponding bit line BL.

[0053] refer to Figures 1 to 4 According to some embodiments, a semiconductor memory device may include an active region 10, a plurality of gate structures 110, a plurality of conductive lines 140, a plurality of memory pads 160, and a data storage pattern 190.

[0054] The substrate 100 may be a silicon (Si) substrate or silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0055] exist Figure 3 In the diagram, the upper surfaces of the separators (105 and 106) and the upper surface of the substrate 100 are shown as being in the same plane, but are not limited to this. Due to manufacturing process considerations, Figure 3 The height of the upper surface of the shown isolation membranes (105 and 106) may be related to Figure 4 The differences are shown.

[0056] exist Figure 3 In the diagram, the second isolation film 106 is shown to be formed on the upper surface of the first isolation film 105, but is not limited thereto. Alternatively, the second isolation film 106 may not be formed on the upper surface of the first isolation film 105, and the upper surface of the first isolation film 105 may be located in the same plane as the upper surface of the substrate 100.

[0057] In the fifth direction D5, the depth of the first isolation membrane 105 may be different from the depth of the second isolation membrane 106. The lowest surface of the first isolation membrane 105 may be located on a different plane from the lowest surface of the second isolation membrane 106. The lowest surface of the first isolation membrane 105 may be located below the lowest surface of the second isolation membrane 106.

[0058] The gate structure 110 may be formed within the substrate 100 and the isolation films (105 and 106). The gate structure 110 may be formed on the active region 10 defined by the isolation films (105 and 106).

[0059] The gate structure 110 may extend in the third direction D3. The gate structures 110 may be spaced apart from each other in the fourth direction D4.

[0060] The gate structure 110 may each include a gate trench 115, a gate insulating film 111, a gate electrode 112, a gate capping pattern 113, and a gate capping conductive film 114 formed in the substrate 100 and the isolation films (105 and 106). The gate electrode 112 of the gate structure 110 may correspond to the word line WL.

[0061] The gate trench 115 of the gate structure 110 can be disposed within the substrate 100 and the isolation films (105 and 106). The gate trench 115 can be arranged across the active region 10. The gate trench 115 can extend longitudinally in the third direction D3.

[0062] The bottom surface of the gate trench 115 may be curved. The gate trench 115 may be relatively deep within the isolation films (105 and 106) and relatively shallow within the active region 10. For example, the depth of the gate trench 115 within the isolation films (105 and 106) may be greater than its depth within the active region 10. The lowermost end of the gate trench 115 formed in the isolation films (105 and 106) may be lower than the lowermost end of the gate trench 115 formed in the active region 10.

[0063] A portion of the gate trench 115 may be formed within the first isolation film 105, while other portions of the gate trench 115 may be formed within the second isolation film 106. One side surface and a portion of the bottom surface of each gate trench in the gate trench 115 may be defined by the first isolation film 105, and the other side surface and the remaining bottom surface of each gate trench in the gate trench 115 may be defined by the second isolation film 106.

[0064] In an embodiment, the bottom surface of the gate trench 115 in the first isolation membrane 105 and the bottom surface of the gate trench 115 in the second isolation membrane 106 may be located on different planes.

[0065] The bit line connection region of the active region 10, the memory connection region of the active region 10, and the gate electrode 112 of the gate structure 110 can form a buried channel transistor.

[0066] The gate insulating film 111 of the gate structure 110 may extend along the sidewalls and bottom surface of the gate trench 115. The gate insulating film 111 may extend along at least a portion of the contour of the gate trench 115.

[0067] The gate insulating film 111 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material with a dielectric constant greater than that of silicon oxide. Examples of high-k dielectric materials may include hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

[0068] The gate electrode 112 can be disposed on the gate insulating film 111. The gate electrode 112 can partially fill the gate trench 115.

[0069] The gate cap conductive film 114 may extend along the upper surface of the gate electrode 112. In a semiconductor memory device according to some embodiments, the gate cap conductive film 114 may cover the entire upper surface of the gate electrode 112.

[0070] The gate electrode 112 may include at least one of the following: doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional (2D) material, metal, and metal alloy. The gate capping conductive film 114 may include, for example, polysilicon or polysilicon-germanium, but is not limited thereto.

[0071] A gate capping pattern 113 of the gate structure 110 may be disposed on the gate electrode 112 and the gate capping conductive film 114. The gate capping pattern 113 may fill the remaining portion of the gate trench 115 after the gate electrode 112 and the gate capping conductive film 114 are formed. The gate insulating film 111 is shown extending along the sidewall of the gate capping pattern 113, but is not limited thereto.

[0072] The gate cap pattern 113 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0073] Although not shown, an impurity-doped region may be formed on at least one side of the gate structure 110. The impurity-doped region may correspond to the source / drain regions of the transistor. The impurity-doped region may be formed in the memory connection region and the bit line connection region.

[0074] Bit line structure 140ST may each include a conductive line 140 and a wire capping film 144. The conductive line 140 of bit line structure 140ST may extend in a fourth direction D4. The conductive line 140 may intersect with the active region 10 defined by the isolation films (105 and 106). The conductive line 140 may correspond to the bit line BL.

[0075] Conductive lines 140 may include at least one of, for example, doped semiconductor materials, conductive silicide compounds, conductive metal nitrides, two-dimensional materials, and metals. In some embodiments of the semiconductor memory device, the two-dimensional (2D) material may be a metallic material or a semiconductor material. 2D materials may include, but are not limited to, 2D allotropes or 2D compounds, such as at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). That is, the above-described 2D materials are merely examples and do not limit the types of 2D materials that may be included in the semiconductor memory device according to some embodiments.

[0076] The conductive line 140 can be single-layered or double-layered. Alternatively, as shown in the figure, the conductive line 140 can be multi-layered, with each layer including a first conductive line 141, a second conductive line 142, and a third conductive line 143. The conductive line 140 is depicted as three layers, but is not limited thereto. That is, the conductive line 140 can comprise a single layer or a stack of multiple conductive layers.

[0077] A wire capping film 144 of the bitline structure 140ST can be disposed on the conductive line 140. The wire capping film 144 can extend along the upper surface of the conductive line 140 in a fourth direction D4. Each wire capping film 144 may each include at least one of, for example, a silicon nitride film, a silicon oxynitride film, a silicon carbonitride film, and a silicon carbonitride film. In semiconductor memory devices according to some embodiments, each wire capping film 144 may each include a silicon nitride film. The wire capping film 144 is depicted as a single layer, but is not limited thereto.

[0078] The bit line contact 146 of the bit line structure 140ST can be disposed between the conductive line 140 and the substrate 100. For example, the conductive line 140 can be disposed on the bit line contact 146. For example, the bit line contact 146 can be disposed at the position where the conductive line 140 intersects with the center portion of the active region 10, and has an elongated island shape. The bit line contact 146 can be disposed between the bit line connection region of the active region 10 and the conductive line 140. The bit line contact 146 can be connected to the bit line connection region.

[0079] Multiple bit line contacts 146 can be arranged along the fourth direction D4. Conductive lines 140 can be provided on the bit line contacts 146 and can extend along the fourth direction D4.

[0080] Bit line contact 146 can electrically connect conductive line 140 to substrate 100. Bit line contact 146 can correspond to direct contact DC. Bit line contact 146 can include at least one of, for example, doped semiconductor material, conductive silicide, conductive metal nitride, and metal.

[0081] exist Figure 3In this embodiment, the thickness of the conductive line 140 in the region overlapping with the upper surface of the bit line contact portion 146 can be less than the thickness of the conductive line 140 in the region not overlapping with the upper surface of the bit line contact portion 146. In another embodiment, the thickness of the conductive line 140 in the region overlapping with the upper surface of the bit line contact portion 146 and the thickness of the conductive line 140 in the region not overlapping with the upper surface of the bit line contact portion 146 can be the same.

[0082] The cell insulating film 130 can be disposed on the substrate 100 and the isolation films (105 and 106). For example, the cell insulating film 130 can be disposed on the portions of the substrate 100 and the isolation films (105 and 106) where the bit line contacts 146 are not formed. The cell insulating film 130 can be disposed between the substrate 100 and the conductive line 140, and between the isolation films (105 and 106) and the conductive line 140. In a semiconductor memory device according to some embodiments, the upper surface of the bit line contacts 146 may be higher than the upper surface of the cell insulating film 130 relative to the upper surface of the substrate 100.

[0083] The unit insulating film 130 may be a single layer. Alternatively, as shown in the figure, the unit insulating film 130 may be multilayered, each including a first unit insulating film 131 and a second unit insulating film 132. For example, the first unit insulating film 131 may include, but is not limited to, a silicon oxide film, and the second unit insulating film 132 may include, but is not limited to, a silicon nitride film. In embodiments, each unit insulating film 130 may include three or more insulating films.

[0084] Spacers 150 can be disposed on the sidewalls of the conductive line 140 and the wire sealing film 144. In the portion of the conductive line 140 where the bit contact portion 146 is formed, spacers 150 can be formed on the substrate 100 and the isolation films (105 and 106). Spacers 150 can be disposed on the sidewalls of the conductive line 140, the sidewalls of the wire sealing film 144, and the sidewalls of the bit contact portion 146.

[0085] In the remaining portions of the conductive line 140 where the bit contact portion 146 is not formed, spacers 150 may be provided on the unit insulating film 130. Spacers 150 may be provided on the sidewalls of the conductive line 140 and the wire sealing film 144.

[0086] The spacer 150 is depicted as a single layer, but is not limited thereto. In embodiments, the spacer 150 may have a multilayer structure. The spacer 150 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, air, and combinations thereof.

[0087] A gate pattern 170 may be disposed on the substrate 100 and the isolation films (105 and 106). The gate pattern 170 may be configured to overlap with the gate structure 110 formed within the substrate 100 and the isolation films (105 and 106). The gate pattern 170 may be disposed on the gate cap pattern 113.

[0088] The fence pattern 170 may be disposed between the bit line structures 140ST and extend in the fourth direction D4. The fence pattern 170 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0089] Multiple storage contacts 120 may be disposed between adjacent conductive lines 140 in a third direction D3. Storage contacts 120 may be disposed between adjacent fence patterns 170 in a fourth direction D4. Storage contacts 120 may overlap with the substrate 100 and isolation films (105 and 106) between adjacent conductive lines 140 in a fifth direction D5. Storage contacts 120 may be connected to the storage connection area of ​​the active region 10. Storage contacts 120 may correspond to buried contacts BC.

[0090] The storage contact 120 may include at least one of, for example, a doped semiconductor material, a conductive silicide, a conductive metal nitride, and a metal.

[0091] Storage pad 160 can be disposed on storage contact 120. Storage pad 160 can be electrically connected to storage contact 120. Storage pad 160 can be connected to storage connection area of ​​active area 10. Storage pad 160 can correspond to bonding pad LP.

[0092] The storage pad 160 may overlap a portion of the upper surface of the conductive line 140. The storage pad 160 may include at least one of, for example, a doped semiconductor material, a conductive silicide, a conductive metal nitride, a conductive metal carbide, and a metal.

[0093] A pad isolation insulating film 180 can be disposed on the storage pad 160 and the conductive line 140. For example, the pad isolation insulating film 180 can be disposed on the line capping film 144. The pad isolation insulating film 180 can define the storage pad 160 by forming multiple isolation regions. The pad isolation insulating film 180 may not cover the upper surface of the storage pad 160. The pad isolation insulating film 180 may fill the pad isolation groove. The pad isolation groove can separate adjacent storage pads 160.

[0094] The pad isolation insulating film 180 may include an insulating material and may electrically isolate the storage pads 160 from each other. For example, the pad isolation insulating film 180 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride, but is not limited thereto.

[0095] An etch stop film 295 may be disposed on the upper surface of the storage pad 160 and the pad isolation insulating film 180. The etch stop film 295 may include at least one of, for example, silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonoxide, and silicon boron nitride.

[0096] Data storage pattern 190 can be disposed on storage pad 160. Data storage pattern 190 can be connected to storage pad 160. A portion of data storage pattern 190 can be disposed within etch stop film 295.

[0097] For example, the data storage pattern 190 can be a capacitor. The data storage pattern 190 can include a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193. For example, the upper electrode 193 can be a plate-shaped upper electrode.

[0098] A lower electrode 191 may be disposed on a storage pad 160. The lower electrode 191 may, for example, have a cylindrical shape. A capacitor dielectric film 192 may be disposed on the lower electrode 191. The capacitor dielectric film 192 may be formed along the contour of the lower electrode 191. An upper electrode 193 may be disposed on the capacitor dielectric film 192. The upper electrode 193 may surround the outer sidewall of the lower electrode 191. The upper electrode 193 is depicted as a single layer, but is not limited thereto. In an embodiment, the lower electrode 191 may have an open cylindrical shape.

[0099] The lower electrode 191 and the upper electrode 193 may each include, but are not limited to, at least one of the following: doped semiconductor material, conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride), metal (e.g., ruthenium, iridium, titanium or tantalum), and conductive metal oxide (e.g., iridium oxide or niobium oxide).

[0100] The capacitor dielectric film 192 may include, but is not limited to, at least one of, silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, and combinations thereof. The capacitor dielectric film 192 may include at least one of, ferroelectric, antiferroelectric, and paraelectric materials. The capacitor dielectric film 192 may include, for example, one of, the following materials: ferroelectric material, antiferroelectric material, paraelectric material, a combination of ferroelectric and antiferroelectric materials, a combination of ferroelectric and paraelectric materials, a combination of paraelectric and antiferroelectric materials, and a combination of ferroelectric, antiferroelectric, and paraelectric materials.

[0101] In a semiconductor device according to some embodiments, the capacitor dielectric film 192 may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are deposited sequentially. In a semiconductor device according to some embodiments, the capacitor dielectric film 192 may include a hafnium (Hf)-containing dielectric film.

[0102] Alternatively, the data storage pattern 190 may be a variable resistance pattern capable of switching between two resistance states in response to an electrical pulse applied to the storage element. For example, the data storage pattern 190 may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material whose crystal state changes according to the current level.

[0103] Figure 5 and Figure 6 This is a diagram used to illustrate a semiconductor memory device according to some embodiments. Figure 5 This is a diagram illustrating the active region, first isolation film, and second isolation film of a semiconductor memory device according to some embodiments. Figure 6 It is along Figure 5 The cross-sectional view of line BB. Figure 5 The line BB in the middle and Figure 1 The line BB in the middle corresponds to this.

[0104] refer to Figure 5 and Figure 6 In a semiconductor memory device according to some embodiments, the second isolation film 106 may be multilayered.

[0105] For example, the second separator 106 may each include a first membrane 106_1 and a second membrane 106_2. The second membrane 106_2 may be formed on the first membrane 106_1. The first membrane 106_1 may include trenches. The second membrane 106_2 may fill the trenches in the first membrane 106_1.

[0106] The first film 106_1 and the second film 106_2 may each include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, but are not limited thereto. In some embodiments, the first film 106_1 may include a silicon oxide film, while the second film 106_2 may include a silicon nitride film.

[0107] Figures 7 to 18 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to some embodiments. For ease of illustration, emphasis will be placed on... Figures 1 to 6 The differences in the descriptions provided. Figure 7 It shows the layout of the active region, the first isolation membrane, and the first trench. Figure 8 It is along Figure 7 The cross-sectional view taken from line AA. Figure 9 It is along Figure 7 The cross-sectional view of line BB. Figure 11 It is along Figure 10 The cross-sectional view taken from line AA. Figure 12 It is along Figure 10 The cross-sectional view of line BB. Figure 14 It is along Figure 13The cross-sectional view taken from line AA. Figure 15 It is along Figure 13 The cross-sectional view of line BB. Figure 16 It shows the layout of the active region, the first isolation membrane, and the second isolation membrane. Figure 17 It is along Figure 16 The cross-sectional view taken from line AA. Figure 18 It is along Figure 16 The cross-sectional view of line BB.

[0108] refer to Figures 7 to 9 A device isolation trench ST defining a first preliminary active region 101 can be formed within the substrate 100. The device isolation trench ST can be formed by forming a mask pattern on the substrate 100 and using the mask pattern as an etching mask to etch the substrate 100 to a predetermined depth.

[0109] The component isolation trench ST may have a first width between adjacent first preliminary active regions 101 along the first direction D1, and a second width smaller than the first width between adjacent first preliminary active regions 101 along the second direction D2. The depth of the portion of the component isolation trench ST having the first width may differ from the depth of the portion having the second width. For example, the depth of the portion of the component isolation trench ST having the first width may be greater than the depth of the portion of the component isolation trench ST having the second width.

[0110] The first preliminary active region 101 may be strip-shaped, with its major axis along the first direction D1. The first preliminary active region 101 may have a minor axis along the second direction D2. The first preliminary active region 101 may extend longitudinally along the first direction D1 and may be arranged in two dimensions along the third direction D3 and the fourth direction D4. From a planar perspective (e.g., from the perspective of a plane including the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4), the first preliminary active region 101 may be arranged in a zigzag pattern.

[0111] Subsequently, a first isolation film 105 can be formed in the component isolation trench ST. The first isolation film 105 can be formed conformally along the contour of the first preliminary active region 101 and the upper surface of the component isolation trench ST. The first isolation film 105 can be formed along the sidewalls and bottom surface of the component isolation trench ST.

[0112] A first isolation membrane 105 conformally covers the upper surface of the first preliminary active region 101 and the outline of the element isolation trench ST. A first trench TR1 may be formed within the element isolation trench ST. The first isolation membrane 105 may form the first trench TR1 between adjacent first preliminary active regions 101 along the first direction D1 and between adjacent first preliminary active regions 101 along the second direction D2. In an embodiment, the first isolation membrane 105 may fill the element isolation trench ST, and then the first trench TR1 may be formed in the first isolation membrane 105 by partially removing the first isolation membrane 105. Each first trench TR1 may be located in a region defined by four corresponding adjacent active regions (two adjacent active regions in the first direction D1 and two adjacent active regions in the second direction D2).

[0113] refer to Figures 10 to 12 An extended process can be performed to extend the first trench TR1 (see...). Figure 7 The second trench TR2 is formed by etching a portion of the first isolation film 105. In an embodiment, the upper surface of the first preliminary active region 101 may be exposed. A portion of the element isolation trench ST may also be exposed. For example, the upper surface of the etched first isolation film 105 may be lower than the upper surface of the first preliminary active region 101. In an embodiment, a portion of the first isolation film 105 may be removed by an isotropic etching process (e.g., a wet etching process). For example, the first isolation film 105 may be wet-etched to extend the first trench TR1 to the second trench TR2. Each first trench surrounded by four adjacent active regions may extend to the corresponding second trench, and the wet etching process may selectively remove the first isolation film 105 from the four adjacent first preliminary active regions. The wet etching process may have etching selectivity for the first isolation film 105 relative to the first preliminary active region 101.

[0114] A portion of the upper surface of the first isolation membrane 105 may not be on the same plane as the upper surface of the first preliminary active region 101. A portion of the upper surface of the first isolation membrane 105 may be lower than the upper surface of the first preliminary active region 101. In an embodiment, the upper surface of the first isolation membrane 105 may be on the same plane as at least a portion of the upper surface of the first preliminary active region 101.

[0115] The second trench TR2 may be defined by the first preliminary active region 101 and the first isolation film 105. For example, the second trench TR2 may be defined by the remaining portions of the first preliminary active region 101 and the first isolation film 105 after a wet etching process. The second trench TR2 may expose the opposite ends of the first preliminary active region 101 in the first direction D1. The second trench TR2 may also expose portions of the opposite sidewalls of the first preliminary active region 101 in the second direction D2.

[0116] refer to Figures 13 to 15 A second preliminary active region 102 can be epitaxially grown from the first preliminary active region 101 exposed by the second trench TR2. For example, the opposite ends of each of the first preliminary active regions 101 in the first direction D1 and a portion of each of the opposite sidewalls of the first preliminary active regions 101 in the second direction D2 can be exposed by four corresponding adjacent second trenches TR2. Accordingly, an active region 10 comprising the first preliminary active region 101 and the second preliminary active region 102 can be formed. The above-referenced... Figure 1 and Figure 2 The active region 10 is described.

[0117] refer to Figures 16 to 18 A second isolation membrane 106 can be formed to fill the second trench TR2. The upper surface of the second isolation membrane 106 can be located in the same plane as the upper surface of the active region 10. Additionally, when the upper surface of the first isolation membrane 105 is lower than the upper surface of the active region 10, the second isolation membrane 106 can be formed on the first isolation membrane 105.

[0118] Accordingly, a separator (105 and 106) comprising a first separator 105 and a second separator 106 can be formed. The upper surfaces of the separators (105 and 106) can be located in the same plane as the upper surface of the active region 10.

[0119] Subsequently, reference Figures 1 to 4 A gate structure 110 can be formed within the substrate 100 and the isolation films (105 and 106). A bit line structure 140ST can be formed on the gate structure 110. A data storage pattern 190 can be formed on the bit line structure 140ST.

[0120] To increase the contact margin between the active region 10 and the storage contact 120, it is necessary to increase the length of the active region 10 in the longitudinal direction (i.e., the first direction D1). However, increasing the length of the active region 10 in the first direction D1 may cause the corners of the active region 10 to become rounded due to the three-dimensional (3D) effect that may occur during the formation of the component isolation trench ST. Therefore, the ends of the active region 10 may be convex in the longitudinal direction, making it difficult to ensure the contact area between the active region 10 and the storage contact 120. Furthermore, increasing the length of the active region 10 in the first direction D1 may require increasing the spacing between adjacent active regions 10 in the first direction D1, which makes it challenging to form a component isolation trench ST with sufficient depth to ensure isolation between the active regions 10.

[0121] However, a method of manufacturing a semiconductor memory device according to some embodiments includes: forming a first preliminary active region 101; exposing at least a portion of the first preliminary active region 101 by an extended process; and forming a second preliminary active region 102 from the exposed first preliminary active region 101 to form an active region 10. For example, an active region 10 with an increased length in the first direction D1 can be formed without forming a device isolation trench ST, thereby increasing the length of the active region 10 in the first direction D1. Therefore, a device isolation trench ST with sufficient depth can be formed to isolate the active region 10, and as the area of ​​the opposite ends of the active region 10 increases, the contact margin between the active region 10 and the memory contact 120 can be improved.

[0122] Figures 19 to 21 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to some embodiments. Figures 19 to 21 It can represent Figures 13 to 15 The subsequent steps shown. Figure 20 It is along Figure 19 The cross-sectional view taken by line AA, and Figure 21 It is along Figure 19 The cross-sectional view of line BB.

[0123] refer to Figures 19 to 21 A first membrane 106_1 extending along the contour of the second trench TR2 can be formed. A second membrane 106_2 can fill the second trench TR2 on the first membrane 106_1. Accordingly, a second isolation membrane 106 including the first membrane 106_1 and the second membrane 106_2 can be formed. The upper surfaces of the isolation membranes (105 and 106) can be in the same plane as the upper surface of the active region 10.

[0124] Then, refer to again Figure 3 , Figure 5 and Figure 6 A gate structure 110 can be formed within the substrate 100 and the isolation films (105 and 106). A bit line structure 140ST can be formed on the gate structure 110. A data storage pattern 190 can be formed on the bit line structure 140ST.

[0125] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to these embodiments, but can be made in various other forms. Those skilled in the art will understand that the technical scope or essential features of the present disclosure can be modified and implemented in other specific forms without departing from the spirit of the invention. Therefore, the above embodiments should be understood as illustrative in all respects and not restrictive.

Claims

1. A semiconductor memory device, comprising: A substrate having a plurality of active regions, wherein each of the plurality of active regions extends longitudinally in a first direction; and An isolation film is disposed on the substrate and defines each of the plurality of active regions. Each of the plurality of active regions includes: The first extension and the second extension are opposite to each other in the first direction; and A connecting portion connects the first extension portion to the second extension portion, and has a varying width in a second direction perpendicular to the first direction. Wherein, the maximum width of each of the first extension portion and the second extension portion in the second direction is greater than the minimum width of the connecting portion in the second direction.

2. The semiconductor memory device according to claim 1, in, The connecting part includes: The main body extends longitudinally in the first direction and has a minimum width in the second direction; A first extension extends from a first side of the main body in the second direction; and The second extension extends from the second side of the main body in the second direction, and The first side and the second side extend in the first direction and are spaced apart from each other in the second direction.

3. The semiconductor memory device according to claim 2, in, The isolation membrane comprises: The first part is disposed in the space between the first extension and the first extension portion; The second part is disposed in the space between the first extension and the second expansion; The third part is disposed in the space between the first extension and the second extension; and The fourth part is disposed in the space between the second extension and the second expansion.

4. The semiconductor memory device according to claim 2, in, A portion of the first extension overlaps with a portion of the second extension in the second direction.

5. The semiconductor memory device according to claim 2, in, The isolation membrane comprises: A first insulating membrane contacts a portion of the first side of the body and a portion of the second side of the body; and The second isolation membrane is in contact with the outer wall of the first extension and the outer wall of the second extension.

6. The semiconductor memory device according to claim 5, in, The second isolation membrane is a single layer.

7. The semiconductor memory device according to claim 5, in, The second separator is multilayered.

8. The semiconductor memory device according to claim 2, in, Each of the first extension and the second extension has a convex surface.

9. The semiconductor memory device according to claim 1, further comprising: Multiple data storage patterns are on the substrate; as well as A pair of buried contacts electrically connect the first extension and the second extension to a pair of data storage patterns among the plurality of data storage patterns.

10. The semiconductor memory device according to claim 1, further comprising: Multiple bit lines are arranged in a third direction and extend in a fourth direction different from the first and second directions, wherein the multiple bit lines are disposed on the substrate, and the third direction is perpendicular to the fourth direction; and Multiple direct contact portions electrically connect the multiple bit lines to the substrate.

11. The semiconductor memory device according to claim 1, further comprising: Multiple word lines extend upward in a third direction different from the first and second directions, wherein the multiple word lines are disposed on the substrate and arranged in a fourth direction perpendicular to the third direction; Specifically, for the first active region among the plurality of active regions, two adjacent word lines among the plurality of word lines overlap with the first active region and are spaced apart from the first extension and the second extension of the first active region when viewed in a plan view.

12. A semiconductor memory device, comprising: A substrate having a plurality of active regions, wherein each of the plurality of active regions extends longitudinally in a first direction. Each of the plurality of active regions includes: The first extension and the second extension are opposite to each other in the first direction; and A connecting portion connects the first extension portion to the second extension portion, and has a varying width in a second direction perpendicular to the first direction. The connecting part includes: The first part is connected to the first extension part; The second part is connected to the second extension part; and The third part, located between the first and second parts, and The width of the third portion in the second direction is greater than the width of each of the first portion and the second portion in the second direction.

13. The semiconductor memory device according to claim 12, in, Each of the first extension and the second extension protrudes from the connecting portion in the first direction.

14. The semiconductor memory device according to claim 12, in, The maximum width of each of the first extension and the second extension in the second direction is greater than the minimum width of the connecting portion in the second direction.

15. The semiconductor memory device according to claim 12, further comprising: A pair of data storage patterns on each of the plurality of active regions of the substrate; as well as A pair of buried contacts electrically connect the first extension and the second extension to the pair of data storage patterns.

16. The semiconductor memory device of claim 12, further comprising: Multiple letter lines extend upwards in a third direction, different from the first and second directions. The plurality of word lines are disposed within the substrate and arranged in a fourth direction perpendicular to the third direction. Specifically, for the first active region among the plurality of active regions, two adjacent word lines among the plurality of word lines overlap with the first active region and are spaced apart from the first extension and the second extension of the first active region when viewed in a plan view.

17. The semiconductor memory device according to claim 12, in, The connecting part further includes: The fourth part connects the first part and the third part; and The fifth part connects the second part and the third part, and The width of each of the fourth and fifth portions in the second direction is greater than the width of each of the first and second portions in the second direction.

18. The semiconductor memory device according to claim 17, in, The width of the third portion in the second direction is greater than the width of each of the fourth and fifth portions in the second direction.

19. A semiconductor memory device, comprising: A substrate having a plurality of active regions, wherein each of the plurality of active regions has a long axis in a first direction and a short axis in a second direction perpendicular to the first direction; An isolation membrane is disposed on the substrate and defines each of the plurality of active regions; Multiple word lines are disposed within the substrate and extend upward in a third direction; Multiple bit lines are disposed on the substrate and extend in a fourth direction perpendicular to the third direction; and Multiple data storage patterns on the substrate, Each of the plurality of active regions includes: The first extension and the second extension are opposite to each other in the first direction; and A connecting portion connects the first extension portion to the second extension portion, and has a varying width in the second direction. When viewed in a plan view, each of the first extension and the second extension has a semi-circle. Wherein, at the boundary between the first extension portion and the connecting portion, the width of the first extension portion in the second direction is greater than the width of the connecting portion in the second direction. Wherein, at the boundary between the second extension and the connecting portion, the width of the second extension in the second direction is greater than the width of the connecting portion in the second direction, and Specifically, for the first active region among the plurality of active regions, two corresponding data storage patterns among the plurality of data storage patterns are electrically connected to the first extension and the second extension of the first active region.

20. The semiconductor memory device according to claim 19, in, For the first active region among the plurality of active regions, two adjacent word lines in the plurality of word lines overlap with the first active region and are spaced apart from the first extension and the second extension of the first active region when viewed in a plan view.

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