Semiconductor device including bit lines

Abstract

A semiconductor device includes a semiconductor material layer including a first channel region and a charge storage region, and extending in a first horizontal direction; a first word line vertically overlapping the first channel region and extending in a second horizontal direction; a first bit line proximate to a first end of the semiconductor material layer in the first horizontal direction, and extending in a vertical direction next to the first end; a second channel region vertically overlapping the charge storage region; and a second bit line proximate to a second end of the semiconductor material layer in the first horizontal direction, and extending in the vertical direction next to the second end. Each first bit line includes a first conductive layer and a first liner layer surrounding a side surface of the first conductive layer. The first liner layer of the first bit line contacts the first channel region, extends in the vertical direction, and includes an oxide semiconductor material.

Description

Technical Field

[0001] The present invention relates generally to a semiconductor device including bit lines. Background Technology

[0002] With the increasing demand for high performance, high speed, and / or multifunctionality in semiconductor devices, the integration level of semiconductor devices is becoming increasingly sophisticated. When manufacturing semiconductor devices with fine patterns corresponding to this trend of high integration, it is necessary to achieve patterns with fine widths or fine spacing. Summary of the Invention

[0003] One aspect of the present invention is to provide a semiconductor device including bit lines shared by adjacent memory cells.

[0004] According to one aspect of the present invention, a semiconductor device includes: semiconductor material layers extending in a first horizontal direction and spaced apart from each other in the first horizontal direction, each semiconductor material layer including a first channel region and a charge storage region; first word lines overlapping the first channel regions of the semiconductor material layers in a vertical direction and extending in a second horizontal direction intersecting the first horizontal direction; a first bit line adjacent to a first end of the semiconductor material layer in the first horizontal direction and extending in the vertical direction, the first end being adjacent to the first channel region of the semiconductor material layer; a second channel region overlapping the charge storage regions of the semiconductor material layer in the vertical direction; and a second bit line adjacent to a second end of the semiconductor material layer in the first horizontal direction and extending in the vertical direction, the second end being adjacent to the charge storage region of the semiconductor material layer. Each first bit line includes a first conductive layer and a first pad layer extending around a side surface of the first conductive layer. The first pad layer of each first bit line contacts a corresponding first channel region in the first channel region, extends in the vertical direction, and includes an oxide semiconductor material.

[0005] According to one aspect of the present invention, a semiconductor device includes: memory cells, each memory cell including a first transistor, a second transistor, and a charge storage region, the first transistor including a first channel region, the second transistor including a second channel region, the charge storage region being located at the same horizontal height as the first channel region, overlapping the second channel region in a vertical direction, and being disposed in a first horizontal direction; a first bit line extending between the memory cells in the vertical direction and electrically connected to the first transistor; and a second bit line extending between the memory cells in the vertical direction and electrically connected to the second transistor. The memory cells include first and second memory cells adjacent in the first horizontal direction. The first memory cells and the second memory cells share the first bit line. The first bit line includes a first conductive layer and a first pad layer extending around a side surface of the first conductive layer. The first pad layer extends in the vertical direction and contacts the first channel region.

[0006] According to one aspect of the present invention, a semiconductor device includes: a semiconductor material layer extending in a first horizontal direction and including a first channel region and a charge storage region; a first word line overlapping the first channel region of the semiconductor material layer in a vertical direction and extending in a second horizontal direction intersecting the first horizontal direction; a second channel region overlapping the charge storage region of the semiconductor material layer in the vertical direction; a second word line contacting the second channel region and extending in the second horizontal direction between the second channel region and the first word line; a first bit line extending in the vertical direction from one side of the first channel region of the semiconductor material layer; and a second bit line extending in the vertical direction from one side of the second channel region. Attached Figure Description

[0007] The above and other aspects, features and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a circuit diagram of a memory cell of a semiconductor device according to an example embodiment; Figure 2 This is a conceptual perspective view of a semiconductor device according to an example embodiment; Figure 3 This is a top view of a semiconductor device according to an example embodiment; Figure 4 It is along Figure 3The vertical cross-sectional views of lines I-I' and II-II' of the semiconductor device shown; Figure 5 yes Figure 4 An enlarged view of a portion of the semiconductor device shown; Figure 6 It is along Figure 3 The vertical cross-sectional view of the semiconductor device shown by line III-III'; Figure 7 It is along Figure 3 The diagram shows the vertical cross-sectional views of lines IV-IV' and V-V' of the semiconductor device. Figure 8 and Figure 9 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment; Figure 10 and Figure 11 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment; Figures 12 to 14 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment; Figure 15 This is a conceptual perspective view of a semiconductor device according to an example embodiment; and Figures 16A to 30C These are top views and vertical cross-sectional views illustrating intermediate processes in a method of manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0008] Preferred embodiments will be described below with reference to the accompanying drawings.

[0009] Figure 1 This is a circuit diagram of a memory cell of a semiconductor device according to an example embodiment. Figure 2 This is a conceptual perspective view of a semiconductor device based on an example embodiment.

[0010] refer to Figure 1 and Figure 2 Storage units MC1, MC2, MC3, MC4, MC5, and MC6 can be arranged horizontally. For example, the first storage unit MC1, the second storage unit MC2, and the third storage unit MC3 can be arranged sequentially in the X direction, and the fourth storage unit MC4, the fifth storage unit MC5, and the sixth storage unit MC6 can also be arranged sequentially in the X direction. The fourth storage unit MC4, the fifth storage unit MC5, and the sixth storage unit MC6 can be spaced apart from the first storage unit MC1, the second storage unit MC2, and the third storage unit MC3 in the Y direction, respectively. Figure 1Storage cells MC1, MC2, MC3, MC4, MC5, and MC6 are shown arranged at the same vertical height, and the storage cells can be arranged in multiple layers in the vertical direction (Z direction). The X and Y directions can be horizontal directions that intersect each other, and the Z direction can be a vertical direction perpendicular to the X and Y directions.

[0011] Each memory cell MC1, MC2, MC3, MC4, MC5, and MC6 may include a write transistor Wtr, a read transistor Rtr, and a memory node SN. The memory node SN may be used as the gate of the read transistor Rtr (e.g., a floating gate) and may be electrically connected to the write transistor Wtr. For example, the memory node SN may be electrically connected to the channel CH1 of the write transistor Wtr.

[0012] Each of the memory cells MC1, MC2, MC3, MC4, MC5, and MC6 can operate as a DRAM memory cell and may not include a capacitor. In this DRAM memory cell, write operations for storing data and read operations for retrieving data are performed. For example, each of the memory cells MC1, MC2, MC3, MC4, MC5, and MC6 can store data in the memory node SN instead of in a capacitor. Each of the memory cells MC1, MC2, MC3, MC4, MC5, and MC6 can be referred to as a 2T (dual transistor) memory cell.

[0013] The gate of the write transistor Wtr can be electrically connected to the write word line WWL extending in the Y direction. For example, the gates of the write transistors Wtr of the second memory cell MC2 and the fifth memory cell MC5 can be electrically connected to the same write word line WWL. The channel CH2 of the read transistor Rtr can be electrically connected to the read word line RWL extending in the Y direction. For example, the channel CH2 of the read transistors Rtr of the second memory cell MC2 and the fifth memory cell MC5 can be electrically connected to the same read word line RWL.

[0014] Write bit line WBL and read bit line RBL can extend vertically between memory cells MC1, MC2, MC3, MC4, MC5, and MC6. Write bit line WBL and read bit line RBL can be alternately set in the X direction. A write transistor Wtr can be selected by applying an appropriate voltage delivered by a write word line WWL and a write bit line WBL. A read transistor Rtr can be selected by applying an appropriate voltage delivered by a read word line RWL and a read bit line RBL.

[0015] According to the embodiments, since adjacent memory cells MC1, MC2, MC3, MC4, MC5, and MC6 in the X direction can share the write bit line WBL or the read bit line RBL, the size of the semiconductor device in the X direction can be reduced and the integration level of the memory cells can be improved. For example, the first memory cell MC1 and the second memory cell MC2 can share the write bit line WBL, and the second memory cell MC2 and the third memory cell MC3 can share the read bit line RBL.

[0016] According to an embodiment, adjacent memory cells MC1, MC2, MC3, MC4, MC5, and MC6 in the X direction can be symmetrically arranged about the write bit line WBL or the read bit line RBL. For example, the write transistor Wtr and read transistor Rtr of the first memory cell MC1 and the second memory cell MC2 can be symmetrically arranged about an axis perpendicular to the write bit line WBL. The write transistor Wtr and read transistor Rtr of the second memory cell MC2 and the third memory cell MC3 can be symmetrically arranged about the read bit line RBL.

[0017] The write transistor Wtr stores charge in the storage node SN. The threshold voltage of the read transistor Rtr, which acts as the gate of the storage node SN, can be changed based on the amount of charge stored in the storage node SN. Depending on the threshold voltage of the read transistor Rtr, the data stored in the storage cell can be read as either "0" or "1".

[0018] During a write operation, a programming voltage Vpgm can be applied to the write bit line WBL, and a boost voltage Vpp can be applied to the write word line WWL to store charge in the storage node SN. A second write control voltage can be applied to the read word line RWL and the read bit line RBL, and this second write control voltage can be ground voltage GND.

[0019] During a read operation, a read voltage Vread can be applied to the read word line RWL to read data from the read bit line RBL. A voltage different from the voltage on the read word line RWL can be applied to the read bit line RBL; for example, ground voltage GND can be applied. Ground voltage GND can be applied to the write bit line WBL, and a negative voltage Vbb2 can be applied to the write word line WWL.

[0020] Figure 3 This is a top view of a semiconductor device according to an example embodiment. Figure 4 It is along Figure 3 The diagram shows vertical cross-sectional views of the semiconductor device taken along lines I-I' and II-II'. Figure 5 yes Figure 4 An enlarged view of a portion of the semiconductor device shown. Figure 5 It can correspond to Figure 4 Region A in a semiconductor device. Figure 6 It is along Figure 3 The diagram shows a vertical cross-section of the semiconductor device taken from line III-III'. Figure 7 It is along Figure 3 The diagram shows a vertical cross-sectional view of the semiconductor device taken along lines IV-IV' and V-V'.

[0021] refer to Figures 3 to 7 The semiconductor device 100 according to an embodiment may include a semiconductor material layer 12, a dielectric layer 15, a first gate dielectric pattern 20, a first word line 30, a first bit line 40, a second gate dielectric pattern 50, a second word line 60, a second channel region 63, and a second bit line 70 disposed on a substrate 10. The first word line 30 may be a word line for a write operation and may be referred to as a write word line 30. The first bit line 40 may be a bit line for a write operation and may be referred to as a write bit line 40. The second word line 60 may be a word line for a read operation and may be referred to as a read word line 60. The second bit line 70 may be a bit line for a read operation and may be referred to as a read bit line 70.

[0022] The portion of the semiconductor material layer 12 that overlaps with the write word line 30 in the vertical direction can be referred to as the first channel region 13, and the portion of the semiconductor material layer 12 that overlaps with the second channel region 63 in the vertical direction can be referred to as the charge storage region 14. As used herein, “element A overlaps with element B in direction X” (or similar language) means that there is at least one line extending in direction X and intersecting both elements A and B.

[0023] refer to Figure 1 and Figure 2 The described write transistor Wtr may include a first channel region 13. The first channel region 13 may be electrically connected to the write word line 30. As may be used herein, the term "connection" (or "making a connection," or similar terms such as "contact" or "making a contact") is intended to refer to a physical connection and / or electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. The first channel region 13 may correspond to... Figure 2 The channel CH1 is defined, and the write word line 30 can correspond to the write word line WWL. The portion of the write word line 30 that overlaps with the first channel region 13 in the vertical direction can be used as the gate of the write transistor Wtr. The portion of the dielectric layer 15 located between the first channel region 13 and the write word line 30, as well as the portion of the first gate dielectric pattern 20, can be included in the write transistor Wtr.

[0024] refer to Figure 1and Figure 2 The described read transistor Rtr may include a second channel region 63. The second channel region 63 may be electrically connected to the read word line 60. The second channel region 63 may correspond to... Figure 2 The channel CH2, and the read word line 60 may correspond to the read word line RWL. The charge storage region 14 may be electrically connected to the first channel region 13 and may include a reference. Figure 1 and Figure 2 The described storage node SN. The charge storage region 14 can also be used as the gate of the read transistor Rtr. The portion of the dielectric layer 15 located between the second channel region 63 and the charge storage region 14, as well as the portion of the second gate dielectric pattern 50, can be included in the read transistor Rtr.

[0025] The first channel region 13, the write word line 30, the dielectric layer 15, the first gate dielectric pattern 20, the second channel region 63, the charge storage region 14, and the second gate dielectric pattern 50 can constitute a memory cell MC. For example, Figure 5 The components of a storage cell MC are shown. The storage cell MC may have the same features as the reference. Figure 1 and Figure 2 The described storage units MC1, MC2, MC3, MC4, MC5 and MC6 have the same or similar structure.

[0026] The semiconductor material layer 12 may extend in the X direction and may be spaced apart from each other in the X, Y, and Z directions. The semiconductor material layer 12 may include at least one of a polycrystalline semiconductor material, an oxide semiconductor material (such as indium gallium zinc oxide (IGZO)), or a two-dimensional material (such as molybdenum disulfide (MoS2)). In an embodiment, the semiconductor material layer 12 may include an oxide semiconductor material.

[0027] The oxide semiconductor material can be indium gallium zinc oxide (IGZO). However, the embodiments are not limited to this. For example, the oxide semiconductor material may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), indium zinc oxide (InZnO), and oxygen. At least one of indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), or indium gallium silicon oxide (InGaSiO).

[0028] Two-dimensional materials may include at least one of a transition metal dichalcogenide (TMD) material layer, a black phosphorus material layer, or a hexagonal boron nitride (hBN) material layer having semiconductor properties. For example, two-dimensional materials may include at least one of BiOSe, Cr1, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, or Janus 2D (two-dimensional) materials that can form two-dimensional materials.

[0029] As described above, each semiconductor material layer 12 may include a first channel region 13 and a charge storage region 14. At least a portion of the first channel region 13 may be disposed at the same horizontal height as the charge storage region 14 in the Z direction. For example, the first channel region 13 may have the same cross-sectional thickness as the charge storage region 14, and the upper and lower surfaces of the first channel region 13 may be coplanar with the upper and lower surfaces of the charge storage region 14, respectively. In an embodiment, the first channel region 13 may include the same material as the charge storage region 14 and may be integrally formed. The boundary between the first channel region 13 and the charge storage region 14 may not be observable. The first channel region 13 of each semiconductor material layer 12 may overlap with the write word line 30 in the vertical direction, and the charge storage region 14 of each semiconductor material layer 12 may overlap with the second channel region 63 in the vertical direction.

[0030] In an embodiment, the carrier density and conductivity of the charge storage region 14 may be greater than those of the first channel region 13. For example, the semiconductor material layer 12 may include an oxide semiconductor material, and the concentration of oxygen vacancies in the charge storage region 14 may be greater than the concentration of oxygen vacancies in the first channel region 13. In an embodiment, the charge storage region 14 may be doped with impurities to improve conductivity, and for example, the impurities may include fluorine (F).

[0031] The dielectric layer 15 may cover at least one of the upper and lower surfaces of the semiconductor material layer 12 and may extend in a horizontal direction. For example, both the first channel region 13 and the charge storage region 14 may be covered by the dielectric layer 15. The dielectric layer 15 may overlap the semiconductor material layer 12 in a vertical direction, and the side surfaces of the semiconductor material layer 12 may be coplanar with the side surfaces of the dielectric layer 15. The dielectric layer 15 may protect the semiconductor material layer 12 during the manufacturing process and may also be used as the gate dielectric layer of the write transistor Wtr or the read transistor Rtr. Each dielectric layer 15 may include at least one of silicon oxide or a high-k dielectric. For example, the high-k dielectric may be formed from, but is not limited to, the following materials: HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof. Each dielectric layer 15 may be formed as a single layer or multiple layers of the above materials.

[0032] The write word lines 30 can extend in the Y direction and can be spaced apart from each other in the X direction and the vertical direction (Z direction). For example, two write word lines 30 can be spaced apart from each other in the vertical direction between two adjacent semiconductor material layers 12. The X-direction length of the write word lines 30 can be less than the X-direction length of the semiconductor material layer 12. The write word lines 30 can overlap with the first channel region 13 of the semiconductor material layer 12 in the vertical direction. The write word lines 30 can be arranged in a dual-gate structure. For example, for each first channel region 13, one write word line 30 can be arranged above and below the first channel region 13. Since the write word lines 30 can be arranged in a dual-gate structure, the amount of current flowing in the first channel region 13 can be increased. In addition, electrical coupling between the write word lines 30 constituting different memory cells MC can be prevented or reduced between adjacent memory cells MC in the vertical direction.

[0033] According to an embodiment, the write word line 30 may be configured as a gate-all-around (GAA) structure surrounding the first channel region 13. The term "around" (or "perform around," or similar terms) as may be used herein is intended to generally refer to an element, structure, or layer extending around another element, structure, or layer on all sides, or wrapping, surrounding, or enclosing another element, structure, or layer, but breaks or gaps may also be present. Thus, for example, a material layer having voids or gaps may still "around" the other layer it surrounds.

[0034] The write word line 30 may include doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof. For example, at least one write word line 30 may be formed from doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotube, or a combination thereof.

[0035] The semiconductor device 100 may further include a first insulating layer 22 and a second insulating layer 24. The first gate dielectric pattern 20, the first insulating layer 22, and the second insulating layer 24 may be disposed between two vertically adjacent semiconductor material layers 12 and may contact the write word line 30. For example, the first gate dielectric pattern 20 may include a horizontal portion and a vertical portion, the horizontal portion extending horizontally while contacting the dielectric layer 15, and the vertical portion extending vertically from one end of the horizontal portion. Figure 5 As shown in the cross-sectional view, the first gate dielectric pattern 20 can have a U-shape with its opening facing the X direction. Figure 6 As shown, the first gate dielectric pattern 20 may cover the upper surface of the substrate 10. The second insulating layer 24 may be disposed between two adjacent write word lines 30 in the vertical direction and may extend in the Y direction. The first insulating layer 22 may extend between the first gate dielectric pattern 20 and the second insulating layer 24 and may contact the write word lines 30. In the cross-sectional view, the first insulating layer 22 may have a U-shape with its opening facing the X direction.

[0036] The first gate dielectric pattern 20 may include at least one of silicon oxide or a high-k dielectric. The first insulating layer 22 and the second insulating layer 24 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. The first insulating layer 22 may include a material that has etch selectivity relative to the second insulating layer 24. For example, the first insulating layer 22 may include silicon nitride, and the second insulating layer 24 may include silicon oxide.

[0037] The write bit lines 40 can extend in the vertical direction and can be spaced apart from each other in the Y direction. The write bit lines 40 can contact and be electrically connected to the vertically spaced semiconductor material layers 12. For example, the write bit lines 40 can be disposed between adjacent semiconductor material layers 12 in the X direction.

[0038] In an embodiment, each write bit line 40 may include a first conductive layer 42 and a first pad layer 44. The first conductive layer 42 may extend in a vertical direction and may have a cylindrical shape. In a top view, the first conductive layer 42 is shown as rectangular, but is not limited thereto. According to an embodiment, the first conductive layer 42 may have a circular or elliptical shape in a top view. The first pad layer 44 may surround the first conductive layer 42 (i.e., extend around the first conductive layer 42) and may extend horizontally along the side surface of the first conductive layer 42. The first pad layer 44 may contact and be electrically connected to the vertically spaced first channel regions 13. According to an embodiment, the first pad layer 44 may further extend horizontally to cover the lower surface of the first conductive layer 42.

[0039] The first conductive layer 42 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof. The first pad layer 44 may include an oxide semiconductor material. In some embodiments, the first pad layer 44 may include the same material as the semiconductor material layer 12, such as IGZO. In some embodiments, the semiconductor material layer 12 and the first pad layer 44 may include different oxide semiconductor materials. In some embodiments, the carrier density and conductivity of the first pad layer 44 may be greater than those of the first channel region 13. For example, the concentration of oxygen vacancies in the first pad layer 44 may be greater than the concentration of oxygen vacancies in the first channel region 13. In some embodiments, the indium (In) concentration of the first pad layer 44 may be higher than the indium (In) concentration of the first channel region 13.

[0040] The semiconductor device 100 may further include a capping layer 32. The capping layer 32 may be located between write word lines 30 and write bit lines 40, and between write bit lines 40 spaced apart in the Y direction. The capping layer 32 may electrically insulate the write word lines 30 and write bit lines 40. The capping layer 32 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof.

[0041] The second channel region 63 can extend in the Y direction and can be spaced apart from each other in the X direction and vertical direction. For example, two second channel regions 63 can be disposed vertically spaced between two adjacent semiconductor material layers 12 in the vertical direction. The X-direction length of the second channel region 63 can be less than the X-direction length of the semiconductor material layer 12. The second channel region 63 can be configured to be adjacent to the charge storage region 14 of the semiconductor material layer 12. For example, the second channel region 63 can overlap with the charge storage region 14 of the semiconductor material layer 12 in the vertical direction. The second channel region 63 can be configured in a dual-channel structure. For example, for each charge storage region 14, a second channel region 63 can be disposed above and below the charge storage region 14. Since the second channel region 63 can be configured in a dual-channel structure, the amount of current flowing in the charge storage region 14 can be increased. In addition, electrical coupling between the second channel regions 63 constituting different memory cells MC in the vertical direction and the charge storage region 14 can be prevented or reduced.

[0042] According to an embodiment, the second channel region 63 may be configured as a fully encircling channel structure surrounding the charge storage region 14. At least a portion of the second channel region 63 may be positioned at the same horizontal height as the write word line 30 in the Z direction. In an embodiment, the upper and lower surfaces of the second channel region 63 may be coplanar with the upper and lower surfaces of the write word line 30, respectively. The second channel region 63 may have the same vertical thickness as the write word line 30, but is not limited thereto.

[0043] The second channel region 63 may include at least one of a polycrystalline semiconductor material layer, an oxide semiconductor material (such as IGZO), or a two-dimensional material (such as MoS2). In an embodiment, the second channel region 63 may include an oxide semiconductor material.

[0044] The read word line 60 may extend in the Y direction and may be spaced apart from each other in the X direction and the vertical direction (Z direction). The read word line 60 may be disposed between the write word line 30 and the second channel region 63. For example, between two adjacent semiconductor material layers 12 in the vertical direction, two read word lines 60 may be spaced apart from each other in the vertical direction. The read word line 60 may contact the end of the second channel region 63 and may be spaced apart from the write word line 30 in the X direction. According to an embodiment, the read word line 60 may be disposed in a fully surrounding gate structure around the charge storage region 14. At least a portion of the read word line 60 may be disposed at the same horizontal height as the write word line 30 and the second channel region 63. In an embodiment, the upper and lower surfaces of the read word line 60 may be coplanar with the upper and lower surfaces of the write word line 30, respectively. The read word line 60 may have the same vertical thickness as the write word line 30 and the second channel region 63, but is not limited thereto.

[0045] The read word line 60 may include doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube or a combination thereof.

[0046] The semiconductor device 100 may further include a third insulating layer 52 and a fourth insulating layer 54. A second gate dielectric pattern 50 may extend horizontally between the dielectric layer 15 and the read word line 60, and between the dielectric layer 15 and the second channel region 63. The second gate dielectric pattern 50 may also extend vertically between the dielectric layer 15 and the read bit line 70, and between the charge storage region 14 and the read bit line 70. The second gate dielectric pattern 50 may also contact the first gate dielectric pattern 20 and may extend vertically. The second gate dielectric pattern 50 may cover the upper surface of the uppermost dielectric layer 15.

[0047] In an embodiment, a portion of the second gate dielectric pattern 50 may be integrally formed with the first gate dielectric pattern 20. For example, a portion of the second gate dielectric pattern 50 covering the upper surface of the uppermost dielectric layer 15 may be integrally formed with the first gate dielectric pattern 20.

[0048] The fourth insulating layer 54 may be disposed between two adjacent read word lines 60 in the vertical direction and between the second channel region 63, and may extend in the Y direction. The third insulating layer 52 may extend between the second gate dielectric pattern 50 and the fourth insulating layer 54, and may contact the read word lines 60. In cross-section, the third insulating layer 52 may have a U-shape with an opening facing the X direction.

[0049] The second gate dielectric pattern 50 may include at least one of silicon oxide or a high-k dielectric.

[0050] In another example, each of the first gate dielectric pattern 20 and the second gate dielectric pattern 50 may include a data storage layer and a dielectric layer. For example, each of the first gate dielectric pattern 20 and the second gate dielectric pattern 50 may include a ferroelectric layer that may have polarization characteristics that vary with an electric field and may have residual polarization due to dipoles even in the absence of an external electric field. Data can be recorded using the polarization states within the ferroelectric layer. Therefore, each of the first gate dielectric pattern 20 and the second gate dielectric pattern 50 may include a ferroelectric layer, which may be referred to as a data storage layer. The ferroelectric layer (which may serve as a data storage layer) may include Hf-based compounds, Zr-based compounds, and / or Hf-Zr-based compounds. For example, the Hf-based compound may be an HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf-Zr-based compound may include a hafnium zirconium oxide (HZO)-based ferroelectric material. The ferroelectric layer (which can serve as a data storage layer) may comprise a ferroelectric material doped with at least one of the following impurities: C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, or Sr. For example, the ferroelectric layer (which can serve as a data storage layer) may be a material in which at least one of the following impurities, C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, or Sr, is doped into at least one of HfO2, ZrO2, or HZrO.

[0051] In the first gate dielectric pattern 20 and the second gate dielectric pattern 50, the data storage layer is not limited to the materials of the types described above, and may include materials capable of storing data.

[0052] The third insulating layer 52 and the fourth insulating layer 54 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. The third insulating layer 52 may comprise a material that is etch-selective relative to the fourth insulating layer 54. For example, the third insulating layer 52 may comprise silicon nitride, and the fourth insulating layer 54 may comprise silicon oxide.

[0053] The read bit lines 70 may extend in the vertical direction and may be spaced apart from each other in the Y direction. The read bit lines 70 may contact and be electrically connected to the vertically spaced second channel regions 63. For example, the read bit lines 70 may be located between adjacent semiconductor material layers 12 in the X direction. The write bit lines 40 and read bit lines 70 may be alternately arranged in the X direction.

[0054] In an embodiment, each read bit line 70 may include a second conductive layer 72 and a second pad layer 74. The second conductive layer 72 may extend in a vertical direction and may have a columnar shape. In a top view, the second conductive layer 72 is shown as rectangular, but is not limited thereto. According to an embodiment, the second conductive layer 72 may have a circular or elliptical shape in a top view. The second pad layer 74 may surround the second conductive layer 72 and may extend in a horizontal direction along the side surface of the second conductive layer 72. The second pad layer 74 may contact and be electrically connected to the vertically spaced second channel regions 63. For example, the second pad layer 74 may include the same material as the second channel regions 63 and may be integrally formed. The second pad layer 74 may be spaced apart from the semiconductor material layer 12 and the dielectric layer 15, and a second gate dielectric pattern 50 is interposed between the second pad layer 74 and the semiconductor material layer 12 and the dielectric layer 15. According to an embodiment, the second pad layer 74 may further extend in a horizontal direction to cover the lower surface of the second conductive layer 72.

[0055] The second conductive layer 72 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotubes, or combinations thereof. The second pad layer 74 may include an oxide semiconductor material. In an embodiment, the second pad layer 74 may include the same material as the second channel region 63, such as IGZO. According to an embodiment, the second channel region 63 and the second pad layer 74 may include different oxide semiconductor materials, and the second pad layer 74 may be formed in a separate process from the second channel region 63. In an embodiment, the carrier density and conductivity of the second pad layer 74 may be greater than those of the second channel region 63. For example, the concentration of oxygen vacancies in the second pad layer 74 may be greater than the concentration of oxygen vacancies in the second channel region 63.

[0056] The semiconductor device 100 may further include a spacer pattern 82. The spacer pattern 82 may be disposed between read bit lines 70 spaced apart in the Y direction. The spacer pattern 82 may electrically insulate the write bit lines 40. Figure 3 As shown, the spacer pattern 82 may extend in the X direction and may contact the read word line 60. The spacer pattern 82 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof.

[0057] According to an embodiment, adjacent memory cells MC in the X direction can share write bit line 40 or read bit line 70. For example, in Figure 4In the cross-sectional view shown, write bit lines 40 can be electrically connected to first channel regions 13 spaced apart from each other in the X direction, and the spaced-apart first channel regions 13 can be components of different memory cells MC. Read bit lines 70 can be electrically connected to second channel regions 63 spaced apart from each other in the X direction, and the spaced-apart second channel regions 63 can be components of different memory cells MC. Since adjacent memory cells MC share write bit lines 40 or read bit lines 70, the size of the semiconductor device in the X direction can be reduced, and the integration level of the memory cells MC can be improved.

[0058] According to an embodiment, only one of the write bit line 40 or the read bit line 70 may be shared between memory cells MC. For example, the write bit line 40 may not be shared, and the two write bit lines 40 may be arranged between adjacent memory cells MC in the X direction. Alternatively, the read bit line 70 may not be shared, and the two read bit lines 70 may be arranged between adjacent memory cells MC in the X direction.

[0059] According to an embodiment, adjacent memory cells MC in the X direction can be arranged symmetrically (e.g., mirror-symmetrically) with respect to write bit line 40 or read bit line 70. For example, as Figure 3 and Figure 4 As shown, the first channel region 13, charge storage region 14, write word line 30, read word line 60, and read bit line 70 can be symmetrically arranged with respect to an axis extending vertically through the write bit line 40. The first channel region 13, charge storage region 14, write word line 30, write bit line 40, and read word line 60 can be symmetrically arranged with respect to an axis extending vertically through the read bit line 70.

[0060] Figure 8 and Figure 9 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment.

[0061] refer to Figure 8 The semiconductor device 100a may include a write word line 30 that overlaps with the first channel region 13 in a vertical direction and a second channel region 63 that overlaps with the charge storage region 14 in a vertical direction. In embodiments, the vertical thickness of the write word line 30 and the vertical thickness of the second channel region 63 may be different. For example, the vertical thickness of the write word line 30 may be less than the vertical thickness of the second channel region 63. The vertical thickness of the read word line 60 may be the same as the vertical thickness of the second channel region 63, and may be greater than the vertical thickness of the write word line 30.

[0062] refer to Figure 9The semiconductor device 100b may include a write word line 30 that overlaps with the first channel region 13 in a vertical direction and a second channel region 63 that overlaps with the charge storage region 14 in a vertical direction. In embodiments, the vertical thickness of the write word line 30 and the vertical thickness of the second channel region 63 may be different. For example, the vertical thickness of the write word line 30 may be greater than the vertical thickness of the second channel region 63. The vertical thickness of the read word line 60 may be the same as the vertical thickness of the second channel region 63, and may be less than the vertical thickness of the write word line 30.

[0063] Figure 10 and Figure 11 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment.

[0064] refer to Figure 10 The semiconductor device 100c may include write bit lines 40 and read bit lines 70 disposed between semiconductor material layers 12 spaced apart in the X direction. In an embodiment, the lower surfaces of the write bit lines 40 and the read bit lines 70 may be disposed at a horizontal height lower than the upper end (i.e., the upper surface) of the substrate 10 in the vertical direction (Z direction). For example, the write bit line 40 may pass through a first gate dielectric pattern 20 and may extend partially into the substrate 10. The read bit line 70 may pass through a second gate dielectric pattern and may extend partially into the substrate 10.

[0065] refer to Figure 11 The semiconductor device 100d may include a write bit line 40 and a read bit line 70 disposed between semiconductor material layers 12 spaced apart in the X direction. In an embodiment, the write bit line 40 may further include a first barrier layer 46 located between a first conductive layer 42 and a first pad layer 44. The first barrier layer 46 may prevent metallic materials included in the first conductive layer 42 from diffusing into the first pad layer 44. The first barrier layer 46 may cover the lower and side surfaces of the first conductive layer 42 and may have a U-shape. The term "cover" (or "to cover," or similar term) as may be used herein is intended to refer generally to an element, structure, or layer being directly on or over another element, structure, or layer, or an element, structure, or layer being on or over another element, structure, or layer through one or more other intermediate elements, structures, or layers therebetween. In an embodiment, the read bit line 70 may further include a second barrier layer 76 located between a second conductive layer 72 and a second pad layer 74. The second barrier layer 76 may prevent metallic materials included in the second conductive layer 72 from diffusing into the second pad layer 74. The second barrier layer 76 may cover the lower surface and side surface of the second conductive layer 72, and may have a U-shape.

[0066] Figures 12 to 14 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment.

[0067] refer to Figure 12 The semiconductor device 100e may include a semiconductor material layer 12 and a dielectric layer 15 covering the semiconductor material layer 12. In embodiments, the dielectric layer 15 may be disposed only on the upper or lower surface of each semiconductor material layer 12. For example, the dielectric layer 15 may cover the lower surface of each semiconductor material layer 12. The upper surface of each semiconductor material layer 12 may be in contact with a first gate dielectric pattern 20 and a second gate dielectric pattern 50. In embodiments, the distance between the semiconductor material layer 12 and two write word lines 30 adjacent to the semiconductor material layer 12 in the vertical direction may be different. For example, the semiconductor material layer 12 may be configured to be closer to the write word line 30 located at a relatively higher horizontal height among the two adjacent write word lines 30 in the vertical direction. In embodiments, the distance between the semiconductor material layer 12 and two second channel regions 63 adjacent to the semiconductor material layer 12 in the vertical direction may be different. For example, the semiconductor material layer 12 may be configured to be closer to the second channel region 63 located at a relatively higher horizontal height among the two adjacent second channel regions 63 in the vertical direction.

[0068] refer to Figure 13 The semiconductor device 100f may include a semiconductor material layer 12 and a dielectric layer 15 disposed on the semiconductor material layer 12. In embodiments, the dielectric layer 15 may be disposed only on the upper or lower surface of each semiconductor material layer 12. For example, the dielectric layer 15 may cover the upper surface of each semiconductor material layer 12. The lower surface of each semiconductor material layer 12 may contact a first gate dielectric pattern 20 and a second gate dielectric pattern 50. In embodiments, the distance between the semiconductor material layer 12 and two write word lines 30 adjacent to the semiconductor material layer 12 in the vertical direction may be different. For example, the semiconductor material layer 12 may be configured to be closer to the write word line 30 located at a relatively lower horizontal height among the two adjacent write word lines 30 in the vertical direction. In embodiments, the distance between the semiconductor material layer 12 and two second channel regions 63 adjacent to the semiconductor material layer 12 in the vertical direction may be different. For example, the semiconductor material layer 12 may be configured to be closer to the second channel region 63 located at a relatively lower horizontal height among the two adjacent second channel regions 63 in the vertical direction.

[0069] refer to Figure 14 ,and Figure 4 Unlike the semiconductor device 100 shown, the dielectric layer 15 may be omitted in the semiconductor device 100g. For example, the upper or lower surface of each semiconductor material layer 12 may be in contact with the first gate dielectric pattern 20 and the second gate dielectric pattern 50.

[0070] Figure 15 This is a conceptual perspective view of a semiconductor device based on an example embodiment.

[0071] refer to Figure 15 The semiconductor device 100h may include a first structure ST1 and a second structure ST2 located below the first structure ST1 in the vertical direction. The first structure ST1 may include a reference. Figures 1 to 14 The memory cells MC of the semiconductor devices 100, 100a, 100b, 100c, 100d, 100e, 100f and 100g are described.

[0072] The second structure ST2 may include a peripheral circuit region PERI, and the peripheral circuit region PERI may include peripheral circuit elements, including peripheral transistors. For example, logic elements such as inverter circuits, NAND gate circuits, NOR gate circuits, AND gate circuits, OR gate circuits, XOR gate circuits, XNOR gate circuits, NOT gate circuits, antifuse, etc., may be provided in the peripheral circuit region PERI. The peripheral circuit region PERI may also include peripheral circuits such as sense amplifiers, sub-word line drivers, etc., for the operation of the memory cell MC, as well as peripheral circuits for data or command input / output or power / ground input.

[0073] In an embodiment, the second structure ST2 may be bonded to the first structure ST1. For example, the first structure ST1 may include a first bonding pad located on its lower surface, and the second structure ST2 may include a second bonding pad located on its upper surface and bonded to the first bonding pad. The first bonding pad and the second bonding pad may be electrically connected to the first structure ST1 and the second structure ST2.

[0074] In an embodiment, the semiconductor device 100h may include a connection plug that extends through (i.e., extends into or penetrates) the bonding surface between the first structure ST1 and the second structure ST2. The connection plug may electrically connect the first structure ST1 and the second structure ST2.

[0075] In an embodiment, the second structure ST2 may be disposed on the first structure ST1.

[0076] Figures 16A to 30C These are top views and vertical cross-sectional views illustrating a sequence of intermediate processes in a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 28A , Figure 29A and Figure 30A It corresponds to Figure 3 Top view. Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20 , Figure 21 , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27A , Figure 28B , Figure 29B and Figure 30B It corresponds to Figure 4 Vertical cross-sectional view. Figure 24C It corresponds to Figure 6 Vertical cross-sectional view. Figure 25C , Figure 26C , Figure 27B , Figure 28C , Figure 29C and Figure 30C It corresponds to Figure 7 Vertical cross-sectional view.

[0077] refer to Figure 16A and Figure 16B A stacked structure (11a, 12, and 15) can be formed on the substrate 10. The stacked structure may include a first sacrificial layer 11a, a semiconductor material layer 12, and a dielectric layer 15. Multiple semiconductor material layers 12 may be spaced apart from each other in the vertical direction (Z direction), and each dielectric layer 15 may cover the lower and upper surfaces of each semiconductor material layer 12. The first sacrificial layer 11a may fill the space between the dielectric layers 15. For example, the first sacrificial layer 11a and the semiconductor material layers 12 may be alternately arranged in the vertical direction, and the dielectric layer 15 may be disposed between the first sacrificial layer 11a and the semiconductor material layers 12. The term "filling" (or "performing filling," or similar terms) is intended to refer to completely filling a defined space (e.g., the space between the dielectric layers 15) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have voids or other spaces throughout.

[0078] The first sacrificial layer 11a may include a material that has etch selectivity relative to the semiconductor material layer 12 and the dielectric layer 15. The first sacrificial layer 11a may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. For example, the first sacrificial layer 11a may include silicon nitride. The semiconductor material layer 12 may include a semiconductor material and may include, for example, an oxide semiconductor material. The dielectric layer 15 may include a dielectric material and may include, for example, AlO, but is not limited thereto.

[0079] According to an embodiment, for each semiconductor material layer 12, a dielectric layer 15 may not be formed on at least one of the upper and lower surfaces of the semiconductor material layer 12, and the semiconductor material layer 12 may be in contact with the first sacrificial layer 11a. For example, according to an embodiment, it is possible to manufacture... Figures 12 to 14 The semiconductor devices shown are 100e, 100f, and 100g.

[0080] refer to Figure 17A and Figure 17B A second sacrificial layer 11b can be formed. The second sacrificial layer 11b can be formed by patterning the stacked structures (11a, 12, and 15) using anisotropic etching and then filling them with an insulating material. The second sacrificial layers 11b can extend in the X and Z directions and can be spaced apart from each other in the Y direction. The second sacrificial layer 11b can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. For example, the second sacrificial layer 11b can include the same material as the first sacrificial layer 11a and can include, for example, silicon nitride.

[0081] After forming the second sacrificial layer 11b, the stacked structure (11a, 12, and 15) can be anisotropically etched to form the first trench T1 and the second trench T2. The first trench T1 and the second trench T2 can be alternately arranged in the X direction. This can be done at the corresponding write bit line 40 (e.g., Figure 3 and Figure 4 A first trench T1 is formed at the position shown, and a second trench T2 can be formed at the position corresponding to the read bit line 70.

[0082] According to an embodiment, the upper surface of the substrate 10 can be partially etched during the process of forming the first trench T1 and the second trench T2. For example, according to an embodiment, it is possible to manufacture... Figure 10 The semiconductor device 100c shown is shown.

[0083] The semiconductor material layer 12 can be patterned by forming a second sacrificial layer 11b, a first trench T1, and a second trench T2, and the semiconductor material layers 12 can be spaced apart from each other in the X and Y directions. A portion of the semiconductor material layer 12 adjacent to the first trench T1 can be referred to as the first channel region 13.

[0084] refer to Figure 18A and Figure 18BA first buried layer 18 can be formed to fill the second trench T2. The first buried layer 18 can be formed only in the second trench T2 by forming an insulating material layer filling both the first trench T1 and the second trench T2, and then removing the insulating material layer filling the first trench T1. The first buried layer 18 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. For example, the first buried layer 18 may include silicon oxide.

[0085] In this embodiment, an annealing process can be performed after the formation of the first buried layer 18. The annealing process can supply oxygen atoms into the semiconductor material layer 12. For example, when the semiconductor material layer 12 comprises an oxide semiconductor material, the annealing process can reduce oxygen vacancies in the semiconductor material layer 12. The first channel region 13 can be exposed through the first trench T1, but the charge storage region 14 may not be exposed. Figure 5 This allows the concentration of oxygen vacancies in each first channel region 13 to be lower than the concentration of oxygen vacancies in each charge storage region 14. Therefore, the carrier concentration and conductivity of the charge storage region 14 can be greater than those of the first channel region 13. The term "exposed" (or "performed exposure," or similar terms) may be used herein to describe the relationship between elements in an intermediate process of a reference semiconductor device fabrication, but specific elements may not need to be exposed in the finished device. Similarly, the term "not exposed" may be used to describe the relationship between elements in an intermediate process of a reference semiconductor device fabrication, but specific elements may not need to be unexposed in the finished device.

[0086] refer to Figure 19A and Figure 19B The first sacrificial layer 11a and the second sacrificial layer 11b exposed through the first trench T1 can be partially etched. The first sacrificial layer 11a and the second sacrificial layer 11b can be etched to form the first opening OP1. The first opening OP1 can extend horizontally from the first trench T1 and can expose the upper or lower surface of the dielectric layer 15 and the side surface of the first sacrificial layer 11a. The dielectric layer 15 may include a material that is etch-selective relative to the first sacrificial layer 11a and the second sacrificial layer 11b, and therefore may not be etched in the process of forming the first opening OP1. The dielectric layer 15 can protect the semiconductor material layer 12 in the process of forming the first opening OP1.

[0087] refer to Figure 20A dielectric material layer 20p and a first insulating material layer 22p can be formed. The dielectric material layer 20p can be formed along the upper or lower surface of the dielectric layer 15 exposed through the first trench T1 and the first opening OP1, and along the side surface of the first sacrificial layer 11a. The dielectric material layer 20p can also cover the upper surface of the substrate 10, the upper surface of the uppermost dielectric layer 15, and the upper surface of the first buried layer 18. In an embodiment, the dielectric material layer 20p can surround the first channel region 13 and can extend in the Y direction. For example, the dielectric material layer 20p can cover the upper or lower surface of the dielectric layer 15 and can contact the side surface of the first channel region 13. The first insulating material layer 22p can be conformally formed on the dielectric material layer 20p and can extend in the Y direction. The term “conformally” (or “conformal”, or similar term) as may be used in the context of material layers or coatings herein is intended to refer generally to a material layer or coating having a substantially uniform cross-sectional thickness relative to the contour of the surface on which the material layer is applied. A second insulating material layer 24p can be formed on the first insulating material layer 22p, and then the second insulating material layer 24p can be etched so that the first insulating material layer 22p can be exposed in the first trench T1. The second insulating material layer 24p can fill the first opening OP1 and can extend in the Y direction.

[0088] The first insulating layer 22p and the second insulating layer 24p may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. The first insulating layer 22p may comprise a material that is etch-selective relative to the second insulating layer 24p. For example, the first insulating layer 22p may comprise silicon nitride, and the second insulating layer 24p may comprise silicon oxide.

[0089] refer to Figure 21 The first insulating material layer 22p can be etched to form the insulating layer 22. The first insulating material layer 22p may include a material that has etch selectivity relative to the dielectric material layer 20p and the second insulating material layer 24p, and can therefore be selectively etched. The first insulating layers 22 may be disposed between the semiconductor material layers 12 and may be spaced apart from each other in the vertical direction.

[0090] The dielectric material layer 20p and the second insulating material layer 24p exposed by etching the first insulating material layer 22p can be partially etched. For example, the thickness of a portion of the exposed dielectric material layer 20p and the thickness of a portion of the exposed second insulating material layer 24p can be reduced in the vertical direction. Although the upper surface of the uppermost dielectric layer 15 and the upper surface of the first buried layer 18 are shown as being covered by the etched dielectric material layer 20p, this is not a limitation. According to an embodiment, the upper surface of the uppermost dielectric layer 15 and the upper surface of the first buried layer 18 can be exposed.

[0091] refer to Figure 22A and Figure 22B Write word lines 30 can be formed. Write word lines 30 can extend in the Y direction and can be spaced apart from each other in the X direction. Write word lines 30 can be formed to overlap with the first channel region 13 of the semiconductor material layer 12 in the vertical direction. For example, two write word lines 30 can be formed between two adjacent semiconductor material layers 12 in the vertical direction, and the two write word lines 30 can be spaced apart from each other in the vertical direction, with the second insulating material layer 24p located between the two write word lines 30. The lowest write word line 30 can be a dummy word line.

[0092] refer to Figure 23A and Figure 23B A capping layer 32 can be formed. The capping layer 32 can be prepared by forming a capping material layer that contacts the write word line 30 and fills the first trench T1, and then anisotropically etching the capping material layer. The capping layer 32 can extend in the Y direction and can include openings located in portions corresponding to the write bit lines 40 described below. The capping layer 32 can comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof.

[0093] In this embodiment, the semiconductor material layer 12, the dielectric layer 15, the dielectric material layer 20p, and the second insulating material layer 24p can be partially etched using an etching process. The dielectric material layer 20p and the second insulating material layer 24p can be etched to form the first gate dielectric pattern 20 and the second insulating layer 24.

[0094] refer to Figures 24A to 24C Write bit lines 40 can be formed in the capping layer 32. Each write bit line 40 may include a first conductive layer 42 and a first pad layer 44 surrounding the first conductive layer 42. The first pad layer 44 may extend in a horizontal direction to cover the side surface of the first conductive layer 42 and may extend in a vertical direction to contact a plurality of vertically spaced semiconductor material layers 12. For example, the first pad layer 44 may contact a first channel region 13.

[0095] The first pad layer 44 may include a conductive material, and may include, for example, an oxide semiconductor material. Since both the first pad layer 44 and the semiconductor material layer 12 include oxide semiconductor materials, the first pad layer 44 can reduce the resistance between the semiconductor material layer 12 and the first conductive layer 42. In an embodiment, the concentration of oxygen vacancies in each first pad layer 44 may be higher than the concentration of oxygen vacancies in each first channel region 13, and the carrier concentration and conductivity of the first pad layer 44 may be higher than the carrier concentration and conductivity of the first channel region 13.

[0096] refer to Figures 25A to 25C The first buried layer 18 can be removed, and the side surfaces of the semiconductor material layer 12 and the dielectric layer 15 can be exposed through the second trench T2. The portion of the semiconductor material layer 12 exposed by the second trench T2 can be referred to as the charge storage region 14.

[0097] In this embodiment, a doping process can be performed after the first buried layer 18 is removed. The doping process can introduce impurities into the charge storage region 14. For example, the impurities may include fluorine (F). Because the charge storage region 14 contains impurities, the carrier concentration and conductivity of the charge storage region 14 can be higher than those of the first channel region 13.

[0098] refer to Figures 26A to 26C The first sacrificial layer 11a and the second sacrificial layer 11b can be removed to form the second opening OP2. The second opening OP2 can extend horizontally from the second trench T2 and can expose the upper or lower surface of the dielectric layer 15. The dielectric layer 15 may include a material that is etch-selective relative to the first sacrificial layer 11a and the second sacrificial layer 11b, and therefore may not be etched in the process of forming the second opening OP2. The dielectric layer 15 can protect the semiconductor material layer 12 in the process of forming the second opening OP2.

[0099] refer to Figure 27A and Figure 27B A second gate dielectric pattern 50, a third insulating layer 52, and a fourth insulating layer 54 can be formed. The second gate dielectric pattern 50, the third insulating layer 52, and the fourth insulating layer 54 can be connected with a reference... Figure 20 and Figure 21 The dielectric material layer 20p, the first insulating layer 22, and the second insulating material layer 24p described are formed using the same or similar processes. The second gate dielectric pattern 50, the third insulating layer 52, and the fourth insulating layer 54 may each have the same or similar structures as the first gate dielectric pattern 20, the first insulating layer 22, and the second insulating layer 24.

[0100] A second gate dielectric pattern 50 may be formed along the upper or lower surface of the dielectric layer 15. The second gate dielectric pattern 50 may also cover the upper surface of the substrate 10, the upper surface of the uppermost dielectric layer 15, and the upper surface of the write bit line 40. In an embodiment, the second gate dielectric pattern 50 may surround the charge storage region 14 and may extend in the Y direction. For example, the second gate dielectric pattern 50 may cover the upper or lower surface of the dielectric layer 15 and may contact the side surface of the charge storage region 14. A third insulating layer 52 may be formed by conformally depositing an insulating material layer on the second gate dielectric pattern 50 and then etching the insulating material layer. The third insulating layer 52 may extend in the Y direction. A fourth insulating layer 54 may be formed on the third insulating layer 52 and may extend in the Y direction.

[0101] The third insulating layer 52 and the fourth insulating layer 54 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. The third insulating layer 52 may comprise a material that is etch-selective relative to the fourth insulating layer 54. For example, the third insulating layer 52 may comprise silicon nitride, and the fourth insulating layer 54 may comprise silicon oxide.

[0102] refer to Figures 28A to 28C A read word line 60 can be formed. The read word lines 60 can extend in the Y direction and can be spaced apart from each other in the X direction. The read word lines 60 can overlap with the charge storage region 14 of the semiconductor material layer 12 in the vertical direction. For example, two read word lines 60 can be formed between two adjacent semiconductor material layers 12 in the vertical direction, and the two read word lines 60 can be spaced apart from each other in the vertical direction, with the fourth insulating layer 54 located between the two read word lines 60. The lowest read word line 60 can be a dummy word line.

[0103] At least a portion of the read word line 60 may be positioned at the same horizontal height as the write word line 30 in the vertical direction. In an embodiment, the upper and lower surfaces of the read word line 60 may be positioned at the same horizontal height as the upper and lower surfaces of the write word line 30, respectively, but are not limited thereto. According to an embodiment, the upper and lower surfaces of the read word line 60 may not be positioned at the same horizontal height as the upper and lower surfaces of the write word line 30. Figure 8 and Figure 9 As shown, according to an embodiment, the vertical thickness of the read word line 60 may be different from the vertical thickness of the write word line 30.

[0104] refer to Figures 29A to 29CA second channel region 63 and a second pad layer 74 can be formed. The second channel region 63 can be prepared by forming a semiconductor material layer that contacts the read word line 60 and then anisotropically etching the semiconductor material layer. The second pad layer 74 can be formed simultaneously with the second channel region 63. For example, the second pad layer 74 may include the same material as the second channel region 63 and can be integrally formed. The second channel region 63 and the second pad layer 74 may include an oxide semiconductor material.

[0105] The second channel region 63 may overlap with the charge storage region 14 in the vertical direction and may extend in the horizontal direction. At least a portion of the second channel region 63 may be positioned at the same horizontal height as the read word line 60 and the write word line 30 in the vertical direction. The second pad layer 74 may extend in the vertical direction and may contact the second channel region 63.

[0106] refer to Figures 30A to 30C A second buried layer 80 may be formed on the second liner layer 74 to fill the second trench T2. The second buried layer 80 may extend in the second trench T2 in the Y direction. The second buried layer 80 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. For example, the second buried layer 80 may include silicon oxide.

[0107] After the second buried layer 80 is formed, it can be patterned using an anisotropic etching process. The etched second buried layers 80 can be spaced apart in the Y direction. The second channel region 63 and the second pad layer 74 can be etched using an etching process. Spacer patterns 82 can be formed in the space from which portions of the second buried layer 80 have been removed. Spacer patterns 82 can extend in both the X and vertical directions and can be spaced apart in the Y direction. Spacer patterns 82 can be disposed between adjacent read word lines 60 in the X direction and between adjacent charge storage regions 14 in the Y direction. Spacer patterns 82 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectrics, or combinations thereof. Spacer patterns 82 can include materials with etch selectivity relative to the second buried layer 80.

[0108] Refer again Figures 3 to 7 The second buried layer 80 can be removed, and the semiconductor device 100 can be manufactured by forming a second conductive layer 72 in the space from which the second buried layer 80 has been removed. The second conductive layer 72 and the second pad layer 74 can form read bit lines 70. The read bit lines 70 can extend in the vertical direction and can be spaced apart from each other in the Y direction. The read bit lines 70 can be electrically connected to the second channel region 63.

[0109] According to embodiments of the technical concept of the present invention, memory cells that are adjacent to each other in the horizontal direction can share write bit lines or read bit lines to reduce the size of the semiconductor device in the horizontal direction.

[0110] The various advantages and effects of the present invention are not limited to the above description, and the various advantages and effects of the present invention will be more easily understood in the process of explaining the specific embodiments.

[0111] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A semiconductor material layer extending in a first horizontal direction and spaced apart from each other in the first horizontal direction, each of the semiconductor material layers including a first channel region and a charge storage region; The first word line at least partially overlaps with the first channel region of the semiconductor material layer in the vertical direction and extends in a second horizontal direction intersecting the first horizontal direction, the vertical direction being perpendicular to the first horizontal direction and the second horizontal direction; The first bit line, each first bit line is adjacent to a first end of the corresponding semiconductor material layer in the semiconductor material layer in the first horizontal direction and extends in the vertical direction, the first end being adjacent to the first channel region of the corresponding semiconductor material layer in the semiconductor material layer; The second channel region overlaps at least partially with the charge storage region of the semiconductor material layer in the vertical direction; as well as The second bit line, each of the second bit lines being adjacent to the second end of the corresponding semiconductor material layer in the first horizontal direction and extending in the vertical direction, the second end being adjacent to the charge storage region of the corresponding semiconductor material layer in the semiconductor material layer. Each of the first bit lines includes a first conductive layer and a first pad layer extending around the side surface of the first conductive layer, and The first pad layer of the first bit line contacts the first channel region, extends in the vertical direction, and comprises an oxide semiconductor material.

2. The semiconductor device according to claim 1, wherein, Each of the semiconductor material layers includes a single component, the single component including the charge storage region and the first channel region of the same material.

3. The semiconductor device according to claim 1, wherein, The first word line is symmetrically arranged about the first bit line.

4. The semiconductor device according to claim 1, wherein, The second channel region is symmetrically arranged about the second bit line.

5. The semiconductor device according to claim 1, wherein, Each of the charge storage region and the first channel region comprises an oxide semiconductor material.

6. The semiconductor device according to claim 5, wherein, The concentration of oxygen vacancies in each of the charge storage regions is greater than the concentration of oxygen vacancies in each of the first channel regions.

7. The semiconductor device according to claim 5, wherein, The concentration of oxygen vacancies in each of the first liner layers is greater than the concentration of oxygen vacancies in each of the first channel regions.

8. The semiconductor device according to claim 5, wherein, Each of the charge storage regions includes fluorine.

9. The semiconductor device according to claim 1, wherein, At least a portion of the second channel region is coplanar with the first character line.

10. The semiconductor device according to claim 1, wherein, The thickness of each second channel region in the vertical direction is different from the thickness of each first letter in the vertical direction.

11. The semiconductor device of claim 1, further comprising a second word line, the second word line contacting the second channel region and disposed between the second channel region and the first word line.

12. The semiconductor device according to claim 1, wherein, Each of the second bit lines includes a second conductive layer and a second pad layer extending around the side surface of the second conductive layer, and The second pad layer of the second bit line contacts the second channel region, extends in the vertical direction, and comprises an oxide semiconductor material.

13. The semiconductor device according to claim 12, wherein, Each of the second liner layers comprises the same material as the second channel region and is integrally formed with the corresponding second channel region.

14. The semiconductor device of claim 1, further comprising a dielectric layer extending in the first horizontal direction and / or the second horizontal direction between the first word line and the semiconductor material layer and between the second channel region and the semiconductor material layer.

15. The semiconductor device according to claim 14, wherein, The dielectric layer is in contact with at least one of the upper or lower surfaces of the semiconductor material layer.

16. A semiconductor device, the semiconductor device comprising: The memory cell includes a first transistor, a second transistor, and a charge storage region. The first transistor includes a first channel region, the second transistor includes a second channel region, and the charge storage region is coplanar with the first channel region, at least partially overlaps with the second channel region in a vertical direction, and is disposed in a first horizontal direction perpendicular to the vertical direction. The first bit line extends in the vertical direction between the memory cells and is electrically connected to the first transistor in the memory cell; as well as A second bit line extends in the vertical direction between the memory cells and is electrically connected to the second transistor in the memory cell. The storage unit includes a first storage unit and a second storage unit that are adjacent to each other in the first horizontal direction. The first storage unit and the second storage unit share the first bit line. The first bit line includes a first conductive layer and a first pad layer extending around the side surface of the first conductive layer, and The first pad layer extends in the vertical direction and contacts the first channel region in the first transistor.

17. The semiconductor device according to claim 16, wherein, The first bit line is in contact with the first channel region of the first transistor in the first memory cell and the second memory cell.

18. The semiconductor device of claim 16, wherein, The storage unit includes a third storage unit adjacent to the first storage unit in the first horizontal direction. The first storage unit is located between the second storage unit and the third storage unit, and The first storage unit and the third storage unit share the second bit line.

19. The semiconductor device according to claim 16, wherein, The first transistor in the memory cell includes a first word line, which at least partially overlaps with the first channel region in the vertical direction. At least a portion of the first character line is coplanar with the second channel region.

20. A semiconductor device, the semiconductor device comprising: A semiconductor material layer extending in a first horizontal direction and including a first channel region and a charge storage region; The first word line overlaps at least partially with the first channel region of the semiconductor material layer in a vertical direction and extends in a second horizontal direction that intersects the first horizontal direction, the vertical direction being perpendicular to both the first horizontal direction and the second horizontal direction; A second channel region, which at least partially overlaps with the charge storage region of the semiconductor material layer in the vertical direction; The second character line contacts the second channel area and extends in the second horizontal direction between the second channel area and the first character line; The first bit line extends from one side of the first channel region of the semiconductor material layer in the vertical direction; as well as The second bit line extends from one side of the second channel region in the vertical direction.

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