Method for manufacturing a semiconductor device

Abstract

The present disclosure relates to a manufacturing method of a semiconductor device. After a silicon oxide film is formed on a main surface of a semiconductor substrate to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film using a photoresist pattern formed thereon as an etching mask, and then a further anisotropic etching is performed on the silicon oxide film. Thus, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining under the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.

Description

Cross-references to related applications

[0001] The disclosure of Japanese Patent Application No. 2024-224408, filed on December 19, 2024 (including the specification, drawings and abstract), is incorporated herein by reference in its entirety. Background Technology

[0002] The present invention relates to a method for manufacturing a semiconductor device, and is preferably applicable, for example, to a method for manufacturing a semiconductor device having a non-volatile memory.

[0003] Non-volatile memory with a floating gate electrode is known as a type of non-volatile memory. In a non-volatile memory with a floating gate electrode, charge accumulates in the floating gate electrode, thereby allowing information to be stored.

[0004] The following is a technique disclosed.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2011-199124

[0006] Patent document 1 discloses a technology related to a non-volatile memory with a floating gate electrode. Summary of the Invention

[0007] There is a need to improve the performance of semiconductor devices, including non-volatile memories with floating gate electrodes.

[0008] Other objects and novel features of the invention will become clear from the description in this specification and the accompanying drawings.

[0009] According to one embodiment, a floating gate electrode is formed on the main surface of a semiconductor substrate via a first gate insulating film, and a gate electrode is formed on the main surface of the semiconductor substrate via a second gate insulating film. Then, a first sidewall spacer is formed on the side surface of the floating gate electrode, and a second sidewall spacer is formed on the side surface of the gate electrode. Next, a silicon oxide film is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the first sidewall spacer, and the second sidewall spacer. Then, after forming a mask layer on the silicon oxide film, isotropic etching is performed on the silicon oxide film using the mask layer as an etching mask. Then, anisotropic etching is performed on the silicon oxide film using the mask layer as an etching mask. Therefore, the silicon oxide film exposed from the mask layer is removed, and a first insulating film made of the silicon oxide film retained below the mask layer is formed. The first insulating film covers the floating gate electrode. Then, after removing the mask layer, a metal silicide layer is formed on the gate electrode. Then, a silicon nitride film is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the first sidewall spacer, and the second sidewall spacer. A first insulating film is inserted between the floating gate electrode and the silicon nitride film.

[0010] According to one embodiment, the performance of a semiconductor device can be improved. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view of the main parts of the semiconductor device according to an embodiment;

[0012] Figure 2 This is a cross-sectional view of the main parts of the semiconductor device according to an embodiment;

[0013] Figure 3 It refers to a process flow that indicates a part of the manufacturing process of a semiconductor device according to an embodiment;

[0014] Figure 4 This is a cross-sectional view of the main parts of the semiconductor device in the manufacturing process according to the embodiment;

[0015] Figure 5 Is with Figure 4 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0016] Figure 6 It is from Figure 4 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0017] Figure 7 Is with Figure 6 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0018] Figure 8 It is from Figure 6 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0019] Figure 9 Is with Figure 8 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0020] Figure 10 It is from Figure 8 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0021] Figure 11 Is with Figure 10 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0022] Figure 12 It is from Figure 10 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0023] Figure 13 Is with Figure 12 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0024] Figure 14 It is from Figure 12 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0025] Figure 15 Is with Figure 14 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0026] Figure 16 It is from Figure 14 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0027] Figure 17 Is with Figure 16 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0028] Figure 18 It is from Figure 16 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0029] Figure 19 Is with Figure 18 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0030] Figure 20 It is from Figure 18 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0031] Figure 21 Is with Figure 20 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0032] Figure 22 It is from Figure 20 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0033] Figure 23 Is with Figure 22 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0034] Figure 24 It is from Figure 22 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0035] Figure 25 Is with Figure 24 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0036] Figure 26 It is from Figure 24 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0037] Figure 27 Is with Figure 26 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0038] Figure 28 It is from Figure 26 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0039] Figure 29 Is with Figure 28 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0040] Figure 30 It is from Figure 28 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0041] Figure 31 Is with Figure 30 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0042] Figure 32 It is from Figure 30Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0043] Figure 33 Is with Figure 32 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0044] Figure 34 It refers to a process flow that is part of the manufacturing process of the semiconductor device according to the first study example;

[0045] Figure 35 It is a cross-sectional view of the main parts of the semiconductor device in the manufacturing process according to the first research example;

[0046] Figure 36 Is with Figure 35 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0047] Figure 37 It is from Figure 35 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0048] Figure 38 Is with Figure 37 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0049] Figure 39 It is from Figure 37 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0050] Figure 40 It is a cross-sectional view of the main parts of the semiconductor device in the manufacturing process according to the second research example;

[0051] Figure 41 Is with Figure 40 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0052] Figure 42 It is from Figure 40 Cross-sectional view of the main parts of a semiconductor device in a continuing manufacturing process;

[0053] Figure 43 Is with Figure 42 The semiconductor device shown is a cross-sectional view of the main parts of the manufacturing process of the same semiconductor device.

[0054] Figure 44 It is from Figure 42 Cross-sectional views of the main components of a semiconductor device during the ongoing manufacturing process; and

[0055] Figure 45 Is with Figure 44 A cross-sectional view of the main parts of the same semiconductor device in the manufacturing process. Detailed Implementation

[0056] In the embodiments described below, for convenience, the invention will be described in multiple parts or embodiments as needed. However, unless otherwise stated, these parts or embodiments are not independent of each other, and one part or embodiment may relate to all or part of another part or embodiment as an example of modification, detail, or supplementary description. Furthermore, in the embodiments described below, when referring to the number of elements (including number of pieces, numerical values, quantities, ranges, etc.), unless otherwise stated, the number of elements is not limited to a specific number, unless such number is obviously limited in principle. Numbers greater than or less than a specific number also apply. Furthermore, in the embodiments described below, it is self-evident that, unless otherwise stated, components (including element steps, etc.) are not always essential, unless the component is obviously essential in principle. Similarly, in the embodiments described below, when referring to the shape of components, their positional relationships, etc., unless otherwise stated, this includes substantially similar and analogous shapes, unless it can be imagined that they are obviously excluded in principle. The same applies to the numerical values ​​and ranges mentioned above.

[0057] In the following, embodiments will be described in detail with reference to the accompanying drawings. Note that throughout the drawings used to describe the embodiments, components with the same function are denoted by the same reference numerals, and repeated descriptions thereof are omitted. Furthermore, unless specifically required in the following embodiments, descriptions of the same or similar parts are generally not repeated.

[0058] Furthermore, in some of the figures used in the embodiments, shading may be omitted even in cross-sectional views to make the figures easier to see. Additionally, shading lines may be used even in plan views to make the figures easier to read.

[0059] Furthermore, a planar view corresponds to viewing an object from a plane substantially parallel to the main surface or back surface of the semiconductor substrate SB. Additionally, the bottom surface and lower surface have the same meaning.

[0060] Furthermore, in this application, MOSFET (metal-oxide-semiconductor field-effect transistor) includes not only MOSFETs that use an oxide film as the gate insulating film, but also MOSFETs that use an insulating film other than an oxide film as the gate insulating film.

[0061] Example

[0062] Structure of semiconductor devices

[0063] refer to Figure 1 and Figure 2 A semiconductor device according to an embodiment will be described. Figure 1 The image shows a cross-sectional view of the main part of the memory formation area, in which memory elements (storage elements) MC constituting non-volatile memory (non-volatile storage element or flash memory) are formed. Figure 1 The X, Y, and Z directions are shown. The X and Y directions are substantially parallel to the main surface of the semiconductor substrate SB, and the Z direction is substantially perpendicular to the main surface of the semiconductor substrate SB. The X, Y, and Z directions are perpendicular to each other. Figure 1 The cross-sectional view shown is parallel to the X and Z directions and perpendicular to the Y direction. Figure 2 The diagram shows a cross-sectional view of the main portion of the peripheral circuit region in which the peripheral circuitry is formed. The peripheral circuitry is circuitry that differs from non-volatile memory and includes, for example, a processor such as a central processing unit (CPU), control circuitry, sense amplifiers, column decoders, row decoders, and input / output circuitry.

[0064] like Figure 1 As shown, the semiconductor device according to an embodiment includes a semiconductor substrate SB, a p-type well PW1, a control gate electrode CG, a floating gate electrode FG, a gate insulating film GF1, a gate insulating film GF2, an n-type semiconductor region SD1, an n-type semiconductor region SD2, an n-type semiconductor region SD3, sidewall spacers SW1, sidewall spacers SW2, and an insulating film BL. Figure 2 As shown, the semiconductor device according to the embodiment further includes a p-type well PW2, a gate electrode GE, a gate insulating film GF3, a sidewall spacer SW3, an n-type semiconductor region SD4, and an n-type semiconductor region SD5. Figure 1 and Figure 2 As shown, the semiconductor device according to the embodiment further includes a metal silicide layer SL, an insulating film SN, an insulating film SO, a plug PG, and a wire M1.

[0065] refer to Figure 1 This will describe the memory formation area.

[0066] The semiconductor substrate SB is made of, for example, p-type single-crystal silicon. The semiconductor substrate SB has a main surface and a back surface opposite to the main surface.

[0067] p-type well PW1, n-type semiconductor region SD1, n-type semiconductor region SD2 and n-type semiconductor region SD3 are formed in semiconductor substrate SB.

[0068] The control gate electrode CG is formed on the main surface of the semiconductor substrate SB (on the p-type well PW1) via a gate insulating film GF1. Therefore, the gate insulating film GF1 is interposed between the control gate electrode CG and the semiconductor substrate SB. The gate width direction of the control gate electrode CG is the Y direction, and the gate length direction of the control gate electrode CG is the X direction.

[0069] A floating gate electrode FG is formed on the main surface of the semiconductor substrate SB (on the p-type well PW1) via a gate insulating film GF2. Therefore, the gate insulating film GF2 is interposed between the floating gate electrode FG and the semiconductor substrate SB. The gate width direction of the floating gate electrode FG is the Y-direction, and the gate length direction of the floating gate electrode FG is the X-direction. The control gate electrode CG and the floating gate electrode FG are spaced apart from each other.

[0070] Sidewall spacers SW1 are formed on the side surface (sidewall) of the control gate electrode CG as a sidewall insulating film. Sidewall spacers SW2 are formed on the side surface (sidewall) of the floating gate electrode FG as a sidewall insulating film.

[0071] The control gate electrode CG and the floating gate electrode FG are adjacent to each other in the X direction. In the X direction, the n-type semiconductor region SD2 is located between the n-type semiconductor regions SD1 and SD3. The control gate electrode CG and the floating gate electrode FG are located on the portion of the semiconductor substrate SB between the n-type semiconductor regions SD1 and SD3. Specifically, the control gate electrode CG is located on the portion of the semiconductor substrate SB between the n-type semiconductor regions SD1 and SD2. Furthermore, the floating gate electrode FG is located on the portion of the semiconductor substrate SB between the n-type semiconductor regions SD2 and SD3.

[0072] n-type semiconductor regions SD1, SD2, and SD3 are formed in a p-type well PW1. n-type semiconductor region SD1 is the semiconductor region used as either the source or drain. SD1 includes n-type semiconductor region E1 and n-type semiconductor region H1. The n-type impurity concentration in n-type semiconductor region H1 is higher than that in n-type semiconductor region E1. Therefore, n-type semiconductor region SD1 has a lightly doped drain (LDD) structure. n-type semiconductor region E1 is located below the sidewall spacer SW1. In the plan view, n-type semiconductor region E1 is located between n-type semiconductor region H1 and the control gate electrode CG.

[0073] The n-type semiconductor region SD2 is a semiconductor region used as the source or drain. The n-type semiconductor region SD2 includes n-type semiconductor regions E2a, E2b, and H2. The n-type impurity concentration in n-type semiconductor region H2 is higher than that in n-type semiconductor regions E2a and E2b. Therefore, the n-type semiconductor region SD2 has an LDD structure. n-type semiconductor region E2a is located below sidewall spacer SW1, and n-type semiconductor region E2b is located below sidewall spacer SW2. In the plan view, n-type semiconductor region E2a is located between n-type semiconductor region H2 and the control gate electrode CG, and n-type semiconductor region E2b is located between n-type semiconductor region H2 and the floating gate electrode FG.

[0074] The n-type semiconductor region SD3 is a semiconductor region used for the source or drain. The n-type semiconductor region SD3 includes n-type semiconductor region E3 and n-type semiconductor region H3. The n-type impurity concentration in n-type semiconductor region H3 is higher than that in n-type semiconductor region E3. Therefore, the n-type semiconductor region SD3 has an LDD structure. The n-type semiconductor region E3 is located below the sidewall spacer SW2. In the plan view, the n-type semiconductor region E3 is located between the n-type semiconductor region H3 and the floating gate electrode FG.

[0075] A metal silicide layer SL is formed on each of the upper surfaces of the n-type semiconductor regions H1, H2, and H3, and on the upper surface of the control gate electrode CG. The metal silicide layer SL is not formed on the floating gate electrode FG.

[0076] An insulating film (silicon oxide film) BL is formed to cover the floating gate electrode FG and the sidewall spacers SW2. The entire upper surface of the floating gate electrode FG is covered by the insulating film BL. In the plan view, the floating gate electrode FG is located inside the insulating film BL. The control gate electrode CG is not covered by the insulating film BL. That is, in the plan view, the control gate electrode CG does not overlap with the insulating film BL. The insulating film BL is made of silicon oxide.

[0077] Of the two ends of the insulating film BL in the X direction, one end is located on the n-type semiconductor region H2, and the other end is located on the n-type semiconductor region H3. Therefore, a portion of the n-type semiconductor region H2 is covered by the insulating film BL, while the remaining portion of the n-type semiconductor region H2 is exposed from the insulating film BL. A metal silicide layer SL is formed on the remaining portion of the n-type semiconductor region H2 exposed from the insulating film BL. The metal silicide layer SL is not formed on the portion of the n-type semiconductor region H2 that is covered by the insulating film BL.

[0078] A portion of the n-type semiconductor region H3 is covered by the insulating film BL, while the remaining portion of the n-type semiconductor region H3 is exposed from the insulating film BL. A metal silicide layer SL is formed on the remaining portion of the n-type semiconductor region H3 exposed from the insulating film BL. A metal silicide layer SL is not formed on the portion of the n-type semiconductor region H3 covered by the insulating film BL.

[0079] refer to Figure 2 This will describe the peripheral circuit area.

[0080] like Figure 2 As shown, a p-type well PW2 is formed in a semiconductor substrate SB, and n-type semiconductor regions SD4 and SD5 are formed in the p-type well PW2. In the plan view, the p-type well PW2 and p-type well PW1 are spaced apart from each other.

[0081] The gate electrode GE is formed on the main surface of the semiconductor substrate SB (on the p-type well PW2) via a gate insulating film GF3. The gate electrode GE is the gate electrode of the MOSFET1 used in the peripheral circuit. Sidewall spacers SW3 are formed on the side surface (sidewall) of the gate electrode GE as sidewall insulating films.

[0082] Each of the n-type semiconductor regions SD4 and SD5 is a semiconductor region used for MOSFET1, serving as either the source or drain. One of the n-type semiconductor regions SD4 and SD5 serves as the source region of MOSFET1, and the other serves as the drain region of MOSFET1. In the plan view, the gate electrode GE is located between n-type semiconductor regions SD4 and SD5.

[0083] The n-type semiconductor region SD4 includes n-type semiconductor region E4 and n-type semiconductor region H4. The n-type impurity concentration of n-type semiconductor region H4 is higher than that of n-type semiconductor region E4. The n-type semiconductor region SD5 includes n-type semiconductor region E5 and n-type semiconductor region H5. The n-type impurity concentration of n-type semiconductor region H5 is higher than that of n-type semiconductor region E5. Therefore, each of the n-type semiconductor regions SD4 and SD5 has an LDD structure. The n-type semiconductor regions E4 and E5 are located below the sidewall spacer SW3. In the plan view, n-type semiconductor region E4 is located between n-type semiconductor region H4 and gate electrode GE, and n-type semiconductor region E5 is located between n-type semiconductor region H5 and gate electrode GE. A metal silicide layer SL is formed on each of the gate electrode GE, n-type semiconductor region H4, and n-type semiconductor region H5. (See insulating film BL). Figure 1The corresponding components were not formed on the gate electrode GE, n-type semiconductor region H4, and n-type semiconductor region H5.

[0084] refer to Figure 1 and Figure 2 The insulating film SN and the structure above the insulating film SN will be described.

[0085] An insulating film (silicon nitride film) SN is formed on the main surface of the semiconductor substrate SB to cover the control gate electrode CG, the floating gate electrode FG, the gate electrode GE, the sidewall spacers SW1, SW2, and SW3, the metal silicide layer SL, and the insulating film BL. An insulating film SO is formed on the insulating film SN.

[0086] The insulating film SN is made of silicon nitride. The thickness of the insulating film SN is less than the thickness of the insulating film SO. The insulating film SO is made of a different material than the insulating film SN, and is preferably made of silicon oxide. As the insulating film SO, a low dielectric constant film (low-k film) with a dielectric constant lower than that of silicon oxide can also be used. A layered film including the insulating film SN and the insulating film SO can be used as an interlayer insulating film.

[0087] An insulating film BL is inserted between the floating gate electrode FG and the insulating film SN. Therefore, the floating gate electrode FG does not contact the insulating film SN. The metal silicide layer SL on the control gate electrode CG contacts the insulating film SN. The metal silicide layer SL on the gate electrode GE contacts the insulating film SN.

[0088] A conductive plug PG is formed in a contact hole that penetrates the insulating films SO and SN. A wire M1 is formed on the insulating film SO. The upper surface of the plug PG is in contact with the wire M1.

[0089] The plug PG is positioned above each of the n-type semiconductor regions H1, H3, H4, and H5, the control gate electrode CG, and the gate electrode GE. Figure 1 and Figure 2 The diagram shows plugs PG positioned above n-type semiconductor region H1, n-type semiconductor region H4, and n-type semiconductor region H5. Since plugs PG are not positioned above the floating gate electrode FG, the potential of the floating gate electrode FG is the floating potential.

[0090] The illustrations and descriptions of the structure above the insulating film SO and the conductor M1 are omitted.

[0091] A memory element (memory element or memory cell) MC used as non-volatile memory includes a control transistor (selection transistor) with a control gate electrode CG and a memory transistor (memory transistor) with a floating gate electrode FG. The control transistor and the memory transistor are connected in series. An n-type semiconductor region SD1 serves as the drain region of the control transistor, an n-type semiconductor region SD3 serves as the source region of the memory transistor, and an n-type semiconductor region SD2 serves as both the source region of the control transistor and the drain region of the memory transistor. Alternatively, an n-type semiconductor region SD1 serves as the source region of the control transistor, an n-type conductor region SD3 serves as the drain region of the memory transistor, and an n-type semiconductor region SD2 serves as both the drain region of the control transistor and the source region of the memory transistor. The floating gate electrode FG serves as a charge accumulation layer. Due to the accumulation or retention of charge in the floating gate electrode FG, information can be stored in the memory element MC.

[0092] During a write operation on the memory element MC, charge (in this case, electrons) is injected from the semiconductor substrate SB into the floating gate electrode FG. During an erase operation on the memory element MC, the charge (in this case, electrons) accumulated in the floating gate electrode FG is moved within the semiconductor substrate SB. The threshold voltage of the memory transistor differs between the state where charge has accumulated in the floating gate electrode FG and the state where no charge has accumulated in the floating gate electrode FG; therefore, due to the difference in the threshold voltage of the memory transistor, the information stored in the memory element MC can be read.

[0093] In addition, Figure 1 The image shows a single memory element MC. In practice, multiple memory elements MC are formed in an array on the main surface of a semiconductor substrate SB.

[0094] The case where both the control transistor and the memory transistor are n-channel MOSFETs has been described. It is also possible for both the control transistor and the memory transistor to be p-channel MOSFETs.

[0095] The case where MOSFET1 used in the peripheral circuit is an n-channel MOSFET has already been described. It is also possible for MOSFET1 used in the peripheral circuit to be a p-channel MOSFET. The peripheral circuit may also have both n-channel and p-channel MOSFETs.

[0096] Manufacturing process of semiconductor devices

[0097] refer to Figures 3 to 35 A method for manufacturing a semiconductor device according to an embodiment will be described. Figure 3 It is a process flow indicating the steps involved in forming the insulating film BL. Figure 4, Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 and Figure 34 Each instruction and Figure 1 The corresponding cross-section. Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 and Figure 35 Each instruction and Figure 2 Corresponding cross-sections. In this case, the scenario where the memory element MC is formed in the memory formation region and the n-channel MOSFET1 is formed in the peripheral circuit region will be described. A p-channel MOSFET can be formed instead of the n-channel MOSFET1, or both an n-channel MOSFET1 and a p-channel MOSFET can be formed.

[0098] like Figure 4 and Figure 5 As shown, a semiconductor substrate (semiconductor wafer) SB made of p-type single-crystal silicon or the like is provided (prepared).

[0099] Next, on the main surface of the semiconductor substrate SB, a device isolation region (not shown) defining the active region is formed by STI (shallow trench isolation).

[0100] Next, p-type wells PW1 and PW2 are formed in the semiconductor substrate SB by ion implantation. PW1 and PW2 are spaced apart from each other in a planar view. PW1 is formed from the main surface of the semiconductor substrate SB to a predetermined depth in the memory formation region (see [reference]). Figure 4 The p-type well PW2 is formed in the peripheral circuit region from the main surface of the semiconductor substrate SB to a predetermined depth (see [link]). Figure 5 ).

[0101] Next, as Figure 6 and Figure 7As shown, an insulating film GF is formed on the main surfaces of the semiconductor substrate SB (the front surfaces of p-type well PW1 and p-type well PW2). The insulating film GF is made of silicon oxide film or the like, and can be formed by thermal oxidation or the like.

[0102] Next, a silicon film PS is formed as a conductive film on the main surface of the semiconductor substrate SB, i.e., on the insulating film GF. The silicon film PS is made of polycrystalline silicon and can be formed by chemical vapor deposition (CVD).

[0103] Next, as Figure 8 and Figure 9 As shown, a silicon film PS is patterned using photolithography and dry etching to form a control gate electrode CG, a floating gate electrode FG, and a gate electrode GE. The control gate electrode CG, floating gate electrode FG, and gate electrode GE are fabricated from the patterned silicon film PS and formed on the main surface of the semiconductor substrate SB via an insulating film GF. The control gate electrode CG, floating gate electrode FG, and gate electrode GE are spaced apart from each other.

[0104] The insulating film GF located below the control gate electrode CG is gate insulating film GF1, the insulating film GF located below the floating gate electrode FG is gate insulating film GF2, and the insulating film GF located below the gate electrode GE is gate insulating film GF3. The control gate electrode CG is formed on the p-type well PW1 via gate insulating film GF1. The floating gate electrode FG is formed on the p-type well PW1 via gate insulating film GF2. The gate electrode GE is formed on the p-type well PW2 via gate insulating film GF3.

[0105] Next, as Figure 10 and Figure 11 As shown, n-type semiconductor regions E1, E2, E3, E4 and E5 are formed in the semiconductor substrate SB by using ion implantation.

[0106] n-type semiconductor region E1, n-type semiconductor region E2, and n-type semiconductor region E3 are formed in p-type well PW1 (see [link]). Figure 10 n-type semiconductor regions E4 and E5 are formed in the p-type well PW2 (see [link]). Figure 11 The control gate electrode CG, the floating gate electrode FG, and the gate electrode GE can each be used as a mask to prevent ion implantation.

[0107] Therefore, n-type semiconductor region E4 is formed in a manner self-aligned with one side surface of the gate electrode GE in p-type well PW2, and n-type semiconductor region E5 is formed in a manner self-aligned with the other side surface of the gate electrode GE in p-type well PW2. n-type semiconductor region E1 is formed in a manner self-aligned with one side surface of the control gate electrode CG in p-type well PW1. n-type semiconductor region E3 is formed in a manner self-aligned with one side surface of the floating gate electrode FG in p-type well PW1. n-type semiconductor region E2 is formed in a manner self-aligned with the other side surface of both the control gate electrode CG and the floating gate electrode FG in p-type well PW1. In the plan view, n-type semiconductor region E2 is formed between the control gate electrode CG and the floating gate electrode FG.

[0108] Next, as Figure 12 and Figure 13 As shown, sidewall spacers SW1, SW2, and SW3 are formed. Sidewall spacer SW1 is formed on the side surface (sidewall) of the control gate electrode CG. Sidewall spacer SW2 is formed on the side surface (sidewall) of the floating gate electrode FG. Sidewall spacer SW3 is formed on the side surface (sidewall) of the gate electrode GE.

[0109] For example, an insulating film (e.g., a silicon oxide film) is formed on the entire main surface of the semiconductor substrate SB to cover the control gate electrode CG, the floating gate electrode FG, and the gate electrode GE, and then the insulating film is etched back by anisotropic etching. Therefore, sidewall spacers SW1, SW2, and SW3 can be formed because the insulating film is selectively retained on the side surfaces of each of the control gate electrode CG, the floating gate electrode FG, and the gate electrode GE.

[0110] Next, as Figure 14 and Figure 15 As shown, n-type semiconductor regions H1, H2, H3, H4, and H5 are formed in the semiconductor substrate SB by ion implantation. The control gate electrode CG, sidewall spacer SW1, floating gate electrode FG, sidewall spacer SW2, gate electrode GE, and sidewall spacer SW3 can each be used as a mask to prevent ion implantation.

[0111] Therefore, n-type semiconductor region H4 is formed in a manner self-aligned with the sidewall spacer SW3 on one side surface of the gate electrode GE in p-type well PW2, and n-type semiconductor region H5 is formed in a manner self-aligned with the sidewall spacer SW3 on the other side surface of the gate electrode GE in p-type well PW2. n-type semiconductor region H1 is formed in a manner self-aligned with the sidewall spacer SW1 on one side surface of the control gate electrode CG in p-type well PW1. n-type semiconductor region H3 is formed in a manner self-aligned with the sidewall spacer SW2 on one side surface of the floating gate electrode FG in p-type well PW1. n-type semiconductor region H2 is formed in a manner self-aligned with the sidewall spacers SW1 and SW2 on the other side surface of the control gate electrode CG and the floating gate electrode FG in p-type well PW1. The n-type semiconductor region E2 below the sidewall spacer SW1 is an n-type semiconductor region E2a, and the n-type semiconductor region E2 below the sidewall spacer SW2 is an n-type semiconductor region E2b.

[0112] As a result, an n-type semiconductor region SD1, comprising n-type semiconductor regions E1 and H1, an n-type semiconductor region SD2, comprising n-type semiconductor regions E2a, E2b, and H2, and an n-type semiconductor region SD3, comprising n-type semiconductor regions E3 and H3, are formed in the p-type well PW1. An n-type semiconductor region SD4, comprising n-type semiconductor regions E4 and H4, and an n-type semiconductor region SD5, comprising n-type semiconductor regions E5 and H5, are formed in the p-type well PW2.

[0113] Next, as Figure 16 and Figure 17 As shown, an insulating film (silicon oxide film) BL1 is formed on the main surface of the semiconductor substrate SB to cover the control gate electrode CG, the floating gate electrode FG, the gate electrode GE, sidewall spacers SW1, SW2, SW3, n-type semiconductor regions H1, H2, H3, H4, and H5. Figure 3 (Step S1). The insulating film BL1 is made of silicon oxide and can be formed by CVD or the like. In step S1, the thickness of the insulating film BL1 obtained during the formation of the insulating film BL1 is called the film thickness of the insulating film BL1.

[0114] Next, a photoresist pattern (mask layer) RP1 is formed on the insulating film BL1 using photolithography. Figure 3 Step S2 in the process.

[0115] The photoresist pattern RP1 has a floating gate electrode FG located therein in the planar view. In other words, in the planar view, the floating gate electrode FG completely overlaps with the photoresist pattern RP1. Figure 16 In the case of [specific configuration], in the plan view, the floating gate electrode FG and the sidewall spacer SW2 are located inside the photoresist pattern RP1. In the plan view, the gate electrode CG, sidewall spacer SW1, gate electrode GE, and sidewall spacer SW3 are controlled to not overlap with the photoresist pattern RP1.

[0116] Next, as Figure 18 and Figure 19 As shown, using the photoresist pattern RP1 as an etching mask, isotropic etching is performed on the insulating film BL1 exposed from the photoresist pattern RP1. Figure 3 (Step S3 in the process). Through the isotropic etching step in step S3, the thickness of the insulating film BL1 exposed from the photoresist pattern RP1 is reduced.

[0117] Specifically, the thickness T2 of the insulating film BL1 obtained immediately after the isotropic etching step in step S3 is less than the thickness T1 of the insulating film BL1 obtained immediately before the isotropic etching step in step S3. Here, thickness T1 and thickness T2 each correspond to the thickness of the insulating film BL1 not covered by the photoresist pattern RP1. Furthermore, thickness T1 is substantially the same as the film thickness of the insulating film BL1.

[0118] However, the etching amount (etching thickness) of the insulating film BL1 in the isotropic etching step of step S3 is less than the thickness T1 of the insulating film BL1 immediately before performing the isotropic etching step of step S3. Therefore, although the thickness of the insulating film BL1 not covered by the photoresist pattern RP1 is reduced due to the isotropic etching step of step S3, it does not become zero, and the insulating film BL1 remains delaminated even after the isotropic etching step of step S3 ends. In other words, the thickness T2 is greater than zero. Therefore, after the isotropic etching step of step S3 and before the anisotropic etching step of step S4, the control gate electrode CG, floating gate electrode FG, gate electrode GE, sidewall spacers SW1, SW2, SW3, n-type semiconductor regions H1, H2, H3, H4, and H5 are covered by the insulating film BL1 and are not exposed.

[0119] The etching amount (etching thickness) of the insulating film BL1 in the isotropic etching step S3 refers to the reduction in the thickness of the insulating film BL1 in the isotropic etching step S3. That is, the etching amount (etching thickness) of the insulating film BL1 in the isotropic etching step S3 corresponds to the difference (T1-T2) between the thickness T1 of the insulating film BL1 obtained immediately before performing the isotropic etching step S3 and the thickness T2 of the insulating film BL1 obtained immediately after performing the isotropic etching step S3.

[0120] Next, as Figure 20 and Figure 21 As shown, the photoresist pattern RP1 was used as an etching mask to perform anisotropic etching on the insulating film BL1. Figure 3 (Step S4). Through the anisotropic etching step in step S4, the insulating film BL1 exposed from the photoresist pattern RP1 is removed, and the insulating film BL1 remains below the photoresist pattern RP1. With the insulating film BL1 remaining below the photoresist pattern RP1, the insulating film BL is formed. The planar dimensions and planar position of the insulating film BL substantially correspond to the planar dimensions and planar position of the photoresist pattern RP1. The thickness of the insulating film BL is substantially the same as the film thickness of the insulating film BL1 in step S1.

[0121] The insulating film BL is formed to at least cover the floating gate electrode FG, and preferably covers the floating gate electrode FG and the sidewall spacer SW2. The control gate electrode CG and the gate electrode GE are not covered by the insulating film BL. In the plan view, the floating gate electrode FG completely overlaps with the insulating film BL, while the control gate electrode CG and the gate electrode GE do not overlap with the insulating film BL.

[0122] The anisotropic etching step in step S4 removes the insulating film BL1 not covered by the photoresist pattern RP1; that is, in the planar view, the entire insulating film BL1 not covered by the photoresist pattern RP1 is removed. As a result, by performing the anisotropic etching step in step S4, the upper surfaces of the control gate electrode CG, the gate electrode GE, the n-type semiconductor region H1, the n-type semiconductor region H2, the n-type semiconductor region H3, the n-type semiconductor region H4, and the n-type semiconductor region H5 are exposed.

[0123] Note that in Figure 20In this case, the insulating film BL overlaps with a portion of the upper surface of the n-type semiconductor region H2 and a portion of the upper surface of the n-type semiconductor region H3. In this case, the upper surface of the n-type semiconductor region H2 has a portion covered by the insulating film BL and a portion not covered by the insulating film BL, and the upper surface of the n-type semiconductor region H3 has a portion covered by the insulating film BL and a portion not covered by the insulating film BL.

[0124] Since the insulating film BL1 exposed from the photoresist pattern RP1 is removed by the isotropic etching step in step S3 and the anisotropic etching step in step S4, the insulating film BL can have a stepped or inclined surface DS formed on its end.

[0125] Next, remove the photoresist pattern RP1 ( Figure 3 Step S5 in the process.

[0126] Next, as Figure 22 and Figure 23 As shown, a metal film ME is formed on the main surface (the entire surface of the main surface) of the semiconductor substrate SB to cover the control gate electrode CG, the floating gate electrode FG, the gate electrode GE, sidewall spacers SW1, SW2, SW3, n-type semiconductor regions H1, H2, H3, H4, and H5, and the insulating film BL. The metal film ME is made of, for example, a cobalt film, a nickel film, or a nickel-platinum alloy film, and can be formed by sputtering or the like.

[0127] The metal film ME is in contact with the upper surfaces of the control gate electrode CG, the gate electrode GE, the n-type semiconductor region H1, the n-type semiconductor region H2, the n-type semiconductor region H3, the n-type semiconductor region H4, and the n-type semiconductor region H5. Since the insulating film BL is inserted between the metal film ME and the floating gate electrode FG, the metal film ME is not in contact with the floating gate electrode FG.

[0128] Next, the semiconductor substrate SB is heat-treated to allow the corresponding upper portions of the control gate electrode CG, gate electrode GE, n-type semiconductor regions H1, H2, H3, H4, and H5 to react with the metal film ME. The result is as follows: Figure 24 and Figure 25As shown, a metal silicide layer SL, serving as a reaction layer between silicon and metal, is formed on each of the control gate electrode CG, gate electrode GE, n-type semiconductor regions H1, H2, H3, H4, and H5. Since the insulating film BL is interposed between the metal film ME and the floating gate electrode FG, the metal film ME does not react with the floating gate electrode FG. Therefore, the metal silicide layer SL is not formed on the floating gate electrode FG. In other words, the formation step of the metal silicide layer SL is performed with the insulating film BL covering the floating gate electrode FG, and therefore, the metal silicide layer SL is also not formed on the floating gate electrode FG.

[0129] Next, the unreacted metal film ME is removed by wet etching or other methods. Figure 24 and Figure 25 The image shows the state after the removal of the unreacted metal film ME. Therefore, the metal silicide layer SL is formed using a self-aligned silicide technique.

[0130] Next, as Figure 26 and Figure 27 As shown, an insulating film (silicon nitride film) SN is formed on the main surface of the semiconductor substrate SB to cover the control gate electrode CG, the floating gate electrode FG, the gate electrode GE, sidewall spacers SW1, SW2, SW3, n-type semiconductor regions H1, H2, H3, H4, and H5, the metal silicide layer SL, and the insulating film BL. The insulating film SN is made of silicon nitride and can be formed by CVD or the like.

[0131] An insulating film BL is inserted between the floating gate electrode FG and the insulating film SN, and therefore, the floating gate electrode FG does not contact the insulating film SN. The metal silicide layers SL on the control gate electrode CG, SL on the gate electrode GE, SL on the n-type semiconductor region H1, SL on the n-type semiconductor region H2, SL on the n-type semiconductor region H3, SL on the n-type semiconductor region H4, and SL on the n-type semiconductor region H5 are in contact with the insulating film SN.

[0132] Next, an insulating film SO is formed on the insulating film SN. The thickness of the insulating film SO is greater than the thickness of the insulating film SN. The insulating film SO is made of a different material than the insulating film SN, preferably silicon oxide. A low dielectric constant film can also be used as the insulating film SO. After the insulating film SO is formed, the upper surface of the insulating film SO is planarized as needed by CMP (chemical mechanical polishing) or the like.

[0133] like Figure 26 and Figure 27 As shown, a photoresist pattern (mask layer) RP2 is formed on the insulating film SO by photolithography.

[0134] Next, as Figure 28 and Figure 29 As shown, using a photoresist pattern RP2 as an etching mask, the insulating film SO is etched to form contact holes CT within the insulating film SO. Etching is performed under conditions where the etching rate of the insulating film SN is lower than the etching rate of the insulating film SO. Therefore, contact holes CT penetrate the insulating film SO, and the insulating film SN exposed within the contact holes CT acts as an etching stop film. Thus, the contact holes CT penetrate the insulating film SO but not the insulating film SN.

[0135] Next, as Figure 30 and Figure 31 As shown, using a photoresist pattern RP2 as an etching mask, the insulating film SN exposed from the insulating film SO is etched. At this time, etching of the insulating film SN is performed under the condition that the etching rate of the insulating film SN is greater than the etching rate of the insulating film SO. Therefore, the contact hole CT penetrates the insulating film SN, and correspondingly, the metal silicide layer SL is exposed in the contact hole CT. As a result, a contact hole CT is formed that penetrates both the insulating film SO and the insulating film SN.

[0136] Next, as Figure 32 and Figure 33 As shown, a conductive plug PG is formed in the contact hole CT.

[0137] For example, a barrier conductor film is formed on the bottom surface of the contact hole CT, the side surface of the contact hole CT, and the upper surface of the insulating film SO. Next, a main conductive film made of tungsten or the like is formed on the barrier conductor film to bury the contact hole CT. Subsequently, the main conductive film and the barrier conductor film disposed outside the contact hole CT are removed by CMP or the like. Thus, the plug PG can be formed.

[0138] Next, as Figure 32 and Figure 33 As shown, a conductor M1 is formed on an insulating film SO. For example, a conductor film is formed on the insulating film SO. Subsequently, the conductor film is patterned by photolithography and etching, thereby forming the conductor M1 made of the conductor film. As the conductor M1, aluminum wire is preferred, but conductors using other metallic materials (e.g., tungsten wire) can also be used. In addition, copper wire formed by damascene technology can also be used as the conductor M1.

[0139] The illustrations and descriptions of the steps for further forming an insulating film and a wire on the conductor M1 and the insulating film SO will be omitted.

[0140] Research Background

[0141] The inventors have investigated a non-volatile memory with a floating gate electrode. In a non-volatile memory with a floating gate electrode, information can be stored therein by accumulating charge in the floating gate electrode. Therefore, it is important to enhance the charge retention characteristics of the non-volatile memory, and it is necessary to prevent charge from unintentionally flowing out of the floating gate electrode from outside the floating gate electrode.

[0142] According to the inventors' research, a phenomenon was found where charge (in this case, electrons) moves from the floating gate electrode FG through the insulating film BL to the insulating film SN, which is a cause of the reduced charge retention characteristics of non-volatile memory. Since the hydrogen content of the silicon nitride film is greater than that of the silicon oxide film, the silicon nitride film has trap sites (positively charged trap sites) attributable to hydrogen. The insulating film BL, made of silicon oxide, is interposed between the floating gate electrode FG and the insulating film SN, made of silicon nitride. Therefore, when the thickness of the insulating film BL is small, the charge (in this case, electrons) accumulated in the floating gate electrode FG passes through the insulating film BL (silicon oxide film) and moves to the insulating film SN (silicon nitride film), and can be trapped in the trap sites in the insulating film SN. As the thickness of the insulating film BL decreases, the phenomenon of charge accumulated in the floating gate electrode FG passing through the insulating film BL and being trapped in the insulating film SN becomes more likely.

[0143] To prevent the charge accumulated in the floating gate electrode FG from passing through the insulating film BL and being trapped in the insulating film SN, increasing the thickness of the insulating film BL is effective. The greater the thickness of the insulating film BL, the greater the distance between the floating gate electrode FG and the insulating film SN (silicon nitride film), thus reducing the likelihood of the charge accumulated in the floating gate electrode FG passing through the insulating film BL and moving to the insulating film SN. Therefore, increasing the thickness of the insulating film BL enhances the charge retention characteristics of the non-volatile memory. However, with increased insulating film BL thickness, the semiconductor device manufacturing process requires further improvements and innovations. Otherwise, defects may occur in the semiconductor device, as is clear from the inventors' research.

[0144] Figure 34 It is a process flow indicating a part of the manufacturing process of the semiconductor device of the first research example studied by the inventor, and corresponds to Figure 3 . Figures 35 to 39 This is a cross-sectional view showing the main parts of the manufacturing process of a semiconductor device according to a first research example studied by the inventors. Figure 35 , Figure 37 and Figure 39 It shows the relationship with Figure 1 The corresponding cross-section, and Figure 36and Figure 38 It shows the relationship with Figure 2 The corresponding cross-section.

[0145] like Figure 14 and Figure 15 As shown, after the processes of forming n-type semiconductor regions H1, H2, H3, H4, and H5, in the case of the first research example, as... Figure 35 and Figure 36 As shown, an insulating film BL101 corresponding to the insulating film BL1 is formed. Figure 34 (Step S101). An insulating film BL101 is formed on the main surface of the semiconductor substrate SB to cover the control gate electrode CG, the floating gate electrode FG, the gate electrode GE, sidewall spacers SW1, SW2, SW3, n-type semiconductor regions H1, H2, H3, H4, and H5. Similar to the insulating film BL1, the insulating film BL101 is made of silicon oxide, but the film thickness of the insulating film BL101 is less than that of the insulating film BL1.

[0146] Next, a photoresist pattern RP1 is formed on the insulating film BL101 using photolithography. Figure 34 Step S102 in the process.

[0147] Next, in the case of the first study example, such as Figure 37 and Figure 38 As shown, using the photoresist pattern RP1 as an etching mask, anisotropic etching is performed on the insulating film BL101 exposed from the photoresist pattern RP1. Figure 34 (Step S104 in the first research example). Specifically, in the case of the first research example, after the formation of the photoresist pattern RP1 and before the removal of the photoresist pattern RP1, the isotropic etching step is not performed on the insulating film BL101, but the anisotropic etching step in step S104 is performed on the insulating film BL101.

[0148] The anisotropic etching step in step S104 removes the insulating film BL101 exposed from the photoresist pattern RP1, while retaining the insulating film BL101 beneath the photoresist pattern RP1. The retained insulating film BL101 beneath the photoresist pattern RP1 causes the formation of insulating film BL2. Insulating film BL2 corresponds to insulating film BL, but the thickness of insulating film BL2 is less than the thickness of insulating film BL. This is because the thickness of insulating film BL101 is less than the thickness of insulating film BL1. Insulating film BL2 is formed to cover the floating gate electrode FG and the sidewall spacer SW2. The control gate electrode CG and the gate electrode GE are not covered by insulating film BL2.

[0149] The anisotropic etching step in step S104 removes the insulating film BL101 that is not covered by the photoresist pattern RP1, thereby exposing the upper surfaces of the control gate electrode CG, the gate electrode GE, the n-type semiconductor region H1, the n-type semiconductor region H2, the n-type semiconductor region H3, the n-type semiconductor region H4, and the n-type semiconductor region H5.

[0150] Next, remove the photoresist pattern RP1 ( Figure 34 Step S105 in the process.

[0151] Then, the metal film (ME) formation step and subsequent steps are performed. As a result, a metal film (ME) is obtained. Figure 32 The corresponding structure Figure 39 The structure.

[0152] In the case of the first research example, due to the small thickness of the insulating film BL101, the thickness of the insulating film BL2 included in the manufactured semiconductor device is inevitably also small. With a small thickness of the insulating film BL2, there is a concern that the charge accumulated in the floating gate electrode FG may pass through the insulating film BL2 and be trapped in the insulating film SN. Therefore, the charge retention characteristics of the non-volatile memory may be reduced.

[0153] refer to Figures 40 to 45 This section describes the case where the film thickness of insulating film BL101 is increased. The case where the film thickness of insulating film BL101 is increased is referred to as the second research example. Also in the case of the second research example, the application... Figure 34 The processing flow in the process. Figure 40 , Figure 42 and Figure 44 It shows the relationship with Figure 1 The corresponding cross-section, and Figure 41 , Figure 43 and Figure 45 It shows the relationship with Figure 2 The corresponding cross-section.

[0154] like Figure 14 and Figure 15 As shown, after performing the process of forming n-type semiconductor regions H1, H2, H3, H4, and H5, in the case of the second research example, as... Figure 40 and Figure 41 As shown, an insulating film BL101 is formed ( Figure 34 Step S101 in the second study example ( Figure 40 and Figure 41 The insulating film BL101 in the first study example has a film thickness greater than that in the first study example. Figure 35and Figure 36 The film thickness of the insulating film BL101 in the second study example (). Figure 40 and Figure 41 The film thickness of the insulating film BL101 in the example () is similar to that in the embodiment () Figure 16 and Figure 17 The thickness of the insulating film BL1 in the ) is basically the same.

[0155] Next, a photoresist pattern RP1 (in step S102) is formed on the insulating film BL101 by photolithography. Figure 34 ).

[0156] Next, in the case of the second study example, such as Figure 42 and Figure 43 As shown, anisotropic etching was performed on the insulating film BL101 exposed from the photoresist pattern RP1 using the photoresist pattern RP1 as an etching mask. Figure 34 In step S104 of the study, specifically, in the case of the second study example, after the formation of the photoresist pattern RP1 and before the removal of the photoresist pattern RP1, the isotropic etching step is not performed on the insulating film BL101, but the anisotropic etching step in step S104 is performed on the insulating film BL101.

[0157] The insulating film BL101 exposed from the photoresist pattern RP1 is removed by the anisotropic etching step in step S104, and the insulating film BL101 remains below the photoresist pattern RP1. The insulating film BL101 remaining below the photoresist pattern RP1 causes the formation of the insulating film BL2. Figure 42 (Second Research Example) The thickness of the insulating film BL2 shown is greater than Figure 37 The thickness of the insulating film BL2 shown in the first research example is because... Figure 40 (Second Research Example) The insulating film BL101 shown has a film thickness greater than Figure 35 The thickness of the insulating film BL101 is shown in the first research example. The insulating film BL2 is formed to cover the floating gate electrode FG and the sidewall spacer SW2. The control gate electrode CG and the gate electrode GE are not covered by the insulating film BL2.

[0158] The anisotropic etching step in step S104 removes the insulating film BL101 that is not covered by the photoresist pattern RP1, thereby exposing the upper surfaces of the control gate electrode CG, the gate electrode GE, the n-type semiconductor region H1, the n-type semiconductor region H2, the n-type semiconductor region H3, the n-type semiconductor region H4, and the n-type semiconductor region H5.

[0159] In the case of the second research example, when the anisotropic etching step in step S104 ends, as Figure 42 and Figure 43 As shown, the insulating film BL101 is retained in the shape of a sidewall spacer on the side surfaces of sidewall spacers SW1 and SW3, thereby forming sidewall spacers SW101 and SW103. Sidewall spacer SW101 (see...) Figure 42 The insulating film BL101 is formed by the spacer SW1 remaining on the side surface of the sidewall spacer SW1. Sidewall spacer SW103 (see...) Figure 43 It is formed by an insulating film BL101 retained on the side surface of the sidewall spacer SW3. Figure 42 In this case, the height of the sidewall spacer SW101 is lower than the height of the sidewall spacer SW1. Figure 43 In this case, the height of the sidewall spacer SW103 is lower than the height of the sidewall spacer SW3.

[0160] The reasons for the formation of sidewall spacers SW101 and SW103 will be described below.

[0161] When the insulating film BL101 is formed in step S101, if the thickness of the insulating film BL101 is large, the thicknesses of the insulating film BL101 on the side surfaces of sidewall spacers SW1, SW2, and SW3 will inevitably be large. When anisotropic etching is performed on the insulating film BL101 in step S104 when the thicknesses of the insulating film BL101 on the side surfaces of sidewall spacers SW1 and SW3 are large, it is difficult to completely remove the insulating film BL101 on the side surfaces of sidewall spacers SW1 and SW3. Therefore, the insulating film BL101 retained after the anisotropic etching step in step S104 causes the formation of sidewall spacers SW101 and SW103.

[0162] If the over-etching amount in the anisotropic etching step of step S104 is increased, it can be considered that the formation of sidewall spacers SW101 and SW103 can be prevented. However, if the over-etching amount in the anisotropic etching step of step S104 is increased, there is concern that the exposed semiconductor substrate SB (n-type semiconductor regions H1, H2, H3, H4, and H5) may be excessively damaged due to over-etching. Therefore, it is undesirable to increase the over-etching amount in the anisotropic etching step of step S104 to prevent the formation of sidewall spacers SW101 and SW103.

[0163] After the anisotropic etching step in step S104, the photoresist pattern RP1 is removed. Figure 34 (Step S105 in the text). Subsequently, as... Figure 44 and Figure 45 As shown, the metal film ME and heat treatment steps are performed to form a metal silicide layer SL. Specifically, the metal silicide layer SL is formed by a self-aligned silicide process.

[0164] In the case where a metal silicide layer SL is formed by a self-aligned silicide process in the presence of sidewall spacers SW101, such as Figure 44 As shown, the upper surfaces of the n-type semiconductor region H1 covered by the sidewall spacer SW101 and the upper surfaces of the n-type semiconductor region H2 covered by the sidewall spacer SW101 are not covered with a metal silicide layer SL. When the metal silicide layer SL is formed by a self-aligned silicide process in the presence of the sidewall spacer SW103, as... Figure 45 As shown, the upper surface of the n-type semiconductor region H4 covered by the sidewall spacer SW103 and the upper surface of the n-type semiconductor region H5 covered by the sidewall spacer SW103 are not covered by a metal silicide layer SL.

[0165] Therefore, when the sidewall spacer SW101 is formed, compared to the case where the sidewall spacer SW101 is not formed, the areas of the metal silicide SL formed on the n-type semiconductor region H1 and the area of ​​the metal silicide SL formed on the n-type semiconductor region H2 are smaller, and therefore, the source resistance and drain resistance of the control transistor increase. Similarly, when the sidewall spacer SW103 is formed, compared to the case where the sidewall spacer SW103 is not formed, the areas of the metal silicide SL formed on the n-type semiconductor region H4 and the area of ​​the metal silicide SL formed on the n-type semiconductor region H5 are smaller, and therefore, the source resistance and drain resistance of MOSFET1 increase. The increase in the source resistance and drain resistance of the transistor leads to a decrease in the performance of the semiconductor device including such a transistor.

[0166] Furthermore, when forming the sidewall spacer SW101, it is difficult to precisely control the width W101 of the sidewall spacer SW101 (see...). Figure 42 Furthermore, the width W101 of the sidewall spacer SW101 may vary. Therefore, in the case of forming the sidewall spacer SW101, the width W201 of the metal silicide SL formed on the n-type semiconductor region H1 (see...) Figure 44 ) and the width W202 of the metal silicide SL formed on the n-type semiconductor region H2 (see Figure 44The source and drain resistances of the control transistor may change. Similarly, in the case of forming the sidewall spacer SW103, it is difficult to precisely control the width W103 of the sidewall spacer SW103 (see...). Figure 43 Furthermore, the width W103 of the sidewall spacer SW103 may vary. Therefore, in the case of forming the sidewall spacer SW103, the width W204 of the metal silicide SL formed on the n-type semiconductor region H4 (see...) Figure 45 ) and the width W205 of the metal silicide SL formed on the n-type semiconductor region H5 (see Figure 45 The source and drain resistances of MOSFET1 are likely to change, which will cause variations in their respective values. Variations in the source and drain resistances of the transistor degrade the performance of the semiconductor device including the associated transistor. Note that widths W101, W201, and W202 correspond to dimensions (widths) along directions parallel to the gate length direction of the control gate electrode CG. Widths W103, W204, and W205 correspond to dimensions (widths) along directions parallel to the gate length direction of the gate electrode GE.

[0167] Therefore, in order to improve the performance of semiconductor devices, it is desirable to prevent the formation of sidewall spacers SW101 and SW103.

[0168] exist Figures 35 to 36 In the case of the first research example shown, the insulating film BL101 has a smaller film thickness, thereby preventing the formation of sidewall spacers SW101 and SW103. This is because, when the insulating film BL101 is formed in step S101, if the film thickness of the insulating film BL101 is smaller, the thickness of the insulating film BL101 on the side surface of sidewall spacer SW1, the side surface of sidewall spacer SW2, and the side surface of sidewall spacer SW3 will inevitably become smaller. When anisotropic etching of the insulating film BL10 is performed in step S104 with the insulating film BL101 on the side surface of sidewall spacer SW1 and the side surface of sidewall spacer SW3 having a smaller thickness, etching residues of the insulating film BL101 are less likely to remain on the side surfaces of sidewall spacers SW1 and SW3. As a result, the formation of sidewall spacers SW101 and SW103 can be prevented.

[0169] However, with a small thickness of the insulating film BL101, the thickness of the insulating film BL2 included in the manufactured semiconductor device is inevitably also small. This means that the charge accumulated in the floating gate electrode FG may pass through the insulating film BL2 and be trapped in the insulating film SN. Due to this phenomenon, there are concerns that the charge retention characteristics of non-volatile memory may be degraded.

[0170] Therefore, in application Figure 34 Under the current process flow, it is difficult to simultaneously increase the thickness of the insulating film BL2 and prevent the formation of sidewall spacers SW101 and SW103.

[0171] Regarding the main features and effects

[0172] In this embodiment, the steps for forming the insulating film BL include step S1 (forming the insulating film BL1), step S2 (forming the photoresist pattern RP1), step S3 (isotropic etching of the insulating film BL1), step S4 (anisotropic etching of the insulating film BL1), and step S5 (removing the photoresist pattern RP1). Therefore, it is possible to simultaneously increase the thickness of the insulating film BL1 and prevent the formation of sidewall spacers SW101 and SW103. This will be described in more detail below.

[0173] If the thickness of the insulating film BL1 in step S1 is large, the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW1, the side surface of the sidewall spacer SW2, and the side surface of the sidewall spacer SW3 will inevitably increase. In step S3, isotropic etching is performed on the insulating film BL1 exposed from the photoresist pattern RP1, thereby reducing the thickness of the insulating film BL1 exposed from the photoresist pattern RP1. Step S3 is performed with the insulating films BL1 on the side surface of the sidewall spacer SW1 and the side surface of the sidewall spacer SW3 exposed from the photoresist pattern RP1. Therefore, through the isotropic etching step in step S3, the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW1 and the side surface of the sidewall spacer SW3 is reduced.

[0174] Note that in step S3, since it is not anisotropic etching but isotropic etching performed in step S3, the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW1 and the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW3 can be reduced. It is difficult to reduce the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW1 and the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW3 by anisotropic etching.

[0175] Following the isotropic etching step in step S3, the anisotropic etching step in step S4 is performed. Therefore, even if the insulating film BL1 has a large thickness in step S1, the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW1 and the side surface of the sidewall spacer SW3 can be reduced by the isotropic etching in step S3, and then the anisotropic etching step in step S4 is performed. When the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW1 and the side surface of the sidewall spacer SW3 is small, anisotropic etching can be performed on the insulating film BL1 in step S4, making it unlikely that etching residues of the insulating film BL1 will remain on the side surfaces of the sidewall spacers SW1 and SW3 when step S4 ends. Therefore, the formation of sidewall spacer SW101 due to etching residues of the insulating film BL1 on the side surface of the sidewall spacer SW1 can be prevented. In addition, it can prevent the formation of sidewall spacers SW103 due to etching residues of insulating film BL1 on the side surface of sidewall spacers SW3.

[0176] In this embodiment, after performing the forming step of insulating film BL1 in step S1 and the forming step of photoresist pattern RP1 in step S2, and before performing the anisotropic etching step in step S4, the isotropic etching step in step S3 is performed, resulting in a reduction in the thickness of insulating film BL1 on the side surface of sidewall spacer SW1 and the thickness of insulating film BL1 on the side surface of sidewall spacer SW3. Due to this reduction, even if the film thickness of insulating film BL1 is large in step S1, the formation of sidewall spacer SW101 on the side surface of sidewall spacer SW1 and sidewall spacer SW103 on the side surface of sidewall spacer SW3 can be prevented when step S4 ends. As a result, it is possible to simultaneously increase the thickness of insulating film BL1 and form sidewall spacers SW101 and SW103.

[0177] Therefore, in this embodiment, the thickness of the insulating film BL1 in step S1 can be increased, thereby suppressing or preventing the phenomenon that charge (in this case, electrons) accumulated in the floating gate electrode FG passes through the insulating film BL and is trapped in the insulating film SN in the manufactured semiconductor device. Therefore, the charge retention characteristics of the non-volatile memory can be enhanced. Therefore, the performance of the semiconductor device including this non-volatile memory can be improved.

[0178] Furthermore, in this embodiment, the formation of the sidewall spacer SW101 can be prevented, thereby preventing the area of ​​the metal silicide SL formed on the n-type semiconductor region H1 and the area of ​​the metal silicide SL formed on the n-type semiconductor region H2 from decreasing due to the presence of the sidewall spacer SW101. As a result, the source resistance and drain resistance of the control transistor can be suppressed. Furthermore, since the formation of the sidewall spacer SW101 can be prevented, the width W1 of the metal silicide SL formed on the n-type semiconductor region H1 (see...) can be prevented. Figure 24 ) and the width W2 of the metal silicide SL formed on the n-type semiconductor region H2 (see Figure 24 The resistance varies due to the presence of the sidewall spacer SW101. As a result, variations in the source and drain resistances of the control transistor can be suppressed or prevented. Therefore, the performance of the semiconductor device including this non-volatile memory can be improved.

[0179] Furthermore, in this embodiment, since the formation of the sidewall spacer SW103 can be prevented, the area of ​​the metal silicide SL formed on the n-type semiconductor region H4 and the area of ​​the metal silicide SL formed on the n-type semiconductor region H5 can be prevented from decreasing due to the presence of the sidewall spacer SW103. As a result, the source resistance and drain resistance of MOSFET1 can be suppressed. Furthermore, since the formation of the sidewall spacer SW103 can be prevented, the width W4 of the metal silicide SL formed on the n-type semiconductor region H4 (see...) can be prevented. Figure 25 ) and the width W5 of the metal silicide SL formed on the n-type semiconductor region H5 (see Figure 25 The source and drain resistances of MOSFET1 change due to the presence of the sidewall spacer SW103. As a result, changes in the source and drain resistances of MOSFET1 can be suppressed or prevented. Therefore, the performance of the semiconductor device including this non-volatile memory and peripheral circuitry can be improved.

[0180] In step S1, the thickness of the insulating film BL1 is preferably equal to or greater than 70 nm. Therefore, increasing the thickness of the insulating film BL between the insulating film SN and the floating gate electrode FG (70 nm or greater) can precisely suppress or prevent the phenomenon where accumulated charge (in this case, electrons) in the floating gate electrode FG passes through the insulating film BL and is trapped in the insulating film SN. Thus, the charge retention characteristics of the non-volatile memory can be precisely enhanced.

[0181] In step S3, the etching amount (etching thickness) of the insulating film BL1 in the isotropic etching step is preferably equal to or greater than 20% of the film thickness of the insulating film BL1 in step S1. For example, if the film thickness of the insulating film BL1 in step S1 is 100 nm, the etching amount of the insulating film BL1 in the isotropic etching step in step S3 is preferably equal to or greater than 20 nm. Therefore, through the isotropic etching step in step S3, the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW1 and the thickness of the insulating film BL1 on the side surface of the sidewall spacer SW3 can be precisely reduced. Therefore, when the anisotropic etching step in step S4 ends, the formation of sidewall spacer SW101 on the side surface of the sidewall spacer SW1 and sidewall spacer SW103 on the side surface of the sidewall spacer SW3 can be prevented.

[0182] Here, in the second research example described above, it is assumed that an isotropic etching step is performed instead of the anisotropic etching step in step S104. In this case, only the insulating film BL101 exposed from the photoresist pattern RP1 is removed by isotropic etching. In this case, the amount of isotropic etching of the insulating film BL101 exposed from the photoresist pattern RP1 increases, therefore, there is concern that the width of the sidewall spacer SW1 may become smaller than the desired value.

[0183] In this embodiment, the insulating film BL1 exposed from the photoresist pattern RP1 is removed by the isotropic etching step in step S3 and the anisotropic etching step in step S4. Therefore, the defect that the width of the sidewall spacer SW1 becomes smaller than the desired value due to the increased amount of isotropic etching of the insulating film BL1 exposed from the photoresist pattern RP1 can be prevented.

[0184] Therefore, the etching amount of the insulating film BL1 in the isotropic etching step of step S3 is preferably equal to or greater than 20% and equal to or less than 70% of the film thickness of the insulating film BL1 in step S1. For example, if the film thickness of the insulating film BL1 in step S1 is 100 nm, the etching amount of the insulating film BL1 in the isotropic etching step of step S3 is preferably equal to or greater than 20 nm and equal to or less than 70 nm. Therefore, it is possible to prevent the defect that the width of the sidewall spacer SW1 becomes smaller than the desired value due to the increase in the amount of isotropic etching of the relevant insulating film BL1.

[0185] Furthermore, in the anisotropic etching step of step S4, it is preferable that the insulating film BL1 is not retained on the side surfaces of the sidewall spacers SW1 and SW3. Specifically, at the end of the anisotropic etching step in step S4, it is preferable that the sidewall spacers SW101 are not formed on the side surface of the sidewall spacers SW1, and preferably that the sidewall spacers SW103 are not formed on the side surface of the sidewall spacers SW3. Therefore, the aforementioned defects caused by the presence of the sidewall spacers SW101 and SW103 can be precisely prevented. Therefore, at the end of the anisotropic etching step in step S4, it is preferable that the etching amount of the insulating film BL1 is set in the isotropic etching step in step S3 so that the insulating film BL1 is not retained on the side surfaces of the sidewall spacers SW1 and SW3.

[0186] However, in the anisotropic etching step of step S4, a portion of the insulating film BL1 may also remain on the side surfaces of the sidewall spacers SW1 and SW3. Specifically, at the end of the anisotropic etching step in step S4, sidewall spacers SW101 may be formed on the side surface of sidewall spacers SW1, and sidewall spacers SW103 may be formed on the side surface of sidewall spacers SW3. However, compared to not performing the isotropic etching in step S3, performing the isotropic etching in step S3 can reduce the width W101 of sidewall spacers SW101 and the width W103 of sidewall spacers SW103 formed in step S4. Therefore, compared to not performing the isotropic etching in step S3, performing the isotropic etching in step S3 can prevent defects caused by the presence of sidewall spacers SW101 and sidewall spacers SW103.

[0187] Note that at the end of the anisotropic etching step in step S4, when the sidewall spacer SW101 is formed on the side surface of the sidewall spacer SW1, the width W101 of the sidewall spacer SW101 (specifically, the width of the insulating film BL1 retained on the side surface of the sidewall spacer SW1) is preferably equal to or less than 10 nm. At the end of the anisotropic etching step in step S4, when the sidewall spacer SW103 is formed on the side surface of the sidewall spacer SW3, the width W103 of the sidewall spacer SW103 (specifically, the width of the insulating film BL1 retained on the side surface of the sidewall spacer SW3) is preferably equal to or less than 10 nm. Specifically, the etching amount of the insulating film BL1 in the isotropic etching step in step S3 is preferably set such that the width W101 of the sidewall spacer SW101 and the width W103 of the sidewall spacer SW103 formed in step S4 are equal to or less than 10 nm. Therefore, defects caused by the presence of sidewall spacer SW101 and defects caused by the presence of sidewall spacer SW103 can be suppressed.

[0188] The invention has been specifically described above based on embodiments. However, it goes without saying that the invention is not limited to the above embodiments, and various modifications and changes can be made within the scope of the invention. Explanation of reference numerals in the attached figures 1: MOSFET BL, BL1, BL2, BL101: Insulating film CG: Control gate electrode E1, E2, E2a, E2b, E3, E4, E5: n-type semiconductor regions H1, H2, H3, H4, H5: n-type semiconductor regions FG: Floating gate electrode GE: Gate electrode GF: Insulating film GF1, GF2, GF3: Gate insulating film M1: Wire MC: Memory Element PG: Plug PS: Silicone film PW1, PW2: p-type traps SB: Semiconductor substrate SD1, SD2, SD3, SD4, SD5: n-type semiconductor regions SL: Metal silicide layer SN: Insulating film SO: Insulating film SW1, SW2, SW3, SW101, SW103: Sidewall spacers

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) Fabrication of a semiconductor substrate having a main surface; (b) A floating gate electrode for storage of a first transistor is formed on the main surface of the semiconductor substrate via a first gate insulating film, and a gate electrode of a second transistor is formed on the main surface of the semiconductor substrate via a second gate insulating film; (c) A first sidewall spacer is formed on the side surface of the floating gate electrode, and a second sidewall spacer is formed on the side surface of the gate electrode; (d) A first semiconductor region of the first transistor and a second semiconductor region of the second transistor are formed in the semiconductor substrate, wherein the first semiconductor region of the first transistor is used as a source or a drain, and the second semiconductor region of the second transistor is used as a source or a drain. (e) After (c) and (d), a silicon oxide film is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the first sidewall spacer and the second sidewall spacer; (f) A mask layer is formed on the silicon oxide film; (g) Using the mask layer as an etching mask, perform isotropic etching on the silicon oxide film; (h) After (g), anisotropic etching is performed on the silicon oxide film using the mask layer as the etching mask; (i) After (h), remove the mask layer; (j) After (i), a metal silicide layer is formed on each of the second semiconductor region and the gate electrode; as well as (k) Following (j), a silicon nitride film is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the first sidewall spacer, and the second sidewall spacer. In step (h), the silicon oxide film exposed from the mask layer is removed by the anisotropic etching, and a first insulating film made of the silicon oxide film retained beneath the mask layer is formed. The first insulating film covers the floating gate electrode, and In the case of (k), the first insulating film is inserted between the floating gate electrode and the silicon nitride film.

2. The method for manufacturing a semiconductor device according to claim 1, Wherein (j) is performed while the first insulating film covers the floating gate electrode, and In (j), a metal-free silicide layer is formed on the floating gate electrode.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising: (l) After (k), a second insulating film is formed on the silicon nitride film; (m) Forming a contact hole that penetrates the second insulating film and the silicon nitride film; as well as (n) After (m), a conductive plug is formed in the contact hole.

4. The method for manufacturing a semiconductor device according to claim 3, The second insulating film is made of a material different from that of the silicon nitride film.

5. The method for manufacturing a semiconductor device according to claim 4, The second insulating film is a silicon oxide film or a low dielectric constant film.

6. The method for manufacturing a semiconductor device according to claim 1, The thickness of the silicon oxide film in (e) is equal to or greater than 70 nm.

7. The method for manufacturing a semiconductor device according to claim 6, The etch thickness of the silicon oxide film in (g) is equal to or greater than 20% of the film thickness of the silicon oxide film in (e).

8. The method for manufacturing a semiconductor device according to claim 6, In (h), the silicon oxide film is not retained on the side surface of the second sidewall spacer.

9. The method for manufacturing a semiconductor device according to claim 6, In (h), the width of the silicon oxide film retained on the side surface of the second sidewall spacer in the first direction is equal to or less than 10 nm, and The first direction is parallel to the gate length direction of the gate electrode.

10. The method for manufacturing a semiconductor device according to claim 1, Wherein (j) includes (j1) A metal film is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the first sidewall spacer, the second sidewall spacer, the first semiconductor region, the second semiconductor region, and the first insulating film. (j2) The metal film is reacted with the second semiconductor region and the gate electrode by heat treatment, thereby forming the metal silicide layer on the second semiconductor region and the gate electrode, and (j3) After (j2), the metal film is removed. In (j1), the metal film is in contact with the second semiconductor region and the gate electrode, and the first insulating film is inserted between the metal film and the floating gate electrode.

11. The method for manufacturing a semiconductor device according to claim 1, The first insulating film covers the floating gate electrode and the first sidewall spacer.

12. The method for manufacturing a semiconductor device according to claim 1, The first insulating film covers a portion of the first semiconductor region, the floating gate electrode, and the first sidewall spacer. In (j), the metal silicide layer is formed on the first semiconductor region that is not covered by the first insulating film.

13. The method for manufacturing a semiconductor device according to claim 1, The first transistor stores information generated due to the accumulation of charge in the floating gate electrode.

14. The method for manufacturing a semiconductor device according to claim 13, The charge mentioned therein is an electron.

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