Semiconductor device, three-dimensional memory structure and method of manufacturing the same

Abstract

The application provides a semiconductor device, a three-dimensional memory structure and a preparation method thereof. The three-dimensional memory structure comprises: a first dielectric layer having a plurality of first grooves arranged alternately; a first conductor extending in a first direction in a meandering manner, and continuously covering the surface of the first dielectric layer in a continuous up-and-down manner, and the parts of adjacent first conductors facing each other in a second direction being staggered; a first stack arranged on the first conductor, and adjacent first stacks being staggered; a second dielectric layer covering the first dielectric layer and the first conductor, and filling between the first stacks, wherein a second groove is formed to expose the surface of each first stack; and a second conductor extending in the second direction in a meandering manner, and continuously covering the sidewall of the second groove and the top wall of the first stack in a continuous up-and-down manner, and the parts of adjacent second conductors facing each other in the first direction being staggered up and down. The three-dimensional memory structure can preferably balance the storage density and the reliability of the memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, a three-dimensional memory structure, and a method for fabricating the same. Background Technology

[0002] Phase-change RAM (PCRAM) is a novel type of memory (three-dimensional memory) that utilizes chalcogenide phase-change materials, which exhibit different resistance characteristics in their amorphous and crystalline states. In practical applications of PCRAM, Joule heating is generated when current passes through the heating electrodes and the phase-change material. The phase-change material undergoes a phase change due to this Joule heating. For high-density three-dimensional PCRAMs, due to the small distance between adjacent phase-change cells, a large amount of heat accumulates inside the memory array as it continuously performs SET (set) or RESET (reset) operations, leading to thermal crosstalk and affecting device reliability. Furthermore, the dense arrangement of wires (word lines and bit lines) in high-density PCRAMs results in parasitic capacitance, which causes resistance drift and reduces device reliability.

[0003] Therefore, the key is to improve the storage density (densification) of memory while ensuring its performance and reliability, or to improve the storage density while ensuring the performance and reliability of memory. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device, a three-dimensional memory structure and a method for fabricating the same, which can better balance storage density and memory performance and reliability.

[0005] To solve the above-mentioned technical problems, the present invention provides a three-dimensional storage structure, comprising:

[0006] A first dielectric layer has a plurality of first grooves arranged alternately along a first direction and a second direction on its surface. The longitudinal cross-sectional shape of each of the first grooves along the first direction and the second direction is an inverted trapezoidal shape. The first direction and the second direction are orthogonal.

[0007] A plurality of first wires extend in a zigzag pattern along the first direction and are spaced apart along the second direction. The first wires conformally cover the surface of the first dielectric layer and the inner wall of the first groove in a continuous up-and-down undulating shape. Adjacent first wires are staggered in the portion directly opposite each other along the second direction.

[0008] A plurality of first stacked bodies disposed on the first conductor include a layered gate material layer, a first isolation material layer and a storage material layer, and adjacent first stacked bodies are disposed on the first conductor on the bottom wall of the first groove and on the first conductor on the first dielectric layer between the first grooves, and are staggered.

[0009] A second dielectric layer covers the first dielectric layer and the first wire, and fills the spaces between the first stack bodies. A plurality of second grooves are formed in the second dielectric layer that correspond to and match each of the first grooves. The bottom of the second grooves and the second dielectric layer between the second grooves expose the surfaces of each of the first stack bodies.

[0010] A plurality of second wires extend in a zigzag pattern along the second direction and are spaced apart along the first direction. The second wires conform to the shape of covering the sidewall of the second groove and the top wall of the first stack body in a continuous up-and-down undulating pattern. Adjacent second wires are staggered in the portion that is directly opposite each other along the first direction.

[0011] Optionally, the angle between the sidewalls of the first groove and the second groove along the first direction and the second direction and their respective bottom walls is 115° to 155°.

[0012] Optional,

[0013] The gating material layer is located below the first insulating material layer, and the storage material layer is located above the first insulating material layer, or...

[0014] The gating material layer is located above the first isolation material layer, and the storage material layer is located below the first isolation material layer.

[0015] Optionally, a second insulating material layer may be provided between the gate material layer and the adjacent conductor and / or between the storage material layer and the adjacent conductor.

[0016] Optionally, the material of the first insulating material layer and / or the second insulating material layer may include carbon.

[0017] Optionally, the second dielectric layer includes an insulating heat insulation layer and an insulating filler layer, the heat insulation layer conformally covering the surface of the first conductor and the sidewalls of the first stack, and the filler layer covering the heat insulation layer.

[0018] Optionally, the three-dimensional storage structure further includes:

[0019] A plurality of second stacked bodies disposed on the second conductor include a layered gate material layer, a first isolation material layer and a storage material layer, and each of the second stacked bodies is disposed on the second conductor on the first stacked body in an alternating manner.

[0020] A third dielectric layer covers the second dielectric layer and the second wire, and fills the spaces between the second stack bodies. A plurality of third grooves corresponding to and matching each of the second grooves are formed in the third dielectric layer, and the surfaces of each of the second stack bodies are exposed.

[0021] A plurality of third conductors extend in a zigzag pattern along the first direction and are spaced apart along the second direction. The third conductors conformally cover the surface of the third dielectric layer, the sidewall of the third groove, and the top wall of the second stack in an undulating manner. Adjacent third conductors are staggered in the portion facing each other along the second direction.

[0022] Optionally, the storage material layer includes any one of phase change materials, resistive switching materials, magnetoresistive materials, and ferroelectric materials.

[0023] According to another aspect of the present invention, a method for manufacturing a three-dimensional storage structure is also provided, comprising:

[0024] A first dielectric layer is provided, on which a plurality of first island-shaped mask patterns are arranged alternately along a first direction and a second direction, wherein the first direction is orthogonal to the second direction;

[0025] An etching process is performed to form a plurality of first grooves in the first dielectric layer between the first island-shaped mask patterns. The longitudinal cross-sectional shape of each of the first grooves along the first direction and the second direction is an inverted trapezoidal shape.

[0026] A first conductive material layer, a gate material layer, a first insulating material layer, and a storage material layer are sequentially formed to conformally cover the surface of the first dielectric layer and the inner wall of the first groove;

[0027] A patterning process is performed on the first conductive material layer, the gate material layer, the isolation material layer and the storage material layer to form a plurality of spaced first wires and a first stack. The first wires all extend along the first direction, and two adjacent first wires are staggered in the part facing each other along the second direction. The first stack is composed of the gate material layer, the isolation material layer and the storage material layer, and is located on the first wires on the bottom wall of the first groove or on the first dielectric layer between adjacent first grooves.

[0028] A second dielectric layer is formed to cover the first dielectric layer and the first wire and fill the space between the first stack bodies. A patterning process is performed on the second dielectric layer to form a plurality of second grooves that correspond to and match each of the first grooves in the second dielectric layer, and to expose the surface of each of the first stack bodies.

[0029] A second conductive material layer is formed to cover the surface of the first stack and the surface of the second dielectric layer. A patterning process is performed on the second conductive material layer to form a plurality of second wires extending along the second direction, and adjacent two second wires are staggered in the portion facing each other along the first direction.

[0030] Optionally, the steps of forming the first wire and the first stack include:

[0031] Multiple strip-shaped first patterned mask layers are formed on the storage material layer, the first patterned mask layers extending along the first direction, and the multiple first patterned mask layers are spaced apart along the second direction;

[0032] An etching process is performed on the storage material layer, the isolation material layer, the gate material layer and the first conductive material layer to expose the first dielectric layer, and the remaining first conductive material layer is used as the first conductor.

[0033] Remove the first patterned mask layer and form a plurality of strip-shaped second patterned mask layers on the storage material layer. The second patterned mask layers extend along the second direction, and the plurality of second patterned mask layers are spaced apart along the first direction.

[0034] An etching process is performed on the storage material layer, the isolation material layer, and the gate material layer to expose the first dielectric layer and the first conductor, and the remaining storage material layer, the isolation material layer, and the gate material layer are used as the first stack.

[0035] Optionally, the step of performing a patterning process on the second dielectric layer to form the second groove includes:

[0036] A polishing process is performed on the second dielectric layer to form a flat surface;

[0037] A plurality of second island-shaped mask patterns are formed on the second dielectric layer, which are staggered along the first direction and the second direction. The second island-shaped mask patterns are located on the second dielectric layer of the stack.

[0038] An etching process is performed to etch the second island-shaped mask pattern and the second dielectric layer to form the second groove and expose the surfaces of each of the stacks.

[0039] Optionally, after forming the second conductive material layer, a gate material layer, an isolation material layer, and a storage material layer are sequentially formed to conformally cover the surface of the second conductive material layer. A patterning process is then performed on the second conductive material layer, the gate material layer, the isolation material layer, and the storage material layer to form the second conductor and the second stack disposed on the second conductor.

[0040] Optionally, the step of forming the second wire and the second stack includes:

[0041] Multiple strip-shaped third patterned mask layers are formed on the storage material layer, the third patterned mask layers extend along the second direction, and the multiple third patterned mask layers are spaced apart along the first direction;

[0042] An etching process is performed on the storage material layer, the isolation material layer, the gate material layer and the second conductive material layer to expose the second dielectric layer, and the remaining second conductive material layer is used as the second conductor.

[0043] Multiple strip-shaped fourth patterned mask layers are formed on the storage material layer, the fourth patterned mask layers extending along the first direction, and the multiple fourth patterned mask layers are spaced apart along the second direction;

[0044] An etching process is performed on the storage material layer, the isolation material layer, and the gate material layer to expose the second dielectric layer and the second conductor, and the remaining storage material layer, the isolation material layer, and the gate material layer are used as the second stack.

[0045] According to another aspect of the present invention, a semiconductor device is also provided, the semiconductor device comprising the three-dimensional storage structure as described above.

[0046] In summary, the semiconductor device, three-dimensional memory structure, and fabrication method provided in this application include a first dielectric layer with a plurality of first grooves arranged alternately along a first direction and a second direction on the surface of the first dielectric layer. The first grooves are in the shape of an inverted trapezoid, and the first direction and the second direction are orthogonal. A plurality of first conductive lines extend in a zigzag pattern along the first direction and are spaced apart along the second direction. The first conductive lines conformally cover the surface of the first dielectric layer and the inner wall of the first grooves, forming a continuous up-and-down undulating shape. The portions of adjacent first conductive lines facing each other in the second direction are staggered. A plurality of first stacked bodies are disposed on the first conductive lines, including a layered gate material layer, a first isolation material layer, and a storage material layer. Each stack of first stacked components is disposed on a first conductor on the bottom wall of a first groove and on a first dielectric layer between the first grooves, forming an undulating shape. A second dielectric layer covers the first dielectric layer and the first conductors, and fills the spaces between the first stacked components. The second dielectric layer forms several inverted trapezoidal second grooves corresponding to the first grooves. The bottom of the second grooves and the second dielectric layer between the second grooves expose the surfaces of each first stacked component. Several second conductors extend in a zigzag pattern along a second direction and are spaced apart along a first direction. The first conductors conformally cover the surface of the second dielectric layer, the sidewalls of the second grooves, and the top wall of the first stacked components, continuously undulating. The portions of adjacent second conductors facing each other in the first direction are staggered vertically. In the three-dimensional storage structure of this application, the portions of adjacent conductors in the same layer are staggered vertically (higher and lower) along both the first and second directions, and the relative distance between adjacent parallel conductors is increased to reduce parasitic capacitance between conductors, thereby reducing resistance drift and improving the reliability of the three-dimensional storage structure. Furthermore, the storage material layers in adjacent first stacks along the first and second directions within the same layer are staggered vertically, increasing the relative distance between them and thus reducing thermal crosstalk, which also helps improve the reliability of the three-dimensional storage structure. Therefore, compared to the flush arrangement of the wires and stacks, the staggered arrangement of the various parts of the wires and the first stacks can increase the relative distance between the stacks without reducing the storage density. In other words, the three-dimensional storage structure of this application can better balance storage density and memory reliability. Attached Figure Description

[0047] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0048] Figure 1 This is a flowchart of a method for manufacturing a three-dimensional storage structure provided in an embodiment of this application;

[0049] Figures 2a to 2k_5 A schematic diagram of the structure corresponding to the steps of the manufacturing method of the three-dimensional storage structure provided in the embodiments of this application;

[0050] Figure 3a and Figure 3b This is a three-dimensional structural diagram of the three-dimensional storage structure provided in the embodiments of this application.

[0051] In the attached figures: 10-First dielectric layer; 11-First island-shaped mask pattern; 12-First groove; 10a-First top wall; 12a-First bottom wall; 12b-First side wall; 12c-Second side wall; 121-Cross-shaped portion; 122-Corner portion; 13-First conductive material layer; 14-Gating material layer; 15-First isolation material layer; 16-Storage material layer; 21a-First patterned mask layer; 13a-First conductor; 131-Recessed portion; 132-Protruding portion; 21b-Second patterned mask layer; 22-First stack; 23-Second dielectric layer; 24-Second island-shaped mask pattern; 23a-Second groove; 24-Second conductive material layer; 24a-Second conductor; 25a-Third patterned mask layer; 25b-Fourth patterned mask layer; 26-Second stack; 31-Third conductor; X-First direction; Y-Second direction. Detailed Implementation

[0052] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0053] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0054] This application provides a method for manufacturing a three-dimensional storage structure.

[0055] Figure 1 A flowchart illustrating a method for manufacturing a three-dimensional storage structure provided in an embodiment of this application.

[0056] like Figure 1As shown, the manufacturing method of the three-dimensional storage structure provided in this embodiment includes:

[0057] S01: A first dielectric layer is provided, on which a plurality of first island-shaped mask patterns are arranged alternately along a first direction and a second direction, wherein the first direction is orthogonal to the second direction;

[0058] S02: Perform an etching process to form a plurality of first grooves in the first dielectric layer between the first island mask patterns, wherein the longitudinal cross-sectional shape of the first grooves along the first direction and the second direction is an inverted trapezoidal shape.

[0059] S03: A first conductive material layer, a gate material layer, a first isolation material layer, and a storage material layer are sequentially formed to cover the surface of the first dielectric layer and the inner wall of the first groove in a conformal manner;

[0060] S04: Perform a patterning process on the first conductive material layer, the gate material layer, the isolation material layer and the storage material layer to form a plurality of spaced first wires and a first stack. The first wires all extend along the first direction, and two adjacent first wires are staggered in the part facing each other along the second direction. The first stack is composed of the gate material layer, the isolation material layer and the storage material layer, and is located on the first wires on the bottom wall of the first groove or on the first dielectric layer between adjacent first grooves.

[0061] S05: A second dielectric layer is formed to cover the first dielectric layer and the first wire and fill the space between the first stack bodies, and a patterning process is performed on the second dielectric layer to form a plurality of second grooves that correspond to and match the first grooves in the second dielectric layer, and to expose the surface of each of the first stack bodies.

[0062] S06: A second conductive material layer is formed to cover the surface of the first stack and the surface of the second dielectric layer, and a patterning process is performed on the second conductive material layer to form a plurality of second wires extending along the second direction, wherein two adjacent second wires are staggered in the portion facing each other along the first direction.

[0063] Figures 2a to 2k_5 The diagram below shows the structural schematics corresponding to the steps of the manufacturing method for the three-dimensional storage structure provided in Embodiment 1. Next, we will combine... Figures 2a to 2k_5 The manufacturing method of the three-dimensional storage structure is described in detail.

[0064] First, please refer to Figure 2a In step S01, a first dielectric layer 10 is provided. The first dielectric layer 10 has a plurality of first island-shaped mask patterns 11 arranged alternately along the first direction X and the second direction Y. The first direction X and the second direction Y are orthogonal.

[0065] The first dielectric layer 10 may be disposed on a substrate, which may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Other matching semiconductor structures (e.g., transistors) may also be disposed on the substrate surface and the first dielectric layer 10. The first dielectric layer 10 may be any suitable insulating material, such as silicon oxide or doped silicon oxide.

[0066] The first island-shaped mask pattern 11 can be an island-shaped photoresist, and a bottom anti-reflective layer can also be provided between the first island-shaped mask pattern 11 and the first dielectric layer 10. For example... Figure 2a As shown in the top view, the first island mask pattern 11 may be rectangular. Multiple first island mask patterns 11 are arranged in a diamond array. In the multiple rows of first island mask patterns 11 arranged along the first direction X, there is a first interval between adjacent rows, and each first island mask pattern 11 in adjacent rows is staggered. In the multiple columns of first island mask patterns 11 arranged along the second direction Y, there is a second interval between adjacent columns, and each first island mask pattern 11 in adjacent columns is staggered. Furthermore, all first island mask patterns 11 in the multiple rows of first island mask patterns 11 arranged along the first direction X are aligned, and all first island mask patterns 11 in the multiple columns of first island mask patterns 11 arranged along the second direction Y are aligned. Of course, in other examples of this embodiment, all the first island mask patterns 11 arranged in multiple rows along the first direction X are aligned every two rows, and all the first island mask patterns 11 arranged in multiple columns along the second direction Y are aligned every two columns.

[0067] Please continue to refer to Figure 2a In this embodiment, with the first direction X as the row and the second direction Y as the column, the first island mask pattern 11 can be square, with the side length of the square being the first width. The first spacing between two adjacent rows of the first island mask pattern 11 can be, for example, 0.5 to 1.5 times the first width, and the second spacing between two adjacent columns of the first island mask pattern 11 can be, for example, 0.5 to 1.5 times the first width. The first island mask patterns 11 are aligned every other row and every other column. In other examples of this application, the first island mask pattern 11 can also be a rectangle with different lengths and widths, and the aforementioned first spacing can also be other values ​​related to the length, and the aforementioned second spacing can also be other values ​​related to the width.

[0068] Next, please refer to Figure 2b A top view diagram shows the execution of step S02, in which an etching process is performed to form a plurality of first grooves 12 in the first dielectric layer 10 between the first island mask patterns 11. The longitudinal cross-sectional shape of the first grooves 12 along the first direction X and the second direction Y is an inverted trapezoidal shape.

[0069] For example, a dry etching process can be used, and appropriate process parameters and process gas can be selected to etch the exposed first dielectric layer 10, forming multiple first grooves 12 with inclined sidewalls in the first dielectric layer 10. Then, the remaining first island-shaped mask pattern 11 and the bottom anti-reflective layer are removed. The inclined sidewalls of the first grooves 12 can be formed in the first dielectric layer 10 by, for example, reducing the bias voltage and adjusting the composition of the process gas. In one example, the angle between each sidewall of the first groove 12 and its bottom wall can be around 135°, for example, 115° to 155°. In another example, the area of ​​the bottom wall of the first groove 12 can be approximately equal to the surface area of ​​the first dielectric layer 10 between adjacent first grooves 12.

[0070] The first groove 12 formed in the first dielectric layer 10 may include two first sidewalls 12b facing (along) the first direction X and two second sidewalls 12c facing the second direction Y. The bottom of the first groove 12 may be a first bottom wall 12a. The area between the first grooves 12 corresponding to the first island mask pattern 11 may be a first top wall 10a. Each first groove 12 is disposed between four first top walls 10a. Figure 2b_1 This is a cross-sectional view of two adjacent rows of the first groove 12 along the first direction X, as shown below. Figure 2b_1 As shown, the longitudinal cross-sectional shape of the first groove 12 along the first direction X is an inverted trapezoidal shape. That is, when viewed from the first direction X, it extends sequentially along the first side wall 12b, the first bottom wall 12a, the first side wall 12b and the first top wall 10a to form a surface with regular protrusions and depressions (undulating). Figure 2b_2 This is a cross-sectional view of two adjacent columns of the first groove 12 along the second direction Y, as shown below. Figure 2b_2 As shown, the longitudinal cross-sectional shape of the first groove 12 along the second direction Y is an inverted trapezoid. That is, when viewed from the second direction Y, it extends sequentially along the second side wall 12c, the first bottom wall 12a, the second side wall 12c and the first top wall 10a to form a surface with regular protrusions and depressions (undulating).

[0071] It should be noted that in the above top view, the first groove 12 is shown as rectangular, but the above multiple first grooves 12 are not completely independent. Two adjacent first grooves 12 along the inclined direction are connected at the corners in the diagonal direction. The first groove 12 is shown as rectangular only for the purpose of illustration. Figure 2b_3 This is a top view of the actual first groove. In practice, as shown... Figure 2b_3As shown, among the multiple first grooves 12, there are four adjacent first grooves 12 that are octagonal. The octagon includes a cross-shaped portion 121 as the main body and corner portions 122 located at the four corners. The cross-shaped portion 121 is the subsequent effective area, while the corner portions 122 are ineffective areas. The first sidewall 12b, the second sidewall 12c, and the first bottom wall 12a are the corresponding portions of the cross-shaped portion 121.

[0072] In addition, by Figure 2b Top view and Figure 2b_1 As can be seen from the cross-sectional view, the centers of two adjacent columns of first island mask patterns 11 are respectively aligned with the centers of the adjacent first bottom wall 12a and first top wall 10a in the same row. In other words, the spacing distance (second spacing distance) between two adjacent columns of first island mask patterns 11 can be determined according to the preset angle between the second side wall 12c and the first bottom wall 12a and the width of the first bottom wall 12a. Similarly, the spacing distance (first spacing distance) between two adjacent rows of first island mask patterns 11 can be determined according to the preset angle between the first side wall 12b and the first bottom wall 12a and the width of the first bottom wall 12a.

[0073] Next, please refer to Figure 2c According to the cross-sectional schematic diagram, in step S03, a first conductive material layer 13, a gate material layer 14, a first isolation material layer 15 and a storage material layer 16 are sequentially formed to cover the surface of the first dielectric layer 10 and the inner wall of the first groove 12 in a conformal manner.

[0074] The first conductive material layer 13 is used to form the first conductive wire 13a. The material of the first conductive material layer 13 can be any suitable metallic material, such as tungsten. The gate material layer 14 is used to form the gate layer. The material of the first conductive material layer 13 can be a bidirectional threshold switching material, such as germanium telluride, germanium sulfide, germanium selenide, tellurium, selenium, and one or more alloys thereof. The storage material layer 16 is used to form the storage layer. The storage material layer 16 can be a storage material based on any suitable storage principle such as phase change storage, resistive switching storage, magnetoresistive storage, and ferroelectric storage, i.e., any one of phase change materials, resistive switching materials, magnetoresistive materials, and ferroelectric materials. The first isolation material layer 15 is used to isolate the gate material layer 14 and the storage material layer 16. The material of the first isolation layer 15 can be, for example, a carbon layer. The thickness of each of the above layers can be determined according to actual needs.

[0075] In one example, in such Figure 2cAs shown in the cross-sectional schematic diagram, a first conductive material layer 13, a gate material layer 14, a first isolation material layer 15, and a storage material layer 16 are sequentially stacked from bottom to top on the first dielectric layer 10. In another example, the first conductive material layer 13, the storage material layer 16, the first isolation material layer 15, and the gate material layer 14 are sequentially stacked from bottom to top on the first dielectric layer 10. It should be noted that, in addition to the storage material layer 16, the gate material layer 14, and the first isolation material layer 15, the films stacked on the first conductive material layer 13 may also include other isolation material layers (e.g., a second isolation material layer) and electrode material layers. The number of the above-mentioned films may be more than one layer, and they can be stacked in any suitable order, forming a complex stacked structure where the electrode materials are stacked in various orders. The materials are not limited to being stacked in one layer and can be stacked repeatedly. For example, in another example, after forming the first conductive material layer 13, a second isolation dielectric layer may be formed first. That is, a second isolation material layer may be provided between the first conductive material layer 13 and the adjacent gate material layer 14 or storage material layer 16. The material of the second isolation material layer may be the same as or similar to the material of the first isolation material layer.

[0076] Next, step S04 is executed to perform a patterning process on the first conductive material layer 13, the gate material layer 14, the first isolation material layer 15 and the storage material layer 16 to form a plurality of spaced first conductors 13a and a first stack 22. The first conductors 13a all extend along the first direction X, and two adjacent first conductors 13a are staggered vertically in the part that is directly opposite along the second direction Y. The first stack 22 is composed of the gate material layer 14, the first isolation material layer 15 and the storage material layer 16, and is located on the first conductors 13a on the first bottom wall 12a of the first groove 12 or on the first dielectric layer 10 between adjacent first grooves 12.

[0077] For example, please refer to Figure 2d The top view diagram shows that multiple strip-shaped first patterned mask layers 21a are formed on the storage material layer 16. The first patterned mask layers 21a extend along a first direction X, and the multiple first patterned mask layers 21a are spaced apart along a second direction Y. The width of the first patterned mask layer 21a can match the corresponding width of the first stack 22 to be formed, and the spacing between adjacent first patterned mask layers 21a can be the spacing between the first stack 22 to be formed. In one example, the width of the first patterned mask layer 21a can match the width of the first bottom wall 12a or the first top wall 10a in the same row, and the spacing between adjacent first patterned mask layers 21a can be the (horizontal) spacing between adjacent first bottom walls 12a and first top walls 10a along the second direction X (i.e., the first spacing distance).

[0078] Please refer to Figure 2e_1 and Figure 2e_2 The cross-sectional schematic diagram shown illustrates the etching process performed on the storage material layer 16, the first isolation material layer 15, the gate material layer 14, and the first conductive material layer 13 to expose the first dielectric layer 10, with the remaining first conductive material layer 13 serving as the first conductive wire 13a.

[0079] The storage material layer 16, the first isolation material layer 15, the gate material layer 14 and the first conductive material layer 13 can be sequentially etched using a dry etching process to expose the first dielectric layer 10, forming a strip-shaped structure extending along the first direction X composed of the above-mentioned film layers. The bottom of the strip-shaped structure is the first conductive wire 13a that extends in a zigzag manner along the first direction X. The first conductor 13a sequentially covers the first bottom wall 12a, the first side wall 12b, the first top wall 10a, the first side wall 12b, and the first bottom wall 12a along the first direction X, forming an undulating shape. The adjacent first conductor 13a sequentially covers the first top wall 10a, the first side wall 12b, the first bottom wall 12a, the first side wall 12b, and the first top wall 10a along the first direction X, forming an undulating shape. Therefore, each pair of adjacent first conductors 13a is undulating, but the patterns of their undulations are staggered. That is, the concave part (on the first bottom wall 12a) of one first conductor 13a is directly opposite the protruding part (on the first top wall 10a) of the adjacent first conductor 13a, causing them to be staggered. The inclined part (on one side of the first side wall 12b) of one first conductor 13a is directly opposite the inclined part (on the other side of the first side wall 12b) of the adjacent first conductor 13a along the other direction, causing them to be inclined and intersecting.

[0080] Please refer to Figure 2f The top view diagram shows that, after removing the first patterned mask layer 21a, multiple strip-shaped second patterned mask layers 21b are formed on the storage material layer 16. The second patterned mask layers 21b extend along the second direction Y, and the multiple second patterned mask layers 21b are spaced apart along the first direction X. The width of the second patterned mask layer 21b can match the corresponding width of the first stack 22 to be formed, and the spacing between adjacent second patterned mask layers 21b can be the spacing between the first stack 22 to be formed. In one example, the width of the second patterned mask layer 21b can match the width of the first bottom wall 12a or the first top wall 10a in the same column, and the spacing between adjacent second patterned mask layers 21b can be the spacing between adjacent first bottom walls 12a and first top walls 10a (i.e., the second spacing distance).

[0081] Please refer to Figure 2g_1 and Figure 2g_2The cross-sectional schematic diagram shows that an etching process is performed on the storage material layer 16, the isolation material layer, and the gate material layer 14 to expose the first dielectric layer 10 and the first conductive line 13a. The remaining storage material layer 16, the first isolation material layer 15, and the gate material layer 14 form the first stack body 22. A dry etching process can be used to sequentially etch the storage material layer 16, the isolation material layer, and the gate material layer 14, stopping the etching at the surface of the first conductive line 13a to expose the first dielectric layer 10 and the first conductive line 13a, forming the first stack body 22 composed of the storage material layer 16, the isolation material layer, and the gate material layer 14. Each first stack body 22 can be rectangular and is located on the first conductive line 13a on the first bottom wall 12a and the first top wall 10a, respectively. Specifically, the first stacked bodies 22 surrounding the first conductor 13a on the first bottom wall 12a are all located on the first conductor 13a on the first top wall 10a, and the first stacked bodies 22 surrounding the first conductor 13a on the first top wall 10a are all located on the first conductor 13a on the first bottom wall 12a. Therefore, any two adjacent first stacked bodies 22 (along the first direction X or the second direction Y) are staggered vertically. It can be understood that the structure and corresponding material of each film layer of the first stacked body 22 are determined by the multiple film layers stacked on the first conductor 13a. Therefore, the first stacked body 22 may also include other film layers besides the three layers mentioned above.

[0082] In other examples of this embodiment, the two patterning steps described above can be interchanged, that is, first forming the second patterned mask layer 21b and performing the corresponding etching process, and then forming the first patterned mask layer 21a and performing the corresponding etching process.

[0083] Next, step S05 is performed to form a second dielectric layer 23 covering the first dielectric layer 10 and the first wire 13a and filling the space between the first stack bodies 22. A patterning process is performed on the second dielectric layer 23 to form a plurality of inverted trapezoidal second grooves 23a corresponding to the first grooves 12 in the second dielectric layer 23, and to expose the surface of each first stack body 22.

[0084] For example, please refer to Figure 2hThe cross-sectional schematic diagram shows a second dielectric layer 23 forming a layer that covers the first dielectric layer 10, the first conductor 13a, and fills the space between the first stack 22. A polishing process is then performed on the second dielectric layer 23 to form a flat surface. The second dielectric layer 23 may include any suitable insulating material. In one example, the second dielectric layer 23 may include an insulating thermal insulation material and an insulating filler material. The thermal insulation material may include, but is not limited to, any one or more of silicon nitride, nano-silica aerogel, polystyrene, and polyurethane. The filler material may be a dielectric material with high filling effect, such as silicon oxide. The steps of forming the second dielectric layer 23 with a flat surface may include: first, forming a thermal insulation material that conformally covers the first conductor 13a and the first stack 22; then, forming a filler material that covers the thermal insulation material and fills the space above the first stack 22; and finally, performing a chemical mechanical polishing process to polish the second dielectric layer 23 to achieve a flat surface. In other examples, the second dielectric layer 23 may also be polished to expose or nearly expose the surface of the first stack 22.

[0085] Please refer to Figure 2i The top view diagram shows that a plurality of second island-shaped mask patterns 24 are formed on the second dielectric layer 23, which are staggered along the first direction X and the second direction Y. The second island-shaped mask patterns 24 are located on the second dielectric layer 23 on the stack. The above-mentioned plurality of second island-shaped mask patterns 24 can be formed on the surface of the second dielectric layer 23 using the same photomask and similar process as that used to form the first island-shaped mask pattern 11. That is, the size and position of the second island-shaped mask pattern 24 can be the same as or nearly the same as the first island-shaped mask pattern 11. In other words, each second island-shaped mask pattern 24 can be located above the first stack 22 located on the first top wall 10a.

[0086] Please refer to Figure 2j The top view shown illustrates the etching process performed to etch the second island-shaped mask pattern 24 and the second dielectric layer 23 to form the second groove 23a and expose the surfaces of each first stack 22.

[0087] In one example, a process similar to etching to form the first groove 12 can be used to etch the second dielectric layer 23 to form a second groove 23a similar to the first groove 12 in the second dielectric layer 23, and expose a portion of the surface of the first stack 22 at the bottom of the second groove 23a. The second island mask pattern 24 is consumed during the above etching process to expose the second dielectric layer 23 below the second island mask pattern 24. The second dielectric layer 23 is etched to expose another portion of the surface of the first stack 22, thereby forming the second groove 23a and exposing all the surfaces of the first stack 22. In other words, the second island mask pattern 24 and the second dielectric layer 23 are etched simultaneously. Each second groove 23a may correspond to (match) a first groove 12. Each second groove 23a may include two third sidewalls facing the first direction X and two fourth sidewalls facing the second direction Y. The bottom of the second groove 23a may be a second bottom wall (i.e., the surface of the first stack 22 at a lower position). The area between the second grooves 23a corresponding to the second island mask pattern 24 may be a second top wall (i.e., the surface of the first stack 22 at a higher position). Each second groove 23a is disposed between four second top walls, and each second top wall is surrounded by four second grooves 23a.

[0088] In another example, the second dielectric layer 23 between the second island mask patterns 24 and the second dielectric layer 23 below the second island mask patterns 24 may also be etched to form the second groove 23a and expose the surfaces of each first stack 22.

[0089] It should be noted that, relative to the etching process that forms the first groove 12, the above etching process can also reduce the damage to the surface of the first stack 22 by controlling the selectivity of the etching gas.

[0090] Next, step S06 is performed to form a second conductive material layer 24 covering the surface of the first stack 22 and the surface of the second dielectric layer 23, and to perform a patterning process on the second conductive material layer 24 to form a plurality of second wires 24a extending along the second direction Y, and adjacent second wires 24a are staggered vertically in the part directly opposite each other along the first direction X.

[0091] In one example, a second conductive material layer 24 can be formed to cover the surface of the first stack 22 and the surface of the second dielectric layer 23. A patterning process is performed on the second conductive material layer 24 to form a plurality of second wires 24a extending along the second direction Y. The first wire 13a, the first stack 22 and the second wire 24a are used as a three-dimensional storage structure. Then, a gate material layer 14, an isolation material layer and a storage material layer 16 are formed sequentially on the second wire 24a and the second dielectric layer 23. The gate material layer 14, the isolation material layer and the storage material layer 16 are patterned to form a second stack 26 on the first wire 13a. In this way, a multi-layer three-dimensional storage structure is formed.

[0092] In another example, the second wire 24a and the second stack 26 can also be formed simultaneously in a manner similar to that used to form the first wire 13a and the first stack 22. For example, please refer to... Figure 2k_1 The cross-sectional view shows that a second conductive material layer 24, a gate material layer 14, a first insulating material layer 15, and a storage material layer 16 are sequentially formed to cover the surface of the second dielectric layer 23 and the inner wall of the second groove 23a. The material of the second conductive material layer 24 can be the same as or similar to the material of the first conductive material layer 13, and the other materials can be as described above.

[0093] Please refer to Figure 2k_2 The top view shows that multiple strip-shaped third patterned mask layers 25a are formed on the storage material layer 16. The third patterned mask layers 25a extend along the second direction Y, and the multiple third patterned mask layers 25a are arranged at intervals along the first direction X. The third patterned mask layers 25a can be referenced to the aforementioned second patterned mask layer 21b.

[0094] Please refer to Figure 2k_3 The cross-sectional view shows that an etching process is performed on the storage material layer 16, the isolation material layer, the gate material layer 14, and the second conductive material layer 24 to expose the second dielectric layer 23, and the remaining second conductive material layer 24 serves as the second conductive wire 24a. Specifically, a dry etching process can be used to sequentially etch the storage material layer 16, the first isolation material layer 15, the gate material layer 14, and the second conductive material layer 24 to expose the second dielectric layer 23, forming a strip-shaped structure extending along the second direction Y, composed of the aforementioned film layers. The bottom of this strip-shaped structure is the second conductive wire 24a, which extends in a zigzag pattern along the second direction Y. The second conductor 24a sequentially covers the second bottom wall, fourth side wall, second top wall, fourth side wall, and second bottom wall along the second direction Y, forming an undulating shape. Adjacent second conductors 24a sequentially cover the second top wall, fourth side wall, second bottom wall, fourth side wall, and second top wall along the second direction Y, forming an undulating shape. Therefore, each pair of adjacent second conductors 24a is undulating, but the patterns of their undulations are staggered. That is, the concave part (on the second bottom wall) of one second conductor 24a is directly opposite the protruding part (on the second top wall) of the adjacent second conductor 24a, causing them to be staggered. The inclined part (on one side of the fourth side wall) of one second conductor is directly opposite the inclined part (on the other side of the fourth side wall) of the adjacent second conductor 24a along the other direction, causing them to be inclined and intersecting.

[0095] Please refer to Figure 2k_4The top view shows that multiple strip-shaped fourth patterned mask layers 25b are formed on the storage material layer 16. The fourth patterned mask layers 25b extend along the first direction X, and the multiple fourth patterned mask layers 25b are arranged at intervals along the second direction Y. The fourth patterned mask layers 25b can be referenced to the aforementioned first patterned mask layer 21a.

[0096] Please refer to Figure 2k_5 The top view shows that an etching process is performed on the storage material layer 16, the isolation material layer, and the gate material layer 14 to expose the second dielectric layer 23 and the second conductive line 24a, with the remaining storage material layer 16, the isolation material layer, and the gate material layer 14 forming the second stack 26. A dry etching process can be used to sequentially etch the storage material layer 16, the first isolation material layer 15, and the gate material layer 14, stopping the etching at the surface of the second conductive line 24a to expose the second dielectric layer 23 and the second conductive line 24a, forming the second stack 26 composed of the storage material layer 16, the first isolation material layer 15, and the gate material layer 14. Each second stack 26 can be rectangular and is located on the second conductive line 24a on the second bottom wall and the second top wall, respectively. Among them, the second stack 26 around the second stack 26 located on the second conductor 24a of the second bottom wall are all located on the second conductor 24a of the second top wall, and the second stack 26 around the second stack 26 located on the second conductor 24a of the second top wall are all located on the second conductor 24a of the second bottom wall. Therefore, any two adjacent second stack 26 (along the first direction X or the second direction Y) are staggered vertically.

[0097] Here, similar methods can be used to form more layers of three-dimensional storage structures.

[0098] This application also provides a three-dimensional storage structure.

[0099] Figure 3a This is a schematic diagram of the three-dimensional storage structure provided in the embodiments of this application.

[0100] Figure 3b This application provides a schematic diagram of the structure of each wire in the three-dimensional storage structure.

[0101] like Figure 3a As shown, the three-dimensional storage structure provided in this embodiment includes a first dielectric layer, a first wire 13a, a first stack 22, a second dielectric layer, and a second wire 24a.

[0102] Figure 3b This only shows a schematic diagram of a portion of the wires in the three-dimensional storage structure. (For example...) Figure 3bAs shown, each first conductor 13a extends in a zigzag pattern along a first direction X, and multiple first conductors 13a are arranged at intervals along a second direction Y. Each first conductor 13a is undulating, including alternating recessed portions 131 and protruding portions 132. The recessed portions 131 are at a lower position, and the protruding portions 132 are at a higher position. The recessed portions 131 and protruding portions 132 are connected by inclined portions. Moreover, the undulation pattern between each pair of adjacent first conductors 13a is different. That is, the recessed portion 131 of one first conductor 13a is directly opposite the protruding portion 132 of the adjacent first conductor 13a, so that the two are staggered vertically. The inclined portion of one first conductor 13a is directly opposite the inclined portion of the adjacent first conductor 13a along another direction, so that the two are inclined and interleaved. The second conductor 24a is another conductor corresponding to the first conductor 13a. The first conductor 13a is, for example, one of a word line or a bit line, and the second conductor 24a is the other of the word line or bit line. The arrangement of the second conductor 24a is similar to that of the first conductor 13a but in a different direction. That is, each second conductor 24a extends in a zigzag manner along the second direction Y, and multiple second conductors 24a are arranged at intervals along the first direction X. Each second conductor 24a is undulating, including alternating recessed portions 131 and protruding portions 132. The recessed portions 131 are at a lower position, and the protruding portions 132 are at a higher position. The recessed portions 131 and the protruding portions 132 are connected by inclined portions. Moreover, the undulating pattern between each pair of adjacent second conductors 24a is different. That is, the recessed portion 131 of one second conductor 24a is directly opposite the protruding portion 132 of the adjacent second conductor 24a, so that the two are staggered vertically. The inclined portion of one second conductor 24a is directly opposite the inclined portion of the adjacent second conductor 24a along another direction, so that the two are staggered in an inclined manner. The third conductor 31 is another conductor corresponding to the second conductor 24a. Its arrangement is similar to the second conductor but in a different direction. In other words, the third conductor 31 can be arranged in the same way as the first conductor 13a. It is easy to see from the above arrangement of the conductors that the staggered (interlaced) arrangement of adjacent conductors in the same layer reduces parasitic capacitance between conductors, suppresses resistance drift, and improves the reliability of the three-dimensional storage structure. On the other hand, the relatively longer spacing between the conductors also increases the heat transfer path, thereby reducing thermal crosstalk and further improving the reliability of the three-dimensional storage structure.

[0103] Figure 3a This is a schematic diagram of some wires and stacked structures in a three-dimensional storage structure. (Example) Figure 3aAs shown, a first stack 22 is disposed between the first conductor 13a and the second conductor 24a, and includes a stacked gate material layer 14, a first isolation material layer 15, and a storage material layer 16. The structure and material of each film layer in the first stack 22 can be referred to the aforementioned manufacturing method, and will not be repeated here. A first stack 22 is provided at the intersection of the projections of each first conductor 13a. The two ends of the first stack 22 are respectively disposed between the recessed portions 131 connecting the first conductor 13a and the second conductor 24a, or between the protruding portions 132 connecting the first conductor 13a and the second conductor 24a. Furthermore, since the spacing between adjacent first conductors 13a is the same as the spacing between the recessed portion 131 and the protruding portion 132 of the second conductor 24a, and the spacing between adjacent second conductors 24a is the same as the spacing between the recessed portion 131 and the protruding portion 132 of the first conductor 13a, the first stacked bodies 22 arranged along the first direction X are alternately disposed on the recessed portion 131 and the protruding portion 132 of the first conductor 13a in a vertically staggered manner. Similarly, the first stacked bodies 22 arranged along the second direction Y are alternately disposed on the recessed portion 131 and the protruding portion 132 of the second conductor 24a in a vertically staggered manner. This results in the storage material layers 16 in adjacent first stacked bodies 22 along the first direction X and the second direction Y being vertically staggered, increasing the relative distance between them, thereby reducing thermal crosstalk and improving the reliability of the three-dimensional storage structure. Additionally, the second stacked bodies 26 on the second conductor 24a are similar to the first stacked bodies 22 and will not be described in detail here.

[0104] The first and second dielectric layers can be any suitable insulating material layers. The first dielectric layer is located below the first conductor. The surface of the first dielectric layer has multiple first grooves, each with an inverted trapezoidal cross-sectional shape along both the first direction X and the second direction Y. These multiple first grooves are arranged alternately along the first and second directions. The first dielectric layer and the first grooves on its surface provide the surface (interface) for forming the aforementioned undulating first conductor. The specific process and principle can be found in the aforementioned manufacturing method. The second dielectric layer fills and covers the first conductor, fills the spaces between the first stack bodies, and forms multiple second grooves that correspond one-to-one with and match the multiple first grooves. The bottom wall of the second groove and the top wall between the second grooves expose the surface of each first stack body. The second dielectric layer and the second grooves on its surface provide the surface for forming the aforementioned undulating second conductor. The specific process and principle can be found in the aforementioned manufacturing method.

[0105] Similarly, the second conductor 24a and the second dielectric layer 23 can continue to be stacked sequentially according to the aforementioned pattern to form a multi-layered three-dimensional storage structure. Of course, the surfaces of each conductor and the spaces between each stack are filled with corresponding dielectric layers. For example... Figure 3a and Figure 3bAs shown, a plurality of second stacks 26 (refer to the first stack 22) are provided on the first conductor 13a of the first stack 22. A third dielectric layer (refer to the second dielectric layer 23, not shown in the figure) is filled between the plurality of second stacks 26. The third dielectric layer is provided with a third groove corresponding to and matching the first groove 12 (or the second groove 23a) and exposes the surface of each second stack 26. A plurality of third conductors 31 are provided on the second stacks 26 and the third dielectric layer. Each third conductor 31 extends in a zigzag manner along the first direction X and multiple conductors are arranged at intervals along the second direction Y. The third conductors 31 conformally cover the sidewall of the third groove and the top surface of the second stack 26 in an undulating manner. Adjacent third conductors 31 are staggered in the part directly opposite along the second direction Y.

[0106] This application also provides a semiconductor device comprising the three-dimensional storage structure described above. The semiconductor device may be a three-dimensional memory, or other electronic devices comprising the three-dimensional storage structure described above.

[0107] In summary, the semiconductor device, three-dimensional memory structure, and fabrication method provided in this application include a first dielectric layer with a plurality of first grooves arranged alternately along a first direction and a second direction on the surface of the first dielectric layer. The first grooves are in the shape of an inverted trapezoid, and the first direction and the second direction are orthogonal. A plurality of first conductive lines extend in a zigzag pattern along the first direction and are spaced apart along the second direction. The first conductive lines conformally cover the surface of the first dielectric layer and the inner wall of the first grooves, forming a continuous up-and-down undulating shape. The portions of adjacent first conductive lines facing each other in the second direction are staggered. A plurality of first stacked bodies are disposed on the first conductive lines, including a layered gate material layer, a first isolation material layer, and a storage material layer. Each stack of first stacked components is disposed on a first conductor on the bottom wall of a first groove and on a first dielectric layer between the first grooves, forming an undulating shape. A second dielectric layer covers the first dielectric layer and the first conductors, and fills the spaces between the first stacked components. The second dielectric layer forms several inverted trapezoidal second grooves corresponding to the first grooves. The bottom of the second grooves and the second dielectric layer between the second grooves expose the surfaces of each first stacked component. Several second conductors extend in a zigzag pattern along a second direction and are spaced apart along a first direction. The first conductors conformally cover the surface of the second dielectric layer, the sidewalls of the second grooves, and the top wall of the first stacked components, continuously undulating. The portions of adjacent second conductors facing each other in the first direction are staggered vertically. In the three-dimensional storage structure of this application, the portions of adjacent conductors in the same layer are staggered vertically (higher and lower) along both the first and second directions, and the relative distance between adjacent parallel conductors is increased to reduce parasitic capacitance between conductors, thereby reducing resistance drift and improving the reliability of the three-dimensional storage structure. Furthermore, the storage material layers in adjacent first stacks along the first and second directions within the same layer are staggered vertically, increasing the relative distance between them and thus reducing thermal crosstalk, which also helps improve the reliability of the three-dimensional storage structure. Therefore, compared to the flush arrangement of the wires and stacks, the staggered arrangement of the various parts of the wires and the first stacks can increase the relative distance between the stacks without reducing the storage density. In other words, the three-dimensional storage structure of this application can better balance storage density and memory reliability.

[0108] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A three-dimensional storage structure, characterized in that, include: A first dielectric layer has a plurality of first grooves arranged alternately along a first direction and a second direction on its surface. The longitudinal cross-sectional shape of each of the first grooves along the first direction and the second direction is an inverted trapezoidal shape. The first direction and the second direction are orthogonal. A plurality of first wires extend in a zigzag pattern along the first direction and are spaced apart along the second direction. The first wires conformally cover the surface of the first dielectric layer and the inner wall of the first groove in a continuous up-and-down undulating shape. Adjacent first wires are staggered in the portion directly opposite each other along the second direction. A plurality of first stacked bodies disposed on the first conductor include a layered gate material layer, a first isolation material layer and a storage material layer, and adjacent first stacked bodies are disposed on the first conductor on the bottom wall of the first groove and on the first conductor on the first dielectric layer between the first grooves, and are staggered. A second dielectric layer covers the first dielectric layer and the first wire, and fills the spaces between the first stack bodies. A plurality of second grooves are formed in the second dielectric layer that correspond to and match each of the first grooves. The bottom of the second grooves and the second dielectric layer between the second grooves expose the surfaces of each of the first stack bodies. A plurality of second wires extend in a zigzag pattern along the second direction and are spaced apart along the first direction. The second wires conform to the shape of covering the sidewall of the second groove and the top wall of the first stack body in a continuous up-and-down undulating pattern. Adjacent second wires are staggered in the portion that is directly opposite each other along the first direction.

2. The three-dimensional storage structure according to claim 1, characterized in that, The angle between the sidewalls of the first groove and the second groove along the first direction and the second direction and their respective bottom walls is 115° to 155°.

3. The three-dimensional storage structure according to claim 1, characterized in that, The gating material layer is located below the first insulating material layer, and the storage material layer is located above the first insulating material layer, or... The gating material layer is located above the first isolation material layer, and the storage material layer is located below the first isolation material layer.

4. The three-dimensional storage structure according to claim 3, characterized in that, A second isolation material layer is provided between the gate material layer and the adjacent conductor and / or between the storage material layer and the adjacent conductor.

5. The three-dimensional storage structure according to claim 4, characterized in that, The material of the first insulating material layer and / or the second insulating material layer includes carbon.

6. The three-dimensional storage structure according to claim 1, characterized in that, The second dielectric layer includes an insulating heat insulation layer and an insulating filler layer, the heat insulation layer conformally covering the surface of the first conductor and the sidewalls of the first stack, and the filler layer covering the heat insulation layer.

7. The three-dimensional storage structure according to claim 1, characterized in that, The three-dimensional storage structure also includes: A plurality of second stacked bodies disposed on the second conductor include a layered gate material layer, a first isolation material layer and a storage material layer, and each of the second stacked bodies is disposed on the second conductor on the first stacked body in an alternating manner. A third dielectric layer covers the second dielectric layer and the second wire, and fills the spaces between the second stack bodies. A plurality of third grooves corresponding to and matching each of the second grooves are formed in the third dielectric layer, and the surfaces of each of the second stack bodies are exposed. A plurality of third conductors extend in a zigzag pattern along the first direction and are spaced apart along the second direction. The third conductors conformally cover the surface of the third dielectric layer, the sidewall of the third groove, and the top wall of the second stack in an undulating manner. Adjacent third conductors are staggered in the portion facing each other along the second direction.

8. The three-dimensional storage structure according to claim 1, characterized in that, The storage material layer includes any one of phase change materials, resistive switching materials, magnetoresistive materials, and ferroelectric materials.

9. A method for manufacturing a three-dimensional storage structure, characterized in that, include: A first dielectric layer is provided, on which a plurality of first island-shaped mask patterns are arranged alternately along a first direction and a second direction, wherein the first direction is orthogonal to the second direction; An etching process is performed to form a plurality of first grooves in the first dielectric layer between the first island-shaped mask patterns. The longitudinal cross-sectional shape of each of the first grooves along the first direction and the second direction is an inverted trapezoidal shape. A first conductive material layer, a gate material layer, a first insulating material layer, and a storage material layer are sequentially formed to conformally cover the surface of the first dielectric layer and the inner wall of the first groove; A patterning process is performed on the first conductive material layer, the gate material layer, the isolation material layer and the storage material layer to form a plurality of spaced first wires and a first stack. The first wires all extend along the first direction, and two adjacent first wires are staggered in the part facing each other along the second direction. The first stack is composed of the gate material layer, the isolation material layer and the storage material layer, and is located on the first wires on the bottom wall of the first groove or on the first dielectric layer between adjacent first grooves. A second dielectric layer is formed to cover the first dielectric layer and the first wire and fill the space between the first stack bodies. A patterning process is performed on the second dielectric layer to form a plurality of second grooves that correspond to and match each of the first grooves in the second dielectric layer, and to expose the surface of each of the first stack bodies. A second conductive material layer is formed to cover the surface of the first stack and the surface of the second dielectric layer. A patterning process is performed on the second conductive material layer to form a plurality of second wires extending along the second direction, and adjacent two second wires are staggered in the portion facing each other along the first direction.

10. The method for manufacturing a three-dimensional storage structure according to claim 9, characterized in that, The steps of forming the first wire and the first stack include: Multiple strip-shaped first patterned mask layers are formed on the storage material layer, the first patterned mask layers extending along the first direction, and the multiple first patterned mask layers are spaced apart along the second direction; An etching process is performed on the storage material layer, the isolation material layer, the gate material layer and the first conductive material layer to expose the first dielectric layer, and the remaining first conductive material layer is used as the first conductor. Remove the first patterned mask layer and form a plurality of strip-shaped second patterned mask layers on the storage material layer. The second patterned mask layers extend along the second direction, and the plurality of second patterned mask layers are spaced apart along the first direction. An etching process is performed on the storage material layer, the isolation material layer, and the gate material layer to expose the first dielectric layer and the first conductor, and the remaining storage material layer, the isolation material layer, and the gate material layer are used as the first stack.

11. The method for manufacturing a three-dimensional storage structure according to claim 9, characterized in that, The step of performing a patterning process on the second dielectric layer to form the second groove includes: A polishing process is performed on the second dielectric layer to form a flat surface; A plurality of second island-shaped mask patterns are formed on the second dielectric layer, which are staggered along the first direction and the second direction. The second island-shaped mask patterns are located on the second dielectric layer of the stack. An etching process is performed to etch the second island-shaped mask pattern and the second dielectric layer to form the second groove and expose the surfaces of each of the stacks.

12. The method for manufacturing a three-dimensional storage structure according to claim 9, characterized in that, After forming the second conductive material layer, a gate material layer, an isolation material layer, and a storage material layer are sequentially formed to conformally cover the surface of the second conductive material layer. A patterning process is performed on the second conductive material layer, the gate material layer, the isolation material layer, and the storage material layer to form the second conductor and the second stack disposed on the second conductor.

13. The method for manufacturing a three-dimensional storage structure according to claim 12, characterized in that, The steps of forming the second wire and the second stack include: Multiple strip-shaped third patterned mask layers are formed on the storage material layer, the third patterned mask layers extend along the second direction, and the multiple third patterned mask layers are spaced apart along the first direction; An etching process is performed on the storage material layer, the isolation material layer, the gate material layer and the second conductive material layer to expose the second dielectric layer, and the remaining second conductive material layer is used as the second conductor. Multiple strip-shaped fourth patterned mask layers are formed on the storage material layer, the fourth patterned mask layers extending along the first direction, and the multiple fourth patterned mask layers are spaced apart along the second direction; An etching process is performed on the storage material layer, the isolation material layer, and the gate material layer to expose the second dielectric layer and the second conductor, and the remaining storage material layer, the isolation material layer, and the gate material layer are used as the second stack.

14. A semiconductor device, characterized in that, The semiconductor device includes a three-dimensional storage structure as described in any one of claims 1 to 8.

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