A field effect transistor and a method of manufacturing the same

Abstract

The application discloses a field effect tube and a preparation method thereof, and relates to the technical field of semiconductor devices. The preparation method of the field effect tube comprises the following steps: providing a substrate; forming a deep N well and a P-type body region on the substrate, the body region is arranged at the outer periphery of the deep N well and is spaced from the deep N well, and a plurality of P-type electric field adjusting structures are embedded in the deep N well; forming a field oxide layer on the upper surface of the substrate, the field oxide layer has at least two first windows on the deep N well and a second window on the body region; forming a drain and a source in the deep N well through the first window and forming a body contact in the body region through the second window, wherein the source surrounds the outer periphery of the drain; and forming polycrystalline silicon on the field oxide layer as a field plate. The field effect tube and the preparation method thereof can homogenize an electric field while simplifying a process flow.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a field-effect transistor and its fabrication method. Background Technology

[0002] In the ultra-high voltage BCD (Ultra-HV Bipolar-CMOS-DMOS) process platform, circular junction field-effect transistors (JFETs) exhibit excellent current conduction capability, uniform electric field distribution characteristics, and outstanding surge protection performance in high-voltage applications due to their unique ring structure. They are widely used in high-reliability scenarios such as power management, motor drives, and automotive electronics. These circular JFETs operate based on the PN junction depletion principle and are voltage-controlled normally-on devices. Their typical structure includes a central drain, a source surrounding the drain, and a P-type body region surrounding the source. The drift region is typically composed of a deep N-well, with localized silicon oxide used for device isolation. To improve breakdown voltage, existing technologies often introduce multiple high-energy ion implantations (such as reducing surface electric field implantation) and multiple P-type electric field modulation structures within the deep N-well to achieve charge balance and surface electric field modulation. Simultaneously, a polysilicon layer covering the LOCOS region is used as a field plate to further optimize the electric field distribution and improve the breakdown voltage. Reduced Surface Field Implantation (RESURF) is a key ion implantation process specifically used in the fabrication of high-voltage power semiconductor devices.

[0003] However, the manufacturing process of the aforementioned high-performance circular JFETs is extremely complex. According to industry practice, the complete process typically involves no fewer than 13 photolithography steps. Among them, the critical ion implantation step alone requires at least six independent photolithography masks, including: deep N-well implantation, deep P-well implantation, high-energy ion RESURF implantation, N+ source / drain implantation, and P+ implantation for bulk contacts. Each additional photolithography layer not only significantly increases mask costs and process cycle time but may also introduce overlay errors, contamination risks, and yield losses. In addition, RESURF can only adjust the electric field on the surface of the deep N-well, resulting in large electric field spikes at both ends of the deep N-well. Summary of the Invention

[0004] The purpose of this application is to provide a field-effect transistor and its fabrication method, which can simplify the process and homogenize the electric field.

[0005] The embodiments of this application are implemented as follows: A first aspect of this application provides a method for fabricating a field-effect transistor (FET), comprising: providing a substrate; forming a deep N-well and a P-type body region on the substrate, the body region surrounding and spaced from the deep N-well, and a plurality of P-type electric field modulation structures embedded within the deep N-well; forming a field oxide layer on the upper surface of the substrate, the field oxide layer having at least two first windows on the deep N-well and a second window on the body region; forming a drain and a source in the deep N-well through the first windows, and forming a body contact in the body region through the second window, wherein the source surrounds the outer periphery of the drain; and forming polysilicon on the field oxide layer as a field plate.

[0006] As one possible implementation, the electric field conditioning structure includes a plurality of arc-shaped conditioning columns extending in a circumferential direction disposed between the source and the drain.

[0007] As one possible implementation, multiple arc-shaped adjustment columns are arranged on multiple concentric circles, and each circle has at least two arc-shaped adjustment columns, with the arc-shaped adjustment columns of adjacent circles being staggered.

[0008] As one possible implementation, the radial length of the arc-shaped adjustment column is greater than 5 μm.

[0009] As one possible implementation, the electric field adjustment structure also includes multiple cylindrical adjustment elements disposed within a deep N-well below the drain electrode.

[0010] As one possible implementation, the diameter of the cylindrical adjusting member is greater than 2μm.

[0011] As one possible implementation, the electric field modulation structure penetrates the deep N-well.

[0012] As one possible implementation, forming a deep N-well and a P-type bulk region on a substrate includes: performing N-type ion implantation on the substrate to form a deep N-well on the substrate; performing P-type ion implantation on the substrate to form a bulk region surrounding and spaced from the deep N-well, and an electric field modulation structure located within the deep N-well.

[0013] As one possible implementation method, the doping concentration of the deep N-well is in the range of 1E. 12 -1E 13 between.

[0014] A second aspect of this application provides a field-effect transistor (FET) fabricated using the aforementioned FET fabrication method, comprising a substrate; a deep N-well and a body region spaced apart on the substrate, the body region surrounding the outer periphery of the deep N-well, and a plurality of P-type electric field modulation structures embedded within the deep N-well; and a field oxide layer located on the substrate surface, the field oxide layer having at least two first windows corresponding to the deep N-well and a second window corresponding to the body region, and the field oxide layer further comprising a drain, a source, and a body contact, the drain and source respectively passing through the first windows and connected to the deep N-well, with the source surrounding the outer periphery of the drain, and the body contact passing through the second window and connected to the body region.

[0015] The beneficial effects of the embodiments of this application include: A method for fabricating a field-effect transistor (FET) includes: providing a substrate; forming a deep N-well and a P-type body region on the substrate, the body region surrounding and spaced from the deep N-well, and embedding multiple P-type electric field modulation structures within the deep N-well; simultaneously forming the body region by ion implantation and the electric field modulation structures within the deep N-well, i.e., forming the body region and the electric field modulation structures in a single ion implantation process; furthermore, the multiple P-type electric field modulation structures embedded in the deep N-well form a uniform electric field distribution, making the electric field tend to be flat along the length of the deep N-well; forming a field oxide layer on the upper surface of the substrate, the field oxide layer having at least two first windows on the deep N-well and a second window on the body region; forming a drain and a source in the deep N-well through the first windows, and forming a body contact in the body region through the second window, wherein the source surrounds the outer periphery of the drain; and forming polysilicon on the field oxide layer as a field plate. The FET of this application can reduce the number of photolithography steps while also homogenizing the electric field, i.e., it can simplify the process flow while homogenizing the electric field. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a method for fabricating a field-effect transistor (FET) as provided in this application embodiment; Figure 2 This is one of the state diagrams for a method of fabricating a field-effect transistor provided in an embodiment of this application; Figure 3 A second state diagram of a method for fabricating a field-effect transistor provided in an embodiment of this application; Figure 4 The third state diagram of a method for fabricating a field-effect transistor provided in this application embodiment; Figure 5 The fourth state diagram of a method for fabricating a field-effect transistor provided in this application embodiment; Figure 6 A schematic diagram of a field-effect transistor provided in an embodiment of this application; Figure 7 for Figure 6 A schematic diagram of the cross-section along AA.

[0018] Icons: 100-Substrate; 110-Deep N-well; 120-Bulk region; 130-Electric field conditioning structure; 131-Arc-shaped conditioning pillar; 132-Columnar conditioning element; 141-Field oxide layer; 151-Source; 152-Drain; 153-Field plate. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. Similar reference numerals and letters in the following drawings indicate similar items. Once an item is defined in one drawing, it does not need to be further defined in other drawings.

[0020] The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and should not be construed as limiting this application. The terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] Unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to connections within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] The active region of a circular JFET device consists of a drain, a source, and a body region. The region between the drain and the source is a deep N-well. The source and drain terminals and the polycrystalline field plate are arranged in concentric circles. When a high voltage is applied to the drain, the current flows radially from the center outwards, and the electric field lines are also uniformly distributed radially. The uniform electric field structure itself has good voltage withstand characteristics.

[0023] This application provides a method for fabricating a field-effect transistor, such as... Figure 1 As shown, it may include: S100: Provides a substrate.

[0024] S200: A deep N-well and a P-type bulk region are formed on the substrate. The bulk region surrounds the outer periphery of the deep N-well and is spaced apart from the deep N-well. Multiple P-type electric field modulation structures are embedded in the deep N-well.

[0025] Among them, such as Figure 2As shown, the substrate 100 serves as the mechanical support and electrical connection basis for the entire device, providing a carrier for subsequent epitaxial growth or implantation processes and determining the overall conductivity of the device. Specifically, a P-type silicon substrate 100 can be used.

[0026] Furthermore, in conjunction with references Figure 2 and Figure 3 S200: An N-type deep N-well 110 and a P-type body region 120 can be formed on the substrate 100.

[0027] The body region 120 surrounds the outer periphery of the deep N-well 110 and is spaced apart from it. Multiple P-type electric field modulation structures 130 are embedded within the deep N-well 110 (e.g., ...). Figure 6 As shown, the P-type electric field conditioning structure 130 embedded in the deep N-well 110 actively adjusts the electric field distribution within the deep N-well 110 by forming a PN junction depletion region.

[0028] Specifically, multiple uniformly distributed P-type electric field adjustment structures 130 can make the electric field tend to be flat in both the longitudinal and transverse directions, thus homogenizing the electric field. When the device is subjected to reverse voltage, the electric field adjustment structure 130 makes the electric field more uniformly distributed within the deep N-well 110, avoiding breakdown caused by electric field concentration.

[0029] Specifically, in this embodiment, the body region 120 and the electric field adjustment structure 130 have the same doping type, both being P-type. Thus, in step S100, the electric field adjustment structure 130 located in the deep N-well 110 can be formed simultaneously with the formation of the body region 120 by ion implantation. That is, the body region 120 and the electric field adjustment structure 130 are formed in one ion implantation process. Compared with the RESURF implantation in the prior art, this reduces one implantation step, thereby reducing the number of photolithography steps.

[0030] It is understandable that, since the body region 120 and the deep N-well 110 are formed during a single ion implantation, the mask must be positioned to correspond with the body region 120 and the deep N-well 110. In other words, compared to the prior art, the window position of the mask needs to be adjusted.

[0031] S300: A field oxide layer is formed on the upper surface of the substrate, the field oxide layer having at least two first windows on the deep N-well and a second window on the bulk region.

[0032] Among them, such as Figure 4 As shown, the field oxide layer 141 is typically made of silicon dioxide and serves as an isolation layer. The first and second windows are fabricated in a single photolithography process.

[0033] S400: Drain and source are formed in the deep N-well through the first window, and body contact is formed in the body region through the second window.

[0034] Among them, such as Figure 5As shown, the source electrode surrounds the outer periphery of the drain electrode.

[0035] In this embodiment, the drain 152 is located in the central region, and the source 151 surrounds the drain 152 in a ring shape. The ring-shaped source 151 structure makes the current path symmetrical and reduces the on-resistance. At the same time, in conjunction with the P-type electric field adjustment structure 130 inside the deep N-well 110, the uniformity of the electric field distribution in the plane is further optimized. The body contact connects to the P-type body region 120 to ensure the potential stability of the body region 120.

[0036] In this embodiment, the field oxygen layer serves as an isolation structure for the source 151, drain 152, and body contact.

[0037] S400: Polycrystalline silicon is formed on the field oxide layer as a field plate.

[0038] like Figure 7 As shown, the field plate 153 regulates the peak value of the surface electric field and suppresses surface breakdown through electrostatic shielding. The field plate 153 works in conjunction with the internal P-type electric field adjustment structure 130 to achieve three-dimensional spatial electric field homogenization.

[0039] In summary, the deep N-well 110, body region 120, and electric field adjustment structure 130 of this application embodiment can be completed through two ion implantations. Specifically, different energies / doses can be used to distinguish between depth and concentration. All contact windows are defined and etched in a single photolithography layer, thereby simplifying the process flow. In addition, the multiple P-type electric field adjustment structures 130 embedded in the deep N-well 110 form a uniform electric field distribution, making the electric field tend to be flat along the length of the deep N-well 110. The top field plate 153 suppresses the electric field concentration at the edge of the drain 152, and the symmetrical arrangement of the ring source 151 and the central drain 152 makes the lateral electric field distribution more uniform. Therefore, the field-effect transistor can reduce the number of photolithography steps while also homogenizing the electric field. In conclusion, the embodiments of this application can simplify the process flow while also homogenizing the electric field.

[0040] In addition, a uniform electric field can significantly increase the breakdown voltage of the device, that is, enhance the device's withstand voltage capability, while reducing conduction loss and switching loss.

[0041] Optional, such as Figure 6 and Figure 7 As shown, the electric field adjustment structure 130 may include a plurality of arc-shaped adjustment columns 131 extending in the circumferential direction of a deep N-well 110 disposed between the source 151 and the drain 152.

[0042] Specifically, multiple arc-shaped adjustment columns 131 are distributed along the circumference, surrounding the central drain electrode 152, and located within the deep N-well 110 between the source electrode 151 and the drain electrode 152.

[0043] In this embodiment, when a high voltage is applied to the drain 152, the deep N-well 110 is N-type and the arc-shaped regulating post 131 is P-type, forming a lateral PN junction between the deep N-well 110 and the arc-shaped regulating post 131. These lateral PN junctions deplete each other, forming a very wide depletion region, thereby effectively carrying the voltage.

[0044] In this embodiment, since the source 151 forms a ring surrounding the drain 152, the current flows radially from the outer peripheral source 151 to the central drain 152. Traditional straight-line regulating columns have inconsistent electric field modulation capabilities in different angular directions, easily causing azimuth-dependent electric field inhomogeneity. In contrast, the arc-shaped regulating column 131 extends circumferentially, its curvature naturally conforming to the current flow lines, providing symmetrical electric field modulation in all radial directions, achieving true two-dimensional planar electric field homogenization.

[0045] Under high reverse bias, the edge of the drain 152 is the area with the most severe electric field concentration. The arc-shaped regulating post 131 is arranged around the drain 152, and its PN junction depletion region can uniformly wrap around the drain 152 from all sides, effectively dispersing the electric field intensity and preventing a certain point from reaching the critical breakdown field strength first.

[0046] As an feasible approach, such as Figure 6 As shown, multiple arc-shaped adjustment columns 131 are arranged on multiple concentric circles, and each circle has at least two arc-shaped adjustment columns 131, with the arc-shaped adjustment columns 131 of adjacent circles being staggered.

[0047] In this embodiment, the arc-shaped adjustment posts 131 are distributed on multiple concentric circles centered on the drain 152, forming a radially layered structure; each circumference contains at least two separate arc-shaped adjustment posts 131 to avoid forming a complete P-ring (otherwise it would block the current path), wherein each circumference may include 2-8 arc-shaped adjustment posts 131. The arc-shaped adjustment posts 131 on adjacent circumferences are staggered in angular position to form a honeycomb-like interlaced pattern.

[0048] Multiple arc-shaped adjustment posts 131 are arranged on multiple circles, forming an alternating structure of P-type, N-type, and P-type-N-type along the direction from the drain 152 to the source 151, forming multiple lateral PN junctions. The electric field of this alternating structure can become flatter and more uniform, thus bearing a higher voltage for the same length.

[0049] Specifically, the doping concentration of the arc-shaped adjustment pillars 131 on two adjacent circles can be the same or different. The inner circle is closer to the drain 152 region with a high electric field and requires stronger charge compensation; the outer circle is closer to the source 151 region with a low electric field and the compensation strength can be appropriately weakened. By varying the size, doping concentration, or number of adjustment pillars on circles with different radii, the equivalent doping distribution along the radial direction can be customized, so that the electric field decays smoothly from the drain 152 to the source 151, approaching an ideal uniform distribution.

[0050] The field-effect transistor in this embodiment controls pinch-off by depleting the deep N-well 110 and the body region 120. Specifically, when the source 151 is not energized, the current normally flows through the deep N-well 110 to the drain 152. When the source 151 is gradually energized, the deep N-well 110 and the body region 120 are depleted, the depletion region narrows, and the current path is pinched off.

[0051] exist Figure 7 In this process, the shape of the arc-shaped adjustment column 131 between the edge of the field oxygen layer 141 and the source electrode 151 can be adjusted (e.g., Figure 7 The rightmost arc-shaped adjusting column (131) is used to adjust the pinch-off voltage. Specifically, the larger the radial dimension of the arc-shaped adjusting column 131, the lower the pinch-off voltage; the smaller the radial dimension of the arc-shaped adjusting column 131, the higher the pinch-off voltage.

[0052] Optionally, the radial length of the arc-shaped adjusting column 131 (e.g.) Figure 3 and Figure 7 The D1 in the sample is greater than 5 μm.

[0053] In the above embodiment, the radial length of the arc-shaped adjustment column 131 is greater than 5 μm, giving it sufficient radial length to enhance charge storage and modulation capabilities, and making the electric field distribution closer to an ideal rectangle.

[0054] In addition, since the arc-shaped adjustment post 131 is arc-shaped and has a relatively complex shape, and due to the limitations of the precision requirements of ion implantation in the existing technology, the radial length of the arc-shaped adjustment post 131 is greater than 5μm, so that it can tolerate the deviation caused by diffraction when light passes through the pattern on the mask during the photolithography process.

[0055] Understandably, the radial length of the arc-shaped adjustment column 131 should not be too large, so as not to affect the normal operation of the deep N-well 110.

[0056] As an feasible approach, such as Figure 6 and Figure 7 As shown, the electric field adjustment structure 130 may also include a plurality of cylindrical adjustment elements 132 disposed in the deep N-well 110 below the drain 152.

[0057] In this embodiment, the cylindrical adjustment member 132 is located in the deep N-well 110 between the heavily doped region of the drain 152 and the substrate 100 in the vertical direction, and extends along the thickness direction of the device.

[0058] The area below the drain 152 is the region with the strongest electric field, especially in the direction perpendicular to the surface where there is a significant electric field gradient. The cylindrical adjustment element 132 is placed below the drain 152. The P-type cylindrical adjustment element 132 forms a vertical PN junction here. Its depletion region can extend upward to the interface of the drain 152 and downward to the depth of the deep N-well 110, effectively dispersing the peak value of the vertical electric field and preventing premature breakdown on the surface or in the body.

[0059] Optionally, the diameter of the cylindrical adjusting member 132 (e.g.) Figure 3 The D2 in the sample is greater than 2μm.

[0060] In this embodiment, similar to the arc-shaped adjusting column 131, the diameter of the cylindrical adjusting member 132 is set to be greater than 2μm.

[0061] As an feasible approach, such as Figure 6 and Figure 7 As shown, the electric field adjustment structure penetrates the deep N-well, that is, the arc-shaped adjustment column 131 and the cylindrical adjustment element 132 penetrate the deep N-well 110.

[0062] The arc-shaped adjustment post 131 and the cylindrical adjustment member 132 extend vertically from the top to the bottom of the deep N-well 110, that is, completely penetrate the entire thickness of the N-type deep N-well 110. The bottom can contact the P-type substrate 100 (or be isolated from but adjacent to it), and the top is close to the surface withstand layer or the highly doped region of the drain 152.

[0063] The arc-shaped adjustment column 131 penetrates the depth of the deep N-well 110 in the vertical direction and forms a continuous arc segment in the horizontal plane, creating a quasi-closed potential contour line to guide the smooth transition of the electric field lines and reduce distortion. The penetrating structure ensures that the P / N charges strictly alternate throughout the depth of the deep N-well 110, making the electric field tend to be uniform in the z-direction as well, avoiding bottom breakdown. The penetrating P-type adjustment structure and the N-region deep N-well 110 form a complete PN column pair, which can be depleted bidirectionally under reverse bias. The depletion region rapidly expands to the entire volume of the deep N-well 110, with no undepleted dead regions, improving the uniformity of the entire deep N-well 110.

[0064] Optionally, forming a deep N-well 110 and a P-type body region 120 on the substrate 100 may include: S210: N-type ion implantation is performed on the substrate to form a deep N-well 110 on the substrate 100; Based on a P-type silicon substrate 100, a deep N-well 110 region is defined by a single mask lithography step, and then phosphorus P is implanted. + or arsenic (As) +Ions form a deep N-well 110, creating a continuous N-type region on the surface of the substrate 100, which serves as a channel for subsequent high-voltage current.

[0065] S220: P-type ion implantation is performed on the substrate to form a bulk region 120 surrounding the outer periphery of the deep N-well 110 and spaced from the deep N-well 110, and an electric field modulation structure 130 located within the deep N-well 110 is formed.

[0066] Using another photomask, boron (B) was simultaneously implanted in the following two regions. + Ions: One region is a P-type body region 120 formed around the deep N-well 110, which is used for the subsequent source 151 and channel formation; the second region is a P-type electric field conditioning structure 130 formed at a specific position inside the deep N-well 110, such as a multi-ring misaligned arc region and a columnar conditioning element 132 below the drain 152. The arc-shaped conditioning column 131 and the columnar conditioning element 132 constitute the electric field conditioning structure 130.

[0067] As can be seen from the above, the body region 120 and the electric field conditioning structure 130 are completed synchronously through the same ion implantation.

[0068] As one feasible approach, the doping concentration of the deep N-well 110 is at 1E. 12 -1E 13 between.

[0069] This application also provides a field-effect transistor (FET), which is fabricated using the above-described FET fabrication method, such as... Figure 6 and Figure 7 As shown, the system includes a substrate 100; a deep N-well 110 and a body region 120 spaced apart on the substrate 100, the body region 120 surrounding the outer periphery of the deep N-well 110, and a plurality of P-type electric field adjustment structures 130 embedded in the deep N-well 110; and a field oxide layer 141 located on the surface of the substrate 100, the field oxide layer 141 having at least two first windows corresponding to the deep N-well 110 and a second window corresponding to the body region 120, the field oxide layer 141 also having a drain 152, a source 151 and a body contact, the drain 152 and the source 151 respectively passing through the first windows and connected to the deep N-well 110, and the source 151 surrounding the outer periphery of the drain 152, and the body contact passing through the second window and connected to the body region 120.

[0070] The field-effect transistor (FET) of this application embodiment is based on the above-described FET fabrication method and includes: a P-type substrate 100; a deep N-well 110 and a P-type body region 120 spaced apart on the substrate 100, wherein the body region 120 surrounds the outer periphery of the deep N-well 110 but does not directly contact it; a plurality of P-type electric field adjustment structures 130 are embedded in the deep N-well 110; a field oxide layer 141 is covered on the surface of the substrate 100, and a window is formed thereon to form a drain 152, a source 151, and a body contact, wherein the source 151 is annularly surrounding the central drain 152, and the body contact connects to the outer body region 120. The electric field adjustment structure 130 includes an arc-shaped adjustment pillar 131 arranged in multiple staggered rings and penetrating the deep N-well 110 and a cylindrical adjustment member 132 below the drain 152.

[0071] When the field-effect transistor is in the off-voltage state, the P-type electric field conditioning structure 130 embedded in the deep N-well 110 forms a three-dimensional superjunction network with the N-type deep N-well 110. Through full-thickness charge balance, the electric field is uniformly distributed in the radial, angular, and vertical directions, effectively suppressing local electric field concentration. At the same time, the symmetrical layout of the ring source 151 and the central drain 152, together with the top field oxide layer 141 and the field plate 153 structure, further optimizes the surface electric field. This synergistic effect achieves all-round electric field homogenization from the bulk to the surface, significantly improving the breakdown voltage.

[0072] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0073] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A method for fabricating a field-effect transistor, characterized in that, include: Provide substrate; A deep N-well and a P-type body region are formed on the substrate. The body region surrounds the outer periphery of the deep N-well and is spaced apart from the deep N-well. A plurality of P-type electric field modulation structures are embedded in the deep N-well. A field oxygen layer is formed on the upper surface of the substrate, the field oxygen layer having at least two first windows on the deep N-well and a second window on the body region; A drain and a source are formed on the deep N-well through the first window, and a body contact is formed in the body region through the second window, wherein the source surrounds the outer periphery of the drain. Polycrystalline silicon is formed on the field oxygen layer as a field plate.

2. The method for fabricating a field-effect transistor according to claim 1, characterized in that, The electric field adjustment structure includes a plurality of arc-shaped adjustment columns extending in a circumferential direction disposed between the source and the drain.

3. The method for fabricating a field-effect transistor according to claim 2, characterized in that, Multiple arc-shaped adjustment columns are arranged on multiple concentric circles, and each circle has at least two arc-shaped adjustment columns, with the arc-shaped adjustment columns of adjacent circles being staggered.

4. The method for fabricating a field-effect transistor according to claim 2, characterized in that, The radial length of the arc-shaped adjustment column is greater than 5 μm.

5. The method for fabricating a field-effect transistor according to claim 1, characterized in that, The electric field adjustment structure also includes a plurality of cylindrical adjustment elements disposed within the deep N-well below the drain electrode.

6. The method for fabricating a field-effect transistor according to claim 5, characterized in that, The diameter of the cylindrical adjusting component is greater than 2 μm.

7. The method for fabricating a field-effect transistor according to claim 1, characterized in that, The electric field modulation structure penetrates the deep N-well.

8. The method for fabricating a field-effect transistor according to claim 1, characterized in that, The formation of a deep N-well and a P-type bulk region on the substrate includes: N-type ion implantation is performed on the substrate to form a deep N-well; P-type ion implantation is performed on the substrate to form a bulk region surrounding the outer periphery of the deep N-well and spaced from the deep N-well, and an electric field modulation structure is formed within the deep N-well.

9. The method for fabricating a field-effect transistor according to claim 1, characterized in that, The doping concentration of the deep N-well is in the range of 1E. 12 -1E 13 between.

10. A field-effect transistor, characterized in that, include: Substrate; A deep N-well and a body region are spaced apart on the substrate, the body region surrounds the outer periphery of the deep N-well, and a plurality of P-type electric field modulation structures are embedded in the deep N-well. A field oxide layer is located on the surface of the substrate. The field oxide layer has at least two first windows corresponding to the deep N-well and a second window corresponding to the body region. A drain, a source, and a body contact are also disposed on the field oxide layer. The drain and the source are respectively connected to the deep N-well through the first windows, and the source surrounds the outer periphery of the drain. The body contact is connected to the body region through the second window.

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