Semiconductor structure and method of forming the same
By forming effective fins suspended on the substrate in the semiconductor structure and covering the device gate structure, the problem of poor gate control over the channel is solved, effective channel control is achieved, short-channel effect is reduced, and semiconductor performance is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2024-12-20
- Publication Date
- 2026-06-23
AI Technical Summary
As semiconductor processes become miniaturized, the distance between the drain and source of traditional planar MOSFETs decreases, reducing the gate's control over the channel and making short-channel effects more likely to occur. The performance of existing semiconductor structures needs to be improved.
By forming an effective fin suspended above the substrate on the substrate, and then extending it across and surrounding the gate structure of the device, the contact area between the gate structure and the fin is increased, thus forming a fin field-effect transistor (FinFET).
This improves the device's gate structure's control over the channel, reduces the short-channel effect, and enhances the performance of the semiconductor structure.
Smart Images
Figure CN122269769A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Currently, in semiconductor manufacturing, as semiconductor processes continue to miniaturize, the distance between the drain and source of traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) is constantly decreasing. The contact area between the bottom of the gate and the drain and source is getting smaller and smaller, which leads to a decrease in the gate structure's control over the channel. The difficulty of pinching off the channel by the gate voltage is also increasing, making the subthreshold leakage phenomenon, also known as the short-channel effect (SCE), more likely to occur.
[0003] To reduce the impact of short-channel effects, semiconductor processes have gradually shifted from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs.
[0004] However, the performance of the semiconductor structures currently being developed needs to be improved. Summary of the Invention
[0005] In view of this, the present invention provides a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.
[0006] The present invention provides a semiconductor structure comprising: a substrate; an effective fin suspended above the substrate; and a device gate structure located above the substrate, the device gate structure spanning the effective fin and surrounding and covering the effective fin.
[0007] Optionally, the height of the effective fin is 40 nm to 70 nm along the normal direction of the substrate surface.
[0008] Optionally, the distance from the bottom of the effective fin to the substrate is 10 nm to 30 nm.
[0009] Optionally, the semiconductor structure further includes an interlayer dielectric layer located on a substrate on the side of the device gate structure, and the interlayer dielectric layer covers the sidewall of the device gate structure.
[0010] Optionally, the semiconductor structure further includes: source / drain doped layers located in the effective fins on both sides of the device gate structure.
[0011] Optionally, the semiconductor structure further includes a well region located in the substrate;
[0012] Wherein, when the transistor corresponding to the effective fin is an N-type transistor, the dopant ions in the well region of the substrate where the effective fin is located are P-type ions; when the transistor corresponding to the effective fin is a P-type transistor, the dopant ions in the well region of the substrate where the effective fin is located are N-type ions.
[0013] Optionally, the substrate includes a substrate and a bottom fin located on the substrate;
[0014] The effective fin is suspended above the bottom fin.
[0015] Optionally, the semiconductor structure further includes an isolation structure located within a substrate on the side of the fin and covering the sidewall of the bottom fin.
[0016] The present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an effective fin suspended above the substrate; and forming a device gate structure located above the substrate, the device gate structure spanning the effective fin and surrounding and covering the effective fin.
[0017] Optionally, the step of forming an effective fin suspended above the substrate includes:
[0018] A channel protrusion structure is formed on the substrate, wherein the channel protrusion structure includes a sacrificial layer and an effective fin located above the sacrificial layer;
[0019] Remove the sacrificial layer so that the effective fin is suspended above the base.
[0020] Optionally, the step of forming the channel protrusion structure on the substrate includes:
[0021] A sacrificial material layer is formed on the substrate;
[0022] A fin material layer is formed on the sacrificial material layer;
[0023] The fin material layer and the sacrificial material layer are patterned to form a channel protrusion structure protruding on the substrate, and the remaining sacrificial material layer is used as the sacrificial layer, and the remaining fin material layer is used as the effective fin.
[0024] Optionally, in the step of patterning the fin material layer and the sacrificial material layer, a portion of the substrate thickness is also patterned to form a bottom fin protruding from the remaining substrate thickness, and the remaining substrate thickness that is not patterned serves as a substrate.
[0025] Optionally, before removing the sacrificial layer, the formation method further includes:
[0026] An isolation structure is formed within the base on the side of the bottom fin, the isolation structure covering the bottom fin and exposing the sacrificial layer.
[0027] Optionally, the process of forming the sacrificial material layer on the substrate includes an epitaxial process.
[0028] Optionally, the removal selectivity ratio between the sacrificial layer and the effective fin is greater than 12:1, and the removal selectivity ratio between the sacrificial layer and the substrate is greater than 12:1.
[0029] Optionally, the material of the sacrificial layer includes silicon germanide or silicon carbide.
[0030] Optionally, before removing the sacrificial layer, the formation method further includes:
[0031] A pseudo-gate structure is formed on the substrate, spanning the channel protrusion structure, the pseudo-gate structure covering part of the top and part of the sidewall of the channel protrusion structure;
[0032] An interlayer dielectric layer is formed on the side of the pseudo-gate structure, covering the sidewall of the pseudo-gate structure;
[0033] After the interlayer dielectric layer is formed, the pseudo-gate structure is removed.
[0034] Optionally, before forming the channel protrusion structure on the substrate, the forming method further includes:
[0035] A well region is formed in the substrate. If the transistor to be formed above the well region is an N-type transistor, the dopant ions in the well region are P-type ions. If the transistor to be formed above the well region is a P-type transistor, the dopant ions in the well region are N-type ions. After the well region is formed, the substrate is subjected to an annealing process.
[0036] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0037] In the semiconductor structure provided by the present invention, the effective fins can be suspended above the substrate, so that the device gate structure can span and surround the effective fins. This increases the contact area between the device gate structure and the effective fins, thereby improving the control capability of the device gate structure over the channel, reducing the short-channel effect, and thus improving the performance of the semiconductor structure.
[0038] In the semiconductor structure formation method provided by the present invention, by forming an effective fin suspended above the substrate, a gap is formed between the effective fin and the substrate. In this way, when forming a device gate structure located above the substrate, the device gate structure can span and surround the effective fin, increasing the contact area between the device gate structure and the effective fin, thereby improving the control capability of the device gate structure over the channel, reducing the short-channel effect, and thus improving the performance of the semiconductor structure. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention;
[0040] Figures 2 to 11 This is a schematic diagram of the structure corresponding to each step in the method for forming the semiconductor structure of the present invention. Detailed Implementation
[0041] As can be seen from the background technology, the performance of currently formed semiconductor structures needs to be improved.
[0042] Research has shown that in a semiconductor structure formation method, to increase the driving current while keeping the fin width constant, it is usually necessary to increase the fin height, which results in a larger aspect ratio (i.e., the ratio of height to width). However, a larger aspect ratio not only increases the manufacturing difficulty but also reduces the gate's control over the channel.
[0043] In another method of forming a semiconductor structure, the gate's control over the channel can be enhanced by reducing the width of the fin, especially the top width, but this will damage the fin surface.
[0044] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an effective fin suspended above the substrate; and forming a device gate structure located above the substrate, the device gate structure spanning the effective fin and surrounding and covering the effective fin.
[0045] In the forming method provided by the present invention, by forming an effective fin suspended above the substrate, a gap is formed between the effective fin and the substrate. In this way, when forming a device gate structure located above the substrate, the device gate structure can span and surround the effective fin, increasing the contact area between the device gate structure and the effective fin, thereby improving the control capability of the device gate structure over the channel, reducing the short-channel effect, and thus improving the performance of the semiconductor structure.
[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be described by way of example below with reference to the accompanying drawings.
[0047] Figure 1 A schematic diagram of one embodiment of the semiconductor structure of the present invention is shown below. Figure 1 As shown, in this embodiment, the semiconductor structure includes: a substrate 100; an effective fin 110 suspended above the substrate 100; and a device gate structure 124 located above the substrate 100, the device gate structure 124 spanning across the effective fin 110 and surrounding and covering the effective fin 110.
[0048] By suspending the effective fin 110 above the substrate 100, the device gate structure 124 can span and surround the effective fin 110, thereby increasing the contact area between the device gate structure 124 and the effective fin 110, thereby improving the control capability of the device gate structure 124 over the channel, reducing the short-channel effect, and thus improving the performance of the semiconductor structure.
[0049] The substrate 100 can provide the basis for the process operation of forming semiconductor structures. These semiconductor structures may include fin field-effect transistors (FinFETs).
[0050] In this embodiment, the substrate 100 may include a substrate (not shown) and a bottom fin (not shown) located on the substrate, wherein the substrate is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.
[0051] In this embodiment, the bottom fin and the substrate are an integral structure. In other embodiments, the bottom fin may also be a semiconductor layer located on the substrate, thereby achieving precise control over the height of the bottom fin.
[0052] Therefore, in this embodiment, the material of the bottom fin is the same as the material of the substrate; for example, the material of the bottom fin is silicon. In other embodiments, the material of the bottom fin can also be a suitable semiconductor material for forming the bottom fin, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the bottom fin can also be different from the material of the substrate.
[0053] In this embodiment, the semiconductor structure further includes a well region 102 located in the substrate 100.
[0054] The trap region 102 can serve as a lateral diffusion region to form a channel with a concentration gradient.
[0055] In the case where the transistor corresponding to the effective fin 110 is an N-type transistor, the doped ions in the well region 102 of the substrate 100 in the region where the effective fin 110 is located are P-type ions; in the case where the transistor corresponding to the effective fin 110 is a P-type transistor, the doped ions in the well region 102 of the substrate 100 in the region where the effective fin 110 is located are N-type ions.
[0056] The effective fin 110 is used to provide a channel for the semiconductor structure.
[0057] In this embodiment, when the base 100 includes a bottom fin, the effective fin 110 can be suspended above the bottom fin.
[0058] By suspending the effective fin 110 above the substrate 100, with a gap between the bottom of the effective fin 110 and the top of the substrate 100, it is advantageous to form a device gate structure 124 that spans and surrounds the effective fin 110.
[0059] In this embodiment, the material of the effective fin 110 is the same as the material of the substrate, for example, the material of the effective fin 110 is silicon. In other embodiments, the material of the effective fin can also be a semiconductor material suitable for forming the effective fin, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the effective fin can also be different from the material of the substrate.
[0060] In this embodiment, the height of the effective fin 210 along the normal direction of the surface of the substrate 100 is 40nm to 70nm, for example, 45nm, 50nm, and 65nm.
[0061] By making the height of the effective fin 210 greater than or equal to 40 nm, the DC current on the effective fin 210 can be increased, thereby enhancing the driving capability of the effective fin 210; and by making the height of the effective fin 210 less than or equal to 70 nm, the capacitance value of the effective fin 210 can be reduced, thereby increasing the switching speed of the semiconductor structure.
[0062] In this embodiment, the distance from the bottom of the effective fin 110 to the substrate 100 can be 10nm to 30nm.
[0063] When the device is in operation, the device gate structure 124 is used to control the opening and closing of the conductive channel.
[0064] In this embodiment, the device gate structure 124 includes a gate dielectric layer 120 and a gate electrode layer 122 located on the gate dielectric layer 120.
[0065] The gate electrode layer 122 is used as an external electrode for electrical connection between the device gate structure 124 and external circuitry.
[0066] In this embodiment, the device gate structure 124 is a metal gate structure.
[0067] Accordingly, the material of the gate electrode layer 122 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).
[0068] In this embodiment, the gate electrode layer 122 includes one or both of a work function layer and an electrode layer.
[0069] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when the semiconductor structure is an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and titanium aluminum carbide; when the semiconductor structure is a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.
[0070] The electrode layer is used for electrical connection with external circuitry. The electrode layer is made of a conductive material, including one or more of tungsten and aluminum. In this embodiment, the electrode layer is made of tungsten.
[0071] The gate dielectric layer 120 is used to achieve electrical isolation between the gate electrode layer 122 and the conductive channel. The material of the gate dielectric layer 120 includes one or more of hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon oxynitride hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, aluminum oxide, silicon oxide, and lanthanum oxide.
[0072] In this embodiment, the device gate structure 124 is a metal gate structure. Therefore, the gate dielectric layer 120 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide.
[0073] The material of the high-k gate dielectric layer can be selected from hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon oxynitride hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide. As an example, the material of the gate dielectric layer 120 is hafnium oxide.
[0074] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may consist only of a gate oxide layer.
[0075] In other embodiments, the device gate structure may also be a polysilicon gate structure.
[0076] See Figure 1The semiconductor structure also includes an interlayer dielectric layer 118, located on the substrate 200 on the side of the device gate structure 124, and the interlayer dielectric layer 118 covers the sidewall of the device gate structure 124.
[0077] The interlayer dielectric layer 118 can be used to isolate adjacent devices.
[0078] In this embodiment, the top height of the interlayer dielectric layer 118 can be flush with the top height of the device gate structure 124.
[0079] In this embodiment, the material of the interlayer dielectric layer 118 can be silicon nitride, making the morphology of the interlayer dielectric layer 118 more regular. In some other embodiments, the material of the interlayer dielectric layer 118 can also be other insulating materials, such as silicon oxide.
[0080] In this embodiment, the semiconductor structure further includes a source / drain doped layer (not shown) located in the effective fins 110 on both sides of the device gate structure 124.
[0081] Source and drain doped layers can be used as the source or drain of a field-effect transistor. When the field-effect transistor is working, the source and drain doped layers can be used to provide carrier sources.
[0082] In this embodiment, the source / drain doped layer may include a stress layer doped with ions. The stress layer can be used to provide stress to the channel region, thereby improving the carrier mobility.
[0083] Specifically, when the semiconductor structure is an NMOS transistor, the source and drain doping layers may include a stress layer doped with N-type ions, and the material of the stress layer may be silicon or silicon carbide; when the semiconductor structure is a PMOS transistor, the source and drain doping layers may include a stress layer doped with P-type ions, and the material of the stress layer may be silicon or silicon germanide.
[0084] In this embodiment, the semiconductor structure may further include: an isolation structure 114 located within the substrate 100 on the side of the effective fin 110.
[0085] The isolation structure 114 can be used to isolate adjacent devices in a semiconductor structure.
[0086] In this embodiment, the isolation structure 114 may be formed of an insulating material. For example, the insulating material may include one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. As an example, the material of the isolation structure 114 is silicon nitride.
[0087] In this embodiment, the isolation structure 114 can be a shallow trench isolation structure.
[0088] In this embodiment, when the base 100 includes a bottom fin, the isolation structure 114 can also cover the sidewall of the bottom fin.
[0089] Figures 2 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0090] refer to Figure 2 Provides a base of 200.
[0091] The substrate 200 can provide the basis for the process operation of forming semiconductor structures. These semiconductor structures may include fin field-effect transistors (FinFETs).
[0092] In this embodiment, the substrate 200 includes a substrate (not shown), and the substrate material is silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be a material suitable for process requirements or easy to integrate.
[0093] See Figure 3 Before the formation of the channel protrusion structure, the formation method also includes: forming a well region 202 in the substrate 200.
[0094] The trap region 202 can serve as a lateral diffusion region to form channels with a concentration gradient.
[0095] In this embodiment, when the transistor to be formed above the well region 202 is an N-type transistor, the dopant ions in the well region 202 are P-type ions; when the transistor to be formed above the well region 202 is a P-type transistor, the dopant ions in the well region 202 are N-type ions.
[0096] In this embodiment, ion implantation process (such as...) Figure 3 (As indicated by the arrow in the image) a well region 202 is formed in the substrate 200.
[0097] In this embodiment, the parameters of the ion implantation process include: implantation energy of 15 KeV to 50 KeV and implantation dose of 5e12 cm⁻¹. -2 up to 5e13 cm -2 The ion implantation angle is 0° to 7°, and the implanted ions include boron ions or phosphorus ions.
[0098] The ion implantation angle refers to the angle between the ion beam and the surface of the substrate 200.
[0099] In this embodiment, by making the implantation energy greater than or equal to 15 KeV, the ion implantation depth can be increased, thereby increasing the thickness of the formed well region 202 and thus reducing the short-channel effect; by making the implantation energy less than or equal to 50 KeV, the lattice damage to the substrate 200 can be reduced.
[0100] In this embodiment, the injected dose is greater than or equal to 5e12 cm. -2 This can increase the ion implantation depth, thereby increasing the thickness of the formed well region 202, and thus reducing the short-channel effect; by making the implantation dose less than or equal to 5e13cm -2 It can reduce lattice damage to substrate 200.
[0101] In this embodiment, by making the ion implantation angle greater than 0°, it is possible to prevent ions from diffusing in the horizontal direction, thereby reducing the impact on the channel and improving the performance of the semiconductor structure; by making the ion implantation angle less than or equal to 7°, it is possible to increase the implantation depth and increase the thickness of the formed well region 202, thereby reducing the short-channel effect.
[0102] See Figure 3 After forming the well region 202, the substrate 200 is subjected to an annealing process.
[0103] Annealing the substrate 200 can repair lattice defects in the substrate 200, thereby improving the lattice quality and crystallization uniformity of the substrate 200.
[0104] In this embodiment, the annealing process includes a rapid thermal annealing (RTA) process, and the parameters of the annealing process include an annealing time of 30s to 60s and an annealing temperature of 900℃ to 1000℃.
[0105] In this embodiment, by making the annealing time greater than or equal to 30s, the repair effect on the lattice defects of the substrate 200 can be improved; by making the annealing time less than or equal to 60s, the depth of heat action can be reduced, thereby reducing the damage to the substrate 200 and improving the formation quality of the substrate 200.
[0106] In this embodiment, by setting the annealing temperature to be greater than or equal to 900°C, the repair effect on the lattice defects of the substrate 200 can be improved; by setting the annealing temperature to be less than or equal to 1000°C, the impact on the substrate 200 can be reduced, thereby improving the formation quality of the substrate 200. In some other embodiments, depending on the actual process, other suitable annealing processes can also be used for annealing, such as spike annealing, laser thermal annealing, etc. The present invention does not limit the annealing process.
[0107] See Figures 4 to 10 This forms an effective fin 210 suspended above the base 200.
[0108] By suspending the effective fin 210 above the substrate 200, and having a gap between the bottom of the effective fin 210 and the top of the substrate 200, it is beneficial to subsequently form a device gate structure that spans and surrounds the effective fin 210.
[0109] The effective fin 210 can be used to provide a conductive channel for a semiconductor structure.
[0110] In this embodiment, the material of the effective fin 210 is the same as the material of the substrate, for example, the material of the effective fin 210 is silicon. In other embodiments, the material of the effective fin can also be a semiconductor material suitable for forming the effective fin, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the effective fin can also be different from the material of the substrate.
[0111] In this embodiment, the height of the effective fin 210 along the normal direction of the surface of the substrate 200 is 40nm to 70nm, for example, 45nm, 50nm, and 65nm.
[0112] By making the height of the effective fin 210 greater than or equal to 40 nm, the DC current on the effective fin 210 can be increased, thereby enhancing the driving capability of the effective fin 210; and by making the height of the effective fin 210 less than or equal to 70 nm, the capacitance value of the effective fin 210 can be reduced, thereby increasing the switching speed of the semiconductor structure.
[0113] The following combination Figures 4 to 10 The steps for forming the effective fin 210 suspended above the base 200 are described in detail.
[0114] See Figure 4 and Figure 5 A channel protrusion structure 212 is formed on the substrate 200.
[0115] The channel protrusion structure 212 is used to provide a process basis for the formation of the effective fin 210.
[0116] In this embodiment, the channel protrusion structure 212 may include a sacrificial layer 208 and an effective fin 210 located above the sacrificial layer 208.
[0117] The effective fin 210 is used to provide a conductive channel for the semiconductor structure, and the sacrificial layer 208 can be used to support the effective fin 210, thereby providing a process basis for the subsequent implementation of the effective fin 210 suspended on the substrate 200.
[0118] In this embodiment, the step of forming the channel protrusion structure 212 on the substrate 200 includes: see Figure 4 A sacrificial material layer 204 is formed on the substrate 200.
[0119] The sacrificial material layer 204 is used to form the sacrificial layer 208.
[0120] In this embodiment, the process of forming the sacrificial material layer 204 on the substrate 200 includes an epitaxial process.
[0121] In some other embodiments, a deposition process (e.g., chemical vapor deposition) may also be used to form a sacrificial material layer 204 on the substrate 200.
[0122] In this embodiment, the thickness of the sacrificial material layer 204 along the normal direction of the surface of the substrate 200 is 10 nm to 30 nm. For example, 15 nm, 20 nm, 25 nm, and 27 nm, etc.
[0123] By making the thickness of the sacrificial material layer 204 greater than or equal to 10 nm, the thickness of the formed sacrificial layer 208 will not be too small, which can reduce the difficulty of removing the sacrificial layer 208; and by making the thickness of the sacrificial material layer 204 less than or equal to 30 nm, the stress of the sacrificial material layer 204 can be reduced, damage to the effective fin 210 can be reduced or avoided, and the morphological quality of the effective fin 210 can be improved.
[0124] In this embodiment, the materials of the sacrificial material layer 204 include silicon germanide and silicon carbide.
[0125] In one specific embodiment, the material of the sacrificial material layer 204 includes silicon germanide.
[0126] In this embodiment, the material of the effective fin 210 is silicon, and the material of the sacrificial layer 208 can be silicon germanide. In this way, the removal selectivity of silicon germanide and silicon is relatively high during the removal of the sacrificial layer 208. By setting the material of the sacrificial layer 208 to silicon germanide and the material of the effective fin 210 to silicon, the impact of the removal process of the sacrificial layer 208 on the effective fin 210 can be effectively reduced, thereby improving the quality of the effective fin 210 and thus helping to improve device performance.
[0127] See next Figure 4 In this embodiment, the step of forming the channel protrusion structure 212 on the substrate 200 further includes forming a fin material layer 206 on the sacrificial material layer 204.
[0128] The fin material layer 206 is used to form the effective fin 210.
[0129] In this embodiment, the process of forming the fin material layer 206 on the sacrificial material layer 204 includes an epitaxial process.
[0130] In some other embodiments, a deposition process (e.g., chemical vapor deposition) may be used to form the fin material layer 206 on the sacrificial material layer 204.
[0131] See Figure 5 In this embodiment, the step of forming the channel protrusion structure 212 on the substrate 200 further includes: patterning the fin material layer 206 and the sacrificial material layer 204 to form the channel protrusion structure 212 protruding on the substrate 200, and using the remaining sacrificial material layer 204 as the sacrificial layer 208, and using the remaining fin material layer 206 as the effective fin 210.
[0132] In this embodiment, the step of patterning the fin material layer 206 and the sacrificial material layer 204 includes: forming a hard mask material layer (not shown) and a photoresist (not shown) sequentially above the fin material layer 206, wherein the photoresist has patterned openings (not shown); using the photoresist as a mask, etching the hard mask material layer along the patterned openings to obtain multiple discrete hard mask layers (not shown); using the hard mask layer as a mask, etching the exposed fin material layer 206 and the sacrificial material layer 204 to expose the surface of the substrate 200, and using the remaining sacrificial material layer 204 as the sacrificial layer 208, and using the remaining fin material layer 206 as the effective fin 210.
[0133] It should be noted that in other embodiments, the channel protrusion structure can also be formed using other patterning processes, such as self-aligned multiple patterning (SAMP). SAMP can include self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP).
[0134] In this embodiment, during the step of patterning the fin material layer 206 and the sacrificial material layer 204, a portion of the thickness of the substrate 200 is also patterned to form a bottom fin (not shown) protruding from the remaining thickness of the substrate 200, and the remaining thickness of the substrate 200 that is not patterned serves as a substrate.
[0135] That is, the portion of the thickness of the trap region 202 located within the base 200 serves as the bottom fin.
[0136] The bottom fin is formed to provide space for the subsequent formation of the isolation structure 214.
[0137] In this embodiment, before performing the step of removing the sacrificial layer 208, see [link to relevant documentation]. Figure 6The method of forming further includes: forming an isolation structure 214 in the base 200 on the side of the bottom fin, the isolation structure 214 covering the bottom fin and exposing the sacrificial layer 208.
[0138] The isolation structure 214 can be used to isolate adjacent devices in a semiconductor structure.
[0139] In this embodiment, the step of forming an isolation structure 214 in the substrate 200 on the side of the bottom fin includes: forming an isolation material layer (not shown) covering the channel protrusion structure 212 on the substrate 200; etching back a portion of the isolation material layer to expose the top and sidewalls of the channel protrusion structure 212, and using the remaining isolation material layer as the isolation structure 214, with the isolation structure 214 exposing the sacrificial layer 208.
[0140] That is, the top of the isolation structure 214 is lower than or flush with the bottom surface of the sacrificial layer 208 so that the sacrificial layer 208 can be removed later.
[0141] In this embodiment, the isolation structure 214 may be formed of an insulating material. For example, the insulating material may include one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride.
[0142] In this embodiment, the isolation structure 214 can be a shallow trench isolation structure.
[0143] In this embodiment, when the fin material layer 206 and the sacrificial material layer 204 are patterned, and a portion of the thickness of the base 200 is also patterned, the isolation structure 214 can cover the sidewall of the bottom fin when the isolation structure 214 is formed.
[0144] In this embodiment, before performing the step of removing the sacrificial layer 208, see [link to relevant documentation]. Figure 7 and Figure 8 The formation method also includes: forming a pseudo-gate structure 216 and an interlayer dielectric layer 218.
[0145] See Figure 7 A pseudo-gate structure 216 is formed on the substrate 200, spanning the channel protrusion structure 212, and the pseudo-gate structure 216 covers part of the top and part of the sidewall of the channel protrusion structure 212.
[0146] The dummy gate structure 216 can be used to pre-reserve space for the subsequent formation of the device gate structure 224.
[0147] In this embodiment, the step of forming a pseudo-gate structure 216 spanning the channel protrusion structure 212 on the substrate 200 may include: forming a pseudo-gate material layer (not shown) covering the channel protrusion structure 212; performing patterning processing on the pseudo-gate material layer to expose part of the top wall and top of the channel protrusion structure 212; and using the remaining pseudo-gate material layer as the pseudo-gate structure 216.
[0148] In this embodiment, the pseudo-gate structure 216 can be a polycrystalline silicon gate structure or an amorphous silicon gate structure.
[0149] In this embodiment, after the isolation structure 214 is formed, the pseudo-gate structure 216 is formed. Therefore, in the step of forming the pseudo-gate structure 216 that spans the channel protrusion structure 212 on the substrate 200, the pseudo-gate structure 216 also covers part of the top of the isolation structure 214.
[0150] See Figure 8 An interlayer dielectric layer 218 is formed on the side of the pseudo-gate structure 216, covering the sidewall of the pseudo-gate structure 216.
[0151] The interlayer dielectric layer 218 can be used to isolate adjacent devices and also to support the effective fin 210 during the removal of the dummy gate structure 216 and the removal of the sacrificial layer 208, so that the effective fin 210 is suspended above the substrate 200.
[0152] In this embodiment, the step of the interlayer dielectric layer 218 may include: forming an interlayer dielectric material layer (not shown) covering the pseudo gate structure 216 on the substrate 200, and removing the interlayer dielectric material layer above the pseudo gate structure 216 using a planarization process with the top of the pseudo gate structure 216 as the stopping position, and the remaining part of the dielectric material layer as the interlayer dielectric layer 218.
[0153] In this embodiment, the top height of the interlayer dielectric layer 218 can be flush with the top height of the pseudo gate structure 310.
[0154] In this embodiment, the material of the interlayer dielectric layer 218 can be silicon nitride. In some other examples, the material of the interlayer dielectric layer 218 can also be other insulating materials, such as silicon oxide.
[0155] It should be noted that after forming the pseudo-gate structure 216 and before forming the interlayer dielectric layer 218, the process further includes forming source / drain doped layers (not shown in the figure) in the channel protrusion structures 212 on both sides of the pseudo-gate structure 216.
[0156] Source and drain doped layers can be used as the source or drain of a field-effect transistor. When the field-effect transistor is working, the source and drain doped layers can provide carrier sources.
[0157] In this embodiment, the source / drain doped layer may include a stress layer doped with ions. The stress layer can be used to provide stress to the channel region, thereby improving the carrier mobility.
[0158] Specifically, when forming an NMOS transistor, the source and drain doping layers may include a stress layer doped with N-type ions, and the material of the stress layer may be silicon or silicon carbide; when forming a PMOS transistor, the source and drain doping layers may include a stress layer doped with P-type ions, and the material of the stress layer may be silicon or silicon germanide.
[0159] In this embodiment, an epitaxial process can be used to form a stress layer, and ions can be self-doped in situ during the formation of the stress layer. The stress layer doped with ions is used as a source / drain doping layer.
[0160] In some other embodiments, after the stress layer is formed, ion implantation can be performed on the stress layer to form source / drain doped layers.
[0161] See Figure 9 After forming the interlayer dielectric layer 218, the pseudo gate structure 216 is removed.
[0162] By removing the pseudo-gate structure 216, the sacrificial layer 208 can be exposed, reducing the difficulty of removing the sacrificial layer 208.
[0163] Furthermore, by removing the dummy gate structure 216, a gate opening spanning the effective fin 210 can be formed in the interlayer dielectric layer 218, thereby providing space for the subsequent formation of the device gate structure.
[0164] See Figure 10 Remove the sacrificial layer 208 so that the effective fin 210 is suspended above the base 200.
[0165] By removing the sacrificial layer 208, a gap is created between the bottom of the effective fin 210 and the top of the substrate 200, thereby enabling the device gate structure to be formed in the gap.
[0166] In this embodiment, during the step of removing the sacrificial layer 208, there is a removal selectivity ratio between the sacrificial layer 208 and the effective fin 210. By making the sacrificial layer 208 and the effective fin 210 have a removal selectivity ratio, the damage to the effective fin 210 can be reduced during the removal of the sacrificial layer 208, the morphological quality of the effective fin 210 can be improved, and the performance of the formed semiconductor structure can be improved.
[0167] In one specific embodiment, in the step of removing the sacrificial layer 208, the removal selectivity ratio between the sacrificial layer 208 and the effective fin 210 is greater than 12:1, which makes the effect of reducing damage to the effective fin 210 significant.
[0168] In this embodiment, during the step of removing the sacrificial layer 208, there is a removal selectivity between the sacrificial layer 208 and the substrate 200. By making the sacrificial layer 208 and the substrate 200 have an etching selectivity, damage to the substrate 200 (e.g., the bottom fin) can be reduced during the removal of the sacrificial layer 208, the morphological quality of the substrate can be improved, and the performance of the formed semiconductor structure can be improved.
[0169] In one specific embodiment, in the step of removing the sacrificial layer 208, the removal selectivity ratio between the sacrificial layer 208 and the substrate 200 is greater than 12:1, which makes the effect of reducing damage to the substrate 200 significant.
[0170] In this embodiment, a vapor etching process is used to etch the exposed sacrificial layer 208 along the extension direction of the effective fin 210. Vapor etching is an isotropic etching process that can etch the sacrificial layer 208 along the extension direction of the effective fin 210. Furthermore, vapor etching easily achieves a large etching selectivity, which helps reduce the difficulty of etching the sacrificial layer 208 and reduces the probability of damage to other film structures (e.g., the effective fin 210 and the substrate 200).
[0171] See Figure 11 A device gate structure 224 is formed above the substrate 200, which spans the effective fin 210 and surrounds and covers the effective fin 210.
[0172] By making the device gate structure 224 span across and surround the effective fin 210, the contact area between the device gate structure 224 and the effective fin 210 can be increased, thereby improving the control capability of the device gate structure 224 over the channel, reducing the short-channel effect, and thus improving the performance of the semiconductor structure.
[0173] When the device is in operation, the device gate structure 224 is used to control the opening and closing of the conductive channel.
[0174] In this embodiment, the device gate structure 224 includes a gate dielectric layer 220 and a gate electrode layer 222 located on the gate dielectric layer 220.
[0175] The gate electrode layer 222 is used as an external electrode for electrical connection between the device gate structure 224 and the external circuit.
[0176] In this embodiment, the device gate structure 224 is a metal gate structure, and the material of the gate electrode layer 222 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).
[0177] In this embodiment, the gate electrode layer 222 includes one or both of a work function layer and an electrode layer.
[0178] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and titanium aluminum carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.
[0179] The electrode layer is used for electrical connection with external circuitry. The electrode layer is made of a conductive material, including one or more of tungsten and aluminum. In this embodiment, the electrode layer is made of tungsten.
[0180] The gate dielectric layer 220 is used to achieve electrical isolation between the gate electrode layer 222 and the conductive channel.
[0181] The material of the gate dielectric layer 220 includes one or more of hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon oxynitride hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, aluminum oxide, silicon oxide, and lanthanum oxide.
[0182] In this embodiment, the device gate structure 224 is a metal gate structure, and the gate dielectric layer 220 includes a high-k gate dielectric layer, which is made of a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon oxynitride hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.
[0183] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.
[0184] It should be noted that the semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.
[0185] While this specification discloses the invention as described above, the invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of this invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: Base; The effective fin is suspended above the base; A device gate structure is located above the substrate, the device gate structure spanning the effective fin and surrounding and covering the effective fin.
2. The semiconductor structure according to claim 1, characterized in that, Along the normal direction of the substrate surface, the height of the effective fin is 40 nm to 70 nm.
3. The semiconductor structure according to claim 1, characterized in that, The distance from the bottom of the effective fin to the substrate is 10 nm to 30 nm.
4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: An interlayer dielectric layer is located on a substrate on the side of the device gate structure, and the interlayer dielectric layer covers the sidewall of the device gate structure.
5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The source and drain doped layers are located in the effective fins on both sides of the gate structure of the device.
6. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure further includes a well region located in the substrate; Wherein, when the transistor corresponding to the effective fin is an N-type transistor, the dopant ions in the well region of the substrate where the effective fin is located are P-type ions; when the transistor corresponding to the effective fin is a P-type transistor, the dopant ions in the well region of the substrate where the effective fin is located are N-type ions.
7. The semiconductor structure according to claim 1, characterized in that, The substrate includes a substrate and a bottom fin located on the substrate; The effective fin is suspended above the bottom fin.
8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes an isolation structure located within the substrate on the side of the effective fin and covering the sidewall of the bottom fin.
9. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Forming an effective fin suspended above the substrate; A device gate structure is formed above the substrate, the device gate structure spanning the effective fin and surrounding and covering the effective fin.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The steps of forming an effective fin suspended above the substrate include: A channel protrusion structure is formed on the substrate, wherein the channel protrusion structure includes a sacrificial layer and an effective fin located above the sacrificial layer; Remove the sacrificial layer so that the effective fin is suspended above the base.
11. The method for forming a semiconductor structure according to claim 10, characterized in that, The step of forming the channel protrusion structure on the substrate includes: A sacrificial material layer is formed on the substrate; A fin material layer is formed on the sacrificial material layer; The fin material layer and the sacrificial material layer are patterned to form a channel protrusion structure protruding on the substrate, and the remaining sacrificial material layer is used as the sacrificial layer, and the remaining fin material layer is used as the effective fin.
12. The method for forming a semiconductor structure according to claim 11, characterized in that, In the step of patterning the fin material layer and the sacrificial material layer, a portion of the substrate thickness is also patterned to form a bottom fin that protrudes from the remaining substrate thickness, and the remaining substrate thickness that is not patterned serves as a substrate.
13. The method for forming a semiconductor structure according to claim 12, characterized in that, Before removing the sacrificial layer, the formation method further includes: An isolation structure is formed within the base on the side of the bottom fin, the isolation structure covering the bottom fin and exposing the sacrificial layer.
14. The method for forming a semiconductor structure according to claim 11, characterized in that, The process of forming the sacrificial material layer on the substrate includes an epitaxial process.
15. The method for forming a semiconductor structure according to claim 10, characterized in that, The removal selectivity ratio between the sacrificial layer and the effective fin is greater than 12:1, and the removal selectivity ratio between the sacrificial layer and the substrate is greater than 12:
1.
16. The method for forming a semiconductor structure according to claim 10, characterized in that, The material of the sacrificial layer includes silicon germanide or silicon carbide.
17. The method for forming a semiconductor structure according to claim 10, characterized in that, Before removing the sacrificial layer, the formation method further includes: A pseudo-gate structure is formed on the substrate, spanning the channel protrusion structure, the pseudo-gate structure covering part of the top and part of the sidewall of the channel protrusion structure; An interlayer dielectric layer is formed on the side of the pseudo-gate structure, covering the sidewall of the pseudo-gate structure; After the interlayer dielectric layer is formed, the pseudo-gate structure is removed.
18. The method for forming a semiconductor structure according to claim 10, characterized in that, Before forming the channel protrusion structure on the substrate, the forming method further includes: A well region is formed in the substrate. If the transistor to be formed above the well region is an N-type transistor, the dopant ions in the well region are P-type ions. If the transistor to be formed above the well region is a P-type transistor, the dopant ions in the well region are N-type ions. After the well region is formed, the substrate is subjected to an annealing process.