Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device of an embodiment includes an element region and a termination region. The element region includes circuit elements such as transistors and the like. The termination region has a first semiconductor region of a first conductivity type, a fourth semiconductor region of a second conductivity type surrounding the element region, a first insulating layer having a first portion and a second portion with the fourth semiconductor region between the first portion and the second portion, and a first conductive layer over the fourth semiconductor region. The first portion and the second portion of the first insulating layer each have a first region adjacent to the fourth semiconductor region, the first region extending to a depth greater than a depth of a second region of the first portion and the second portion.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2024-226406, filed on December 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0004] Power semiconductor devices have a component region and a termination region surrounding the component region. The component region includes, for example, semiconductor components such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). The termination region reduces the intensity of the electric field applied to the pn junction at the termination portion of the termination region and increases the breakdown voltage of the power semiconductor device. To improve the overall breakdown voltage of the power semiconductor device, it is desirable to increase the breakdown voltage of the termination region. Summary of the Invention

[0005] Typically, according to embodiments, a semiconductor device includes: a semiconductor layer having a first surface and a second surface opposite to the first surface; a device region in the semiconductor layer; and a termination region in the semiconductor layer. The termination region surrounds the device region. The device region includes: a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located between the first semiconductor region and the first surface, a third semiconductor region of a first conductivity type located between the second semiconductor region and the first surface, a gate electrode facing the second semiconductor region, a gate insulating film located between the second semiconductor region and the gate electrode, a first electrode on the first surface of the semiconductor layer and electrically connected to the third semiconductor region, and a second electrode on the second surface of the semiconductor layer. The termination region includes: the first semiconductor region; a plurality of fourth semiconductor regions of the second conductivity type located between the first semiconductor region and the first surface, the fourth semiconductor regions being spaced apart from each other in a first direction (the first direction being a direction outward from the device region toward the termination region); and a first insulating layer including a plurality of first portions and a plurality of second portions spaced apart from each other in the first direction. Each fourth semiconductor region is located between first portions and second portions adjacent to each other in the first direction. The termination region also includes a first conductive layer having a plurality of portions, each portion of the first conductive layer being on a first portion, a fourth semiconductor region, and a second portion. A first portion, a fourth semiconductor region, and a second portion are located between a portion of the first conductive layer and the first semiconductor region. A second electrode is also present in the termination region. Each first portion of the first insulating layer includes a first region and a second region. The first region is adjacent to the fourth semiconductor region. The depth of the first region from the first surface is greater than the depth of the second region from the first surface. Each second portion of the first insulating layer includes a third region and a fourth region. The third region is adjacent to the fourth semiconductor region. The depth of the third region from the first surface is greater than the depth of the fourth region from the first surface.

[0006] According to this embodiment, a semiconductor device capable of improving voltage resistance and a method for manufacturing the same can be provided. Attached Figure Description

[0007] Figure 1 This is a schematic top view of a semiconductor device according to an embodiment.

[0008] Figure 2 This is a schematic cross-sectional view of a portion of the semiconductor device in the embodiment.

[0009] Figure 3 This is a schematic cross-sectional view of a portion of the semiconductor device in the embodiment.

[0010] Figure 4This is a schematic cross-sectional view of a portion of the semiconductor device in the embodiment.

[0011] Figure 5 This is a schematic top view of the semiconductor device in the embodiment.

[0012] Figure 6 This is a schematic top view of the semiconductor device in the embodiment.

[0013] Figure 7 This is an enlarged schematic cross-sectional view of a portion of the semiconductor device in the embodiment.

[0014] Figure 8 This is an enlarged schematic cross-sectional view of a portion of the semiconductor device in the embodiment.

[0015] Figures 9 to 18 Aspects of a method for manufacturing a semiconductor device according to an embodiment are described.

[0016] Figure 19 This is an enlarged schematic cross-sectional view of a portion of a comparative example semiconductor device.

[0017] Figure 20 This is an enlarged schematic cross-sectional view of a portion of the semiconductor device of the first variant of the embodiment.

[0018] Figure 21 This is an enlarged schematic cross-sectional view of a portion of the semiconductor device in the second variation of the embodiment. Detailed Implementation

[0019] In the following description, certain exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following description, identical or substantially similar components are designated by the same reference numerals, and descriptions of these components may be appropriately omitted once described.

[0020] In this specification, the symbol n + Type, n type and n - The concentration of type n impurities decreases in the following order: n + Type, n type and n - Type. Symbol p + Type, p type and p - The concentration of p-type impurities decreases in the following order: p + Type, p type and p - type.

[0021] In this specification, the term "n-type impurity concentration" refers to the effective n-type impurity concentration after compensation (networking). Similarly, the term "p-type impurity concentration" refers to the effective p-type impurity concentration after compensation (networking). For example, when the actual n-type impurity concentration is higher than the actual p-type impurity concentration, the net concentration obtained by subtracting the actual p-type impurity concentration from the actual n-type impurity concentration is used as the n-type impurity concentration. The same applies to p-type impurity concentrations.

[0022] In this specification, the distribution and absolute value of impurity concentration in semiconductor regions can be measured, for example, by secondary ion mass spectrometry (SIMS). The relative magnitude relationship between impurity concentrations in two semiconductor regions can be determined, for example, by scanning capacitance microscopy (SCM). The distribution and absolute value of impurity concentration can be measured, for example, by extended resistance analysis (SRA). Using SCM and SRA, the relative magnitude relationship and absolute value of carrier concentration in semiconductor regions can be obtained. By assuming the activation rate of impurities, the relative magnitude relationship between impurity concentrations, impurity concentration distributions, and absolute values ​​of impurity concentrations in two different semiconductor regions can be obtained from the measurements of SCM and SRA.

[0023] Unless otherwise stated, the impurity concentration in a semiconductor region is considered to be the concentration in the central portion of the semiconductor region.

[0024] For example, in this specification, scanning electron microscopy (SEM) or transmission electron microscopy (TEM) can be used to measure the shape, thickness, and distance between components constituting a semiconductor device. Furthermore, for qualitative and quantitative analysis of the chemical composition of the components included in the semiconductor device described in this specification, Rutherford backscattered spectroscopy (RBS), secondary ion mass spectrometry (SIMS), energy-dispersive X-ray spectroscopy (EDX), electron energy loss spectroscopy (EELS), etc., can be used.

[0025] (Example)

[0026] The semiconductor device of the embodiment includes a component region and a termination region surrounding the component region. The component region includes a semiconductor layer, a gate electrode, a gate insulating film, a first electrode, and a second electrode.

[0027] A semiconductor layer having a first surface and a second surface opposite to the first surface includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type disposed between the first semiconductor region and the first surface, and a third semiconductor region of a first conductivity type disposed between the second semiconductor region and the first surface. A gate electrode faces the second semiconductor region. A gate insulating film is disposed between the second semiconductor region and the gate electrode. A first electrode is disposed on one side of the first surface of the semiconductor layer and electrically connected to the third semiconductor region. A second electrode is disposed on one side of the second surface of the semiconductor layer.

[0028] The termination region includes a semiconductor layer, a first insulating layer, a first conductive layer, and a second electrode. The semiconductor layer includes a first semiconductor region and a plurality of fourth semiconductor regions of a second conductivity type, disposed between the first semiconductor region and a first surface and in a direction from the element region toward the termination region. The first insulating layer includes a first portion and a second portion, with the fourth semiconductor region disposed between the first portion and the second portion in the aforementioned direction. The first conductive layer comprises the first portion, the fourth semiconductor regions, and the second portion between the first semiconductor regions.

[0029] The first part includes a first region and a second region. The first region is disposed between the second region and the fourth semiconductor region in the aforementioned direction, and the depth of the first region is greater than the depth of the second region. The second part includes a third region and a fourth region. The third region is disposed between the fourth region and the fourth semiconductor region in the aforementioned direction, and the depth of the third region is greater than the depth of the fourth region.

[0030] The semiconductor device in this example embodiment is an IGBT100. IGBT100 includes a trench-gate type IGBT having a gate electrode in a trench formed in a semiconductor layer. Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

[0031] In this specification, the term "trench" refers to a recess disposed in a semiconductor layer. A "trench" may be part of a semiconductor layer. A "trench" may be filled with, for example, a conductor or an insulator.

[0032] Figure 1 This is a schematic top view of a semiconductor device according to an embodiment.

[0033] like Figure 1 As shown, the IGBT 100 includes a component region 101 and a termination region 102. The termination region 102 surrounds the component region 101.

[0034] Component region 101 operates as an IGBT. When IGBT 100 is in the off state, termination region 102 reduces the intensity of the electric field applied to the pn junction of the termination portion of component region 101. Termination region 102 is used to increase the breakdown voltage of IGBT 100.

[0035] Figure 2 This is a schematic cross-sectional view of a portion of the semiconductor device in the embodiment. Figure 2 This is a schematic cross-sectional view of component region 101. Figure 2 It is along Figure 1 The cross-sectional view taken from line AA'.

[0036] like Figure 1 and Figure 2 As shown, the component region 101 includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a gate electrode 16, a gate insulating film 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring layer 24.

[0037] like Figure 2 As shown, gate trench 41 (trench), p + Type collector region 51 (fifth semiconductor region), n - p-type drift region 52 (first semiconductor region), p-type base region 53 (second semiconductor region) and n-type base region 54 + The emitter region 54 (third semiconductor region) is disposed in the semiconductor layer 10 of the element region 101.

[0038] Layer 10 has a first surface F1 and a second surface F2 opposite to the first surface F1. The "surface" of the first surface F1 and the second surface F2 is, for example, the interface between the semiconductor layer and the insulating layer or the interface between the semiconductor layer and the conductive layer.

[0039] The semiconductor layer 10 is, for example, monocrystalline silicon (single crystal). The film thickness of the semiconductor layer 10 is, for example, 40 μm to 700 μm.

[0040] In this specification, a direction parallel to the first surface F1 is referred to as the first direction. A direction parallel to the first surface F1 but perpendicular to the first direction is referred to as the second direction. In this specification, the term "depth" is defined as the length relative to the first surface F1 in the direction toward the second surface F2.

[0041] The emitter electrode 12 is disposed on the side of the first surface F1 of the semiconductor layer 10. At least a portion of the emitter layer 12 is in contact with the first surface F1.

[0042] The emitter electrode 12 is, for example, a metal. The emitter electrode 12 includes, for example, aluminum.

[0043] Emitter electrode 12 is in contact with emitter region 54. Emitter electrode 12 is electrically connected to emitter region 54. Emitter electrode 12 is electrically connected to base region 53.

[0044] The collector 14 is disposed on the side of the second surface F2 of the semiconductor layer 10. At least a portion of the collector 14 is in contact with the second surface F2.

[0045] Collector 14 is, for example, a metal.

[0046] Collector 14 is in contact with collector region 51. Collector 14 is electrically connected to collector region 51.

[0047] Collector region 51 is a p+ type semiconductor region. Collector region 51 is in contact with the second surface F2. Collector region 51 is electrically connected to collector 14. Collector region 51 is in contact with collector 14. When the IGBT is in the on state, collector region 51 serves as a hole source.

[0048] Drift region 52 is n - Type semiconductor region. Drift region 52 is disposed between collector region 51 and first surface F1.

[0049] When the IGBT is in the on state, the drift region 52 serves as a path for the conduction current. The drift region 52 has the function of being depleted when the IGBT is in the off state and maintaining the IGBT's breakdown voltage.

[0050] The base region 53 is a p-type semiconductor region. The base region 53 is disposed between the drift region 52 and the first surface F1. The base region 53 sandwiches the drift region 52 and the collector region 51 in between.

[0051] In the base region 53, facing the gate electrode 16 to which the gate voltage Vg is applied, an n-type inversion layer is formed when the IGBT is in the on state. The base region 53 serves as the channel region of the transistor.

[0052] Emitter region 54 is n + A semiconductor region. The emitter region 54 is disposed between the base region 53 and the first surface F1. The emitter region 54 is in contact with the gate insulating film 18.

[0053] The concentration of n-type impurities in emitter region 54 is higher than that in drift region 52.

[0054] Emitter region 54 is in contact with emitter electrode 12. Emitter region 54 is electrically connected to emitter electrode 12. When the transistor is in the ON state, emitter region 54 acts as an electron source.

[0055] Gate trench 41 extends from the first surface F1 into the semiconductor layer 10. Gate trench 41 is provided repeatedly along a first direction. Each gate trench 41 extends in a second direction parallel to the first surface F1 but perpendicular to the first direction.

[0056] The gate trench 41 contacts the drift region 52, the base region 53, and the emitter region 54. The gate trench 41 penetrates the base region 53 and reaches the drift region 52.

[0057] The depth of the gate trench 41 is, for example, 3 μm to 7 μm.

[0058] The gate electrode 16 is disposed in the gate trench 41. The gate electrode 16 is electrically connected to the gate electrode pad 22 via the gate wiring layer 24.

[0059] Gate electrode 16 is a conductor. Gate electrode 16 is, for example, a semiconductor or a metal. Gate electrode 16 is, for example, amorphous silicon containing n-type or p-type impurities, or polycrystalline silicon containing n-type or p-type impurities.

[0060] A gate insulating film 18 is disposed between the gate electrode 16 and the semiconductor layer 10. The gate insulating film 18 is disposed between the gate electrode 16 and the base region 53.

[0061] The gate insulating film 18 is an insulator. The gate insulating film 18 is, for example, silicon oxide.

[0062] An interlayer insulating layer 20 is disposed between the gate electrode 16 and the emitter electrode 12. The interlayer insulating layer 20 electrically isolates the gate electrode 16 and the emitter electrode 12 from each other.

[0063] Interlayer insulating layer 20 is an insulator. Interlayer insulating layer 20 is, for example, silicon oxide.

[0064] Gate electrode pads 22 and gate wiring layer 24 are disposed on interlayer insulating layer 20. For example... Figure 1 As shown, the gate wiring layer 24 is connected to the gate electrode pad 22.

[0065] The gate electrode pad 22 and the gate wiring layer 24 are, for example, metal. The gate electrode pad 22 and the gate wiring layer 24 include, for example, aluminum.

[0066] The gate electrode pad 22 and the gate wiring layer 24 are formed of, for example, the same material as the emitter electrode 12. The gate electrode pad 22 and the gate wiring layer 24 are formed, for example, in the same process steps as the emitter electrode 12.

[0067] Figure 3 and Figure 4 This is a schematic cross-sectional view of a portion of the semiconductor device in the embodiment. Figure 3 This is a schematic cross-sectional view of the termination region 102. Figure 3 It is along Figure 1 The cross-sectional view of line BB'. Figure 4 This is a schematic cross-sectional view of the termination region 102. Figure 4 It is along Figure 1 The cross-sectional view taken from line CC'.

[0068] like Figure 1 , Figure 3 and Figure 4 As shown, the termination region 102 includes a semiconductor layer 10, a collector 14 (second electrode), an interlayer insulating layer 20, a field insulating layer 30 (first insulating layer), a field plate layer 32 (first conductive layer), a field plate insulating film 34 (first insulating film), and a protective ring metal layer 36 (second conductive layer).

[0069] In the semiconductor layer 10 of the terminal region 102 (termination region), field trenches 42 and p are provided. + Type collector region 51 (fifth semiconductor region), n - Type drift region 52 (first semiconductor region) and p + Type protection ring region 55 (fourth semiconductor region).

[0070] Protective ring area 55 is p + Type semiconductor region. Guard ring region 55 is disposed between drift region 52 and first surface F1.

[0071] Figure 5 This is a schematic top view of the semiconductor device in the embodiment. Figure 5 This is a view showing the layout pattern of the protective ring area 55.

[0072] like Figure 5 As shown, the guard ring region 55 surrounds the component region 101. The guard ring region 55 has an annular shape.

[0073] The protective ring region 55 is repeatedly arranged in the direction from the component region 101 toward the terminal region 102. Figure 3 In the example, the first direction is the direction from the component region 101 toward the terminal region 102. Figure 4 In the example, the second direction is the direction from the component region 101 toward the terminal region 102. The direction from the component region 101 toward the termination region 102 corresponds to the direction from the termination region 102 toward the component region 101.

[0074] although Figure 1 , Figure 3 , Figure 4 and Figure 5 The example shown is a case where there are three protection ring regions 55, but the number of protection ring regions 55 can be two or four or more.

[0075] Multiple guard ring regions 55 have the function of reducing the intensity of the electric field applied to the pn junction at the end of the element region 101 and improving the breakdown voltage of the IGBT 100.

[0076] For example, the p-type impurity concentration in each guard ring region 55 is higher than the p-type impurity concentration in the base region 53.

[0077] The depth of the guard ring region 55 is greater than the depth of the field trench 42. The depth of the guard ring region 55 is, for example, greater than the depth of the gate trench 41. The depth of the guard ring region 55 is, for example, greater than the depth of the base region 53.

[0078] Each protection ring region 55 is electrically floating. In this case, electrically floating means that it is not electrically connected to any voltage source or ground.

[0079] Field trenches 42 are provided on the side of the first surface F1 of the semiconductor layer 10. Field trenches 42 are repeatedly provided in the direction from the element region 101 toward the terminal region 102.

[0080] The depth of the field trench 42 is, for example, 0.5 μm to 3 μm.

[0081] The field insulation layer 30 is disposed in the field trench 42. The field insulation layer 30 fills the field trench 42.

[0082] The field insulating layer 30 is disposed between two adjacent guard ring regions 55 in the direction from the component region 101 toward the terminal region 102. The guard ring regions 55 are disposed between the field insulating layers 30 in the direction from the component region 101 toward the terminal region 102.

[0083] For example, the field insulation layer 30 has the function of electrically separating the field plate layer 32 and the drift region 52.

[0084] The field insulating layer 30 is an insulator. The field insulating layer 30 is, for example, an oxide. The field insulating layer 30 is, for example, silicon oxide.

[0085] The field plate layer 32 is disposed on the field insulation layer 30 and the guard ring region 55. The field insulation layer 30 and the guard ring region 55 are disposed between the field plate layer 32 and the drift region 52.

[0086] Figure 6 This is a schematic top view of the semiconductor device in the embodiment. Figure 6 This is a view showing the layout pattern of the field plate layer 32.

[0087] like Figure 6 As shown, the field plate layer 32 surrounds the element region 101. The field plate layer 32 has an annular shape.

[0088] Field plate layers 32 are repeatedly provided in the direction from component region 101 toward terminal region 102. Adjacent field plate layers 32 are separated from each other in the direction from component region 101 toward terminal region 102.

[0089] although Figure 1 , Figure 3 , Figure 4 and Figure 6 The example shown is of three field plates 32, but the number of field plates 32 can be two or four or more.

[0090] Multiple field plates 32 have the function of reducing the intensity of the electric field applied to the pn junction at the end of the element region 101 and improving the breakdown voltage of the IGBT 100.

[0091] The field plate layer 32 is, for example, a semiconductor or a metal. The gate electrode 16 is, for example, amorphous silicon containing n-type or p-type impurities, or polycrystalline silicon containing n-type or p-type impurities.

[0092] The field plate layer 32 is formed of, for example, the same material as the gate electrode 16. For example, the field plate layer 32 is formed in the same process steps as the gate electrode 16.

[0093] Field plate layer 32 is electrically connected to guard ring region 55. Field plate layer 32 is electrically floating.

[0094] A field plate insulating film 34 is disposed between the field plate layer 32 and the protective ring region 55. The field plate insulating film 34 is an insulator. For example, the field plate insulating film 34 is silicon oxide.

[0095] The field plate insulating film 34 is formed of, for example, the same material as the gate insulating film 18. The field plate insulating film 34 is formed, for example, in the same process steps as the gate insulating film 18.

[0096] Alternatively, a structure can be adopted in which the field plate insulating film 34 is omitted and the field plate layer 32 contacts the protective ring region 55.

[0097] A protective ring metal layer 36 is disposed on the protective ring region 55 and the field plate layer 32. The field plate layer 32 is disposed between the protective ring metal layer 36 and the protective ring region 55.

[0098] like Figure 1 As shown, a protective ring metal layer 36 surrounds the component region 101. The protective ring metal layer 36 has an annular shape.

[0099] The protective ring metal layer 36 is repeatedly disposed in the direction from the component region 101 toward the terminal region 102. The protective ring metal layers 36 adjacent to each other are separated from each other in the direction from the component region 101 toward the terminal region 102.

[0100] although Figure 1 , Figure 3 and Figure 4 The example shown is a case where there are three protective ring metal layers 36, but the number of protective ring metal layers 36 can be two or four or more.

[0101] Multiple protective ring metal layers 36 shield external electric fields, stabilize the electric field strength of the pn junction at the end of the component region 101, and suppress the breakdown voltage fluctuation of the IGBT 100.

[0102] Each guard ring metal layer 36 is a conductor. The guard ring metal layer 36 is, for example, a metal. The guard ring metal layer 36 includes, for example, aluminum.

[0103] The protective ring metal layer 36 is formed of, for example, the same material as the emitter electrode 12. For example, the protective ring metal layer 36 is formed in the same process steps as the emitter electrode 12.

[0104] The guard ring metal layer 36 is electrically connected to the field plate layer 32 and the guard ring region 55. The guard ring metal layer 36 is electrically floating.

[0105] The interlayer insulation layer 20 is disposed between the field plate layer 32 and the protective ring metal layer 36.

[0106] Figure 7 This is an enlarged schematic cross-sectional view of a portion of the semiconductor device in the embodiment. Figure 7 This is an enlarged schematic cross-sectional view of the termination region 102. Figure 7 It is by Figure 3 An enlarged schematic cross-sectional view of the portion surrounded by the dashed line.

[0107] The field insulation layer 30 includes a first portion 30a and a second portion 30b. A protective ring region 55 is disposed between the first portion 30a and the second portion 30b in the direction from the element region 101 toward the termination region 102. Figure 7 In this context, the direction from the component region 101 toward the termination region 102 is the first direction.

[0108] Part 30a includes a first deep region 30ax (first region) and a first shallow region 30ay (second region). Part 30b includes a second deep region 30bx (third region) and a second shallow region 30by (fourth region).

[0109] In the direction from component region 101 toward terminal region 102, a first deep region 30ax is disposed between a first shallow region 30ay and a guard ring region 55. In the direction from component region 101 toward terminal region 102, a second deep region 30bx is disposed between a second shallow region 30by and a guard ring region 55.

[0110] The depth of the first deep region is 30ax. Figure 7 d1) is deeper than the first shallow region 30ay. Figure 7 The first deep region d1 (d2) is 30ax deep. The depth of the first deep region d1 (d2) is, for example, 1.1 to 1.5 times the depth of the first shallow region d2 (d2) (d2).

[0111] The depth of the field trench 42 in the portion that contacts the first deep region 30ax is greater than the depth of the field trench 42 in the portion that contacts the first shallow region 30ay.

[0112] The second deepest region has a depth of 30bx. Figure 7 The depth of d3 in the second shallow region is 30by. Figure 7 The second deep region d3 (d4) is 30bx deep. The depth of the second deep region d3 (d4) is, for example, 1.1 to 1.5 times the depth of the second shallow region d4 (d4) (d4).

[0113] The depth of the field trench 42 in the portion that contacts the second deep region 30bx is greater than the depth of the field trench 42 in the portion that contacts the second shallow region 30by.

[0114] The guard ring region 55 contacts the first portion 30a and the second portion 30b in the direction from the component region 101 toward the termination region 102. The guard ring region 55 contacts the first deep region 30ax and the second deep region 30bx in the direction from the component region 101 toward the terminal region 102.

[0115] The thickness of the field insulating layer 30 in the first shallow region 30ay in the direction perpendicular to the first surface F1 ( Figure 7 The depth d1 in the first shallow region 30ay is, for example, equal to or less than the depth d2 of the first shallow region 30ay. The thickness of the field insulating layer 30 in the direction perpendicular to the first surface F1 in the second shallow region 30by ( Figure 7 For example, t2 in the second shallow region is equal to or less than the depth d4 of the second shallow region of 30by.

[0116] In a direction perpendicular to the first surface F1, the first portion 30a, the protective ring region 55, and the second portion 30b are disposed between the field plate layer 32 and the drift region 52.

[0117] In a direction perpendicular to the first surface F1, a first portion 30a and a second portion 30b are disposed between the field plate layer 32 and the protective ring region 55. In a direction perpendicular to the first surface F1, a first deep region 30ax and a second deep region 30bx are disposed between the field plate layer 32 and the protective ring region 55.

[0118] The width of each protective ring region 55 in the direction from the component region 101 toward the terminal region 102 ( Figure 7 w1 in the figure is, for example, greater than the distance between the first portion 30a and the second portion 30b of the field insulating layer 30 in the direction from the element region 101 toward the terminal region 102. Figure 7 (L1 in the middle). The width w1 of the protective ring region 55 is, for example, 1.1 to 2 times the distance L1 between the plurality of first parts 30a and the plurality of second parts 30b.

[0119] The protective ring region 55 extends around the bottom of the first part 30a and the bottom of the second part 30b.

[0120] For example, the length of the field plate layer 32 in the direction from the component region 101 toward the terminal region 102 ( Figure 7 w2) is greater than the length of the guard ring region 55 in the direction from the component region 101 toward the terminal region 102. Figure 7 (w1 in the text). The width w2 of the field plate layer 32 is, for example, 1.1 to 20 times the width w1 of the protective ring region 55.

[0121] The field plate layer 32 includes a first wedge-shaped portion 32a (a portion of the first conductive layer) and a second wedge-shaped portion 32b (another portion of the first conductive layer). The first wedge-shaped portion 32a and the second wedge-shaped portion 32b are portions of the field plate layer 32 that protrude toward the semiconductor device 10. The first wedge-shaped portion 32a contacts, for example, a first deep region 30ax of the field insulating layer 30. The second wedge-shaped portion 32b contacts, for example, a second deep region 30bx of the field insulating layer 30.

[0122] The protective ring region 55 is disposed between the first wedge-shaped portion side 32a and the second wedge-shaped portion side 32b in the direction from the component region 101 toward the terminal region 102.

[0123] The width of the protective ring metal layer 36 in the direction from the component region 101 toward the terminal region 102 ( Figure 7 (w3) For example, greater than the width of the guard ring region 55 in the direction from the component region 101 toward the terminal region 102. Figure 7 (w1 in the text). The width w3 of the protective ring metal layer 36 is, for example, 1.1 to 20 times the width w1 of the protective ring region 55.

[0124] Figure 8 This is an enlarged schematic cross-sectional view of a portion of the semiconductor device in the embodiment. Figure 8 This is an enlarged schematic cross-sectional view of the termination region 102. Figure 8 From Figure 7 A cross-sectional view taken where the depicted plane extends further into the page. In other words, Figure 8 Is in the second direction with Figure 7 A cross-sectional view of the spaced-out portions of the page plan.

[0125] like Figure 8 As shown, the guard ring metal layer 36 contacts the guard ring region 55. The guard ring metal layer 36 penetrates the interlayer insulation layer 20, the field plate layer 32, and the field plate insulation film 34. The guard ring metal layer 36 contacts the guard ring region 55, thereby being electrically connected to the guard ring region 55. The field plate layer 32 is electrically connected to the guard ring region 55 at another location (not shown), for example, via the guard ring metal layer 36. The field plate layer 32 is divided into sub-sections spaced apart from each other in a first direction.

[0126] Next, an example of a method for manufacturing the semiconductor device of the embodiment will be described.

[0127] A method for manufacturing a semiconductor device according to an embodiment includes: implanting impurity ions of a second conductivity type into a semiconductor layer of a first conductivity type; forming a ring-shaped semiconductor region of a second conductivity type on the surface of the semiconductor layer; forming a first trench in the semiconductor region on the surface of the semiconductor layer, wherein the depth on the side of the semiconductor region is deeper than that of other portions; and forming a second trench outside the semiconductor region on the surface of the semiconductor layer, wherein the depth on the side of the semiconductor region is deeper than that of other portions.

[0128] The first and second trenches are filled with an insulating film, and a heat treatment is performed to activate the impurities in the semiconductor region, and a conductive film is formed on the insulating film and the semiconductor region. The first and second trenches are in contact with the semiconductor region, and the distance between the first and second trenches in the direction from the inside to the outside of the semiconductor region is less than the width of the semiconductor region in the same direction.

[0129] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. Figures 9 to 18 It corresponds to the position Figure 7 The image.

[0130] First, in n - A first mask material 61 is formed on the surface of a silicon layer 60 (semiconductor layer). The first mask material 61 is, for example, a photoresist formed by photolithography. The first mask material 61 has an annular opening on the surface of the silicon layer 60. A portion of the silicon layer 60 eventually becomes the drift region 52.

[0131] Next, using the first mask material 61 as a mask, boron (B) ions are implanted into the silicon layer 60 to form p + Type 62 silicon region (semiconductor region) Figure 9 Silicon region 62 has a ring shape on the surface of silicon layer 60. Silicon region 62 ultimately becomes protective ring region 55.

[0132] Next, after removing the first mask material 61, a second mask material 63 is formed on the surface of the silicon layer 60. Figure 10The second mask material 63 is, for example, a photoresist formed using a photolithography method. The second mask material 63 has openings both inside and outside the silicon region 62. That is, the second mask material 63... Figure 10 The silicon region 62 in the middle has openings on the left and right sides.

[0133] Next, using the second mask material 63 as a mask, an inner trench 64a (first trench) and an outer trench 64b (second trench) are formed in the silicon layer 60. Figure 11 Inner trench 64a is formed inside silicon region 62. Outer trench 64b is formed outside silicon region 62. Inner trench 64a and outer trench 64b eventually become field trench 42.

[0134] The inner trench 64a has a deeper portion on the silicon region 62 side than the other portion. Figure 11 In addition, the outer groove 64b has a deeper portion than the other portions (E1). Figure 11 (Side E2 on side 62 of silicon region 62).

[0135] The inner trench 64a and the outer trench 64b are formed by, for example, an isotropic dry etching method. The inner trench 64a and the outer trench 64b are formed by, for example, a chemical dry etching method (CDE method).

[0136] In silicon region 62, there are crystal defects generated during boron (B) ion implantation. For example, when etching is performed by an isotropic dry etching method, the etching rate of the portion with crystal defects is higher than that of another portion.

[0137] In this case, such as Figure 11 As shown, a portion of the inner trench 64a on the silicon region 62 side ( Figure 11 The depth of E1 in the inner trench 64a is deeper than the depth of the other part of the inner trench 64a. The depth of the inner trench 64a formed in the silicon region 62 is deeper than the depth of the inner trench 64a formed in another silicon layer 60.

[0138] In addition, such as Figure 11 As shown, a portion of the outer trench 64b on the silicon region 62 side ( Figure 11 The depth of E2 in the outer trench 64b is greater than the depth of another portion of the outer trench 64b. The depth of the outer trench 64b formed in the silicon region 62 is greater than the depth of the outer trench 64b formed in another silicon layer 60.

[0139] Inner trench 64a and outer trench 64b are in contact with silicon region 62. The length of the inner trench 64a and outer trench 64b in the direction from the inside to the outside of silicon region 62 is (…). Figure 11 The L in the figure is smaller than the width of silicon region 62 in the direction from the inside to the outside of silicon region 62. Figure 11(W in the middle).

[0140] Next, remove the second mask material 63 ( Figure 12 )).

[0141] Next, the inner trench 64a and the outer trench 64b are filled with a first silicon oxide film 65 (insulating film). Figure 13 The first silicon oxide film 65 is formed using, for example, a plasma-enhanced chemical vapor deposition (PECVD) method. A portion of the first silicon oxide film 65 eventually becomes the field insulating layer 30.

[0142] Next, a heat treatment is performed to activate the boron (B) in the silicon region 62. The heat treatment is carried out, for example, at a temperature of 1000°C to 1100°C in an inert gas atmosphere. By activating the boron (B) in the silicon region 62, crystal defects in the silicon region 62 are restored (repaired).

[0143] Next, a third mask material 66 is formed on the first silicon oxide film 65. Figure 14 The third mask material 66 is, for example, a photoresist formed by photolithography. The third mask material 66 has an annular opening on the surface of the first silicon oxide film 65.

[0144] Next, a third mask material 66 is used as a mask to remove part of the first silicon oxide film 65 to expose the silicon region 62. Figure 15 The first silicon oxide film 65 is removed, for example, by wet etching. When the first silicon oxide film 65 is removed, a portion of the side surface of the silicon region 62 is exposed.

[0145] Subsequently, the third mask material 66 is removed, and the device region 101 is formed in the region of the silicon layer 60. That is, it ultimately becomes the p-type base region 53, n-type base region 54. + The structure of the emitter region 54, gate trench 41, gate insulating film 18, and gate electrode 16 is formed in Figure 15 The region of silicon layer 60 not specifically depicted in the text.

[0146] Next, a second silicon oxide film 67 is formed on the surface of silicon region 62. The second silicon oxide film 67 is formed, for example, by a thermal oxidation method. The second silicon oxide film 67 can be formed simultaneously with the gate insulating film 18 in device region 101.

[0147] Next, a polycrystalline silicon film 68 (conductive film) containing phosphorus (P) as an impurity is formed on the second silicon oxide film 67. Figure 16 The polysilicon film 68 is formed by depositing the film using, for example, a chemical vapor deposition (CVD) method and patterning it using a dry etching method. The polysilicon film 68 ultimately becomes the field plate layer 32. The polysilicon film 68 can be formed simultaneously with the gate electrode 16 in the device region 101.

[0148] Next, a third silicon oxide film 69 with an opening 69a is formed on the polycrystalline silicon film 68. Figure 17 For example, a third silicon oxide film 69 is formed by depositing a film using a CVD method and opening an opening 69a using a dry etching method. A portion of the third silicon oxide film 69 eventually becomes the interlayer insulating layer 20.

[0149] Next, an aluminum film 70 is formed on the third silicon oxide film 69. Figure 18 The aluminum film 70 is formed, for example, by deposition using a sputtering method and patterning using a dry etching method. A portion of the aluminum film 70 ultimately becomes the protective ring metal layer 36. For example, another portion of the aluminum film 70 becomes the emitter electrode 12, the gate electrode pad 22, and the gate wiring layer 24.

[0150] Subsequently, a silicon region that ultimately becomes collector region 51 and a metal film that ultimately becomes collector 14 are formed on the back side of silicon layer 60 using known process steps.

[0151] IGBT100 can be manufactured using the methods described above.

[0152] Next, the function and effects of the semiconductor device according to the embodiments and the method for manufacturing the semiconductor device will be described.

[0153] Figure 19 This is an enlarged schematic cross-sectional view of a portion of a comparative example semiconductor device. Figure 19 It generally corresponds to Figure 7 The image.

[0154] The comparative example semiconductor device differs from the embodiment semiconductor device in that the depth of the field insulating layer 30 is constant. The comparative example semiconductor device differs from the embodiment semiconductor device in that the first portion and the second portion are not disposed between the first conductive layer and the fourth semiconductor region in a direction perpendicular to the first surface. The comparative example semiconductor device differs from the embodiment semiconductor device in that the width of the fourth semiconductor region in the direction from the element region toward the terminal region is equal to the distance between the first portion and the second portion in that direction.

[0155] In the comparative example IGBT, similar to the IGBT 100 of the embodiment, the field insulating layer 30 includes a first portion 30a and a second portion 30b. In the comparative example IGBT, the depth of the first portion 30a is ( Figure 19 The depth of d5 in the middle and the second part 30b ( Figure 19 d6) is constant. In the comparative example IGBT, the depth of the field trench 42 in contact with the first part side 30a and the depth of the field trench 42 in contact with the second part side 30b are constant.

[0156] In the comparative example IGBT, the thickness of the field insulation layer 30 in the portion where the first part 30a contacts the guard ring region 55 is ( Figure 19 The thickness of ty1 in the first part 30a is less than the thickness of the field insulating layer 30 in the other part of the first part 30a. Figure 19 (t1 in the middle). The thickness of the field insulation layer 30 in the part of the second part 30b that contacts the guard ring region 55 (t1 in the middle). Figure 19 The thickness of ty2 in the second part 30b is less than the thickness of the field insulating layer 30 in the other part of the second part 30b. Figure 19 (t2 in the middle).

[0157] In the comparative example IGBT, no first portion 30a and a second portion 30b are provided between the field plate layer 32 and the guard ring region 55 in a direction perpendicular to the first surface F1. In the comparative example IGBT, the width of the guard ring region 55 in the direction from the element region 101 toward the terminal region 102 is ( Figure 19 w4 in the figure is equal to the distance between the plurality of first portions 30a and the plurality of second portions 30b of the field insulating layer 30 in the direction from the element region 101 toward the terminal region 102. Figure 19 L2 in the middle.

[0158] In the comparative example IGBT, unlike IGBT100, the guard ring region 55 does not extend to the bottom of the first portion 30a and the bottom of the second portion 30b.

[0159] In the comparative example IGBT, the thickness of the field insulation layer 30 in the portion contacting the guard ring region 55 is thinner, thus increasing the electric field strength near the end of the field insulation layer 30. Consequently, the breakdown voltage of the comparative example IGBT is reduced.

[0160] In the IGBT100, the first part 30a includes a first deep region 30ax (first region) and a first shallow region 30ay (second region). The second part 30b includes a second deep region 30bx (third region) and a second shallow region 30by (fourth region).

[0161] In IGBT100, the first deep region has a depth of 30ax ( Figure 7 d1) is deeper than the first shallow region 30ay. Figure 7 The depth of d2 in the middle. Therefore, the thickness of the field insulation layer 30 at the portion where the first part 30a contacts the guard ring region 55 ( Figure 7 The thickness of tx1 in the comparative example is greater than the thickness of the field insulation layer 30 at the portion of the first part 30a of the IGBT that contacts the guard ring region 55. Figure 19 (ty1 in the middle).

[0162] Similarly, the second deep region has a depth of 30 bx ( Figure 7 The depth of d3 in the second shallow region is 30by. Figure 7 The thickness of the field insulation layer 30 in the portion of the second part 30b that contacts the guard ring region 55 is large (deep). Figure 7 The thickness of tx2 in the comparative example is greater than the thickness of the field insulation layer 30 in the portion of the second part 30b of the IGBT that contacts the guard ring region 55. Figure 19 (ty2 in the middle).

[0163] In the IGBT100, the field insulation layer 30 in the portion contacting the guard ring region 55 is thicker, thus reducing the electric field strength near the end of the field insulation layer 30. Therefore, the breakdown voltage of the IGBT100 can be increased.

[0164] From the viewpoint of improving the breakdown voltage of IGBT100, the depth d1 of the first deep region 30ax is preferably at least 1.1 times the depth d2 of the first shallow region 30ay. From the same viewpoint, the depth d3 of the second deep region 30bx is preferably at least 1.1 times the depth d4 of the second shallow region 30by.

[0165] Furthermore, in the IGBT 100, the guard ring region 55 extends around the bottom portion of the first portion 30a and the bottom portion of the second portion 30b of the field insulating layer 30. The guard ring region 55 extends around the bottom of the first portion 30a and the bottom of the second portion 30b, thereby further reducing the electric field strength near the ends of the field insulating layer 30. Therefore, the breakdown voltage of the IGBT 100 can be further improved.

[0166] From the viewpoint of increasing the protection ring region 55 to surround the bottom of the field insulation layer 30 to improve the breakdown voltage of the IGBT 100, the width w1 of the protection ring region 55 is preferably at least 1.1 times, more preferably at least 1.2 times, and even more preferably at least 1.5 times the distance L1 between the first portion 30a and the second portion 30b.

[0167] In the method of manufacturing IGBT 100 according to the embodiment, the end portions of each of the inner trench 64a and the outer trench 64b (which ultimately become field trench 42) are formed as deep on the side surface of the silicon region 62. Therefore, IGBT 100 can be manufactured.

[0168] Specifically, before performing the heat treatment for activating boron (B) in the silicon region 62, the inner trench 64a and outer trench 64b are formed using the CDE method. That is, the silicon layer 60 is etched using the CDE method before crystal defects in the silicon region 62 generated during ion implantation to recover boron (B). Since the etching rate of the portion with crystal defects is higher than that of the other portion, the ends of each of the inner trench 64a and outer trench 64b on the side of the silicon region 62 can be formed deeper.

[0169] As described above, according to the embodiments, IGBTs that can improve breakdown voltage can be provided.

[0170] (First Variation)

[0171] The semiconductor device according to the first modified version differs from the semiconductor device according to the previously described embodiment in that the first portion and the second portion are not disposed between the first conductive layer and the fourth semiconductor region in a direction perpendicular to the first surface. Furthermore, the semiconductor device according to the first modified version differs from the semiconductor device according to the previously described embodiment in that the width of the fourth semiconductor region in the direction from the element region toward the terminal region is equal to the distance between the first portion and the second portion in that direction.

[0172] Figure 20 This is an enlarged schematic cross-sectional view of a portion of the first deformed semiconductor device. Typically, Figure 20 It corresponds to Figure 7 The image.

[0173] In this first modified IGBT, no first portion 30a and a second portion 30b are provided between the field plate layer 32 and the guard ring region 55 in a direction perpendicular to the first surface F1. In the first modified IGBT, the width of the guard ring region 55 in the direction from the element region 101 toward the terminal region 102 is ( Figure 20 w5) is equal to the distance between the plurality of first portions 30a and the plurality of second portions 30b of the field insulating layer 30 in the direction from the element region 101 toward the terminal region 102. Figure 20 L3 in the middle.

[0174] Unlike the side IGBT 100 of the example embodiment already described, in this first variation, the guard ring region 55 does not extend to the bottom of the first portion 30a and the bottom of the second portion 30b.

[0175] In this first modified IGBT, similar to the IGBT 100 portion of the already described embodiment, the thickness of the field insulation layer 30 in the portion contacting the guard ring region 55 is increased, and thus the electric field strength near the end of the field insulation layer 30 is reduced. Therefore, the breakdown voltage of the first modified IGBT can be increased.

[0176] In the first deformed IGBT, inner trench 64a and outer trench 64b are formed using, for example, a reactive ion etching (RIE) method. The first deformed IGBT can be manufactured by selecting a condition in which the ends of the inner trench 64a and outer trench 64b on the silicon region 62 side become deeper as the RIE condition.

[0177] (Second variation)

[0178] The semiconductor device according to the second modification differs from the semiconductor device according to the already described embodiment in that it does not provide a portion of the first conductive layer sandwiching the fourth semiconductor region and another portion of the first conductive layer.

[0179] Figure 21 This is an enlarged schematic cross-sectional view of a portion of the second-modified semiconductor device. Typically, Figure 21 It corresponds to Figure 7 The image.

[0180] In this second-deformed IGBT, the field plate layer 32 does not include the first wedge portion 32a and the second wedge portion 32b.

[0181] In the second modified IGBT, similar to the IGBT 100 of the already described embodiment, the thickness of the field insulation layer 30 in the portion contacting the guard ring region 55 is increased, and the guard ring region 55 surrounds the bottom of the first portion 30a and the bottom of the second portion 30b, thereby reducing the intensity of the electric field near the end of the field insulation layer 30. Therefore, the breakdown voltage of the second modified IGBT can be increased.

[0182] In this second modified IGBT, compared to the IGBT 100 of the embodiment, the thickness of the field insulation layer 30 in the portion contacting the guard ring region 55 is ( Figure 21 The values ​​of tx1 and tx2 in the original text are further increased. Therefore, the breakdown voltage of the second modified IGBT can be further improved compared to the IGBT100 of the already described embodiment.

[0183] When a portion of the first silicon oxide film 65 is removed to expose the silicon region 62, the second deformed IGBT can be formed by using a chemical mechanical polishing (CMP) method instead of a wet etching method.

[0184] According to this second variation, a semiconductor device with an improved breakdown voltage and a method for manufacturing the semiconductor device can be provided.

[0185] In this embodiment, the semiconductor layer is monocrystalline silicon, but the semiconductor layer is not limited to monocrystalline silicon. For example, other monocrystalline semiconductors such as monocrystalline silicon carbide can be used.

[0186] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type can also be p-type and the second conductivity type can also be n-type.

[0187] In this embodiment, the semiconductor device is an IGBT, but it is not limited to IGBTs and can be, for example, a reverse-biased IGBT (RC-IGBT), where the IGBT and the freewheeling diode are formed on the same semiconductor chip. In other examples, the semiconductor device can be a MOSFET.

[0188] In this embodiment, the semiconductor device is a trench gate IGBT, but in other examples, the semiconductor device may be a planar gate IGBT.

[0189] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the embodiments described herein without departing from the spirit of the invention. For example, a component of one embodiment may be replaced or modified with a component of another embodiment. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the invention as described in the claims and their equivalents.

Claims

1. A semiconductor device, comprising: A semiconductor layer having a first surface and a second surface opposite to the first surface; The element region of the semiconductor layer; as well as The termination region of the semiconductor layer, the termination region surrounding the element region, wherein... The component region includes: First semiconductor region of first conductivity type; A second semiconductor region of a second conductivity type located between the first semiconductor region and the first surface; A third semiconductor region of a first conductivity type located between the second semiconductor region and the first surface; Gate electrode facing the second semiconductor region; A gate insulating film located between the second semiconductor region and the gate electrode; A first electrode on the first surface of the semiconductor layer, the first electrode being electrically connected to the third semiconductor region; and The second electrode on the second surface of the semiconductor layer, The termination region includes: The first semiconductor region; A plurality of fourth semiconductor regions of the second conductivity type between the first semiconductor region and the first surface, the fourth semiconductor regions being spaced apart from each other in a first direction, the first direction being a direction outward from the element region toward the termination region; The first insulating layer includes a plurality of first portions and a plurality of second portions spaced apart from each other in the first direction, and each fourth semiconductor region is located between the first portions and second portions that are adjacent to each other in the first direction; A first conductive layer having multiple portions, each portion of the first conductive layer comprising a first portion, a fourth semiconductor region, and a second portion, wherein the first portion, the fourth semiconductor region, and the second portion are located between the portions of the first conductive layer and the first semiconductor region; and The second electrode, Each first portion of the first insulating layer includes a first region and a second region, the first region being adjacent to the fourth semiconductor region. The depth of the first region from the first surface is greater than the depth of the second region from the first surface. Each second portion of the first insulating layer includes a third region and a fourth region, the third region being adjacent to the fourth semiconductor region, and The third region is at a greater depth from the first surface than the fourth region is at a greater depth from the first surface.

2. The semiconductor device according to claim 1, wherein, The depth of the first region is 1.1 to 1.5 times the depth of the second region.

3. The semiconductor device according to claim 1, wherein, Each of the first and second portions of the first insulating layer has a portion between the fourth semiconductor region and a portion of the first conductive layer in a second direction perpendicular to the first surface.

4. The semiconductor device according to claim 1, wherein, The width of each fourth semiconductor region in the first direction is greater than the distance between the other adjacent first portions and second portions of the first insulating layer in the first direction.

5. The semiconductor device according to claim 1, wherein, Each portion of the first conductive layer has a plurality of sub-parts spaced apart from each other in the first direction.

6. The semiconductor device according to claim 1, wherein, The thickness of the first insulating layer in the second region in a second direction perpendicular to the first surface is less than or equal to the depth of the second region in the second direction.

7. The semiconductor device according to claim 1, wherein, Each portion of the first conductive layer is electrically connected to the fourth semiconductor region.

8. The semiconductor device according to claim 1, wherein, The first conductive layer and the plurality of fourth semiconductor regions are electrically floating.

9. The semiconductor device according to claim 1, wherein, The termination region also includes a second conductive layer. Each portion of the first conductive layer is located between the second conductive layer and the fourth semiconductor region.

10. The semiconductor device according to claim 9, wherein, The second conductive layer is electrically connected to the portion of the first conductive layer and the fourth semiconductor region.

11. The semiconductor device according to claim 1, wherein, Each fourth semiconductor region surrounds the element region in a plane parallel to the first surface.

12. The semiconductor device according to claim 1, wherein, The first conductive layer surrounds the element region in a plane parallel to the first surface.

13. The semiconductor device according to claim 9, wherein, The second conductive layer surrounds the element region in a plane parallel to the first surface.

14. The semiconductor device according to claim 1, wherein, The first conductive layer is polycrystalline silicon.

15. The semiconductor device according to claim 1, wherein, The termination region also includes: A first insulating film is located between the portion of the first conductive layer and the fourth semiconductor region.

16. The semiconductor device according to claim 1, wherein, The component region also includes: The fifth semiconductor region of the second conductivity type is located between the first semiconductor region and the second surface and is in contact with the second electrode.

17. The semiconductor device according to claim 1, wherein, The component region also includes: The trench extends from the first surface into the semiconductor layer, and The gate electrode is in the trench.

18. The semiconductor device according to claim 1, wherein, The semiconductor layer is silicon.

19. A method for manufacturing a semiconductor device, the method comprising: By implanting impurity ions of a second conductivity type into a semiconductor layer of a first conductivity type, a ring-shaped semiconductor region of the second conductivity type is formed on the surface of the semiconductor layer. A first trench is formed in the semiconductor region on the surface of the semiconductor layer. A second trench is formed outside the semiconductor region on the surface of the semiconductor layer. The first and second trenches are filled with insulating film. Perform heat treatment to activate the impurities in the semiconductor region. A conductive film is formed over the insulating film and the semiconductor region.

20. The method according to claim 19, wherein, The first trench and the second trench are in contact with the semiconductor region. The distance between the first trench and the second trench in a first direction outward from the semiconductor region is less than the width of the semiconductor region in the first direction.

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