A display backplane and method of manufacturing the same

Abstract

The application discloses a display backboard and a manufacturing method thereof, and comprises the following steps: providing an epitaxial bonding substrate, the epitaxial bonding substrate comprises a substrate and a film layer structure which are sequentially stacked, and the film layer structure comprises a bonding layer, an epitaxial layer and an ohmic contact layer which are sequentially stacked on the substrate; forming a metal layer on a surface of the ohmic contact layer, etching the metal layer to form a plurality of sub-metal layers; forming a transparent protective layer to cover the sub-metal layers and the ohmic contact layer; performing isolation groove etching on a surrounding area of the sub-metal layers to obtain a plurality of LED step structures, the LED step structure comprises a sub-epitaxial layer, a sub-ohmic contact layer, a sub-metal layer and a sub-transparent protective layer which are sequentially stacked; forming a passivation layer to cover an outer wall of the LED step structure and a groove bottom of the isolation groove, and opening a via hole in the passivation layer above each sub-transparent protective layer to expose the sub-transparent protective layer; and forming a common electrode layer to cover the passivation layer and the sub-transparent protective layer in the via hole. The method can effectively prevent the voltage abnormality caused by the etching of the inner side of the ohmic contact layer and the etching damage of the metal layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a display backplane and its manufacturing method. Background Technology

[0002] With the development of Micro LED, smaller chip sizes are gradually becoming a trend, attracting widespread attention in the augmented reality (AR) and virtual reality (VR) display industries. However, as chip size shrinks, the voltage of the light-emitting chip frequently increases dramatically. This is mainly due to the following reasons: During the etching process of the light-emitting chip Mesa, it needs to be repeatedly immersed in solutions such as resist remover and developer. The main purpose of these solutions is to remove the resist and develop the chip. These solutions are weakly alkaline and will cause a chemical reaction when in contact with the ohmic contact layer for a long time. The ohmic contact layer is prone to inward etching. If the ohmic contact layer is corroded, the light-emitting chip cannot form ohmic contacts, resulting in a sharp increase in chip voltage and causing abnormal chip lighting. Moreover, due to the material properties, when etching the passivation layer (PV) of the light-emitting chip, an over-etching amount is usually required to ensure that the PV holes can be etched open. The F-based gas used to etch the PV layer will react with the metal and damage the metal layer, which will further increase the chip voltage and cause abnormal chip lighting. Summary of the Invention

[0003] In view of the shortcomings of the above-mentioned related technologies, the purpose of this application is to provide a display backplane and its manufacturing method, which can effectively prevent the ohmic contact layer from being etched from the inside and the metal layer from being scratched, so as to prevent the chip from lighting abnormally due to voltage influence.

[0004] This application provides a method for manufacturing a display back panel, the steps of which include: An epitaxial bonding substrate is provided, the epitaxial bonding substrate comprising a substrate and a film layer structure stacked sequentially, the film layer structure comprising a bonding layer, an epitaxial layer and an ohmic contact layer stacked sequentially on the substrate; Multiple spaced sub-metal layers are formed on the ohmic contact layer; A transparent protective layer is formed to cover the sub-metal layer and the ohmic contact layer; Isolation trenches are etched in the region surrounding the sub-metal layer and toward the film structure to obtain multiple spaced LED step structures. Each LED step structure corresponds to a sub-metal layer. The LED step structure includes a sub-epitaxy layer, a sub-ohmic contact layer, the sub-metal layer, and a sub-transparent protective layer stacked sequentially. The sub-epitaxy layer, the sub-ohmic contact layer, and the sub-transparent protective layer are obtained by etching the epitaxial layer, the ohmic contact layer, and the transparent protective layer, respectively, through isolation trenches. A passivation layer is formed to cover the outer wall of the LED stepped structure and the bottom of the isolation groove. Through holes are made in the passivation layer above each of the sub-transparent protective layers to expose the sub-transparent protective layers. The outer wall of the LED stepped structure includes the side wall of the LED stepped structure and the sub-transparent protective layer located on the top surface of the LED stepped structure. A common electrode layer is formed to cover the passivation layer and the sub-transparent protective layer within the via, such that the sub-metal layer is connected to the common electrode layer through the sub-transparent protective layer.

[0005] Optionally, the thickness of the transparent protective layer ranges from 100 Å to 500 Å.

[0006] Optionally, the ohmic contact layer includes at least one of GaAs ohmic contact layer and GaP ohmic contact layer.

[0007] Optionally, the metal layer includes at least one of AuGeNi metal layer, Au metal layer, Ge metal layer, Pd metal layer, Ni metal layer and AuGe metal layer.

[0008] Optionally, the depth of the isolation trench etching is from the transparent protective layer to the bonding layer.

[0009] Optionally, when creating vias in the passivation layer on the top surface of each of the LED stepped structures, the following steps are also included: The passivation layer and the bonding layer at the bottom of the isolation trench are etched onto the substrate to divide the bonding layer into a plurality of block pixels, each block pixel including at least one of the LED step structures.

[0010] Optionally, a first pad for connecting a power supply is formed on the common electrode layer; When the block pixel includes multiple LED step structures, a second pad for connecting power is formed on the bonding layer in each block pixel, and the LED step structure is connected to the second pad through the bonding layer.

[0011] Optionally, the preparation of the epitaxial bonding substrate includes the following steps: An epitaxial wafer and a substrate are provided, wherein the epitaxial wafer comprises a substrate, an ohmic contact layer and an epitaxial layer stacked sequentially; A bonding metal layer is formed on the side of the epitaxial wafer away from the substrate and on the surface of the substrate, respectively, and the epitaxial wafer and the substrate are bonded through the bonding metal layer; wherein, the bonding metal layer forms a bonding layer after bonding; Remove the substrate to expose the ohmic contact layer.

[0012] Optionally, a buffer layer and an etch stop layer are further disposed between the substrate and the ohmic contact layer, which are sequentially stacked on the substrate; Removing the substrate to expose the ohmic contact layer includes performing the following steps: Remove the substrate, the buffer layer, and the etch stop layer to expose the ohmic contact layer.

[0013] Optionally, the epitaxial layer includes an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer stacked sequentially, and the ohmic contact layer is disposed on the side of the N-type semiconductor layer away from the quantum well layer or on the side of the P-type semiconductor layer away from the quantum well layer.

[0014] Optionally, the transparent protective layer includes at least one of an ITO protective layer, an IZO protective layer, and an IGZO protective layer.

[0015] This application also provides a display backplate manufactured using the aforementioned display backplate manufacturing method. It includes a substrate, a passivation layer, a common electrode layer, and multiple LED step structures bonded to the substrate. The LED step structure includes sequentially stacked sub-epipolar layers, sub-metal layers, and sub-transparent protective layers. The passivation layer covers the outer wall of the LED step structure and the bottom of the isolation trench. Each sub-transparent protective layer has a via formed above it for exposing the sub-transparent protective layer. The common electrode layer covers the passivation layer and the sub-transparent protective layers within the vias, such that the sub-metal layer is connected to the common electrode layer through the sub-transparent protective layer.

[0016] Optionally, the LED step structure is a MicroLED, MiniLED, or NanoLED.

[0017] The display backplane and its manufacturing method disclosed in this application utilize a transparent protective layer to cover the sub-metal layer and the ohmic contact layer. The ohmic contact layer can avoid repeated immersion in solutions such as resist remover and developer, effectively preventing the ohmic contact layer from being etched from the inside and ensuring the formation of ohmic contacts. At the same time, during PV etching, it effectively protects the metal layer from being scratched and effectively prevents abnormal lighting caused by voltage rise in the chip. Attached Figure Description

[0018] Figure 1 This application provides a schematic diagram showing the structure in which bonding metal layers are respectively provided on the epitaxial wafer and the substrate in an embodiment of the present application; Figure 2 This is a schematic diagram of the structure of the epitaxial wafer and substrate after bonding, provided in an embodiment of this application. Figure 3 This is a schematic diagram of the structure of the epitaxial bonding substrate provided in the embodiments of this application; Figure 4This is a schematic diagram of the structure of a sub-metal layer on an epitaxial bonding substrate provided in an embodiment of this application; Figure 5 A schematic diagram of a structure with a transparent protective layer on an epitaxial bonding substrate provided in an embodiment of this application; Figure 6 A schematic diagram of the structure for etching isolation trenches on an epitaxial bonding substrate provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a passivation layer formed on an epitaxial bonding substrate provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of the etched passivation layer on the epitaxial bonding substrate provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of the display backplate provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure for setting up pads according to an embodiment of this application; Figure 11 A flowchart illustrating a method for manufacturing a display backplane according to an embodiment of this application.

[0019] Explanation of reference numerals in the attached figures: 1-substrate; 2-bonding layer; 3-ohmic contact layer; 31-sub-ohmic contact layer; 4-sub-metal layer; 5-transparent protective layer; 51-sub-transparent protective layer; 6-epitaxy layer; 61-sub-epitaxy layer; 7-passivation layer; 71-via; 8-common electrode layer; 9-first pad; 10-second pad; C-isolation trench. Detailed Implementation

[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0022] In the description of this application, the terms "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0025] See Figures 2 to 11 As shown in the figure, this application discloses a method for manufacturing a display back panel, the steps of which include: An epitaxial bonding substrate is provided, the epitaxial bonding substrate comprising a substrate 1 and a film structure stacked sequentially, the film structure comprising a bonding layer 2, an epitaxial layer 6 and an ohmic contact layer 3 stacked sequentially on the substrate 1; Multiple spaced sub-metal layers 4 are formed on the ohmic contact layer 3; A transparent protective layer 5 is formed to cover the sub-metal layer 4 and the ohmic contact layer 3; Isolation trenches C are etched in the region surrounding the sub-metal layer 4 and toward the film structure to obtain multiple spaced LED step structures. Each LED step structure corresponds to a sub-metal layer 4. The LED step structure includes a sub-epitaxy layer 61, a sub-ohmic contact layer 31, a sub-metal layer 4, and a sub-transparent protective layer 51 stacked sequentially. The sub-epitaxy layer 61, the sub-ohmic contact layer 31, and the sub-transparent protective layer 51 are obtained by etching the epitaxial layer 6, the ohmic contact layer 3, and the transparent protective layer 5, respectively, through isolation trenches C. A passivation layer 7 is formed to cover the outer wall of the LED step structure and the bottom of the isolation groove C. Through holes 71 are opened on the passivation layer above each of the sub-transparent protective layers 51 to expose the sub-transparent protective layers 51. The outer wall of the LED step structure includes the side wall of the LED step structure and the sub-transparent protective layer 51 located on the top surface of the LED step structure. A common electrode layer 8 is formed to cover the passivation layer 7 and the sub-transparent protective layer 51 within the via 71, so that the sub-metal layer 4 is connected to the common electrode layer 8 through the sub-transparent protective layer 51. The display backplane and its manufacturing method of this application utilize a transparent protective layer to cover the sub-metal layer and the ohmic contact layer. The ohmic contact layer can avoid repeated immersion in solutions such as resist remover and developer, effectively preventing the ohmic contact layer from being etched from the inside, ensuring the formation of ohmic contacts. Simultaneously, it effectively protects the metal layer from being scratched during PV etching, effectively preventing abnormal illumination caused by increased chip voltage.

[0026] In this embodiment, the transparent protective layer 5 includes at least one of an ITO protective layer, an IZO protective layer, and an IGZO protective layer. ITO, IZO, and IGZO protective layers themselves possess strong stability, do not react with weak alkalis or weak acids, and do not react with F-based gases during ICP etching; they also have excellent light transmittance, not affecting the chip's light emission; and they themselves have low resistance (negligible), not affecting the chip's voltage.

[0027] In this embodiment, a plurality of spaced sub-metal layers 4 are formed on the ohmic contact layer 3, including the following steps: spin-coating negative photoresist on the ohmic contact layer 3, patterning the negative photoresist to reserve a plurality of evaporation areas, evaporating the sub-metal layers 4 in each evaporation area to obtain a plurality of spaced sub-metal layers 4, and removing the negative photoresist.

[0028] In this embodiment, the thickness of the transparent protective layer 5 ranges from 100 Å to 500 Å. A reasonably thick transparent protective layer 5 effectively protects the metal layer 4 and the ohmic contact layer 3.

[0029] In this embodiment, the ohmic contact layer 3 includes at least one of GaAs ohmic contact layer and GaP ohmic contact layer. Optionally, the ohmic contact layer 3 is a GaAs ohmic contact layer. In this embodiment, the epitaxial layer 6 can be a red epitaxial layer, a blue epitaxial layer, a green epitaxial layer, a two-color epitaxial layer, or a three-color epitaxial layer. The two-color epitaxial layer can be a blue-green stacked epitaxial layer, a red-green stacked epitaxial layer, or other different combinations of two-color epitaxial layers, which is not limited here. The three-color epitaxial layer can be a red-green-blue stacked epitaxial layer, or a combination of other three colors, which is not limited here. For example, if the ohmic contact layer 3 is a GaAs ohmic contact layer, a protective layer is deposited on the surface of the metal layer and the GaAs ohmic contact layer to prevent corrosion of the GaAs ohmic contact layer during repeated immersion in solutions such as resist remover and developer, and to prevent damage to the metal layer during PV etching, thereby reducing the frequency of voltage anomalies.

[0030] In this embodiment, the metal layer includes at least one of AuGeNi metal layer, Au metal layer, Ge metal layer, Pd metal layer, Ni metal layer and AuGe metal layer.

[0031] See Figure 6 As shown, the depth of the etching of the isolation trench C is from the transparent protective layer 5 to the bonding layer 2.

[0032] See Figures 6 to 10 When creating a via 71 on the passivation layer 7 on the top surface of each of the LED step structures, the following steps are also performed: The passivation layer 7 and the bonding layer 2 at the bottom of the isolation trench C are etched to the substrate 1 to divide the bonding layer 2 into a plurality of block pixels, each block pixel including at least one of the LED step structures.

[0033] See Figure 10 As shown, a first pad 9 for connecting the power supply is formed on the common electrode layer 8; When the pixel block includes multiple LED step structures, a second pad 10 for connecting a power source is formed on the bonding layer 2 in each pixel block. The LED step structure is connected to the second pad 10 through the bonding layer 2. When each pixel block includes multiple LED step structures, each pixel block is driven by energizing the bonding layer 2 in each pixel block. The substrate 1 can be a carrier substrate or a driving substrate. Energizing the bonding layer 2 can be done by providing power to the driving substrate or by providing power to the second pad 10 on the bonding layer 2. The carrier substrate can be a Si substrate, a sapphire substrate, a silicon substrate, a silicon carbide substrate, or other types.

[0034] When each pixel includes an LED step structure, substrate 1 is a driving substrate, and the driving circuit of substrate 1 is used for driving. The driving substrate can be a CMOS substrate, circuit board, array substrate, glass driving substrate, flexible driving substrate, lamp board, semiconductor driving substrate or other types of driving substrate, which is not specifically limited in this embodiment. The material of the driving substrate can be glass, transparent plastic, acrylic, quartz, sapphire, semiconductor material, etc., which can be selected according to the actual situation, and is not specifically limited in this embodiment.

[0035] See Figures 1 to 3 As shown, the preparation of the epitaxial bonding substrate includes the following steps: An epitaxial wafer and a substrate 1 are provided, wherein the epitaxial wafer comprises a substrate, an ohmic contact layer 3 and an epitaxial layer 6 stacked sequentially; A bonding metal layer is formed on the side of the epitaxial wafer away from the substrate and on the surface of the substrate, respectively, and the epitaxial wafer and the substrate 1 are bonded through the bonding metal layer; wherein, the bonding metal layer forms a bonding layer after bonding; Remove the substrate to expose the ohmic contact layer 3.

[0036] In this embodiment, the epitaxial wafer is bonded to the substrate 1 via the bonding metal layer, including the following steps: Under preset temperature and preset pressure, the epitaxial wafer is bonded to the substrate 1 through the bonding metal layer, wherein the preset temperature ranges from 250°C to 330°C; and the preset pressure ranges from 6000 kgf to 15000 kgf.

[0037] In this embodiment, the bonding metal layer includes at least one of AuAu bonding metal layer, AuSn bonding metal layer and AuIn bonding metal layer.

[0038] In this embodiment, the thickness of the passivation layer 7 ranges from 200nm to 500nm.

[0039] In this embodiment, a buffer layer and an etching stop layer are also disposed between the substrate and the ohmic contact layer 3, which are sequentially stacked on the substrate; Removing the substrate to expose the ohmic contact layer 3 includes performing the following steps: Remove the substrate, the buffer layer, and the etching stop layer to expose the ohmic contact layer 3. Remove the substrate and etching stop layer by using a mixed solution of ammonia and hydrogen peroxide to remove the substrate from the epitaxial surface, followed by removing the surface stop layer using hydrochloric acid.

[0040] In this embodiment, the epitaxial layer 6 includes an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer stacked sequentially, and the ohmic contact layer 3 is disposed on the side of the N-type semiconductor layer away from the quantum well layer or on the side of the P-type semiconductor layer away from the quantum well layer.

[0041] See Figure 9 and Figure 11As shown in the figure, this application discloses a display backplate, which is manufactured using the above-described display backplate manufacturing method. It includes a substrate 1, a passivation layer 7, a common electrode layer 8, and a plurality of LED step structures bonded to the substrate 1. The LED step structure includes a sub-epipolar layer 61, a sub-metal layer 4, and a sub-transparent protective layer 51 stacked sequentially. The passivation layer 7 covers the outer wall of the LED step structure and the bottom of the isolation groove C. The passivation layer 7 above each sub-transparent protective layer 51 has a via 71 for exposing the sub-transparent protective layer 51. The common electrode layer 8 covers the passivation layer 7 and the sub-transparent protective layer 51 in the via 71, so that the sub-metal layer 4 is connected to the common electrode layer 8 through the sub-transparent protective layer 51.

[0042] In this embodiment, the LED step structure can be a MiniLED, MicroLED, nano-sized LED, or LED of other sizes. It is not limited here and can be selected according to the actual situation.

[0043] In this embodiment, the display back panel can be used as a direct display or a backlight.

[0044] As one implementation method, the display back panel can be a TV, VR / AR device, smart wearable device, mobile phone, vehicle display, etc.

[0045] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method of manufacturing a display backplane, characterized by the steps of include: An epitaxial bonding substrate is provided, the epitaxial bonding substrate comprising a substrate and a film layer structure stacked sequentially, the film layer structure comprising a bonding layer, an epitaxial layer and an ohmic contact layer stacked sequentially on the substrate; Multiple spaced sub-metal layers are formed on the ohmic contact layer; A transparent protective layer is formed to cover the sub-metal layer and the ohmic contact layer; Isolation trenches are etched in the region surrounding the sub-metal layer and toward the film structure to obtain multiple spaced LED step structures. Each LED step structure corresponds to one of the sub-metal layers. Each LED step structure includes a sub-epitaxy layer, a sub-ohmic contact layer, the sub-metal layer, and a sub-transparent protective layer stacked sequentially. The sub-epitaxy layer, the sub-ohmic contact layer, and the sub-transparent protective layer are obtained by etching the epitaxial layer, the ohmic contact layer, and the transparent protective layer through the isolation trenches, respectively. A passivation layer is formed to cover the outer wall of the LED stepped structure and the bottom of the isolation groove. Through holes are made in the passivation layer above each of the sub-transparent protective layers to expose the sub-transparent protective layers. The outer wall of the LED stepped structure includes the side wall of the LED stepped structure and the sub-transparent protective layer located on the top surface of the LED stepped structure. A common electrode layer is formed to cover the passivation layer and the sub-transparent protective layer within the via, such that the sub-metal layer is connected to the common electrode layer through the sub-transparent protective layer.

2. The method of manufacturing a display backplane of claim 1, wherein, The thickness of the transparent protective layer ranges from 100 Å to 500 Å.

3. The method for manufacturing a display backplane according to claim 1 or 2, wherein The ohmic contact layer includes at least one of GaAs ohmic contact layer and GaP ohmic contact layer.

4. The method for manufacturing a display backplane according to claim 1 or 2, wherein The metal layer includes at least one of AuGeNi metal layer, Au metal layer, Ge metal layer, Pd metal layer, Ni metal layer and AuGe metal layer.

5. The method for manufacturing a display backplane according to claim 1 or 2, wherein The depth of the isolation trench etching extends from the transparent protective layer to the bonding layer.

6. The method for manufacturing a display back panel as described in claim 5, characterized in that, When creating vias in the passivation layer on the top surface of each of the LED stepped structures, the following steps are also performed: The passivation layer and the bonding layer at the bottom of the isolation trench are etched onto the substrate to divide the bonding layer into a plurality of block pixels, each block pixel including at least one of the LED step structures.

7. The method for manufacturing a display back panel as described in claim 6, characterized in that, A first pad for connecting a power supply is formed on the common electrode layer; When the block pixel includes multiple LED step structures, a second pad for connecting power is formed on the bonding layer in each block pixel, and the LED step structure is connected to the second pad through the bonding layer.

8. The method for manufacturing a display back panel as described in claim 1, 2, 6, or 7, characterized in that, The preparation of the epitaxial bonding substrate includes the following steps: An epitaxial wafer and a substrate are provided, wherein the epitaxial wafer comprises a substrate, an ohmic contact layer and an epitaxial layer stacked sequentially; A bonding metal layer is formed on the side of the epitaxial wafer away from the substrate and on the surface of the substrate, respectively, and the epitaxial wafer and the substrate are bonded through the bonding metal layer; wherein, the bonding metal layer forms a bonding layer after bonding; Remove the substrate to expose the ohmic contact layer.

9. The method for manufacturing a display back panel as described in claim 8, characterized in that, A buffer layer and an corrosion barrier layer are also disposed between the substrate and the ohmic contact layer, which are sequentially stacked on the substrate. Removing the substrate to expose the ohmic contact layer includes performing the following steps: Remove the substrate, the buffer layer, and the etch stop layer to expose the ohmic contact layer.

10. The method for manufacturing a display back panel as described in claim 1, 2, 6, 7, or 9, characterized in that, The epitaxial layer includes an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer stacked sequentially, and the ohmic contact layer is disposed on the side of the N-type semiconductor layer away from the quantum well layer or on the side of the P-type semiconductor layer away from the quantum well layer.

11. The method for manufacturing a display back panel as described in claim 1, 2, 6, 7, or 9, characterized in that, The transparent protective layer includes at least one of an ITO protective layer, an IZO protective layer, and an IGZO protective layer.

12. A display back panel, manufactured using the method for manufacturing a display back panel as described in any one of claims 1 to 11, characterized in that, The device includes a substrate, a passivation layer, a common electrode layer, and multiple LED step structures bonded to the substrate. The LED step structure includes a sub-epipolar layer, a sub-metal layer, and a sub-transparent protective layer stacked sequentially. The passivation layer covers the outer wall of the LED step structure and the bottom of the isolation trench. The passivation layer above each sub-transparent protective layer has a via for exposing the sub-transparent protective layer. The common electrode layer covers the passivation layer and the sub-transparent protective layer within the via, such that the sub-metal layer is connected to the common electrode layer through the sub-transparent protective layer.

13. The display back panel as described in claim 12, characterized in that, The LED step structure is either MicroLED or MiniLED.

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