Electrical interconnect structure and method of forming the same, panel level package structure

Abstract

An electrical interconnect structure and its formation method, as well as a panel-level packaging structure, are disclosed. The electrical interconnect structure includes: several conductive structures, the surfaces of which have been roughened to form micro-pit structures; and a molding compound layer covering the sidewalls of the conductive structures. The roughened sidewalls of the conductive structures form micro-pit morphologies. This three-dimensional porous structure significantly increases the actual contact area between the conductive structures and the molding compound layer, enabling a tight mechanical bond at the interface of the two dissimilar materials. After the molding compound layer completely covers the roughened sidewalls of the conductive structures, the molding compound material is embedded within the micro-pit structures, generating a significant anchoring effect and effectively suppressing interface delamination. When the packaging structure experiences temperature changes or is subjected to external mechanical loads, the increased interfacial adhesion can uniformly disperse stress, preventing excessive stress concentration at the interface between the conductive structures and the molding compound layer, thereby preventing the generation and propagation of cracks and significantly improving the long-term reliability and failure resistance of the packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an electrical interconnect structure and its formation method, and a panel-level packaging structure. Background Technology

[0002] CoPoS (Chip-on-Panel-on-Substrate) is a next-generation advanced panel-level packaging technology. Its core innovation lies in replacing the traditional circular wafer as the interposer with a square panel, achieving a paradigm shift in manufacturing by "turning the circle into a square." This technology uses novel materials such as glass or sapphire to construct the redistribution layer, and forms a fine interconnect structure through panel-level photolithography and electroplating processes. This supports the integration of larger-sized multi-chips and effectively addresses the rapidly increasing demand for packaging area from AI chips.

[0003] In the interconnection between chips and panels, high-copper pillars play a crucial role as high-density interconnect interfaces pre-fabricated on the chip. They are formed during chip manufacturing by electroplating to create a three-dimensional structure with a significantly higher aspect ratio than traditional bumps, topped with a tin-silver alloy solder cap, enabling high-density flip-chip connections between the bare chip and the panel. High-copper pillars not only inherit the excellent electrical properties and mechanical reliability of copper, but also provide greater thermal cycling stress buffer space by increasing the pillar height, significantly reducing the risk of solder joint fatigue failure. Simultaneously, they meet the stringent requirements for power integrity and signal integrity in fine-pitch interconnect scenarios. This combination leverages the cost and size advantages of panel-level packaging while utilizing the enhanced characteristics of high-copper pillars to provide an efficient interconnect foundation for 2.5D / 3D integration and chip-to-chip architectures, becoming a mainstream development direction in high-performance computing and artificial intelligence accelerators.

[0004] However, the high copper pillars in the existing panel-level packaging structure still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an electrical interconnect structure and its formation method, as well as a panel-level packaging structure, to increase the interfacial bonding between the conductive structure and the molding layer.

[0006] To address the aforementioned problems, the present invention provides an electrical interconnect structure comprising: a plurality of conductive structures, wherein the surface of the conductive structures has a roughened micro-pit structure; the conductive structures serve as through-type vertical conductive channels for shortening the signal transmission path; and a molding layer covering the sidewalls of the conductive structures.

[0007] Optionally, the conductive structure is a monolithic structure.

[0008] Optionally, the conductive structure includes: a plurality of sub-conductive parts stacked sequentially, wherein any two adjacent sub-conductive parts are in contact with each other, and the projection areas of any two adjacent sub-conductive parts toward the stacking direction have an overlapping area.

[0009] Optionally, along the stacking direction, in any two adjacent sub-conductive parts, the projection area of ​​the upper sub-conductive part facing the stacking direction is located within the projection area of ​​the lower sub-conductive part facing the stacking direction; or, along the stacking direction, in any two adjacent sub-conductive parts, the projection area of ​​the lower sub-conductive part facing the stacking direction is located within the projection area of ​​the upper sub-conductive part facing the stacking direction.

[0010] Optionally, the individual sub-conductive parts are coaxially stacked along the stacking direction.

[0011] Optionally, the molding layer exposes the end faces of opposite sides of the conductive structure.

[0012] Optionally, it further includes: a seed layer located on one end face of the conductive structure; the encapsulation layer also covers the sidewall of the seed layer and exposes the end face of the conductive structure on the opposite side.

[0013] Accordingly, the present invention also provides a method for forming an electrical interconnect structure, comprising: forming a plurality of conductive structures, wherein the surface of the conductive structures has a roughened micro-pit structure; the conductive structures serve as through-type vertical conductive channels to shorten the signal transmission path; and forming a molding layer, wherein the molding layer covers the sidewalls of the conductive structures.

[0014] Optionally, the method for forming the conductive structure and the molding compound includes: providing a substrate; forming a seed material layer on the substrate; forming the conductive structure on the seed material layer; etching the seed material layer using the conductive structure as a mask until the substrate is exposed, thereby forming a seed layer; after forming the seed layer, performing the roughening treatment on the surface of the conductive structure to give the surface of the conductive structure a micropit structure; after the roughening treatment, forming a molding compound layer on the substrate, the molding compound layer covering the seed layer and the conductive structure; and performing a planarization treatment on the molding compound layer until the end face of the conductive structure is exposed, thereby forming the molding compound layer.

[0015] Optionally, the method for forming the conductive structure and the molding compound includes: providing a substrate; forming a seed material layer on the substrate; forming the conductive structure on the seed material layer; performing the roughening treatment on the surface of the conductive structure to give the surface of the conductive structure a micropit structure; after the roughening treatment, forming a molding compound layer on the substrate, the molding compound layer covering the conductive structure; performing a planarization treatment on the molding compound layer until the end face of the conductive structure is exposed, thereby forming the molding compound layer; after forming the molding compound layer, removing the substrate and the seed material layer, the molding compound layer exposing the end face of the conductive structure on the opposite side.

[0016] Optionally, the conductive structure is a monolithic structure.

[0017] Optionally, the method for forming the conductive structure on the seed material layer includes: forming a photoresist layer on the seed material layer; performing an exposure and development process on the photoresist layer to form a via, the via exposing the seed material layer; forming the conductive structure in the via using an electroplating process; and removing the photoresist layer after forming the conductive structure.

[0018] Optionally, the conductive structure includes: a plurality of sub-conductive parts stacked sequentially, wherein any two adjacent sub-conductive parts are in contact with each other, and the projection areas of any two adjacent sub-conductive parts toward the stacking direction have an overlapping area.

[0019] Optionally, the method for forming the conductive structure on the seed material layer includes: forming each of the sequentially stacked sub-conductive portions by employing a number of photolithography electroplating processes; wherein each photolithography electroplating process forms one layer of the sub-conductive portion.

[0020] Optionally, the first photolithography electroplating process includes: forming a first photoresist layer on the seed material layer; exposing and developing the first photoresist layer to form a first via, the first via exposing the seed material layer; forming the sub-conductive portion located in the bottom layer in the first via using an electroplating process; and removing the first photoresist layer after forming the sub-conductive portion located in the bottom layer.

[0021] Optionally, each subsequent photolithography electroplating process includes: forming a second photoresist layer on the substrate, the second photoresist layer covering the already formed sub-conductive portion; exposing and developing the second photoresist layer to form a second via, the second via exposing the already formed sub-conductive portion located on the upper layer; forming the sub-conductive portion within the second via using an electroplating process; and removing the second photoresist layer after forming the sub-conductive portion.

[0022] Optionally, along the stacking direction, in any two adjacent sub-conductive parts, the projection area of ​​the upper sub-conductive part facing the stacking direction is located within the projection area of ​​the lower sub-conductive part facing the stacking direction; or, along the stacking direction, in any two adjacent sub-conductive parts, the projection area of ​​the lower sub-conductive part facing the stacking direction is located within the projection area of ​​the upper sub-conductive part facing the stacking direction.

[0023] Optionally, the mixture in the roughening process includes: hydroxyethylidene diphosphonic acid, sodium hydroxide, hydrogen peroxide, benzotriazole, and sulfuric acid.

[0024] Accordingly, the present invention also provides a panel-level packaging structure, comprising: an electrical interconnection structure as described in any of the above technical solutions, the electrical interconnection structure including a first side and a second side opposite to each other; a first rewiring layer located on the first side, the first rewiring layer being electrically connected to one end of the conductive structure; and a second rewiring layer located on the second side, the second rewiring layer being electrically connected to the other end opposite to the conductive structure.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages: In the electrical interconnect structure of this invention, the sidewalls of the conductive structure, after being roughened, form a micro-pit morphology. This three-dimensional porous structure significantly increases the actual contact area between the conductive structure and the molding compound, enabling a tight mechanical bond at the interface of the two dissimilar materials. After the molding compound completely covers the roughened sidewalls of the conductive structure, the molding material embeds into the interior of the micro-pit structure, generating a significant anchoring effect and effectively suppressing interface delamination. When the packaged structure experiences temperature changes or is subjected to external mechanical loads, the increased interface adhesion can uniformly disperse stress, preventing excessive stress concentration at the interface between the conductive structure and the molding compound, thereby preventing the generation and propagation of cracks. This structural design achieves interface strengthening through surface morphology optimization without increasing the size of the conductive structure, thus significantly improving the long-term reliability and failure resistance of the packaged structure.

[0026] Furthermore, the conductive structure includes a plurality of sequentially stacked sub-conductive portions, wherein any two adjacent sub-conductive portions are in contact with each other, and the projected areas of any two adjacent sub-conductive portions facing the stacking direction overlap. By decomposing the conductive structure into a plurality of sequentially stacked sub-conductive portions, the process bottleneck of limited photoresist thickness in a single coating is overcome, allowing for a significant increase in the height of the final conductive structure. The fact that any two adjacent sub-conductive portions are in contact with each other, and that the projected areas of any two adjacent sub-conductive portions facing the stacking direction overlap, ensures the electrical connectivity and structural stability between the interconnected sub-conductive portions. The formed conductive structure can meet the design requirements of large-scale integrated circuits and very large-scale integrated circuits.

[0027] In the method for forming the electrical interconnect structure of the present invention, the sidewalls of the conductive structure are roughened to form a micro-pit morphology. This three-dimensional porous structure can significantly increase the actual contact area between the conductive structure and the molding compound, enabling a tight mechanical bond at the interface of the two heterogeneous materials. After the molding compound completely covers the roughened sidewalls of the conductive structure, the molding material is embedded inside the micro-pit structure, producing a significant anchoring effect and effectively suppressing interface delamination. When the packaged structure experiences temperature changes or is subjected to external mechanical loads, the increased interface adhesion can uniformly disperse stress, preventing excessive stress concentration at the interface between the conductive structure and the molding compound, thereby preventing the generation and propagation of cracks. This structural design achieves interface strengthening through surface morphology optimization without increasing the size of the conductive structure, thus significantly improving the long-term reliability and failure resistance of the packaged structure. Attached Figure Description

[0028] Figures 1 to 7 This is a schematic diagram of the steps in the method for forming the electrical interconnect structure according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the electrical interconnect structure according to another embodiment of the present invention; Figures 9 to 16 This is a schematic diagram of the steps in the method for forming an electrical interconnect structure according to another embodiment of the present invention; Figure 17 This is a schematic diagram of the electrical interconnect structure according to another embodiment of the present invention; Figure 18 This is a schematic diagram of the panel-level packaging structure according to an embodiment of the present invention. Detailed Implementation

[0029] As described in the background section, the high-copper pillars in existing panel-level packaging structures still present numerous problems. These will be explained in detail below.

[0030] As a conductive interconnect structure, the bonding strength between the surface of high-copper pillars and the molding compound often fails to meet reliability requirements under high-stress environments. Due to the significant differences in physicochemical properties between copper and organic molding compounds, weak bonding regions easily form at the interface. Under conditions such as temperature cycling, mechanical stress, or environmental aging, stress concentration easily occurs at the interface, leading to failure modes such as delamination and cracking. Furthermore, as the height of the copper pillar increases, the contact area with the molding compound decreases relatively, further weakening the interfacial mechanical locking effect, making the encapsulation structure more susceptible to crack propagation under thermomechanical stress.

[0031] Based on this, the present invention provides an electrical interconnect structure and its formation method, as well as a panel-level packaging structure. The sidewalls of the conductive structure, after roughening treatment, form a micro-pit morphology. This three-dimensional porous structure significantly increases the actual contact area between the conductive structure and the molding compound, enabling a tight mechanical bond at the interface of the two dissimilar materials. After the molding compound completely covers the roughened sidewalls of the conductive structure, the molding material is embedded within the micro-pit structure, generating a significant anchoring effect and effectively suppressing interface delamination. When the packaging structure experiences temperature changes or is subjected to external mechanical loads, the increased interfacial adhesion can uniformly disperse stress, preventing excessive stress concentration at the interface between the conductive structure and the molding compound, thereby preventing the generation and propagation of cracks. This structural design achieves interface strengthening through surface morphology optimization without increasing the size of the conductive structure, thus significantly improving the long-term reliability and failure resistance of the packaging structure.

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Figures 1 to 7 This is a schematic diagram of the steps in the method for forming the electrical interconnect structure according to an embodiment of the present invention.

[0034] Several conductive structures are formed, and the surface of each conductive structure has a roughened micro-pit structure; each conductive structure is a monolithic structure. Please refer to [reference needed] for the specific formation process. Figures 1 to 6 .

[0035] Please refer to Figure 1 Substrate 100 is provided.

[0036] In this embodiment, the substrate 100 uses a rectangular shape as the basic support platform for subsequent process technologies. Unlike the circular silicon wafers used in traditional wafer-level packaging, the rectangular shape of the substrate 100 is specifically designed for the requirements of CoPoS (Chip-on-Panel-on-Substrate) processes, facilitating the efficient production of large-area panel-level packaging. The substrate 100 provides stable mechanical support and process reference during the fabrication of the conductive structure. After the high-copper pillars are successfully fabricated, the substrate 100 is removed, allowing the formed conductive structure to be directly integrated into the target package structure.

[0037] Please refer to Figure 2 A seed material layer 101 is formed on the substrate 100.

[0038] In this embodiment, the seed material layer 101 is typically formed on the surface of the substrate 100 using a physical vapor deposition process, forming a titanium-copper composite structure as a conductive substrate for subsequent electroplating processes. The seed material layer 101 has good conductivity and adhesion, providing a uniform current distribution path for the electrochemical reaction and ensuring selective deposition of electroplated metal in designated areas.

[0039] After forming the seed material layer 101, the conductive structure is formed on the seed material layer 101. Please refer to [link / reference needed] for the specific formation process. Figures 3 to 6 .

[0040] Please refer to Figure 3 A photoresist layer 102 is formed on the seed material layer 101; the photoresist layer 102 is exposed and developed to form a through hole 103, the through hole 103 exposing the seed material layer 101.

[0041] In this embodiment, the photoresist layer 102 is uniformly coated onto the surface of the seed material layer 101 using a spin-coating or spray-coating process, and a dense photosensitive film is formed after solvent removal by soft baking. The photoresist layer 102 serves as a medium for pattern transfer, forming vias 103 with specific morphologies after exposure and development, precisely defining the deposition area of ​​the sub-conductive portion located in the bottom layer, and achieving selective growth of electroplated metal.

[0042] Please refer to Figure 4 The conductive structure 104 is formed in the through hole 103 by electroplating; after the conductive structure 104 is formed, the photoresist layer 102 is removed.

[0043] In this embodiment, an electroplating process is used to deposit metal material in the through hole 103. By controlling the current density and electroplating time, metal ions are reduced and deposited on the exposed seed material layer 101 surface, filling the through hole 103 from bottom to top to form the conductive structure 104.

[0044] In this embodiment, the conductive structure 104 is made of copper.

[0045] Please refer to Figure 5 The seed material layer 101 is etched using the conductive structure 104 as a mask until the substrate 100 is exposed, thereby forming a seed layer 105.

[0046] In this embodiment, the conductive structure 104 is used as a self-aligned mask to selectively etch the seed material layer 101 below it. The etching process continues until the surface of the substrate 100 is completely exposed, thereby forming a patterned seed layer 105 at the bottom of the conductive structure 104. The seed layer 105 is retained in the area directly below the conductive structure 104.

[0047] Please refer to Figure 6 After the seed layer 105 is formed, the surface of the conductive structure 104 is roughened to give the surface of the conductive structure 104 a micro-pit structure.

[0048] In this embodiment, the mixture in the roughening treatment comprises: hydroxyethylidene diphosphonic acid, sodium hydroxide, hydrogen peroxide, benzotriazole, and sulfuric acid. Hydroxyethylidene diphosphonic acid acts as a chelating agent to form a stable complex with copper ions; sodium hydroxide provides an alkaline environment to regulate the reaction rate; hydrogen peroxide acts as an oxidant to promote selective dissolution of the copper surface; benzotriazole acts as a corrosion inhibitor to suppress excessive corrosion; and sulfuric acid is used to maintain the acidity balance of the solution. Under the synergistic effect of these components, a controllable chemical etching reaction occurs on the copper surface, forming a coral-like micropit structure with three-dimensional network characteristics, significantly increasing the surface area of ​​the conductive structure 104.

[0049] Please refer to Figure 7 After the conductive structure 104 is formed, a molding layer 106 is formed, which covers the sidewalls of the conductive structure 104.

[0050] After the roughening treatment, the sidewalls of the conductive structure 104 form a micro-pit morphology. This three-dimensional porous structure significantly increases the actual contact area between the conductive structure 104 and the molding compound 106, creating a tight mechanical bond at the interface of the two dissimilar materials. After the molding compound 106 completely covers the roughened sidewalls of the conductive structure 104, the molding material embeds into the interior of the micro-pit structure, generating a significant anchoring effect and effectively suppressing interface delamination. When the packaged structure experiences temperature changes or is subjected to external mechanical loads, the increased interfacial adhesion can evenly disperse stress, preventing excessive stress concentration at the interface between the conductive structure 104 and the molding compound 106, thereby preventing the generation and propagation of cracks. This structural design achieves interface strengthening through surface morphology optimization without increasing the size of the conductive structure 104, thus significantly improving the long-term reliability and failure resistance of the packaged structure.

[0051] In this embodiment, the method for forming the molding layer 106 includes: after the roughening treatment, forming a molding material layer (not shown) on the substrate 100, the molding material layer covering the seed layer 105 and the conductive structure 104; performing a planarization treatment on the molding material layer until the end face of the conductive structure 104 is exposed, thereby forming the molding layer 106.

[0052] In this embodiment, the encapsulation layer 106 is made of epoxy resin. Epoxy resin has good insulation, adhesion and process compatibility, and after grinding, it can achieve high coplanarity with the surface of the conductive structure 104.

[0053] Please continue to refer to this. Figure 7 After the molding layer 106 is formed, the substrate 100 is removed.

[0054] In this embodiment, the removal of the substrate 100 can be achieved by a debonding process, that is, by separating the temporarily bonded substrate 100 through thermal, optical or mechanical means.

[0055] Accordingly, this invention also provides an electrical interconnection structure, please refer to the following embodiments. Figure 7 It includes: a plurality of conductive structures 104, the surface of which has a roughened micro-pit structure; and a molding layer 106, which covers the sidewalls of the conductive structures 104.

[0056] After the roughening treatment, the sidewalls of the conductive structure 104 form a micro-pit morphology. This three-dimensional porous structure significantly increases the actual contact area between the conductive structure 104 and the molding compound 106, creating a tight mechanical bond at the interface of the two dissimilar materials. After the molding compound 106 completely covers the roughened sidewalls of the conductive structure 104, the molding material embeds into the interior of the micro-pit structure, generating a significant anchoring effect and effectively suppressing interface delamination. When the packaged structure experiences temperature changes or is subjected to external mechanical loads, the increased interfacial adhesion can evenly disperse stress, preventing excessive stress concentration at the interface between the conductive structure 104 and the molding compound 106, thereby preventing the generation and propagation of cracks. This structural design achieves interface strengthening through surface morphology optimization without increasing the size of the conductive structure 104, thus significantly improving the long-term reliability and failure resistance of the packaged structure.

[0057] In this embodiment, the conductive structure 104 is a single-monostructure structure.

[0058] In this embodiment, it further includes: a seed layer 105, which is located on one end face of the conductive structure 104; the encapsulation layer 106 also covers the sidewall of the seed layer 105 and exposes the end face of the conductive structure 104 on the opposite side.

[0059] Figure 8 This is a schematic diagram of the electrical interconnect structure according to another embodiment of the present invention.

[0060] This embodiment is based on the above embodiment ( Figure 7 The electrical interconnect structure will continue to be described based on the previous embodiment. The rest is the same as the previous embodiment, except that the conductive structure 104 and the molding layer 106 are formed using different methods, and the electrical interconnect structure does not have the seed layer 105. The following will provide a detailed description in conjunction with the accompanying drawings.

[0061] Please refer to Figure 8 The molding layer 106 exposes the end faces of opposite sides of the conductive structure 104.

[0062] In this embodiment, the method for forming the conductive structure 104 and the molding layer 106 includes: providing a substrate 100; forming a seed material layer 101 on the substrate 100; forming the conductive structure 104 on the seed material layer 101; performing the roughening treatment on the surface of the conductive structure 104 to give the surface of the conductive structure 104 a micro-pit structure; after the roughening treatment, forming a molding material layer (not shown) on the substrate 100, the molding material layer covering the seed layer 105 and the conductive structure 104; performing a planarization treatment on the molding material layer until the end face of the conductive structure 104 is exposed, forming the molding layer 106; after forming the molding layer 106, removing the substrate 100 and the seed material layer 101, the molding layer 106 exposing the end face of the conductive structure 104 on the opposite side.

[0063] Figures 9 to 16 This is a schematic diagram of the steps in the method for forming an electrical interconnect structure according to another embodiment of the present invention.

[0064] Several conductive structures are formed, each with a roughened micro-pit structure on its surface. Each conductive structure includes several sequentially stacked sub-conductive portions, where any two adjacent sub-conductive portions are in contact with each other, and the projected areas of any two adjacent sub-conductive portions facing the stacking direction overlap. For a detailed formation process, please refer to [reference needed]. Figures 9 to 15 .

[0065] Please refer to Figure 9 Substrate 200 is provided.

[0066] In this embodiment, the substrate 200 uses a rectangular shape as the basic support platform for subsequent process technologies. Unlike the circular silicon wafers used in traditional wafer-level packaging, the rectangular shape of the substrate 200 is specifically designed for the requirements of CoPoS (Chip-on-Panel-on-Substrate) processes, facilitating efficient production of large-area panel-level packaging. The substrate 200 provides stable mechanical support and process reference during the fabrication of the conductive structure. After the high-copper pillars are successfully fabricated, the substrate 200 is removed, allowing the formed conductive structure to be directly integrated into the target package structure.

[0067] Please refer to Figure 10 A seed material layer 201 is formed on the substrate 200.

[0068] In this embodiment, the seed material layer 201 is typically formed on the surface of the substrate 200 using a physical vapor deposition process, forming a titanium-copper composite structure as a conductive substrate for subsequent electroplating processes. The seed material layer 201 has good conductivity and adhesion, providing a uniform current distribution path for the electrochemical reaction and ensuring selective deposition of electroplated metal in designated areas.

[0069] After forming the seed material layer 201, the sub-conductive portion located on the bottom layer is formed using a first photolithography electroplating process. For details of the formation process, please refer to [link to documentation]. Figures 11 to 13 .

[0070] Please refer to Figure 11 A first photoresist layer 202 is formed on the seed material layer 201; the first photoresist layer 202 is exposed and developed to form a first through hole 203, the first through hole 203 exposing the seed material layer 201.

[0071] In this embodiment, the first photoresist layer 202 is uniformly coated onto the surface of the seed material layer 201 by spin coating or spray coating, and a dense photosensitive film is formed after solvent removal by soft baking. The first photoresist layer 202 serves as a medium for pattern transfer, forming the first through-hole 203 with a specific morphology after exposure and development, precisely defining the deposition area of ​​the sub-conductive part located in the bottom layer, and realizing selective growth of electroplated metal.

[0072] Please refer to Figure 12 The sub-conductive portion 204 located at the bottom layer is formed in the first through hole 203 by electroplating.

[0073] In this embodiment, an electroplating process is used to deposit metal material in the first through hole 203. By controlling the current density and electroplating time, metal ions are reduced and deposited on the exposed surface of the seed material layer 201, filling the first through hole 203 from bottom to top to form the sub-conductive part 204 located at the bottom layer.

[0074] Please refer to Figure 13 After forming the sub-conductive portion 204 located at the bottom layer, the first photoresist layer 202 is removed.

[0075] In this embodiment, after the sub-conductive portion 204 located at the bottom layer is electroplated, the first photoresist layer 202 is removed by a photoresist removal process, exposing the sub-conductive portion 204 at the bottom layer. The seed material layer 201 is still retained and continues to serve as the conductive substrate for subsequent electroplating processes.

[0076] Please refer to Figure 14After the first photolithography electroplating process, the remaining sequentially stacked sub-conductive portions 204 are formed by continuing the photolithography electroplating process several times.

[0077] In this embodiment, each subsequent photolithography and electroplating process includes: forming a second photoresist layer on the substrate 200, the second photoresist layer covering the already formed sub-conductive portion 204; performing an exposure and development process on the second photoresist layer to form a second via, the second via exposing the already formed sub-conductive portion 204 located on the upper layer; forming the sub-conductive portion 204 within the second via using an electroplating process; and removing the second photoresist layer (not shown) after forming the sub-conductive portion 204.

[0078] In this embodiment, the stacking direction is the surface normal direction of the substrate 200.

[0079] In this embodiment, the specific operation process of photoresist layer formation and removal, as well as electroplating deposition, involved in each subsequent photolithography electroplating process can refer to the process of the first photolithography electroplating process, and will not be repeated here.

[0080] Along the stacking direction, the height of the sub-conductive part 204 ranges from 100 micrometers to 140 micrometers; the number of layers of the sub-conductive part 204 in the conductive structure ranges from 2 to 6 layers.

[0081] In this embodiment, each photolithography electroplating process forms one layer of the sub-conductive portion 204. Taking four layers of the sub-conductive portion 204 as an example, four photolithography electroplating processes are required. The height of the sub-conductive portion 204 is 120 micrometers each time.

[0082] In this embodiment, the sub-conductive part 204 is made of copper.

[0083] In this embodiment, the height of the conductive structure along the stacking direction is greater than 380 micrometers.

[0084] In this embodiment, along the stacking direction, in any two adjacent sub-conductive portions 204, the projection area of ​​the upper sub-conductive portion 204 facing the stacking direction is located within the projection area of ​​the lower sub-conductive portion 204 facing the stacking direction. This structural design, where the upper sub-conductive portion 204 is recessed within the projection area of ​​the lower sub-conductive portion 204, effectively reduces the stringent requirements for photolithographic alignment accuracy, thereby relaxing the control window for overlay accuracy and significantly improving the tolerance for alignment errors during multilayer stacking.

[0085] In this embodiment, the projected area of ​​the sub-conductive portion 204 facing the stacking direction is circular, and the diameter difference between the circular projections of any two adjacent sub-conductive portions 204 is in the range of 10 micrometers to 15 micrometers. This range of 10 to 15 micrometers ensures sufficient alignment tolerance, reduces the stringent requirements for photolithography overlay accuracy, and decreases process complexity. It also avoids excessive diameter variations in the sub-conductive portions 204 during layer-by-layer stacking, preventing the top-layer sub-conductive portion 204 from being too small, which could lead to a surge in contact resistance or connection failure. Simultaneously, it prevents the top-layer sub-conductive portion 204 from being too large, encroaching on surrounding wiring space, effectively suppressing the risk of interlayer short circuits and ensuring wiring density.

[0086] In other embodiments, the shape of the projection area of ​​the sub-conductive part facing the stacking direction may also include: a rectangle or a polygon, specifically a regular pentagon or a regular hexagon.

[0087] In this embodiment, the sub-conductive parts 204 are coaxially stacked along the stacking direction. By arranging the sub-conductive parts 204 coaxially along the stacking direction, the geometric centers of the multi-layer structure are completely coincident, ensuring uniform force transmission in each layer, avoiding lateral stress concentration and structural tilting risks caused by eccentric stacking, and significantly improving the overall mechanical stability and deformation resistance of the stack.

[0088] By decomposing the conductive structure into multiple sequentially stacked sub-conductive portions 204, the process bottleneck of limited photoresist thickness in a single coating is overcome, allowing for a significant increase in the height of the final conductive structure. Any two adjacent sub-conductive portions 204 are in contact with each other, and the projected areas of any two adjacent sub-conductive portions 204 facing the stacking direction overlap, thereby ensuring electrical connectivity and structural stability between the interconnected sub-conductive portions 204. The resulting conductive structure meets the design requirements of large-scale integrated circuits and very large-scale integrated circuits.

[0089] Please refer to Figure 15 After the conductive structure is formed, the surface of the conductive structure is roughened to give the surface of the conductive structure a micro-pit structure.

[0090] In this embodiment, the mixture in the roughening treatment comprises: hydroxyethylidene diphosphonic acid, sodium hydroxide, hydrogen peroxide, benzotriazole, and sulfuric acid. Hydroxyethylidene diphosphonic acid acts as a chelating agent to form a stable complex with copper ions; sodium hydroxide provides an alkaline environment to regulate the reaction rate; hydrogen peroxide acts as an oxidant to promote selective dissolution of the copper surface; benzotriazole acts as a corrosion inhibitor to suppress excessive corrosion; and sulfuric acid is used to maintain the acidity balance of the solution. Under the synergistic effect of these components, a controllable chemical etching reaction occurs on the copper surface, forming a coral-like micropit structure with three-dimensional network characteristics, significantly increasing the surface area of ​​the conductive structure.

[0091] Please refer to Figure 16 After the conductive structure is formed, a molding layer 205 is formed, which covers the sidewalls of the conductive structure.

[0092] After the roughening treatment, the sidewalls of the conductive structure form a micro-pit morphology. This three-dimensional porous structure significantly increases the actual contact area between the conductive structure and the molding compound 205, creating a tight mechanical bond at the interface of the two dissimilar materials. After the molding compound 205 completely covers the roughened sidewalls of the conductive structure, the molding material embeds into the interior of the micro-pit structure, generating a significant anchoring effect and effectively suppressing interface delamination. When the packaged structure experiences temperature changes or is subjected to external mechanical loads, the increased interfacial adhesion can evenly distribute stress, preventing excessive stress concentration at the interface between the conductive structure and the molding compound 205, thereby preventing the generation and propagation of cracks. This structural design achieves interface strengthening through surface morphology optimization without increasing the size of the conductive structure, thus significantly improving the long-term reliability and failure resistance of the packaged structure.

[0093] In this embodiment, the method for forming the molding compound 205 includes: after the roughening treatment, forming a molding compound material layer (not shown) on the substrate 200, the molding compound material layer covering the conductive structure; performing a planarization treatment on the molding compound material layer until the end face of the conductive structure is exposed, thereby forming the molding compound 205; after forming the molding compound 205, removing the substrate 200 and the seed material layer 201, the molding compound 205 exposing the end face of the conductive structure on the opposite side.

[0094] In this embodiment, the molding layer 205 is made of epoxy resin. Epoxy resin has good insulation, adhesion and process compatibility, and after grinding, it can achieve high coplanarity with the surface of the conductive structure.

[0095] In this embodiment, the substrate 200 can be removed using a debonding process, that is, by separating the temporarily bonded substrate 200 through thermal, optical, or mechanical means. The seed material layer 201 can be removed using an etching process or a chemical mechanical polishing process.

[0096] In other embodiments, the method for forming the conductive structure and the molding compound layer may further include: providing a substrate; forming a seed material layer on the substrate; forming the conductive structure on the seed material layer; etching the seed material layer using the conductive structure as a mask until the substrate is exposed, thereby forming a seed layer; after forming the seed layer, performing the roughening treatment on the surface of the conductive structure to give the surface of the conductive structure a micropit structure; after the roughening treatment, forming a molding compound layer on the substrate, the molding compound layer covering the seed layer and the conductive structure; performing a planarization treatment on the molding compound layer until the end face of the conductive structure is exposed, thereby forming the molding compound layer; and after forming the molding compound layer, removing the substrate.

[0097] Accordingly, this invention also provides an electrical interconnection structure, please refer to the following embodiments. Figure 16 It includes: a plurality of conductive structures, the surface of which has a roughened micro-pit structure; and a molding layer 205, which covers the sidewalls of the conductive structures.

[0098] After the roughening treatment, the sidewalls of the conductive structure form a micro-pit morphology. This three-dimensional porous structure significantly increases the actual contact area between the conductive structure and the molding compound 205, creating a tight mechanical bond at the interface of the two dissimilar materials. After the molding compound 205 completely covers the roughened sidewalls of the conductive structure, the molding material embeds into the interior of the micro-pit structure, generating a significant anchoring effect and effectively suppressing interface delamination. When the packaged structure experiences temperature changes or is subjected to external mechanical loads, the increased interfacial adhesion can evenly distribute stress, preventing excessive stress concentration at the interface between the conductive structure and the molding compound 205, thereby preventing the generation and propagation of cracks. This structural design achieves interface strengthening through surface morphology optimization without increasing the size of the conductive structure, thus significantly improving the long-term reliability and failure resistance of the packaged structure.

[0099] In this embodiment, the conductive structure includes: a plurality of sub-conductive parts 204 stacked sequentially, wherein any two adjacent sub-conductive parts 204 are in contact with each other, and the projection areas of any two adjacent sub-conductive parts 204 toward the stacking direction have an overlapping area.

[0100] By decomposing the conductive structure into multiple sequentially stacked sub-conductive portions 204, the process bottleneck of limited photoresist thickness in a single coating is overcome, allowing for a significant increase in the height of the final conductive structure. Any two adjacent sub-conductive portions 204 are in contact with each other, and the projected areas of any two adjacent sub-conductive portions 204 facing the stacking direction overlap, thereby ensuring electrical connectivity and structural stability between the interconnected sub-conductive portions 204. The resulting conductive structure meets the design requirements of large-scale integrated circuits and very large-scale integrated circuits.

[0101] In this embodiment, along the stacking direction, in any two adjacent sub-conductive portions 204, the projection area of ​​the upper sub-conductive portion 204 facing the stacking direction is located within the projection area of ​​the lower sub-conductive portion 204 facing the stacking direction. By designing the upper sub-conductive portion 204 to be recessed within the projection area of ​​the lower sub-conductive portion 204, or vice versa, the stringent requirements for lithographic alignment accuracy are effectively reduced, thereby relaxing the control window for overlay accuracy and significantly improving the tolerance for alignment errors during multilayer stacking.

[0102] Along the stacking direction, the height of the sub-conductive part 204 ranges from 100 micrometers to 140 micrometers; the number of layers of the sub-conductive part 204 in the conductive structure ranges from 2 to 6 layers.

[0103] In this embodiment, the sub-conductive part 204 is made of copper.

[0104] In this embodiment, the height of the conductive structure along the stacking direction is greater than 380 micrometers.

[0105] In this embodiment, the projected area of ​​the sub-conductive portion 204 facing the stacking direction is circular, and the diameter difference between the circular projections of any two adjacent sub-conductive portions 204 is in the range of 10 micrometers to 15 micrometers. This range of 10 to 15 micrometers ensures sufficient alignment tolerance, reduces the stringent requirements for photolithography overlay accuracy, and decreases process complexity. It also avoids excessive diameter variations in the sub-conductive portions 204 during layer-by-layer stacking, preventing the top-layer sub-conductive portion 204 from being too small, which could lead to a surge in contact resistance or connection failure. Simultaneously, it prevents the top-layer sub-conductive portion 204 from being too large, encroaching on surrounding wiring space, effectively suppressing the risk of interlayer short circuits and ensuring wiring density.

[0106] In other embodiments, the shape of the projection area of ​​the sub-conductive part facing the stacking direction may also include: a rectangle or a polygon, specifically a regular pentagon or a regular hexagon.

[0107] In this embodiment, the sub-conductive parts 204 are coaxially stacked along the stacking direction. By arranging the sub-conductive parts 204 coaxially along the stacking direction, the geometric centers of the multi-layer structure are completely coincident, ensuring uniform force transmission in each layer, avoiding lateral stress concentration and structural tilting risks caused by eccentric stacking, and significantly improving the overall mechanical stability and deformation resistance of the stack.

[0108] In this embodiment, the molding layer 205 exposes the end faces of opposite sides of the conductive structure.

[0109] In other embodiments, the method further includes: a seed layer located on one end face of the conductive structure; the encapsulation layer also covers the sidewall of the seed layer and exposes the end face of the conductive structure on the opposite side (not shown).

[0110] Figure 17 This is a schematic diagram of the electrical interconnect structure according to another embodiment of the present invention.

[0111] This embodiment is based on the above embodiment ( Figure 16 Based on the above embodiments, the electrical interconnection structure will continue to be described. The rest is the same as the above embodiments, except that the structural form of the conductive structure is different. The following will be described in detail with reference to the accompanying drawings.

[0112] Please refer to Figure 17 Along the stacking direction, in any two adjacent sub-conductive parts 204, the projection area of ​​the lower sub-conductive part 204 toward the stacking direction is located within the projection area of ​​the upper sub-conductive part 204 toward the stacking direction.

[0113] By incorporating the lower sub-conductive portion 204 within the projection range of the upper sub-conductive portion 204, the stringent requirements for photolithography alignment accuracy are effectively reduced, thereby relaxing the control window for overlay accuracy and significantly improving the tolerance for alignment errors during multilayer stacking.

[0114] In this embodiment, the projected area of ​​the sub-conductive portion 204 facing the stacking direction is circular, and the diameter difference between the circular projections of any two adjacent sub-conductive portions 204 is in the range of 10 micrometers to 15 micrometers. This range of 10 to 15 micrometers ensures sufficient alignment tolerance, reduces the stringent requirements for photolithography overlay accuracy, and decreases process complexity. It also avoids excessive diameter variations in the sub-conductive portions 204 during layer-by-layer stacking, preventing the top-layer sub-conductive portion 204 from being too small, which could lead to a surge in contact resistance or connection failure. Simultaneously, it prevents the top-layer sub-conductive portion 204 from being too large, encroaching on surrounding wiring space, effectively suppressing the risk of interlayer short circuits and ensuring wiring density.

[0115] Figure 18This is a schematic diagram of the panel-level packaging structure according to an embodiment of the present invention.

[0116] Please refer to Figure 18 The present invention also provides a panel-level packaging structure, comprising: an electrical interconnection structure as described in any of the above embodiments, the electrical interconnection structure comprising a first side and a second side opposite to each other; a first redistribution layer 300 located on the first side, the first redistribution layer 300 being electrically connected to one end of the conductive structure; and a second redistribution layer 301 located on the second side, the second redistribution layer 301 being electrically connected to the other end opposite to the conductive structure.

[0117] In this embodiment, the panel-level packaging structure integrates the aforementioned electrical interconnect structure to form a through-type vertical conductive channel. The electrical interconnect structure has a first side and a second side facing each other. The first side has a first rewiring layer 300 disposed thereon and electrically connected to one end of the conductive structure. The second side has a second rewiring layer 301 disposed thereon and electrically connected to the other end of the conductive structure. This double-sided rewiring design achieves electrical interconnection between the upper and lower surfaces of the packaging structure. The conductive structure, acting as a high-density interconnect bridge, effectively shortens the signal transmission path, improves packaging integration and electrical performance, and meets the stringent requirements of the panel-level packaging for high bandwidth and low loss.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrical interconnection structure, characterized in that, include: Several conductive structures, wherein the surface of the conductive structures has a roughened micro-pit structure; The conductive structure serves as a through-type vertical conductive channel to shorten the signal transmission path; A molding compound that covers the sidewalls of the conductive structure.

2. The electrical interconnection structure as described in claim 1, characterized in that, The conductive structure is a monomeric structure.

3. The electrical interconnection structure as described in claim 1, characterized in that, The conductive structure includes: a plurality of sub-conductive parts stacked sequentially, wherein any two adjacent sub-conductive parts are in contact with each other, and the projection areas of any two adjacent sub-conductive parts toward the stacking direction have an overlapping area.

4. The electrical interconnection structure as described in claim 3, characterized in that, Along the stacking direction, in any two adjacent sub-conductive parts, the projection area of ​​the upper sub-conductive part toward the stacking direction is located within the projection area of ​​the lower sub-conductive part toward the stacking direction; or, along the stacking direction, in any two adjacent sub-conductive parts, the projection area of ​​the lower sub-conductive part toward the stacking direction is located within the projection area of ​​the upper sub-conductive part toward the stacking direction.

5. The electrical interconnection structure as described in claim 3, characterized in that, Along the stacking direction, each of the sub-conductive parts is coaxially stacked.

6. The electrical interconnection structure as described in claim 1, characterized in that, The molding layer exposes the end faces of the conductive structure on opposite sides.

7. The electrical interconnection structure as described in claim 1, characterized in that, Also includes: A seed layer is located on one end face of the conductive structure; the encapsulation layer also covers the sidewall of the seed layer and exposes the end face of the conductive structure on the opposite side.

8. A method for forming an electrical interconnect structure, characterized in that, include: Several conductive structures are formed, and the surface of the conductive structures has a roughened micro-pit structure; The conductive structure serves as a through-type vertical conductive channel to shorten the signal transmission path; A molding layer is formed, which covers the sidewalls of the conductive structure.

9. The method for forming the electrical interconnect structure as described in claim 8, characterized in that, The method for forming the conductive structure and the molding compound includes: providing a substrate; forming a seed material layer on the substrate; forming the conductive structure on the seed material layer; etching the seed material layer using the conductive structure as a mask until the substrate is exposed, thereby forming a seed layer; after forming the seed layer, performing the roughening treatment on the surface of the conductive structure to give the surface of the conductive structure a micropit structure; after the roughening treatment, forming a molding compound layer on the substrate, the molding compound layer covering the seed layer and the conductive structure; and performing a planarization treatment on the molding compound layer until the end face of the conductive structure is exposed, thereby forming the molding compound layer.

10. The method for forming the electrical interconnect structure as described in claim 8, characterized in that, The method for forming the conductive structure and the molding compound includes: providing a substrate; forming a seed material layer on the substrate; forming the conductive structure on the seed material layer; performing the roughening treatment on the surface of the conductive structure to give the surface of the conductive structure a micropit structure; after the roughening treatment, forming a molding compound layer on the substrate, the molding compound layer covering the conductive structure; performing a planarization treatment on the molding compound layer until the end face of the conductive structure is exposed, thereby forming the molding compound layer; after forming the molding compound layer, removing the substrate and the seed material layer, the molding compound layer exposing the end face of the conductive structure on the opposite side.

11. The method for forming the electrical interconnect structure as described in claim 9 or 10, characterized in that, The conductive structure is a monomeric structure.

12. The method for forming an electrical interconnect structure as described in claim 11, characterized in that, The method for forming the conductive structure on the seed material layer includes: forming a photoresist layer on the seed material layer; exposing and developing the photoresist layer to form a via, the via exposing the seed material layer; forming the conductive structure in the via using an electroplating process; and removing the photoresist layer after forming the conductive structure.

13. The method for forming the electrical interconnect structure as described in claim 9 or 10, characterized in that, The conductive structure includes: a plurality of sub-conductive parts stacked sequentially, wherein any two adjacent sub-conductive parts are in contact with each other, and the projection areas of any two adjacent sub-conductive parts toward the stacking direction have an overlapping area.

14. The method for forming the electrical interconnect structure as described in claim 13, characterized in that, The method for forming the conductive structure on the seed material layer includes: forming each of the sequentially stacked sub-conductive portions by employing a number of photolithography electroplating processes; wherein each photolithography electroplating process forms one layer of the sub-conductive portions.

15. The method for forming the electrical interconnect structure as described in claim 14, characterized in that, The first photolithography electroplating process includes: forming a first photoresist layer on the seed material layer; exposing and developing the first photoresist layer to form a first via, the first via exposing the seed material layer; forming a sub-conductive portion located at the bottom layer in the first via using an electroplating process; and removing the first photoresist layer after forming the sub-conductive portion located at the bottom layer.

16. The method for forming the electrical interconnect structure as described in claim 15, characterized in that, Each subsequent photolithography electroplating process includes: forming a second photoresist layer on the substrate, the second photoresist layer covering the already formed sub-conductive portion; exposing and developing the second photoresist layer to form a second via, the second via exposing the already formed sub-conductive portion located on the upper layer; forming the sub-conductive portion within the second via using an electroplating process; and removing the second photoresist layer after forming the sub-conductive portion.

17. The method for forming an electrical interconnect structure as described in claim 13, characterized in that, Along the stacking direction, in any two adjacent sub-conductive parts, the projection area of ​​the upper sub-conductive part toward the stacking direction is located within the projection area of ​​the lower sub-conductive part toward the stacking direction; or, along the stacking direction, in any two adjacent sub-conductive parts, the projection area of ​​the lower sub-conductive part toward the stacking direction is located within the projection area of ​​the upper sub-conductive part toward the stacking direction.

18. The method for forming an electrical interconnect structure as described in claim 8, characterized in that, The mixture in the roughening process includes: hydroxyethylidene diphosphonic acid, sodium hydroxide, hydrogen peroxide, benzotriazole, and sulfuric acid.

19. A panel-level packaging structure, characterized in that, include: The electrical interconnect structure according to any one of claims 1 to 7, wherein the electrical interconnect structure includes opposing first and second sides; A first rewiring layer is located on the first side, and the first rewiring layer is electrically connected to one end of the conductive structure; A second wiring layer is located on the second side, and the second wiring layer is electrically connected to the other end opposite the conductive structure.

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