Electro-optic modulator and method of manufacturing the same
By using a blocking pattern as a mask during the ion implantation process of a silicon photonic modulator, a stable lateral PN junction structure is formed, which solves the performance inconsistency problem caused by PN junction distance deviation and improves device performance and production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT RESEARCH & DEVELOPMENT CENTER CO LTD
- Filing Date
- 2024-12-24
- Publication Date
- 2026-06-26
AI Technical Summary
In silicon photonic modulators, the distance deviation between PN junctions leads to performance inconsistencies, affecting the performance of the modulator and the performance consistency on the wafer.
By setting a blocking pattern as a mask during ion implantation and removing the blocking pattern in subsequent implantation, two ion implantation regions with controllable spacing are formed, which precisely controls the morphology of the PN junction and forms a stable lateral PN junction structure.
It improves device performance and wafer performance consistency, optimizes process flow, and increases production efficiency.
Smart Images
Figure CN122284149A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon photonics technology, and in particular to an electro-optic modulator and its manufacturing method. Background Technology
[0002] Silicon-based optoelectronics, utilizing the CMOS process platform and employing SOI substrates, achieves photoelectric signal conversion and processing within a single chip. It boasts excellent performance characteristics such as high bandwidth, low power consumption, interference resistance, and high reliability, and is currently widely used in data centers, quantum computing, lidar, biosensing, and many other fields, showing broad development prospects. Silicon photonic devices typically consist of passive and active components; passive components process optical signals, while active components convert photoelectric signals.
[0003] In silicon photonics platforms, the most commonly used electro-optic modulator structure in the industry is the Mach-Zehnder modulator (MZM modulator) that uses the plasma dispersion effect. This involves forming a PN junction in silicon using ion implantation and controlling the carrier concentration in the depletion region of the PN junction by applying voltage across the PN junction. This, in turn, controls the refractive index of silicon in the depletion region. Different refractive indices can be obtained under different voltage controls, thereby achieving the conversion of electrical signals to optical signals. The morphology and performance parameters of the PN junction capacitance have a very important impact on the performance of the modulator.
[0004] As mentioned above, in the fabrication process of traditional MZM modulators, P-type ion implantation and N-type ion implantation are accomplished through photolithography and ion implantation processes, respectively. Figure 1 As shown, the spacing between PN junctions is affected by factors such as overlay precision and changes in the CD value of photolithography, leading to inconsistent PN junction characteristics in different regions of the wafer. Typically, under the combined influence of overlay precision and CD value, the distance deviation between PN junctions is generally greater than 50 nm. The distance between PN junctions significantly affects parameters such as PN junction capacitance and carrier concentration, thus greatly impacting modulator performance.
[0005] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0006] The purpose of this invention is to provide an electro-optic modulator and its manufacturing method to solve the problem of distance deviation between PN junctions.
[0007] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing an electro-optic modulator, comprising:
[0008] A substrate is provided, on which a first device pattern is formed, and a protective layer flush with the top surface is formed on the first device pattern and the substrate, wherein the first device pattern has a first region for ion implantation and a second region for ion implantation;
[0009] A blocking pattern is formed on the protective layer outside the first region, at least covering the second region;
[0010] A first photoresist pattern is formed on the protective layer for ion implantation into the first region, forming a first ion implantation region;
[0011] Remove the first photoresist pattern, form a dielectric layer on the protective layer, and remove the dielectric layer on top of the blocking pattern;
[0012] A second photoresist pattern is formed on the dielectric layer, wherein the opening area of the second photoresist pattern is not smaller than that of the blocking pattern;
[0013] Remove the blocking pattern;
[0014] Ion implantation is performed on the second region to form a second ion implantation region.
[0015] Preferably, forming a dielectric layer on the protective layer and removing the dielectric layer at the top of the blocking pattern includes: forming a dielectric layer on the protective layer and the blocking pattern, wherein the thickness of the dielectric layer is greater than the thickness of the blocking pattern, and thinning the dielectric layer by a chemical mechanical polishing process until the top surface of the blocking pattern is exposed.
[0016] Preferably, the area exposed by the first photoresist pattern includes at least the area corresponding to the first device pattern.
[0017] Preferably, forming the first device pattern includes: forming a top silicon layer on the substrate, and forming the first device pattern by photolithography and etching.
[0018] Preferably, forming the blocking pattern includes: forming a mask layer on the protective layer, and forming the blocking pattern by photolithography and etching the mask layer, wherein the mask layer is made of polycrystalline silicon.
[0019] Preferably, the method further includes: forming a top silicon layer on the substrate, forming a second device pattern and a third device pattern by photolithography and etching, and forming a mask layer on the protective layer after forming the protective layer, forming a fourth device pattern and a fifth device pattern by photolithography and etching the mask layer, wherein the second device pattern and the fourth device pattern constitute a MOS transistor capacitor, and the third device pattern and the fifth device pattern are both gratings.
[0020] Preferably, forming a protective layer flush with the top surface on the first device pattern and the substrate includes: depositing a protective layer on the first device pattern and the substrate, the thickness of the protective layer being greater than the thickness of the first device pattern, and planarizing the protective layer using a CMP process, wherein the material of the protective layer is silicon oxide.
[0021] Preferably, after forming the second ion implantation region, the second photoresist pattern is removed, and the desired medium is deposited on the dielectric layer and the exposed protective layer.
[0022] Preferably, the dielectric layer is made of silicon oxide, the required dielectric is silicon oxide, and the dielectric layer and the required dielectric constitute a filler layer.
[0023] The present invention provides an electro-optic modulator, which is manufactured using the electro-optic modulator manufacturing method described above.
[0024] In the manufacturing method of the electro-optic modulator provided by the present invention, by setting a blocking pattern as an ion implantation mask and removing the blocking pattern in subsequent implantation and performing ion implantation again, two ion implantation regions with controllable spacing are formed, which can form a stable lateral PN junction structure, precisely control the morphology of the PN junction in the MZM modulator, thereby improving device performance and wafer-level performance consistency.
[0025] The electro-optic modulator provided by this invention and the manufacturing method of the electro-optic modulator provided by this invention belong to the same inventive concept. Therefore, the electro-optic modulator provided by this invention has at least all the advantages of the manufacturing method of the electro-optic modulator provided by this invention, which will not be repeated here. Attached Figure Description
[0026] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0027] Figure 1 This is a schematic diagram of the structure after ion implantation in the existing technology;
[0028] Figure 2 This is a schematic diagram of the substrate structure according to an embodiment of the present invention;
[0029] Figure 3 This is a schematic diagram of a mask layer structure according to an embodiment of the present invention;
[0030] Figure 4 This is a schematic diagram of a blocking pattern structure according to an embodiment of the present invention;
[0031] Figure 5 This is a schematic diagram of the structure for forming a first photoresist pattern according to an embodiment of the present invention;
[0032] Figure 6This is a schematic diagram of the structure of the dielectric layer formed according to an embodiment of the present invention;
[0033] Figure 7 This is a schematic diagram of the structure for forming a second photoresist pattern according to an embodiment of the present invention;
[0034] Figure 8 This is a schematic diagram of the structure for forming the second ion implantation region according to an embodiment of the present invention;
[0035] Figure 9 This is a schematic diagram of the structure forming the filling layer according to an embodiment of the present invention;
[0036] Figure 10 This is an execution flowchart of an embodiment of the present invention.
[0037] In the attached image:
[0038] 100. Substrate; 101. Top silicon layer; 101a. First device pattern; 101b. Second device pattern; 101c. Third device pattern; 102. Protective layer; 103. Mask layer; 103a. Blocking pattern; 103b. Fourth device pattern; 103c. Fifth device pattern; 104. First photoresist pattern; 105. First ion implantation region; 106. Dielectric layer; 107. Second photoresist pattern; 108. Second ion implantation region; 109. Filler layer. Detailed Implementation
[0039] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0040] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0041] The inventors discovered that when implementing the MZM electro-optic modulator, N-type ion implantation and P-type ion implantation need to be performed separately in the same area. Since the two ion implantation areas are close to each other, the parameters of the two photolithography steps are different when the area to be implanted is exposed in two separate photolithography steps. Under the influence of overlay accuracy and CD value, the spacing between the N-type ion implantation area and the P-type ion implantation area is difficult to guarantee, which affects the performance of the modulator.
[0042] Based on this, the core idea of this invention is that, unlike the traditional ion implantation mode, by setting a blocking pattern as an ion implantation mask and removing the blocking pattern in subsequent implantation, and then performing ion implantation again, two ion implantation regions with controllable spacing are formed, which can form a stable lateral PN junction structure, precisely control the morphology of the PN junction in the MZM modulator, thereby improving device performance and wafer-level performance consistency.
[0043] For details, please refer to Figures 2-10 This is a schematic diagram of an embodiment of the present invention. Figure 10 As shown, a method for manufacturing an electro-optic modulator includes the following steps:
[0044] S1, a substrate 100 is provided, on which a first device pattern 101a is formed. A protective layer 102 with its top surface flush with the first device pattern 101a and the substrate 100 is formed. The first device pattern 101a has a first region (not labeled) for ion implantation and a second region (not labeled) for ion implantation. The protective layer 102 is made of silicon oxide, and the substrate 100 is a BOX (buried oxide) on an SOI (silicon-on-insulator) substrate.
[0045] Specifically, forming the first device pattern 101a includes: forming a top silicon layer 101 on the substrate 100, and forming the first device pattern 101a by photolithography and etching. It also includes: forming the top silicon layer 101 on the substrate 100, forming a second device pattern 101b and a third device pattern 101c by photolithography and etching; and, after forming the protective layer 102, forming a mask layer 103 on the protective layer 102, and forming a fourth device pattern 103b and a fifth device pattern 103c by photolithography and etching the mask layer 103, wherein the second device pattern 101b and the fourth device pattern 103b constitute a MOS transistor capacitor, and the third device pattern 101c and the fifth device pattern 103c are both gratings.
[0046] In the process of forming the desired silicon-based active devices on an SOI substrate, such as Figure 2 As shown, a top silicon layer 101 is first formed on the substrate 100, and then photolithography, etching, cleaning, and CMP (chemical mechanical polishing) processes are performed on the top silicon layer 101 to form the desired device morphology on the substrate 100. The first device pattern 101a is used for subsequent ion implantation to form an MZM electro-optic modulator, the second device pattern 101b is used to form a MOS transistor capacitor, and the third device pattern 101c is a grating. The formation of a protective layer 102 with a flush top surface on the first device pattern 101a and the substrate 100 includes: depositing a protective layer 102 on the first device pattern 101a and the substrate 100, wherein the thickness of the protective layer 102 is greater than the thickness of the first device pattern 101a, and planarizing the protective layer 102 by CMP process. The material of the protective layer 102 is silicon oxide. The thickness of the protective layer 102 is greater than that of the top silicon layer 101. After the protective layer 102 is deposited, it can be planarized by CMP process.
[0047] In one embodiment, one side of the first region is connected to the second region. The first region and the second region are adjacent to each other and are used for N-type ion implantation and P-type ion implantation, respectively. Obviously, the distance between the first region and the second region can also be flexibly adjusted according to the actual needs of the device.
[0048] S2, a blocking pattern 103a is formed on the protective layer 102 outside the first region, at least covering the second region, the blocking pattern 103a being located on top of the second region. Forming the blocking pattern 103a on the protective layer 102 includes forming a mask layer 103 on the protective layer 102. Specifically, the mask layer 103 is made of polycrystalline silicon, such as... Figure 3 As shown, a blocking pattern 103a, a fourth device pattern 103b, and a fifth device pattern 103c are formed by photolithography and etching of the mask layer 103, as follows: Figure 4 As shown, the fourth device pattern 103b is used to form a MOS transistor capacitor, and the fifth device pattern 103c is a grating. The second device pattern 101b and the fourth device pattern 103b constitute the MOS transistor capacitor.
[0049] Understandable, such as Figure 4 As shown, a barrier pattern 103a is formed using a mask layer 103 through conventional patterning processes such as photolithography, etching, and cleaning. The barrier pattern 103a is not smaller than the second region and is used for ion implantation. Other desired device patterns, including but not limited to MOS transistors, capacitors, and gratings, can also be formed simultaneously in the region of the MZM electro-optic modulator. The morphology of the barrier pattern 103a corresponds to one of the regions requiring ion implantation, and subsequent ion implantation self-alignment processes are performed using the barrier pattern 103a.
[0050] S3, a first photoresist pattern 104 is formed on the protective layer 102 for ion implantation of the first region to form a first ion implantation region 105. The exposed area of the first photoresist pattern 104 includes at least the area corresponding to the first device pattern 101a.
[0051] like Figure 5 As shown, a photoresist layer is formed on the protective layer 102. A first photoresist pattern 104 is formed through processes such as coating, developing, and exposure. The first photoresist pattern 104 covers the areas of the fourth device pattern 103b and the fifth device pattern 103c, and has an opening to expose the first and second areas of the first device pattern 101a. At this time, the second area is blocked and protected by the blocking pattern 103a. Ion implantation is performed on the first area, for example, N-type ions are implanted to ensure that the second area is not affected by ion implantation.
[0052] The material of the photoresist layer is, for example, an adhesive photoresist film used in semiconductor chip packaging or printed circuit board manufacturing. It is usually a photosensitive polymer material, such as polyimide (PI), bis-benzocyclobutene (BCB), or poly(p-phenylene-2,6-BenzobisOxazole) (PBO).
[0053] S4, remove the first photoresist pattern 104, form a dielectric layer 106 on the protective layer 102, and remove the dielectric layer 106 on top of the blocking pattern 103a. Remove the first photoresist pattern 104 by a stripping process.
[0054] Specifically, forming a dielectric layer 106 on the protective layer 102 and removing the dielectric layer 106 at the top of the blocking pattern 103a includes: forming a dielectric layer 106 on the protective layer 102 and the blocking pattern 103a, wherein the thickness of the dielectric layer 106 is greater than the thickness of the blocking pattern 103a, and thinning the dielectric layer 106 by a chemical mechanical polishing process until the top surface of the blocking pattern 103a is exposed, wherein the dielectric layer 106 is made of silicon oxide.
[0055] like Figure 6 As shown, a dielectric layer 106 is used to fill the depression between the blocking pattern 103a, the fourth device pattern 103b, and the fifth device pattern 103c. The uneven surface of the dielectric layer 106 after filling is then subjected to chemical mechanical polishing (CMP) to bring it to rest on the blocking pattern 103a, exposing the top surfaces of the blocking pattern 103a, the fourth device pattern 103b, and the fifth device pattern 103c. The dielectric layer 106 is typically SiO2 to meet the performance requirements of silicon photonic devices. The dielectric layer 106 can be deposited using conventional methods such as CVD, HDP, and HARP.
[0056] S5, a second photoresist pattern 107 is formed on the dielectric layer 106, and the opening area of the second photoresist pattern 107 is not smaller than the blocking pattern 103a. The opening of the second photoresist pattern 107 may be slightly larger than the blocking pattern 103a to expose the blocking pattern 103a, so as to facilitate the quick removal of the blocking pattern 103a.
[0057] S6, remove the blocking pattern 103a.
[0058] like Figure 7As shown, the subsequent ion implantation process continues, forming a photoresist layer on the dielectric layer 106. After photolithography, exposure, etching, and cleaning processes, a second photoresist pattern 107 is formed. The fourth device pattern 103b and the fifth device pattern 103c are both protected by the second photoresist pattern 107, exposing the blocking pattern 103a. A high-selectivity etching process is used to remove the polysilicon blocking pattern 103a in this area, and the image is then placed on the underlying protective layer 102. The high-selectivity etching process can employ a wet process, such as using TMAH solution to remove the blocking pattern 103a, to achieve a high selectivity for both the polysilicon layer and the SiO2 layer. Alternatively, a high-selectivity dry etching process can be used.
[0059] S7, and ion implantation is performed on the second region to form a second ion implantation region 108, such as Figure 8 As shown, after forming the second ion implantation region 108, the second photoresist pattern 107 is removed, and the desired dielectric is deposited on the dielectric layer 106 and the exposed protective layer 102. The dielectric layer 106 is made of silicon oxide, and the desired dielectric is also made of silicon oxide. The dielectric layer 106 and the desired dielectric constitute a filler layer 109. The second photoresist pattern 107 is removed by a photoresist stripping process.
[0060] The second ion implantation process continues, for example, implanting P-type ions. During this process, other device regions are protected by photoresist. Within the MZM electro-optic modulator region, except for the area after removing the blocking pattern 103a, other areas are protected by the dielectric layer 106, ultimately forming the second ion implantation region 108, as shown below. Figure 8 As shown, since the first ion implantation uses the blocking pattern 103a as a hard mask, the second ion implantation only occurs in the area where the blocking pattern 103a is removed. This creates self-alignment between the two implantations, and the relative positions of the two implantations are only affected by the lateral etching amount of the dielectric layer 106 during the removal of the blocking pattern 103a. A high-selectivity removal process can be used, the lateral removal amount of the dielectric layer 106 is very small and easily controlled, ensuring the spacing between the first ion implantation region 105 and the second ion implantation region 108.
[0061] like Figure 9 As shown, dielectric layer 106 is also made of silicon oxide. Silicon oxide is then used to fill the uneven area on top of protective layer 102, and planarization is performed accordingly. The newly deposited silicon oxide and dielectric layer 106 together form filling layer 109. The filling method can employ conventional CMOS dielectric layer filling processes such as CVD, HDP, and HARP, while the planarization process can employ CMP. Subsequent conventional silicon photonics processes can be performed, such as germanium processes, contact hole processes, and back-end metallization processes.
[0062] Based on the same technical concept, this disclosure also provides an electro-optic modulator, which is manufactured using the electro-optic modulator manufacturing method described above.
[0063] In the electro-optic modulator and its manufacturing method provided by this invention, by setting a blocking pattern as a mask for one ion implantation, and removing the blocking pattern in subsequent implantations, followed by ion implantation again, two ion implantation regions with controllable spacing are formed. This allows for the formation of a stable lateral PN junction structure, precisely controlling the morphology of the PN junction in the MZM modulator, thereby improving device performance and wafer-level performance consistency. Using a polysilicon layer for conventional patterning processes such as photolithography, etching, and cleaning, other required device patterns can also be formed simultaneously in the region of the MZM electro-optic modulator while forming the blocking pattern. The formation of the blocking pattern can integrate other device processes, optimize the process flow, and improve production efficiency while ensuring product performance.
[0064] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method of manufacturing an electro-optic modulator, characterized by, include: A substrate is provided, on which a first device pattern is formed, and a protective layer flush with the top surface is formed on the first device pattern and the substrate, wherein the first device pattern has a first region for ion implantation and a second region for ion implantation; A blocking pattern is formed on the protective layer outside the first region, at least covering the second region; A first photoresist pattern is formed on the protective layer for ion implantation into the first region, forming a first ion implantation region; Remove the first photoresist pattern, form a dielectric layer on the protective layer, and remove the dielectric layer on top of the blocking pattern; A second photoresist pattern is formed on the dielectric layer, wherein the opening area of the second photoresist pattern is not smaller than that of the blocking pattern; Remove the blocking pattern; Ion implantation is performed on the second region to form a second ion implantation region.
2. The method of manufacturing an electro-optic modulator according to claim 1, wherein Forming a dielectric layer on the protective layer and removing the dielectric layer at the top of the blocking pattern includes: forming a dielectric layer on the protective layer and the blocking pattern, wherein the thickness of the dielectric layer is greater than the thickness of the blocking pattern, and thinning the dielectric layer by a chemical mechanical polishing process until the top surface of the blocking pattern is exposed.
3. The method of manufacturing an electro-optic modulator according to claim 1, wherein The area exposed by the first photoresist pattern includes at least the area corresponding to the first device pattern.
4. The method of manufacturing an electro-optic modulator of claim 1, wherein, Forming the first device pattern includes: forming a top silicon layer on the substrate, and forming the first device pattern by photolithography and etching.
5. The method of fabricating an electro-optic modulator of claim 1, wherein, Forming the blocking pattern includes: forming a mask layer on the protective layer, and forming the blocking pattern by photolithography and etching the mask layer, wherein the mask layer is made of polycrystalline silicon.
6. The method of manufacturing an electro-optic modulator of claim 1, wherein, Also includes: A top silicon layer is formed on the substrate, and a second device pattern and a third device pattern are formed by photolithography and etching. After the protective layer is formed, a mask layer is formed on the protective layer, and a fourth device pattern and a fifth device pattern are formed by photolithography and etching of the mask layer. The second device pattern and the fourth device pattern constitute a MOS transistor capacitor, and the third device pattern and the fifth device pattern are both gratings.
7. The method of fabricating an electro-optic modulator of claim 1, wherein, Forming a protective layer flush with the top surface on the first device pattern and the substrate includes: depositing a protective layer on the first device pattern and the substrate, wherein the thickness of the protective layer is greater than the thickness of the first device pattern, and planarizing the protective layer by a CMP process, wherein the material of the protective layer is silicon oxide.
8. The method of fabricating an electro-optic modulator of claim 1, wherein, After the second ion implantation region is formed, the second photoresist pattern is removed, and the desired dielectric is deposited on the dielectric layer and the exposed protective layer.
9. The method of manufacturing an electro-optic modulator according to claim 8, wherein, The dielectric layer is made of silicon oxide, the required medium is silicon oxide, and the dielectric layer and the required medium constitute a filling layer.
10. An electro-optic modulator, characterized by It is manufactured using the manufacturing method of the electro-optic modulator as described in any one of claims 1-9.