A method and apparatus for verifying a digital circuit, an electronic device, and a medium
By parsing the hardware description language code and performing time delay compensation to generate a second clock signal, and combining it with simulation waveforms for digital circuit verification, the problem of complex verification environment setup in existing technologies is solved, and efficient and reliable circuit verification is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-26
AI Technical Summary
In the process of digital circuit design verification, existing technologies are difficult to simplify the construction of the verification environment, especially for complex circuits under test such as serial interfaces and sequential logic circuits. The monitoring equipment is difficult to set up, and the scoring board comparison is complicated, resulting in low verification efficiency and unreliable results.
By parsing the hardware description language code, the control and clock signals are determined, and a second clock signal is generated through time delay compensation. The simulation waveform is then used for verification, simplifying the verification environment and avoiding the need to build a monitor and scoreboard. The simulation waveform is extracted using EDA tools for verification.
It simplifies the process of setting up the verification environment, improves verification efficiency and accuracy, reduces verification difficulty, and ensures the reliability of verification results.
Smart Images
Figure CN122287490A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, electronic device and medium for verifying digital circuits. Background Technology
[0002] In the digital circuit design verification process, Hardware Description Language (HDL) is typically used for circuit development, and Electronic Design Automation (EDA) tools are used for simulation testing to verify whether the circuit functionality meets design requirements. Currently, before verifying a digital circuit, a verification environment for the circuit under test (DUT) needs to be set up. For example, a monitor is set up to listen to the output signals of the DUT in real time, and a scoring board is set up to compare the monitored signal values with the expected signal values. However, for complex DUTs such as serial interfaces and sequential logic circuits, the monitor needs to identify communication timing, filter signal glitches, and handle reset interrupts, making its setup very difficult. The scoring board, which needs to classify and compare various signal values, further increases the cost of building the verification environment. Therefore, simplifying the digital circuit verification environment and improving verification efficiency is a current focus. Summary of the Invention
[0003] This application provides a method, apparatus, electronic device, and medium for verifying digital circuits, thereby simplifying the setup environment for digital circuit verification and improving verification efficiency.
[0004] This application provides a method for verifying digital circuits, including: Obtain the hardware description language code of the circuit under test; Based on hardware description language code, the first control signal in the circuit under test, as well as the first clock signal and data signal corresponding to the first control signal, are determined. According to the preset processing rules, the first clock signal is processed to obtain the second clock signal. The second clock signal is used to correct the transmission delay of the first control signal in the circuit under test in order to determine the sampling time of the data signal. Acquire the first simulation waveform of the first control signal during the simulation process of the circuit under test, the second simulation waveform of the first clock signal during the simulation process, the third simulation waveform of the second clock signal during the simulation process, and the fourth simulation waveform of the data signal during the simulation process. The circuit under test is verified based on the first, second, third, and fourth simulated waveforms, and the verification results are obtained.
[0005] This application also provides a verification device for digital circuits, comprising: The first acquisition module is used to acquire the hardware description language code of the circuit under test; The determination module is used to determine the first control signal in the circuit under test, as well as the first clock signal and data signal corresponding to the first control signal, based on hardware description language code. The processing module is used to process the first clock signal according to the preset processing rules to obtain the second clock signal. The second clock signal is used to correct the transmission delay of the first control signal in the circuit under test in order to determine the sampling time of the data signal. The second acquisition module is used to acquire the first simulation waveform of the first control signal in the simulation process of the circuit under test, the second simulation waveform of the first clock signal in the simulation process, the third simulation waveform of the second clock signal in the simulation process, and the fourth simulation waveform of the data signal in the simulation process. The verification module is used to verify the circuit under test based on the first, second, third, and fourth simulation waveforms and obtain the verification results.
[0006] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the verification method for any of the digital circuits described above.
[0007] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the verification method for any of the above-described digital circuits.
[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the verification method for any of the above-described digital circuits.
[0009] This application accurately locates the first control signal and its corresponding first clock signal and data signal by parsing the hardware description language code. Furthermore, the first clock signal undergoes delay compensation processing to obtain a second clock signal. This second clock signal is used to offset the transmission delay of the first control signal during transmission in the circuit under test (DUT) to determine the data signal acquisition time. Finally, the simulation waveforms of each signal throughout the simulation process are combined to complete the verification of the DUT. Therefore, it is evident that during the simulation process, there is no need to build a complex monitor in the verification environment to detect the signal values in real time, nor is there a need to build a scoring board to compare signal values. In the verification environment, only an excitation signal needs to be input to the DUT, and the simulation waveforms of each signal can be obtained using waveform extraction functions such as those in EDA tools. This simplifies the setup process of the verification environment, reduces the verification difficulty of digital circuits, and improves verification efficiency. Simultaneously, by accurately determining the data signal acquisition time through the second clock signal and correcting the transmission deviation of the first control signal, the verification process becomes more accurate and reliable. Attached Figure Description
[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 A flowchart illustrating a digital circuit verification method provided in an embodiment of this application; Figure 2 A schematic diagram illustrating a scenario of erroneous data collection due to transmission delay provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the optimized correct data acquisition scenario provided in the embodiments of this application; Figure 4 This is a schematic diagram illustrating an application scenario of a verification platform provided in an embodiment of this application; Figure 5 A schematic diagram of the structure of a digital circuit verification device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0013] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0014] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0015] First, the application scenarios of the embodiments of this application will be introduced by way of example.
[0016] In the field of digital circuit design, hardware description languages (HDLs) are often used to write hardware code to implement circuit functions. Electronic design automation (EDA) tools are then used for simulation verification to ensure the circuit meets design requirements. Before verifying the circuit under test (DUT), a verification environment must first be set up. This environment typically consists of three main components: drivers, monitors, and a scoring board. Drivers are used to input various excitation signals to the DUT to simulate actual circuit operation. Monitors are used to listen to the output interface signals of the DUT in real time, capturing signal changes and recording relevant data. The scoring board compares the signal values collected by the monitor with the expected signal values to ultimately determine whether the DUT's functionality meets design requirements.
[0017] For special scenarios such as serial interface circuits and highly complex sequential logic circuits, the setup of the monitor is quite challenging. It not only requires accurate identification of the communication start timing and synchronous recording of bus transmission information, but also functions such as signal glitches filtering and reset / interrupt handling. When a bus error occurs or the circuit is reset midway, the monitor must immediately clear invalid records and re-enter signal identification mode. In some complex scenarios, behavioral-level replication of the circuit under test is also necessary, which increases the construction cycle and technical threshold of the verification environment. Meanwhile, the scoring board needs to classify and identify the communication type based on signal content and then match and compare it with benchmark data in the database, further increasing the complexity of setting up the verification environment and reducing verification efficiency.
[0018] For large-scale integrated circuits, simulation processes are often time-consuming, and opportunities for debugging the verification environment are limited, leading to insufficient debugging of the verification environment and consequently reducing the reliability of the verification results. Furthermore, while existing EDA tools possess basic waveform signal extraction capabilities, can capture signal value changes and annotate the timing of those changes, and support simple combinational logic operations, they have significant limitations in sequential logic processing. Specifically, they cannot perform sequential logic operations or accurately determine the optimal sampling time for data signals. Therefore, they are difficult to replace monitors for effective verification of timing-sensitive circuits.
[0019] In view of this, embodiments of this application provide a method for verifying digital circuits, which simplifies the construction of verification scenarios and improves verification efficiency.
[0020] It should be noted that the digital circuit verification method provided in this embodiment of the invention can be executed by a digital circuit verification device. This device can be implemented as part or all of an electronic device through software, hardware, or a combination of both. The electronic device can be a server or a terminal. In this embodiment, the server can be a single server or a server cluster composed of multiple servers. The terminal can be a smartphone, personal computer, tablet computer, wearable device, or other intelligent hardware device such as a smart robot. The following method embodiments will use an electronic device as an example for explanation.
[0021] According to an embodiment of the present invention, a verification method for digital circuits is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
[0022] This embodiment provides a method for verifying digital circuits, which can be used in the aforementioned electronic devices, such as servers. Figure 1 This is a flowchart of a digital circuit verification method provided by an embodiment of the present invention, such as... Figure 1 As shown, the process includes: S101, obtain the hardware description language code of the circuit under test.
[0023] Specifically, the circuit under test is a digital circuit whose functionality and timing correctness need to be verified, including but not limited to Universal Asynchronous Receiver / Transmitter (UART) serial interface circuits and Serial Peripheral Interface (SPI) communication circuits. The hardware description language (HDL) code of the circuit under test describes its port definitions, logic structure, timing relationships, and functional implementation. For example, the HDL code can be used.
[0024] S102, based on hardware description language code, determines the first control signal in the circuit under test, as well as the first clock signal and data signal corresponding to the first control signal.
[0025] Specifically, the first control signal refers to the signal in the circuit under test that controls data transmission and the circuit's operating state, determining the start of data transmission, enabling, etc. Examples include the transmit enable signal for UART and the chip select signal for SPI.
[0026] The first clock signal is a clock signal that provides a timing reference for the effective triggering of the first control signal and the synchronous transmission of digital signals. For example, if the first control signal is the transmit enable signal tx_en of the UART module, the corresponding first clock signal can be 16 times the baud rate.
[0027] Data signals refer to the valid information signals transmitted in the circuit under test, such as UART serial data signals.
[0028] S103, process the first clock signal according to the preset processing rules to obtain the second clock signal.
[0029] The second clock signal is used to correct the transmission delay of the first control signal in the circuit under test, so as to determine the sampling time of the data signal.
[0030] Specifically, the transmission delay of the first control signal in the circuit under test refers to the time delay caused by the transmission of the first control signal through the internal wiring and logic units of the circuit under test. This transmission delay can lead to asynchrony between the first control signal and the digital signal; therefore, the first clock signal needs to be processed. Preset processing rules include, but are not limited to, duration compensation, phase adjustment, and edge shaping of the first clock signal, thereby correcting the transmission deviation of the first control signal to accurately determine the sampling time of the data signal.
[0031] S104, acquire the first simulation waveform of the first control signal in the simulation process of the circuit under test, the second simulation waveform of the first clock signal in the simulation process, the third simulation waveform of the second clock signal in the simulation process, and the fourth simulation waveform of the data signal in the simulation process.
[0032] Specifically, the circuit under test is simulated to obtain the simulation waveforms mentioned above. It is understandable that for the verification scenario of the circuit under test, only the aforementioned drivers need to input various excitation signals to the circuit under test; there is no need to build the aforementioned monitor and scoring board, thus simplifying the verification environment.
[0033] For example, the above simulation waveforms can be obtained using EDA tools.
[0034] S105 verifies the circuit under test based on the first, second, third, and fourth simulated waveforms, and obtains the verification results.
[0035] Specifically, the acquisition time of the digital signal is determined by the first, second, and third simulated waveforms. Based on the fourth simulated waveform, the signal value of the digital signal at the acquisition time is determined, and the signal value is compared with the preset signal value to complete the verification of the circuit under test.
[0036] In this embodiment, the first control signal and its corresponding first clock signal and data signal are accurately located by parsing the hardware description language code. Furthermore, the first clock signal is processed with time delay compensation to obtain a second clock signal. The second clock signal is used to offset the transmission delay of the first control signal during transmission in the circuit under test to determine the data signal acquisition time. Finally, the simulation waveforms of each signal throughout the simulation process are combined to complete the verification of the circuit under test. Therefore, it is evident that during the simulation process, there is no need to build a complex monitor in the verification environment to detect the signal values in real time, nor is there a need to build a scoring board to compare signal values. In the verification environment, only an excitation signal needs to be input to the circuit under test, and the simulation waveforms of each signal can be obtained using waveform extraction functions such as those in EDA tools. This simplifies the setup process of the verification environment, reduces the verification difficulty of digital circuits, and improves verification efficiency. Simultaneously, the second clock signal accurately determines the data signal acquisition time and corrects the transmission deviation of the first control signal, making the verification process more accurate and reliable.
[0037] In some embodiments, based on the foregoing embodiments, a first control signal in the circuit under test and a first clock signal corresponding to the first control signal are determined based on hardware description language code, specifically including the following: First, the hardware description language code is parsed to obtain at least one control signal and at least one clock signal in the circuit under test.
[0038] Specifically, control signals refer to all signals in the circuit under test that have control functions, covering various non-data signals such as trigger, enable, and mode selection, including but not limited to chip select signals and clock polarity selection signals in the SPI module. Clock signals are all signals in the circuit under test that provide timing references.
[0039] For example, the hardware description language code is parsed by an HDL code parsing tool, which traverses the port declarations and internal signal definition statements in the hardware description language code, extracts signal type identifiers, signal names, associated logic, etc., and filters all control signals and clock signals by identifying preset words corresponding to the clock, such as clk and clock.
[0040] Then, in response to the input operation of clock control information, an initial clock signal corresponding to the first control signal is determined.
[0041] Among them, the clock control information is used to indicate the mapping relationship between the control signal and the clock signal in the circuit under test.
[0042] Specifically, clock control information can be obtained by the user based on the circuit design document. For example, the user can input clock control information such as "the tx_en signal is triggered synchronously by the uart_baud_clk clock" through the interactive interface of the verification tool, configuration file import, or command line input.
[0043] Finally, the first clock signal is determined based on the initial clock signal.
[0044] In one possible implementation, the first clock signal is determined based on the initial clock signal, specifically including the following: In response to the input of frequency division information, the initial clock signal is divided to obtain the first clock signal.
[0045] Among them, the frequency division information is used to indicate the frequency division multiple of the frequency division operation.
[0046] Specifically, frequency division refers to the process of proportionally reducing the frequency of a first clock signal. For example, dividing a 50MHz initial clock signal by 10 results in a 5MHz clock signal. The division factor refers to the ratio of the original clock frequency to the target clock frequency in the frequency division operation, determining the proportion by which the clock frequency is reduced. For example, when the division factor is 16, the clock frequency becomes 1 / 16 of the original.
[0047] For example, a frequency division operation is performed on the initial clock signal based on the division factor using digital logic circuits such as counters and frequency dividers.
[0048] Of course, in addition to the division factor, the frequency division information can also include the clock phase and duty cycle after division.
[0049] During operation, the circuit under test (DUT) may internally divide the input clock according to its functional requirements. For example, an SPI module might internally divide its 100MHz system clock into a 10MHz communication clock. This results in the actual operating clock frequency of the DUT being inconsistent with the initial external clock frequency. If the initial clock signal is directly used as the first clock signal, there will be a frequency deviation from the actual internal clock frequency of the DUT, leading to errors in the determination of candidate sampling times and thus distorting the verification results. Therefore, after obtaining the frequency division information, a frequency division operation is performed on the initial clock signal based on the division factor indicated by the frequency division information. This ensures that the final first clock signal is consistent with the actual internal clock frequency of the DUT, guaranteeing the accuracy of timing verification.
[0050] In this embodiment of the application, the hardware description language code is parsed to extract the control signal and clock signal in the circuit under test. Combined with the input clock control information, the initial clock signal is matched to the first control signal to ensure the compatibility between the clock signal and the control signal.
[0051] In some embodiments, based on any of the foregoing embodiments, the first clock signal is processed according to a preset processing rule to obtain a second clock signal, specifically including the following: First, the first clock signal is inverted to obtain the inverted first clock signal.
[0052] Specifically, inversion refers to the logical operation of flipping the high and low levels of a clock signal. That is, when the original signal is high, it outputs a low level after inversion, and when the original signal is low, it outputs a high level. The signal frequency and period are not changed. For example, inverting a 5MHz first clock signal with a 50% duty cycle still results in a 5MHz clock, only the edge triggering timing is reversed compared to the original signal.
[0053] Then, based on a preset delay duration, the inverted first clock signal is delayed to obtain the second clock signal.
[0054] Specifically, delay processing refers to postponing the effective edge of the first clock signal by a preset delay time, without changing the signal's frequency, duty cycle, or amplitude. For example, delaying an inverted 5MHz clock by 0.1ns will delay all its edge triggering times by 0.1ns compared to the original inverted clock. The preset delay time is a fixed duration set according to the signal transmission delay of the circuit under test, used to compensate for the transmission delay of the first control signal within the circuit. For example, for a high-speed serial interface circuit, the preset delay time is set to 1.5ns.
[0055] For example, the inverted first clock signal is delayed using a timing logic unit, such as a shift register.
[0056] In this way, the first clock signal is optimized through inversion and delay processing to generate a second clock signal used to correct the transmission delay. The inversion process adjusts the effective edge of the clock to match the triggering logic of the circuit under test, while the delay processing cancels out the signal transmission delay, ensuring the accuracy of the data sampling time.
[0057] Figure 2 This is a diagram illustrating a scenario where erroneous data collection is caused by transmission delay. For example... Figure 2 As shown, when the first control signal is delayed after being transmitted through the circuit under test, if the data signal is used directly when the first clock signal and the first control signal are high, the data will be sampled once at the beginning and end of each data segment, resulting in the sampled data being "AABBCCDDEEFFGG", which does not match the actual transmitted data "ABCDEFG".
[0058] Figure 3 This is a diagram illustrating the optimized and correct data acquisition scenario. (Example) Figure 3 As shown, by inverting the first clock signal and introducing a small delay to generate the second clock signal, the first clock signal, the second clock signal, and the first control signal are ANDed. Data signals are sampled only when the result of the AND operation is high. At the stable midpoint of each data segment, “ABCDEFG” consistent with the actual transmitted data is collected, thus solving the sampling error problem caused by the transmission delay of the first control signal.
[0059] In one possible implementation, the method provided in this application embodiment further includes the following: First, obtain the netlist file of the circuit under test.
[0060] Specifically, a netlist file is a structured file that describes the device connections, port mappings, and timing information in the circuit under test, including gate-level cells, routing delays, etc. For example, an EDA tool or a place-and-route tool can be used to extract the netlist file.
[0061] Then, the netlist file is parsed to obtain the path delay parameters corresponding to the first control signal.
[0062] Specifically, the path delay parameter describes the time delay caused by factors such as logic gates and wiring during the transmission of a signal from the input port to the output port.
[0063] Optionally, the path delay parameter corresponding to the first control signal can be obtained in the following way: Parse at least one parallel transmission path in the netlist file, obtain the path delay parameter corresponding to each parallel transmission path, and determine the path delay parameter corresponding to the first control signal as the maximum path delay parameter to cover the delay compensation requirements under the worst-case condition and ensure sampling stability.
[0064] For example, the timing analysis engine built into the EDA tool can be used to analyze the port connection relationships and delay data in the network file to locate each transmission path (i.e., parallel transmission path) from the input of the first control signal to the output. Further, the path delay parameter is determined based on the number of logic gates in the path and their preset delay values, as well as the number of wirings and their preset delay values. For instance, inside the circuit under test, after the tx_vld signal is generated by a certain logic gate, it needs to pass through 3 NAND gates and 2 wiring segments to reach the output pin. The preset delay value for each NAND gate is 0.02ns, and the preset delay value for each wiring segment is 0.03ns. Therefore, the path delay parameter for tx_vld is (3 × 0.02) + (2 × 0.03) = 0.12ns.
[0065] Finally, based on the path delay parameters and the clock period of the first clock signal, the preset delay duration is determined.
[0066] Specifically, the clock cycle refers to the time it takes for a clock signal to complete one high-low level transition, which is the reciprocal of the clock frequency.
[0067] For example, the preset delay duration is greater than the path delay parameter and less than a preset proportion of the clock cycle. The preset proportion can be set according to actual conditions, for example, 0.25. This is because if the preset delay duration is less than or equal to the path delay parameter, it cannot completely compensate for the transmission delay of the first control signal within the circuit, resulting in timing misalignment between the clock signal edge and the control and data signals, and the sampling time may still fall in the unstable transition region of the data signal. If the preset delay duration exceeds the preset proportion of the clock cycle (usually 50% of the clock cycle is taken as a safety threshold), the sampling time will fall into the valid range of the next set of data, causing sampling data misalignment or duplication, and disrupting the timing integrity of data transmission. Therefore, setting the preset delay duration to a range greater than the path delay parameter and less than the preset proportion of the clock cycle can accurately compensate for the transmission delay of the control signal, ensuring that the sampling time falls within the stable range of the current data segment, while also preventing sampling from exceeding the boundary of the next set of data. This ensures both the effectiveness of timing correction and the accuracy and integrity of data sampling.
[0068] In some instances, based on any of the foregoing embodiments, the circuit under test is verified using the first, second, third, and fourth simulation waveforms to obtain verification results, which specifically include the following: a1, based on the first, second, and third simulated waveforms, determines the sampling time of the data signal.
[0069] Specifically, the first control signal has a transmission delay inside the circuit under test. Directly using the first clock signal for sampling will result in sampling errors. By introducing a second clock signal that has been inverted and delayed, the path delay can be effectively compensated, ensuring that the sampling time falls within the stable data range and avoiding the acquisition of erroneous or unstable data.
[0070] For example, based on the first simulated waveform, the second simulated waveform, and the third simulated waveform, the time point when the first control signal, the first clock signal, and the second clock signal simultaneously meet the preset valid conditions (such as the signal values being high at the same time) is identified, and this time point is used as the sampling time of the data signal.
[0071] a2, based on the fourth simulation waveform, determines the first signal value of the data signal at the sampling time.
[0072] For example, in an EDA tool, the sampling time determined above is located, and the level state or value of the fourth simulation waveform at that sampling time is read and used as the first signal value of the data signal output.
[0073] a3, based on the first signal value and the first preset signal value corresponding to the data signal, obtains the verification result.
[0074] Specifically, the first preset signal value is set based on the functional requirements of the circuit under test, and is the expected value that the data signal should output at the corresponding time.
[0075] For example, if the first signal value is the same as the first preset signal value, it is determined that the circuit under test meets the design requirements; if the first signal value is different from the first preset signal value, it is determined that the circuit under test does not meet the design requirements.
[0076] In one possible implementation, the sampling time of the data signal is determined as follows: First, based on the first simulation waveform, multiple candidate moments in the simulation process are determined.
[0077] In each candidate time, the signal value of the first control signal is the second preset signal value corresponding to the first control signal.
[0078] Specifically, the second preset signal value represents the effective level state of the first control signal, such as a high level or a low level. The candidate times are the set of time points when the first control signal is in a preset effective state, serving as a preliminary selection of sampling times. For example, the time when the first control signal is at a high level is a candidate time, corresponding to the effective interval of the data signal.
[0079] For example, the timestamps of the first simulation waveform are traversed, and all moments when the level of the first control signal is equal to the second preset signal value are selected as candidate moments.
[0080] Secondly, based on the second simulation waveform, the signal value of the first clock signal at the first candidate time is determined.
[0081] The first candidate time is one of several candidate times.
[0082] Next, based on the third simulation waveform, the signal value of the second clock signal at the first candidate time is determined.
[0083] Next, a logical AND operation is performed on the signal values of the first control signal, the first clock signal, and the second clock signal at the first candidate time to obtain the operation result corresponding to the first candidate time.
[0084] Specifically, the level values of the first control signal, the first clock signal, and the second clock signal are ANDed at the same time. The result is 1 (true) only when all signals are at a valid level, otherwise it is 0.
[0085] Finally, after determining the calculation results corresponding to all candidate times, the candidate times whose calculation results are the preset calculation results are determined as the sampling times.
[0086] In this way, multiple candidate times are first obtained by filtering through the first control signal, and then the sampling time that meets all timing conditions is determined by combining the level of the first clock signal and the level of the second clock signal, thus avoiding the problems of sampling repetition and data misalignment caused by the transmission delay of the first control signal in the circuit under test.
[0087] In this embodiment, the sampling time is determined by the simulated waveforms of the first control signal, the first clock signal, and the second clock signal. This effectively avoids sampling errors caused by transmission delays in the hardware under test. Reliable data acquisition and circuit verification can be achieved without building a complex monitor and scoring board, which improves the efficiency of setting up the verification environment, enhances verification efficiency, and ensures the accuracy and reliability of the verification results.
[0088] In some embodiments, this application provides a verification platform comprising a driver, an auxiliary signal generator, and a circuit under test (DUT). The DUT is connected to the driver and the auxiliary signal generator. The driver is used to input various excitation signals to the DUT. The auxiliary signal generator is used to process a first clock signal according to preset processing rules to generate a second clock signal.
[0089] During the compilation phase of the verification platform, a behavior-level auxiliary signal generator is automatically generated to receive the first clock signal and output the second clock signal, thus completing timing correction without modifying the original design of the circuit under test.
[0090] Figure 4 This is a schematic diagram illustrating an application scenario for a verification platform. For example... Figure 4 As shown, the verification platform includes a driver, an auxiliary signal generator, and a circuit under test (DUT). The driver inputs a drive signal to the DUT to simulate an actual working scenario. The auxiliary signal generator receives a first clock signal from the DUT and processes it according to preset processing rules to generate a second clock signal. After the simulation phase, the original listener is replaced with a script that determines the sampling time based on the first control signal, the first clock signal, and the second clock signal, and exports data signals from the waveform file based on the sampling time. This script outputs the acquired signal values to a scoring board, compares them with the expected data generated by the reference model, and completes the functional verification. Figure 4 In this process, the listener and scoreboard are separated from the verification platform (i.e., the scenario setup). Only the driver needs to be completed to start the simulation of the circuit under test. In addition, the newly added auxiliary signal generator and the above scripts are versatile, which greatly simplifies the verification environment setup process and improves verification efficiency and flexibility.
[0091] The above mainly describes the solution provided by the embodiments of this application from a methodological perspective.
[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0093] This application also provides a digital circuit verification device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0094] This embodiment provides a verification device for digital circuits, such as... Figure 5 As shown, it includes: The first acquisition module 501 is used to acquire the hardware description language code of the circuit under test; The determination module 502 is used to determine the first control signal in the circuit under test, as well as the first clock signal and data signal corresponding to the first control signal, based on the hardware description language code. The processing module 503 is used to process the first clock signal according to a preset processing rule to obtain a second clock signal, wherein the second clock signal is used to correct the transmission delay of the first control signal in the circuit under test in order to determine the sampling time of the data signal. The second acquisition module 504 is used to acquire the first simulation waveform of the first control signal in the simulation process of the circuit under test, the second simulation waveform of the first clock signal in the simulation process, the third simulation waveform of the second clock signal in the simulation process, and the fourth simulation waveform of the data signal in the simulation process. The verification module 505 is used to verify the circuit under test based on the first simulation waveform, the second simulation waveform, the third simulation waveform, and the fourth simulation waveform, and obtain the verification result.
[0095] The apparatus provided in this application accurately locates the first control signal and its corresponding first clock signal and data signal by parsing the hardware description language code. Furthermore, the first clock signal undergoes delay compensation processing to obtain a second clock signal. The second clock signal is used to offset the transmission delay of the first control signal during transmission in the circuit under test to determine the data signal acquisition time. Finally, the simulation waveforms of each signal throughout the simulation process are combined to complete the verification of the circuit under test. Therefore, it is evident that during the simulation process, there is no need to build a complex monitor in the verification environment to detect the signal values in real time, nor is there a need to build a scoring board to compare signal values. In the verification environment, only an excitation signal needs to be input to the circuit under test, and the simulation waveforms of each signal can be obtained using waveform extraction functions such as those in EDA tools. This simplifies the setup process of the verification environment, reduces the verification difficulty of digital circuits, and improves verification efficiency. Simultaneously, the second clock signal accurately determines the data signal acquisition time and corrects the transmission deviation of the first control signal, making the verification process more accurate and reliable.
[0096] In one possible implementation, the determining module 502 is specifically used to parse the hardware description language code to obtain at least one control signal and at least one clock signal in the circuit under test. In response to the input operation of clock control information, an initial clock signal corresponding to the first control signal is determined, wherein the clock control information is used to indicate the mapping relationship between the control signal and the clock signal in the circuit under test; The first clock signal is determined based on the initial clock signal.
[0097] In one possible implementation, the determining module 502 is specifically used to perform a frequency division operation on the initial clock signal in response to the input operation of the frequency division information to obtain a first clock signal, wherein the frequency division information is used to indicate the frequency division multiple of the frequency division operation.
[0098] In one possible implementation, the processing module 503 is specifically used to invert the first clock signal to obtain the inverted first clock signal. Based on a preset delay duration, the inverted first clock signal is delayed to obtain the second clock signal.
[0099] In one possible implementation, the determining module 502 is also used to obtain the netlist file of the circuit under test; The netlist file is parsed to obtain the path delay parameters corresponding to the first control signal; The preset delay duration is determined based on the path delay parameter and the clock period of the first clock signal.
[0100] In one possible implementation, the verification module 505 is specifically used to determine the sampling time of the data signal based on the first simulated waveform, the second simulated waveform, and the third simulated waveform; Based on the fourth simulation waveform, the first signal value of the data signal at the sampling time is determined; The verification result is obtained based on the first signal value and the first preset signal value corresponding to the data signal.
[0101] In one possible implementation, the verification module 505 is specifically used to determine multiple candidate moments in the simulation process based on the first simulation waveform, wherein at each candidate moment the signal value of the first control signal is a second preset signal value corresponding to the first control signal; Based on the second simulation waveform, the signal value of the first clock signal at the first candidate time is determined, wherein the first candidate time is one of multiple candidate times; Based on the third simulation waveform, the signal value of the second clock signal at the first candidate time is determined; Perform a logical AND operation on the signal values of the first control signal, the first clock signal, and the second clock signal at the first candidate time to obtain the operation result corresponding to the first candidate time. Once the calculation results corresponding to all candidate times are determined, the candidate times whose calculation results are the preset calculation results are determined as the sampling times.
[0102] For a description of the features in the embodiment corresponding to the verification device for digital circuits, please refer to the relevant description of the embodiment corresponding to the verification method for digital circuits, which will not be repeated here.
[0103] Embodiments of this application also provide an electronic device, such as... Figure 6 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the above-described digital circuit verification method embodiments.
[0104] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described digital circuit verification method embodiments when it is run.
[0105] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0106] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described digital circuit verification method embodiments.
[0107] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described digital circuit verification method embodiments.
[0108] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0109] The present application provides a detailed description of a digital circuit verification method, apparatus, electronic device, and medium. Specific examples have been used to illustrate the principles and implementation methods of the present application. The descriptions of these embodiments are merely illustrative and are intended to aid in understanding the method and its core concepts. It should be noted that those skilled in the art can make various improvements and modifications to the present application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.
Claims
1. A method for verifying digital circuits, characterized in that, The method includes: Obtain the hardware description language code of the circuit under test; Based on the hardware description language code, a first control signal in the circuit under test, as well as a first clock signal and a data signal corresponding to the first control signal, are determined. According to the preset processing rules, the first clock signal is processed to obtain the second clock signal, wherein the second clock signal is used to correct the transmission delay of the first control signal in the circuit under test, so as to determine the sampling time of the data signal; Acquire the first simulation waveform of the first control signal in the simulation process of the circuit under test, the second simulation waveform of the first clock signal in the simulation process, the third simulation waveform of the second clock signal in the simulation process, and the fourth simulation waveform of the data signal in the simulation process; The circuit under test is verified based on the first simulation waveform, the second simulation waveform, the third simulation waveform, and the fourth simulation waveform, and the verification results are obtained.
2. The method according to claim 1, characterized in that, Based on the hardware description language code, determining the first control signal in the circuit under test and the first clock signal corresponding to the first control signal includes: The hardware description language code is parsed to obtain at least one control signal and at least one clock signal in the circuit under test. In response to the input operation of clock control information, an initial clock signal corresponding to the first control signal is determined, wherein the clock control information is used to indicate the mapping relationship between the control signal and the clock signal in the circuit under test; The first clock signal is determined based on the initial clock signal.
3. The method according to claim 2, characterized in that, Determining the first clock signal based on the initial clock signal includes: In response to the input operation of the frequency division information, the initial clock signal is divided to obtain the first clock signal, wherein the frequency division information is used to indicate the frequency division multiple of the frequency division operation.
4. The method according to any one of claims 1-3, characterized in that, The step of processing the first clock signal according to a preset processing rule to obtain the second clock signal includes: The first clock signal is inverted to obtain the inverted first clock signal; Based on a preset delay duration, the inverted first clock signal is delayed to obtain the second clock signal.
5. The method according to claim 4, characterized in that, The method further includes: Obtain the netlist file of the circuit under test; The netlist file is parsed to obtain the path delay parameters corresponding to the first control signal; The preset delay duration is determined based on the path delay parameter and the clock period of the first clock signal.
6. The method according to any one of claims 1-3, characterized in that, The circuit under test is verified based on the first simulated waveform, the second simulated waveform, the third simulated waveform, and the fourth simulated waveform to obtain verification results, including: Based on the first simulated waveform, the second simulated waveform, and the third simulated waveform, the sampling time of the data signal is determined; Based on the fourth simulation waveform, determine the first signal value of the data signal at the sampling time; The verification result is obtained based on the first signal value and the first preset signal value corresponding to the data signal.
7. The method according to claim 6, characterized in that, Determining the sampling time of the data signal based on the first simulated waveform, the second simulated waveform, and the third simulated waveform includes: Based on the first simulation waveform, multiple candidate moments are determined during the simulation process, wherein at each candidate moment, the signal value of the first control signal is a second preset signal value corresponding to the first control signal; Based on the second simulation waveform, the signal value of the first clock signal at the first candidate time is determined, wherein the first candidate time is one of the plurality of candidate times; Based on the third simulation waveform, determine the signal value of the second clock signal at the first candidate time. Perform a logical AND operation on the signal values of the first control signal, the first clock signal, and the second clock signal at the first candidate time to obtain the operation result corresponding to the first candidate time. After determining the calculation results corresponding to all the candidate times, the candidate time whose calculation result is a preset calculation result is determined as the sampling time.
8. A verification device for digital circuits, characterized in that, The device includes: The first acquisition module is used to acquire the hardware description language code of the circuit under test; The determination module is used to determine, based on the hardware description language code, a first control signal in the circuit under test, and a first clock signal and a data signal corresponding to the first control signal; The processing module is used to process the first clock signal according to a preset processing rule to obtain a second clock signal, wherein the second clock signal is used to correct the transmission delay of the first control signal in the circuit under test in order to determine the sampling time of the data signal; The second acquisition module is used to acquire the first simulation waveform of the first control signal in the simulation process of the circuit under test, the second simulation waveform of the first clock signal in the simulation process, the third simulation waveform of the second clock signal in the simulation process, and the fourth simulation waveform of the data signal in the simulation process. The verification module is used to verify the circuit under test based on the first simulation waveform, the second simulation waveform, the third simulation waveform, and the fourth simulation waveform, and obtain the verification result.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the verification method for the digital circuit as described in any one of claims 1-7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the verification method for the digital circuit as described in any one of claims 1-7.