Non-volatile memory and electronic devices

Abstract

A non-volatile memory and electronic device are disclosed. The memory includes: a memory cell array; multiple word lines and multiple bit lines; a sense amplifier (SA) array; a reference cell for generating a reference current; a first current mirror circuit; and a second current mirror circuit. The first current mirror circuit mirrors the acquired reference current, converts the mirrored reference current into a first reference voltage and provides it to a first group of SA cells in the SA array, and provides the mirrored current to the second current mirror circuit. The second current mirror circuit mirrors the mirrored current and converts it into a second reference voltage, providing the second reference voltage to a second group of SA cells in the SA array. These two groups of SA cells are connected to bit lines in different regions of the memory block. By providing specially configured current mirror circuits, a reliable reference power supply signal is provided to SA cells located far from the reference cell, thereby improving the transient response and noise immunity of the reference signal.

Description

[0001] This application is a divisional application of the invention patent application with application number 202110903152.2, application date August 6, 2021, and invention title "Non-volatile memory and electronic device". Technical Field

[0002] This invention relates to the field of semiconductor storage technology, and more particularly to a non-volatile memory and electronic device. Background Technology

[0003] Flash memory, with its high storage density, high reliability, and low power consumption, is increasingly widely used today. A key indicator determining the quality of flash memory is its read performance. Memory access time depends on the read speed of the associated read circuitry. For example, in smartphones, faster flash memory access times can improve the overall operating speed of the phone, its ability to perform parallel operations, and the amount of data it can process. Flash memory includes NAND flash memory and NOR flash memory. NOR flash memory, also known as code-based memory, supports Execute-In-Place (XIP). NOR flash memory is typically used in conjunction with microcontrollers and requires frequent read operations.

[0004] However, the pursuit of greater storage capacity requires more storage cells to be included inside the chip, resulting in an increase in the overall chip area and a corresponding increase in the number of sense amplifiers (SAs).

[0005] The increase in SA and the overall chip area will lead to an increase in the load on the reference voltage signal, a slower setup speed, and affect the speed of SA-related operations (especially read operations), thereby causing a decrease in the overall chip performance.

[0006] Therefore, an improved reference voltage provision scheme is needed. Summary of the Invention

[0007] One technical problem this disclosure aims to solve is to provide a non-volatile memory that provides a reliable reference power supply signal to the SA cell, which is far from the reference cell, by providing a specially configured current mirror circuit, thereby improving the transient response and noise immunity of the reference signal.

[0008] According to a first aspect of this disclosure, a non-volatile memory is provided, comprising: a memory cell array; multiple word lines and multiple bit lines; a sense amplifier (SA) array; a reference cell for generating a reference current; a first current mirror circuit; and a second current mirror circuit, wherein the first current mirror circuit mirrors the acquired reference current, converts the mirrored reference current into a first reference voltage and provides it to a first group of SA cells in the SA array, the first current mirror circuit provides the mirrored current of the reference current to the second current mirror circuit, the second current mirror circuit mirrors the mirrored current of the reference current and converts it into a second reference voltage, and provides the second reference voltage to a second group of SA cells in the SA array, wherein the first group of SA cells and the second group of SA cells are connected to bit lines in different regions of a memory block.

[0009] Optionally, the SA array includes N SA cells arranged along a first direction of the layout, and the first group of SA cells includes SA0~SA0 arranged sequentially along the first direction. n-1 The second group of SA units includes SA units arranged sequentially in the first direction. n ~SA N-1 .

[0010] Optionally, the distance between the first current mirror circuit and the second current mirror circuit and the SA array is less than the distance between the reference cell and the SA array.

[0011] Optionally, the reference unit and the first current mirror circuit are arranged on one side of the layout in a first direction, and the second current mirror circuit is arranged in the middle of the layout in the first direction.

[0012] Optionally, the reference unit and the first current mirror circuit are arranged on one side of the power pad in the layout.

[0013] Optionally, the first current mirror circuit includes: a first sub-current mirror circuit for obtaining a reference current from the reference unit; and a second sub-current mirror circuit for providing a mirror current of the reference current.

[0014] Optionally, the second sub-current mirror circuit includes an input branch, a first mirror branch, and a second mirror branch, wherein the input branch is used to acquire a reference current from the first sub-current mirror circuit, the first mirror branch is used to perform current mirroring on the reference current and provide the first reference voltage to the first group of SA cells based on the mirrored current on the first mirror branch, and the second mirror branch is used to perform current mirroring on the reference current and provide the mirrored current of the reference current to the second current mirror circuit.

[0015] Optionally, the second current mirror circuit includes: an input branch for acquiring a mirror current of the reference current from the first current mirror circuit; and a mirror branch for mirroring the mirror current of the reference current and providing the second reference voltage to the second group of SA units based on the mirror current on the branch.

[0016] Optionally, the distance between the second group of SA units and the reference unit is greater than the distance between the first group of SA units and the reference unit.

[0017] Optionally, the reference unit has a threshold voltage corresponding to the operation, which is a read operation, an erase verification operation, or a program verification operation.

[0018] Optionally, the verification voltage applied to the control gate of the selected memory cell in the erase verification operation is different from the read voltage in the read operation. Correspondingly, the reference current in the erase verification operation is different from the reference current in the read operation, and the reference voltage in the erase verification operation is different from the reference voltage in the read operation.

[0019] According to a second aspect of this disclosure, a NOR flash memory that can be implemented by the memory according to the first aspect is provided.

[0020] According to a third aspect of this disclosure, an electronic device is provided that includes the memory described in the first and / or second aspects.

[0021] Therefore, by adding an additional mirror branch to the first-stage current mirror and adding a second-stage current mirror in the middle of the SA layout, the SA load far from the reference cell can be driven, thereby effectively improving the transient response and noise immunity of the reference voltage signal in large-scale circuits. Attached Figure Description

[0022] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, in which the same reference numerals generally represent the same components.

[0023] Figure 1 It is an electronic device that includes a memory according to an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram of NOR flash memory.

[0025] Figure 3 The basic operating principle of the readout amplifier SA is shown in the SA unit.

[0026] Figure 4 A schematic diagram of a current mirror circuit according to an embodiment of the present invention is shown.

[0027] Figure 5 A schematic diagram of the layout of a current mirror circuit according to an embodiment of the present invention is shown.

[0028] Figure 6 A circuit diagram of a first current mirror circuit according to an embodiment of the present invention is shown.

[0029] Figure 7 A circuit diagram of a second current mirror circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0030] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0031] Various embodiments will be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same parts in the various drawings and embodiments of the invention.

[0032] Note that the accompanying drawings are simplified schematics and therefore not necessarily drawn to scale. In some cases, portions of the drawings may have been exaggerated to more clearly illustrate certain features of the illustrated embodiments.

[0033] It should be further noted that specific details are set forth in the following description to facilitate understanding of the invention; however, the invention may be practiced without some of these specific details. Additionally, it should be noted that well-known structures and / or processes may be described only briefly or not at all to avoid obscuring this disclosure with unnecessary well-known details.

[0034] It should also be noted that in some cases, it will be apparent to those skilled in the art that, unless otherwise specifically stated, an element (also referred to as a feature) associated with one embodiment described may be used alone or in combination with other elements of another embodiment.

[0035] The various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. For ease of understanding, the following will first be combined with... Figure 1 Describe the application environment of this invention.

[0036] Figure 1 It is an electronic device that includes a non-volatile memory according to an embodiment of the present invention. As shown in the figure, the device 10 includes a host 200 and a memory 300.

[0037] Here, host 200 refers to the part that implements the key functions of device 10, that is, the main part of device 10, and host 200 (or device 10) can be any suitable electronic device. In one embodiment, device 10 can be an electronic device, including but not limited to portable electronic devices such as mobile phones, tablets, wearable devices, and laptops, or non-portable electronic devices such as desktop computers, game consoles, televisions, set-top boxes, and projectors. In this case, memory 300 can be a device that provides storage services for standalone electronic devices.

[0038] In other embodiments, device 10 may also be an electronic device with relatively independent functions (these electronic devices are often key components of electronic devices), such as a separately sold smart screen, main control chip, camera assembly, etc. These electronic devices typically need to be assembled; for example, a smart screen is assembled into a mobile phone to provide services to consumers (e.g., users who purchase the mobile phone). In this case, memory 300 may be a device that provides the necessary storage services for the electronic device.

[0039] For example, when device 10 is a smartphone, memory 300 may be a storage chip that provides storage services for the smartphone. When device 10 is a smart screen that makes up a smartphone, memory 300 may be a storage chip that provides storage services for the smart screen to achieve all its functions.

[0040] The memory 300 can respond to requests from the host 200. For example, the memory 300 can store data provided by the host 200 and can also provide the stored data to the host 200. The data stored in the memory 300 can be accessed by the host 200. The memory 300 can be used as the main memory or auxiliary memory of the host 200. Here, the data stored in the memory 300 can include not only data files in a narrow sense (e.g., photographs, written Word documents, etc.), but also other data in a broader sense, such as command data and address data.

[0041] In theory, the memory 300 can be implemented using any of a variety of storage devices, depending on the protocol of the host interface electrically connected to the host 200. In this invention, flash memory is preferably used to implement the memory 300. Flash memory includes NAND flash memory and NOR flash memory. The various components contained within the memory 300 (e.g., components 310-370) can be integrated into a single semiconductor device. For example, the various components contained within the memory 300 can be integrated into a single semiconductor device to form a solid-state drive (SSD). When the memory 300 is used as an SSD, the operating speed of the host 200 electrically connected to the memory 300 can be significantly improved.

[0042] Specifically, in memory 300, memory array 320 can store data accessed by host 300. Controller 310 can control data exchange between memory array 320 and host 200, as well as various operations on memory array 320, such as read operations, programming operations (write operations), and erase operations.

[0043] Specific reference Figure 1 The memory 300 can be implemented as NOR flash memory 300 and may include a controller 310, multiple word lines (WL), multiple bit lines (BL), a memory cell array 320, a word line decoder 330, a readout amplifier (SA or sensing circuit) 340, a bit line decoder 350, a charge pump (or power supply unit) 360, and a buffer unit (or page buffer) 370.

[0044] Please see Figure 2 , Figure 2 A schematic diagram of a NOR flash memory block is shown. Figure 2 The storage block can be viewed as a block of the storage cell array 320. The block consists of 64 rows. A storage unit with N columns, where N is, for example, equal to 1024. 8. Therefore, when reading line by line, Figure 1 The page buffer 370 shown can store 1KB of data in each read. The memory cell array 320 includes multiple blocks, each formed, for example, in a common well. The memory cell can be a transistor with a floating gate or a transistor with a charge trapping layer formed by an insulating film; the transistor also includes a source, a drain, and a control gate. The memory cell is connected via the multiple word lines WL0-WL0. 63 and the multiple bit lines BL0-BL N-1 Addressing. Each row of memory cells is connected to the same word line; specifically, the control gate of each row of memory cells is connected to the same word line. Each column of memory cells is connected to the same bit line; specifically, the drain of each column of memory cells is connected to the same bit line. The source of the memory cell is grounded or connected to the source line.

[0045] The controller 310 is used to decode commands, addresses, or data exchanged with the host 200 transmitted by the host 200, and to execute instructions from the host 200 and / or access the storage unit array 320. The instructions are used to perform operations on the storage unit array 320, and the operations include at least read operations, write operations, erase operations, erase verification operations, and other operations.

[0046] The page buffer 370 is used to store data read from the memory cell array 320 or data to be written to a page. The page buffer 370 is, for example, a static random-access memory (SRAM). The page buffer 370 includes multiple memory cells, which correspond to a row of memory cells.

[0047] The charge pump 360 is used to provide various voltages required for read operations, write operations, erase operations, and erase verification operations. For example, the charge pump 360 is used to provide erase operation voltage, or erase verification voltage, or software programming voltage.

[0048] Word line decoder 330 through Figure 1 Multiple word lines (WLs) are connected to the memory cell array 320. A word line decoder 330 is used to select at least one word line based on address information. A bit line decoder 350 is coupled to a bit line (BL) and used to select at least one bit line based on address information. A sense amplifier 340 can be used in read or verification operations to compare the current flowing through the selected memory cell with a reference current and provide corresponding outputs. Specifically, the sense amplifier 340 may include a sense amplifier (SA) array composed of multiple SA cells, for example... Figure 2 SA0-SA shown N-1 When a row of storage units contains 1024 When 8 storage units can store 1KB of data, the corresponding storage block typically needs to be equipped with 1024... 8 bit lines, and the corresponding 1024 8 SA units. It should be understood that... Figure 1 The multiple WL and BL lines shown are merely illustrative of the existence of multiple WL and BL lines connected to the decoder, and do not imply the specific number of lines.

[0049] Each SA unit can be viewed as a current comparator. Each SA unit is connected to a BL line; for example, SA unit SA0 is connected to BL0, SA unit SA1 is connected to BL1, ..., SA N-1 Connecting to BL N-1 Each SA unit can also be connected to its own reference voltage V. REF It determines the stored content of the memory cell and outputs it based on the current on the bit line BL.

[0050] Figure 3 The basic operating principle of the SA cell is illustrated. Specifically, the SA cell compares the current I of the sensed memory cell. CELL Size and reference current I of the reference cell REF The size. One input terminal of the SA cell is connected to the drain terminal of the sensed memory cell via the bit line BL. BL can be... Figure 2 As shown in BL0~BL N-1 Any BL in i The SA unit shown in the diagram can be the corresponding SA. i , where i is any value from 0 to N-1. The reference cell and the memory cell, for example, have the same specifications. The reference cell has a threshold voltage corresponding to the operation. The operation is, for example, a read operation, an erase verification operation, or a program verification operation. The reference cell generates a reference current I. REF The current is supplied to the SA unit via a current mirror circuit.

[0051] During a read operation, the bit line BL is charged and clamped to a predetermined voltage (e.g., 0.8V) by a precharge clamping circuit, and a read voltage V is applied to the control gate of the memory cell to be read by a charge pump and a word line decoder. read During a read operation, the transistor storing "1" will be in the on state under the read voltage, and the current I on BL will... CELL Relatively large (greater than the reference current I) REF The transistor storing "0" will be in the off state under the read voltage, and the current I on BL will... CELL Relatively small (less than the reference current I) REF Therefore, for different I CELL The SA unit can output different comparison results from the input, corresponding to high levels (e.g., power supply voltage V). DD A high level (e.g., 0) indicates whether the selected memory cell on the corresponding bit line BL is in a programming or erasing state. Erasing verification or programming verification operations are similar to read operations. The magnitude of the verification voltage applied to the control gate of the selected memory cell in an erase verification operation differs from the magnitude of the read voltage in a read operation; correspondingly, the reference current is different, and the reference voltage V0 is also different. REF They are not the same either.

[0052] Since the memory contains a large number of SA cells, the reference current I is usually transmitted through a circuit. REF Convert to reference voltage V REF Then the SA unit itself will generate the reference voltage V. REF Convert to reference current I REF As the capacity of flash memory chips continues to increase, a single read operation requires providing a reference voltage V to more SA cells.REF In combination with the above Figure 2 The described row of storage units includes 1024 Eight storage units, and equipped with a corresponding 1024 In the example with 8 SA units, each read can transfer 1024. 8 bits of data are stored in page buffer 370, and at the same time, 1024 also need to be stored. Eight SA cells provide a reference voltage V REF Existing current mirror circuits for non-volatile memories can no longer meet the high-speed and accurate read operation requirements of high-capacity memory chips. Therefore, this invention provides a new current mirror circuit to provide improved transient response and noise immunity of the reference voltage signal for high-capacity memory chips.

[0053] Figure 4 A schematic diagram of a current mirror circuit according to an embodiment of the present invention is shown. As shown, the current mirror circuit 400 includes a reference unit 410 for generating a reference current, a first current mirror circuit 420, and a second current mirror circuit 430. The above-described current mirror circuit is used in the non-volatile memory (especially NOR flash memory) of the present invention and is capable of providing a reference voltage for the SA cell in the memory. It should be understood that the non-volatile memory of the present invention, in addition to Figure 4 In addition to the current mirror circuit shown, it may also include a memory cell array, multiple word lines and multiple bit lines, and a sense amplifier (SA) array, etc. Figure 2 The structure shown.

[0054] In addition, it should also be understood that, Figure 4 The arrows pointing from the reference unit 410 to the first current mirror circuit 420, and from the first current mirror circuit 420 to the second current mirror circuit 430, are intended to indicate that the reference current is provided by the reference unit 410 to the first current mirror circuit 420 and then by the first current mirror circuit 420 to the second current mirror circuit 430, rather than indicating the direction of the reference current. In practical applications, the reference current may have the same or opposite direction as the arrows, depending on the specific circuit voltage settings.

[0055] Specifically, the reference unit 410 is used to generate the reference current I. REF For example, reference unit 410 can be used with devices such as... Figure 2 The memory cell shown is similar, consisting of a transistor including a floating gate or charge trapping layer, and generating a reference current I for comparison under the control voltage of the control gate. REF .

[0056] The first current mirror circuit 420 is connected to the reference unit 410. The reference current I generated by the reference unit 410... REFIt can be fed into the first current mirror circuit 420 for mirroring. The mirrored current of the reference current obtained by mirroring (which can also be I) REF Then it can be sent to the second current mirror circuit 430 connected to the first current mirror circuit 420.

[0057] Specifically, the first current mirror circuit 420 can mirror the obtained reference current I. REF Converted to the first reference voltage V REF1 The first reference voltage is then provided to the first group of SA cells. Similarly, the second current mirror circuit 430 can mirror the obtained reference current I. REF Converted to a second reference voltage V REF2 The second reference voltage is provided to the second group of SA units. The sense amplifier (SA) array includes a first group of SA units and a second group of SA units. The first group of SA units and the second group of SA units participate in the read operation simultaneously; that is, the first group of SA units and the second group of SA units are circuits that need to perform comparison operations simultaneously in a single read operation. In one embodiment, the first group of SA units and the second group of SA units can be used to connect bit lines of different regions in the memory block. For example, the first group of SA units corresponds to the bit lines of different regions in the memory block. Figure 1 The second group of SA cells corresponds to the bit line located on the other side of the layout.

[0058] In this context, the SA cells in the first group of SA cells are arranged adjacent to each other in the chip layout; similarly, the SA cells in the second group of SA cells are also arranged adjacent to each other in the chip layout.

[0059] Since the current mirror circuit needs to be arranged as close as possible to the SA cells that provide the reference voltage, the first current mirror circuit is arranged close to the first group of SA cells, the second current mirror circuit is arranged close to the second group of SA cells, and the distance between the first current mirror circuit and the second current mirror circuit and the SA array is less than the distance between the reference cell and the SA array.

[0060] In other words, in order for the current mirror circuit to provide the reference voltage V to the SA cell as close as possible... REF To reduce noise disturbance, the first and second current mirror circuits are arranged separately, and each provides a reference voltage V only to the SA cell in its vicinity. REF For example, each SA unit is connected to the one of the first current mirror circuit 420 and the second current mirror circuit 430 that is closer to it and receives a reference voltage. For example, Figure 4 SA0~SA are shown connected to the first current mirror circuit 420. n-1 SA connected to the second current mirror circuit 430 n ~SA N-1Here, the preferred value of n is half of N (or at least close to half), i.e., n = N / 2.

[0061] Furthermore, since the first current mirror circuit 420 directly obtains the reference current from the reference cell 410, the reference cell 410 is arranged adjacent to the first current mirror circuit 420 in the layout design. Therefore, the distance between the second group of SA cells and the reference cell is greater than the distance between the first group of SA cells and the reference cell.

[0062] Therefore, by introducing the first current mirror circuit 420 and the second current mirror circuit 430, reference voltage V is provided for different groups of SA units that need to operate simultaneously. REF This enables each SA unit to establish the reference voltage V more quickly. REF This improves the transient response of the reference signal in high-capacity flash memory, thereby enhancing the overall read efficiency of the flash memory chip.

[0063] Furthermore, since the reference voltage signal located far from the output position of the current mirror circuit on the layout is susceptible to noise disturbance, in order to further improve noise immunity, in some embodiments, the distribution of each component circuit of the current mirror circuit can be optimized.

[0064] Figure 5 A schematic diagram of the current mirror circuit according to an embodiment of the present invention is shown on a layout. The layout area is outlined in gray dashed lines. In this diagram, for ease of explanation, the word line extension direction can be set as a first direction or the x-direction, and the bit line extension direction can be set as a second direction or the y-direction.

[0065] As shown in the figure, the memory cell array is divided into two groups in the bit line direction; that is, the layout includes two memory cell arrays arranged vertically in the x-direction. Each memory cell array contains a large number of memory cells, for example, each with a capacity of 32Gb.

[0066] Multiple SA units, for example, SA0~SA N-1 Arranged along the x-direction (the first direction of the layout), and divided into two groups, SA0 and SA1, according to the distribution of the memory cell array. Among them, SA0 can correspond to SA0~SA1. n-1 SA1 can correspond to SA n ~SA N-1 Here, n is preferably half, or approximately half, of the value of N.

[0067] Row decoders are arranged on the top and bottom sides of each storage cell array. The row decoders can be implemented, for example... Figure 1 The word-line decoder shown has all or part of its functions.

[0068] The bit line control circuit located on the right side of the memory cell array, connected by a dotted and dashed coil, is used to control the bit lines and can be used to implement... Figure 1 The readout amplifier 340, bit line decoder 350, and even page buffer 370 shown may be all or part of these. This may include, as shown, the SA circuit and current mirror circuit involved in this invention.

[0069] exist Figure 5 In the layout diagram, the first current mirror circuit 420 can correspond to d0, and the second current mirror circuit 430 can correspond to d1. d0 and d1 are both adjacent to the SA array arrangement in the y direction (e.g., adjacent arrangement, or arrangement with a distance of no more than 10 transistor lengths L) to reduce the connection distance with each SA cell.

[0070] Furthermore, the reference unit 410 and the first current mirror circuit 420 can be arranged adjacently, for example, adjacent to each other. Therefore, in addition to including the first current mirror circuit 420, d0 may also include the reference unit 410, thereby providing a basis for the version. Figure 1 Side (e.g.) Figure 5 SA0 (located on the lower side of the middle section) provides a reference voltage V. REF The second current mirror circuit 430 needs to be arranged separately from the first current mirror circuit 420 in order to provide a view of the other side of the layout (e.g., Figure 5 The SA1 cell (on the upper side) provides the reference voltage V. REF In the preferred embodiment illustrated, the second current mirror circuit 430 (i.e., corresponding to d1) can be arranged in the middle of the layout, or near the middle.

[0071] Therefore, by separating the first and second current mirror circuits, the distance between the reference voltage signal and the current mirror circuit used for driving on the layout can be reduced, thereby improving the noise immunity of the circuit.

[0072] Furthermore, the reference unit 410 and the first current mirror circuit 420 can also be arranged adjacent to the power pads, thereby obtaining a more stable control voltage and avoiding initial reference current I. REF Noise is introduced during the generation phase. Here, the power pad can be used to provide the power supply voltage V. DD And other voltages required for memory operations, and capable of achieving Figure 1 The charge pump 360 shown can be used to implement all or part of its functions. Control circuitry arranged near the pads can then be used to achieve... Figure 1 All or part of the functions of the controller 310 shown.

[0073] Furthermore, the present invention designs the circuit configuration of the first current mirror circuit 420 so as to provide a stable reference voltage to at least a portion of SA in a memory block while providing a stable reference current to the second current mirror circuit 430.

[0074] Therefore, in one embodiment, the first current mirror circuit 420 may include a first sub-current mirror circuit for obtaining a reference current I from the reference unit 410. REF Furthermore, the first current mirror circuit 420 may include a second sub-current mirror circuit connected to a mirror branch of the first sub-current mirror circuit. The second sub-current mirror circuit may include three branches, with an input branch used to acquire a reference current I from the first sub-current mirror circuit. REF The first mirror branch is used to mirror the reference current and provides the first reference voltage V to the SA cell based on the mirrored current in this branch. REF1 The second mirror branch can also mirror the reference current and provide the mirrored current of the reference current obtained on this branch to the second current mirror circuit 430.

[0075] In this circuit, the first sub-current mirror circuit can be a current mirror with two branches, each including one MOS transistor. This utilizes the simplest current mirror structure to save chip area. The second sub-current mirror circuit, needing to provide high output impedance and precise current output, requires an additional MOS transistor in each branch to improve the stability of the mirrored current. Therefore, the second sub-current mirror circuit can be a current mirror with three branches, each including two MOS transistors. Since the mirrored branch of the first sub-current mirror circuit is directly connected to the first branch of the second sub-current mirror circuit, the MOS transistors used in the first and second sub-current mirrors have opposite polarities.

[0076] Figure 6 A circuit diagram of a first current mirror circuit according to an embodiment of the present invention is shown. Figure 6 It can be seen as Figure 4 The circuit configuration example of the reference unit 410 and the first current mirror circuit 420 shown can be regarded as a preferred implementation of the first current mirror circuit 420.

[0077] like Figure 6 As shown, the first current mirror circuit 420 includes a first sub-current mirror circuit I, a second sub-current mirror circuit II, and a PMOS transistor MP3. The input branch of the first sub-current mirror circuit I includes a PMOS transistor MP1, and the mirror branch of the first sub-current mirror circuit I includes a PMOS transistor MP2. The reference unit 410 is connected to the PMOS transistor MP1 via an NMOS transistor MN1. The gate of the NMOS transistor MN1 receives the pre-charge voltage V. preThe NMOS transistor MN1 is used to pre-charge the drain of reference cell 410 to a predetermined voltage. Reference cell 410 may have the same structure as the memory cell, for example, it may be a transistor with a control gate. The control gate of reference cell 410 receives a reference word line voltage and generates a reference current I. REF The first sub-current mirror circuit I will reference current I. REF The current mirror is mirrored to PMOS transistor MP2. The second sub-current mirror circuit II includes an input branch, a first mirror branch, and a second mirror branch. The input branch includes NMOS transistors MN2 and MN3. The first mirror branch includes NMOS transistors MN4 and MN5. The second mirror branch includes NMOS transistors MN6 and MN7.

[0078] The input branch of the second sub-current mirror circuit II is connected to the mirror branch of the first sub-current mirror circuit I (i.e., PMOS transistor MP2). Since the mirror branch of the first sub-current mirror circuit I is directly connected to the input branch of the second sub-current mirror circuit II, and the first sub-current mirror circuit I is a current mirror implemented by a PMOS transistor, the second sub-current mirror circuit II is implemented by an NMOS transistor. Unlike the first sub-current mirror I, the second sub-current mirror II uses two MOS transistors arranged on each branch to reduce the difference between the inflow current and the mirror current, and to increase the overall impedance of the current mirror, so as to stably drive a large number of SA cells.

[0079] The first mirror branch of the second sub-current mirror circuit II mirrors the reference current on the input branch. A PMOS transistor MP3 is connected to the first mirror branch of the second sub-current mirror circuit II and configured as a diode. The PMOS transistor MP3 is used to convert the mirrored current on the first mirror branch into a first reference voltage V. REF1 This provides a first reference voltage V to the first group of SA cells connected to the first current mirror circuit 420. REF1 Here, a PMOS transistor MP3 is used for current-to-voltage conversion. Specifically, the source of the PMOS transistor MP3 is connected to the power supply voltage, and the drain and gate are connected. The drain voltage of the PMOS transistor MP3 is the first reference voltage V. REF1 .

[0080] The second mirror branch of the second sub-current mirror circuit II can also mirror the reference current on the input branch and is connected to the second current mirror circuit 430, for example, via a long metal wire (e.g., a wire spanning half the width of the screen), to output the reference current I through the drain of the NMOS transistor MN6. REF . Figure 5The diagram shows the wires connecting d0 and d1, but it should be understood that in the actual layout, the connection between d0 and d1 can have a form suitable for the internal structure of the chip.

[0081] Furthermore, the second current mirror circuit 430 can also be designed to provide a stable reference voltage. Figure 7 A circuit diagram of a second current mirror circuit according to an embodiment of the present invention is shown. Figure 7 As shown, the second current mirror circuit 430 includes a third sub-current mirror circuit, a fourth sub-current mirror circuit, and a PMOS transistor MP6. The input branch of the third sub-current mirror circuit includes a PMOS transistor MP4, and its mirror branch includes a PMOS transistor MP5. The input branch of the third sub-current mirror circuit is connected to the second mirror branch of the second sub-current mirror circuit II. The input branch of the fourth sub-current mirror circuit includes NMOS transistors MN8 and MN9, and its mirror branch includes NMOS transistors MN10 and MN11. The input branch of the fourth sub-current mirror circuit is connected to the mirror branch of the third sub-current mirror circuit, and the mirror branch of the fourth sub-current mirror circuit is connected to the PMOS transistor MP6.

[0082] The fourth sub-current mirror circuit includes an input branch and a mirror branch. The input branch includes NMOS transistors MN8 and MN9, used to obtain a mirror current from the reference current of the first current mirror circuit 420. The mirror branch includes NMOS transistors MN10 and MN11, used to provide the mirror current of the reference current to PMOS transistor MP6. PMOS transistor MP6 is used to convert the mirror current of the reference current in the mirror branch of the fourth sub-current mirror circuit into a second reference voltage V. REF2 And provide it to the second group of SA units.

[0083] exist Figure 7 In the example shown, two MOS transistors are arranged on each branch of the fourth sub-current mirror circuit to reduce the difference between the inflow current and the mirror current, and to increase the overall impedance of the current mirror circuit in order to stably drive a large number of SA cells.

[0084] In a preferred implementation, the first reference voltage provided to the first group of SA units and the second reference voltage provided to the second group of SA units should be the same or approximately the same, so that each SA unit can make a reading determination based on the same reference voltage.

[0085] In other embodiments, a third current mirror circuit can be provided as needed. When providing the third current mirror circuit, a mirror branch can be added to the fourth sub-current mirror circuit of the second current mirror circuit to connect it to the third current mirror circuit. In this case, the first, second, and third current mirror circuits can each be connected to a set of SA units; for example, the first current mirror circuit connects SA0 to SA0. n-1 The second current mirror circuit is connected to SA n ~SA 2n-1 The third current mirror circuit is connected to SA 2n ~ N-1 Here, the preferred value of n is one-third or approximately one-third of N, i.e., n = N / 3. Simultaneously, the positions of the second and third current mirror circuits can be adjusted accordingly, placing them at 1 / 3 and 2 / 3 of the x-direction of the layout, respectively. This further improves the transient response and noise immunity of the reference voltage signal.

[0086] It should be understood that a fourth, fifth, or even more current mirror circuits can be added accordingly, but the addition of the aforementioned current mirror circuits will increase the chip area, so a compromise needs to be considered. It should also be understood that the current mirror circuit of this invention can be applied to other non-volatile memory devices, etc.

[0087] Furthermore, the present invention can also be implemented as an electronic device, including the memory described above.

[0088] In flash memory chips, the reference voltage of the SA cell is obtained by current mirroring the reference current generated by the reference cell to achieve I / V conversion, which has limited output driving capability. Therefore, especially for high-capacity projects, this invention adds a second-stage current mirror in the middle of the SA layout to drive SA loads far from the reference cell. Specifically, a first-stage current mirror is used to mirror the reference current generated by the reference cell to achieve I / V conversion and obtain a reference voltage signal, which is used to drive SA loads close to the reference cell in the layout. Furthermore, through a second current mirroring by the first-stage current mirror, the reference current generated by the reference cell is introduced to the middle of the SA layout. At this point, the second-stage current mirror again obtains the corresponding reference voltage signal through current mirroring, which is used to drive SA loads farther from the reference cell in the layout. Thus, by adding a second-stage current mirror in the middle of the layout, the transient response and noise immunity of the reference voltage signal are effectively improved.

[0089] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A non-volatile memory, comprising: Storage cell array; Multiple word lines and multiple bit lines; Readout amplifier (SA) array; Reference cell, used to generate reference current; First current mirror circuit; as well as Second current mirror circuit, Specifically, the first current mirror circuit mirrors the acquired reference current, converts the mirrored reference current into a first reference voltage, and provides it to the first group of SA cells in the SA array. The first current mirror circuit provides the mirrored current of the reference current to the second current mirror circuit, which mirrors the mirrored current of the reference current and converts it into a second reference voltage, which is then provided to the second group of SA cells in the SA array. The first group of SA cells and the second group of SA cells are connected to the bit lines of different regions in the memory block.

2. The non-volatile memory as described in claim 1, wherein, The SA array includes N SA units arranged along a first direction of the layout, and the first group of SA units includes SA0~SA0 arranged sequentially along the first direction. n-1 The second group of SA units includes SA units arranged sequentially in the first direction. n ~SA N-1 .

3. The non-volatile memory as described in claim 2, wherein, The distance between the first current mirror circuit and the second current mirror circuit and the SA array is less than the distance between the reference cell and the SA array.

4. The non-volatile memory as described in claim 3, wherein, The reference unit and the first current mirror circuit are arranged on one side of the layout in a first direction, and the second current mirror circuit is arranged in the middle of the layout in the first direction.

5. The non-volatile memory as described in claim 4, wherein, The reference cell and the first current mirror circuit are arranged on one side of the power pad in the layout.

6. The non-volatile memory as claimed in claim 1, wherein, The first current mirror circuit includes: The first sub-current mirror circuit is used to obtain the reference current from the reference unit; The second sub-current mirror circuit is used to provide a mirror current of the reference current.

7. The non-volatile memory as claimed in claim 6, wherein, The second sub-current mirror circuit includes an input branch, a first mirror branch, and a second mirror branch, wherein, The input branch is used to obtain the reference current from the first sub-current mirror circuit. The first mirror branch is used to mirror the reference current and provide the first reference voltage to the first group of SA cells based on the mirrored current on the first mirror branch. The second mirror branch is used to mirror the reference current and provide a mirror current of the reference current to the second current mirror circuit.

8. The non-volatile memory as claimed in claim 1, wherein, The second current mirror circuit includes: An input branch is used to obtain a mirror current from the reference current of the first current mirror circuit; and A mirror branch is used to mirror the reference current and provide the second reference voltage to the second group of SA units based on the mirror current on the branch.

9. The non-volatile memory as claimed in claim 1, wherein, The distance between the second group of SA units and the reference unit is greater than the distance between the first group of SA units and the reference unit.

10. The non-volatile memory as claimed in claim 1, wherein, The reference unit has a threshold voltage corresponding to the operation, which is a read operation, an erase verification operation, or a program verification operation.

11. The non-volatile memory of claim 10, wherein, In the erase verification operation, the verification voltage applied to the control gate of the selected memory cell is different from the read voltage in the read operation. Accordingly, the reference current in the erase verification operation is different from the reference current in the read operation, and the reference voltage in the erase verification operation is different from the reference voltage in the read operation.

12. The non-volatile memory according to any one of claims 1-11, wherein, The non-volatile memory is NOR flash memory.

13. An electronic device comprising a memory as claimed in any one of claims 1-12.

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