A solid state disk data read-write and exception recovery method
By integrating an LDPC encoder and an ECC module into the storage controller, combined with dual backup storage technology, the problem of storage system failure caused by multi-bit errors was solved, and stable operation and business continuity were achieved in a high-energy particle radiation environment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU XINSHENG INTELLIGENT TECH CO LTD
- Filing Date
- 2026-06-01
- Publication Date
- 2026-06-26
AI Technical Summary
Existing memory controller chips cannot effectively correct multi-bit errors, leading to memory system failures. In particular, memory reliability is insufficient in high-energy particle radiation environments, making it impossible to guarantee continuous and stable operation.
The storage controller integrates an LDPC encoder for pre-verification, combines it with an ECC error correction module, performs secondary error correction through an LDPC decoder, and uses dual backup storage for critical data. The CPU is used for anomaly handling and system reset recovery.
Without increasing hardware costs, it improves the error correction capability for multi-bit errors, ensures the continuous and stable operation of the storage system under multi-bit flip conditions, avoids business interruption, and improves memory reliability.
Smart Images
Figure CN122290675A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data protection technology, and in particular to a method for reading, writing and recovering data from an anomaly in a solid-state drive. Background Technology
[0002] Currently, most mainstream storage controller chips adopt ECC-based memory error protection mechanisms, supporting only single-bit error correction and double-bit error detection capabilities. When a single-bit soft error occurs in the memory, the controller can complete real-time error correction through the ECC algorithm without affecting the normal operation of the storage disk; when a double-bit error occurs, the controller can only complete error detection and perform abnormal recovery through methods such as resetting the controller.
[0003] For multi-bit errors (≥2 bits), existing ECC mechanisms only have error detection capabilities, not error correction capabilities. Furthermore, the software layer cannot implement effective exception handling and fault isolation, ultimately leading to business interruptions, IO error reports, and other problems. In harsh environments such as high altitudes and strong electromagnetic radiation, high-energy particles can easily cause potential reversals within the storage medium, significantly increasing the incidence of soft errors in memory and greatly increasing the probability of multi-bit errors, which can easily lead to storage system failures.
[0004] In summary, existing storage controller memory only uses single-point ECC protection and does not achieve full-link redundancy and fault tolerance design for memory access. In complex electromagnetic environments, memory reliability bottlenecks are prominent, and breakthroughs are urgently needed in high-reliability hardening technology for the entire path of storage controller memory. Summary of the Invention
[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for solid-state drive data reading, writing and anomaly recovery, which realizes anomaly repair processing when multiple bits flip, ensures that the storage system continues to work stably under multiple bit flip conditions, and does not interrupt IO services, while not significantly increasing hardware costs.
[0006] The objective of this invention is achieved through the following technical solution: A method for solid-state drive data read / write and anomaly recovery, applied in a storage controller, includes: The SATA controller receives a data write command from the host. Based on the data write command, it extracts the host write data, the context of the data write command, and the status information of the write data from the host. It stores the remaining data, excluding the host read / write data, using dual backup storage. The SATA controller performs LDPC verification calculation on the host write data using an integrated LDPC encoder, generates an LDPC checksum, and stores the host write data and the LDPC checksum together in static memory. The flash memory read / write controller reads the host write data from the static memory and writes it to the NAND flash memory. The SATA controller receives data read commands from the host and forwards them directly to the flash memory read / write controller. The flash memory read / write controller reads data from the NAND flash memory, decodes the read data using an integrated LDPC decoder, and writes the decoded normal data into static memory. The SATA controller then reads normal data from static memory and returns it to the host. When the flash memory read / write controller reads host-written data from static memory or the SATA controller reads normal data from static memory, it identifies erroneous data through the integrated ECC error correction module and reports the identified erroneous data anomaly information to the CPU. The CPU then performs anomaly processing according to different error types.
[0007] Furthermore, the internally integrated ECC error correction module identifies erroneous data and reports the identified error data anomaly information to the CPU. The CPU then performs anomaly handling based on different error types, including the following sub-steps: The ECC error correction module identifies error data and sends the error data type, error data flip-by bit, and error data address information to the CPU. The CPU determines whether a single-bit data error has occurred based on the number of bits flipped in the erroneous data. If so, it rereads the data at the erroneous address and writes it back. If not, it further determines whether the erroneous data address is in static memory or ordinary memory. If it occurs in ordinary memory, it performs a system reset and resumes I / O read / write operations. If it occurs in static memory, for data that has been dual-backed up, it restores the data by reading the backup area. For host read / write data, if the data flipped during a read operation, it performs a reread operation; if the data flipped during a write operation, it first performs error correction through the LDPC decoder and then performs a rewrite operation on the corrected data.
[0008] Furthermore, if the incident occurs in ordinary memory, a system reset is performed and I / O read / write operations are resumed, including the following sub-steps: Trigger the power-on initialization process to accelerate system rebuild by utilizing fast rebuild information in static memory and host command context. The SATA controller completes read I / O service recovery and write I / O service recovery based on the information in static memory: When recovering read I / O service, for read I / O services that have not yet started transmission, data is read from the backend again; for read I / O services that have already started transmission, the remaining data is used to reread the uncompleted portion. When recovering write I / O service, data is rewritten for completed write I / O services; for incomplete write I / O services, the SATA controller is configured to continue receiving data.
[0009] Furthermore, the ECC error correction module is integrated into the general memory and static memory of the storage controller, and is implemented using a single-bit error correction code and a multi-bit error detection code.
[0010] Furthermore, the SATA controller, flash memory read / write controller, CPU, general memory, and static memory transmit data via a bus.
[0011] The beneficial effects of this invention are: This invention integrates an LDPC encoder into the SATA front end, pre-completing LDPC verification calculations. When a 2-bit or higher error occurs, secondary error correction can be performed via LDPC before data read / write operations can be completed. This effectively increases 2-bit error correction capability and solves the error correction problem of multi-bit flips without affecting storage system performance. Furthermore, dual backup storage is used for critical data with small data volumes, such as rapidly reconstructed information and host command context. In the event of a 2-bit error, recovery can be directly achieved through backup. Dual backup can be flexibly implemented in software or hardware; software implementation reduces system overhead, while hardware implementation improves data recovery performance. Attached Figure Description
[0012] Figure 1 This is a schematic diagram of the storage controller in this invention. Detailed Implementation
[0013] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0014] See Figure 1 The present invention provides a technical solution: A method for solid-state drive data read / write and anomaly recovery, applied in a storage controller, includes: The SATA controller receives a data write command from the host. Based on the data write command, it extracts the host write data, the context of the data write command, and the status information of the write data from the host. It stores the remaining data, excluding the host read / write data, using dual backup storage. The SATA controller performs LDPC verification calculation on the host write data using an integrated LDPC encoder, generates an LDPC checksum, and stores the host write data and the LDPC checksum together in static memory. The flash memory read / write controller reads the host write data from the static memory and writes it to the NAND flash memory. The SATA controller receives data read commands from the host and forwards them directly to the flash memory read / write controller. The flash memory read / write controller reads data from the NAND flash memory, decodes the read data using an integrated LDPC decoder, and writes the decoded normal data into static memory. The SATA controller then reads normal data from static memory and returns it to the host. When the flash memory read / write controller reads host-written data from static memory or the SATA controller reads normal data from static memory, it identifies erroneous data through the integrated ECC error correction module and reports the identified erroneous data anomaly information to the CPU. The CPU then performs anomaly processing according to different error types.
[0015] Error data is identified through the internally integrated ECC error correction module, and the identified error data anomaly information is reported to the CPU. The CPU performs anomaly handling according to different error types, including the following sub-steps: The ECC error correction module identifies error data and sends the error data type, error data flip-by bit, and error data address information to the CPU. The CPU determines whether a single-bit data error has occurred based on the number of bits flipped in the erroneous data. If so, it rereads the data at the erroneous address and writes it back. If not, it further determines whether the erroneous data address is in static memory or ordinary memory. If it occurs in ordinary memory, it performs a system reset and resumes I / O read / write operations. If it occurs in static memory, for data that has been dual-backed up, it restores the data by reading the backup area. For host read / write data, if the data flipped during a read operation, it performs a reread operation; if the data flipped during a write operation, it first performs error correction through the LDPC decoder and then performs a rewrite operation on the corrected data.
[0016] This invention integrates an LDPC encoder into the SATA front end, pre-completing LDPC verification calculations. When a 2-bit or higher error occurs, secondary error correction can be performed via LDPC before data read / write operations can be completed. This effectively increases 2-bit error correction capability and solves the error correction problem of multi-bit flips without affecting storage system performance. Furthermore, dual backup storage is used for critical data with small data volumes, such as rapidly reconstructed information and host command context. In the event of a 2-bit error, recovery can be directly achieved through backup. Dual backup can be flexibly implemented in software or hardware; software implementation reduces system overhead, while hardware implementation improves data recovery performance.
[0017] If the issue occurs in regular memory, a system reset will be performed and I / O read / write operations will be restored, including the following sub-steps: Trigger the power-on initialization process to accelerate system rebuild by utilizing fast rebuild information in static memory and host command context. The SATA controller completes read I / O service recovery and write I / O service recovery based on the information in static memory: When recovering read I / O service, for read I / O services that have not yet started transmission, data is read from the backend again; for read I / O services that have already started transmission, the remaining data is used to reread the uncompleted portion. When recovering write I / O service, data is rewritten for completed write I / O services; for incomplete write I / O services, the SATA controller is configured to continue receiving data.
[0018] During this process, the SATA controller maintains its original working state, does not perform initialization operations, and continues to process host I / O services directly based on the reconstructed information, achieving uninterrupted service.
[0019] The ECC error correction module is integrated in the general memory and static memory of the storage controller, and is implemented using single-bit error correction and multi-bit error detection error correction codes.
[0020] The SATA controller, flash memory read / write controller, CPU, general memory, and static memory transmit data via a bus.
[0021] This invention is based on mature storage controller technologies such as ECC and LDPC and performs system-level optimization. Without significantly changing the hardware structure, it significantly improves the error correction capability of memory bit flips without significantly increasing costs, making it suitable for application scenarios with high electromagnetic radiation and high reliability requirements, such as aerospace.
[0022] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A method for solid-state drive data read / write and anomaly recovery, applied in a storage controller, characterized in that, include: The SATA controller receives a data write command sent by the host. Based on the data write command, it extracts the host write data, the context of the data write command, and the status information of the write data from the host. It stores the remaining data, except for the host read / write data, using dual backup storage. The SATA controller performs LDPC checksum calculation on the host write data through an integrated LDPC encoder, generates an LDPC checksum, and stores the host write data and the LDPC checksum together in static memory. The flash memory read / write controller reads the host-written data from static memory and writes it to the NAND flash memory; The SATA controller receives data read commands sent by the host and forwards them directly to the flash memory read / write controller. The flash memory read / write controller reads data from the NAND flash memory and decodes the read data using an integrated LDPC decoder, then writes the decoded normal data into static memory. The SATA controller reads normal data from static memory and returns it to the host; When the flash memory read / write controller reads host-written data from static memory or the SATA controller reads normal data from static memory, it identifies erroneous data through the integrated ECC error correction module and reports the identified erroneous data anomaly information to the CPU. The CPU then performs anomaly processing according to different error types.
2. The method for solid-state drive data reading, writing, and anomaly recovery according to claim 1, characterized in that: The process involves identifying error data through an integrated ECC error correction module and reporting the identified error data anomaly information to the CPU. The CPU then performs anomaly processing based on different error types, including the following sub-steps: The ECC error correction module identifies error data and sends the error data type, error data flip-by bit, and error data address information to the CPU. The CPU determines whether a single-bit data error has occurred based on the number of bits flipped in the erroneous data. If so, it rereads the data at the erroneous address and writes it back. If not, it further determines whether the erroneous data address is in static memory or ordinary memory. If it occurs in ordinary memory, it performs a system reset and resumes I / O read and write operations. If it occurs in static memory, for data that has been double-backed up, it restores the data by reading the backup area. For host read and write data, if the data flipping occurs during reading, it performs a reread operation. If a data flip occurs during writing, the data is first corrected using an LDPC decoder, and then rewritten.
3. The method for solid-state drive data reading, writing, and anomaly recovery according to claim 2, characterized in that: If the issue occurs in regular memory, a system reset will be performed and I / O read / write operations will be restored, including the following sub-steps: Trigger the power-on initialization process to accelerate system rebuild by utilizing fast rebuild information in static memory and host command context. The SATA controller completes read I / O service recovery and write I / O service recovery based on the information in static memory: When recovering read I / O service, for read I / O services that have not yet started transmission, data is read from the backend again; for read I / O services that have already started transmission, the remaining data is used to reread the uncompleted portion. When recovering write I / O service, data is rewritten for completed write I / O services; for incomplete write I / O services, the SATA controller is configured to continue receiving data.
4. The method for solid-state drive data reading, writing, and anomaly recovery according to claim 3, characterized in that: The ECC error correction module is integrated in the general memory and static memory of the storage controller, and is implemented using single-bit error correction and multi-bit error detection error correction codes.
5. The solid-state drive data read / write and anomaly recovery method according to claim 3, characterized in that: The SATA controller, flash memory read / write controller, CPU, general memory, and static memory transmit data via a bus.