Dual-gate thin film transistor and display device having the same

Abstract

This disclosure provides a dual-gate thin-film transistor and a display device having the dual-gate thin-film transistor. The dual-gate thin-film transistor includes a first thin-film transistor and a second thin-film transistor connected in series, wherein a first gate electrode and a second gate electrode are connected to each other. A first channel portion and a first gate electrode of the first thin-film transistor overlap each other, wherein a first insulating layer is disposed between the first channel portion and the first gate electrode, and a second channel portion and a second gate electrode of the second thin-film transistor overlap each other, including a plurality of insulating layers of the first and second insulating layers disposed between the second channel portion and the second gate electrode.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0196774, filed on December 26, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to dual-gate thin-film transistors and display devices including the dual-gate thin-film transistors. Background Technology

[0004] Display devices include thin-film transistors (TFTs) that serve as switching or driving elements for pixel circuits and driving circuits in a display panel.

[0005] As operating time increases, thin-film transistors may degrade and their reliability may decrease due to high drain current stress (HDCS) caused by the application of high potential voltage.

[0006] If thin-film transistors deteriorate and become less reliable, the reliability of the display device or the image quality may deteriorate. Summary of the Invention

[0007] This disclosure provides a dual-gate thin-film transistor capable of reducing the degradation of thin-film transistors and a display device including the dual-gate thin-film transistor.

[0008] The problems to be solved by this disclosure are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art to which the technical concept of this disclosure pertains from the following description.

[0009] According to one embodiment of this disclosure, a dual-gate thin-film transistor may include: a first thin-film transistor including a first gate electrode, a first drain electrode, a first source electrode, and a first channel portion between the first drain electrode and the first source electrode; and a second thin-film transistor including a second gate electrode connected to the first gate electrode, a second drain electrode connected to the first source electrode, a second source electrode, and a second channel portion between the second drain electrode and the second source electrode, wherein the first channel portion and the first gate electrode overlap each other, wherein a first insulating layer is located between the first channel portion and the first gate electrode, and the second channel portion and the second gate electrode overlap each other, including a plurality of insulating layers of the first insulating layer and the second insulating layer located between the second channel portion and the second gate electrode.

[0010] According to one embodiment of the present disclosure, a dual-gate thin-film transistor may include: a first thin-film transistor including a first gate electrode, a first drain electrode, a first source electrode, and a first channel portion between the first drain electrode and the first source electrode; and a second thin-film transistor including a second gate electrode connected to the first gate electrode, a second drain electrode connected to the first source electrode, a second source electrode, and a second channel portion between the second drain electrode and the second source electrode, wherein the second thin-film transistor further includes a second light-shielding electrode overlapping the second channel portion, and the first gate electrode and the second gate electrode are disposed in the same layer and integrally formed.

[0011] According to one embodiment of this disclosure, the display may include a display panel and a gate driving circuit for driving gate lines of the display panel. The gate driving circuit includes a stage circuit for outputting gate signals to each of the gate lines. The stage circuit includes: an output portion configured to output a gate signal via a gate output line in response to control by a first control node and a second control node; a first charging portion for charging the first control node; a first discharging portion for discharging the first control node; a second charging portion for charging the second control node; and a second discharging portion for discharging the second control node. The second charging portion may include a dual-gate thin-film transistor connected between a high-potential power supply line supplied with a high-potential power supply voltage and the second control node. The first gate electrode, the second gate electrode, and the first drain electrode of the dual-gate thin-film transistor are connected to the high-potential power supply line, and a second source electrode may be connected to the second control node.

[0012] The display device according to the embodiment includes a plurality of sub-pixels disposed in a display area of ​​a display panel, wherein each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit configured to independently drive the light-emitting element, and the pixel circuit includes: a driving transistor configured to drive the light-emitting element and a sampling thin-film transistor configured to connect the gate electrode and the drain electrode of the driving transistor, and the sampling thin-film transistor may include a dual-gate thin-film transistor.

[0013] According to one embodiment of this disclosure, a dual-gate thin-film transistor may include: a first thin-film transistor including a first gate electrode, a first drain electrode, a first source electrode, and a first channel portion between the first drain electrode and the first source electrode; and a second thin-film transistor including a second gate electrode connected to the first gate electrode, a second drain electrode connected to the first source electrode, a second source electrode, and a second channel portion between the second drain electrode and the second source electrode. The first channel portion and the second channel portion may be formed on the same layer. A first distance between the first channel portion and the first gate electrode may be smaller than a second distance between the second channel portion and the second gate electrode.

[0014] In addition to the means for solving the problems mentioned above, specific details of various embodiments according to this disclosure are also included in the following description and drawings. Attached Figure Description

[0015] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and constituting a part of this application, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure. In the drawings:

[0016] Figure 1A and Figure 1B This is an equivalent circuit diagram of a thin-film transistor according to one embodiment of the present disclosure.

[0017] Figure 2 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure.

[0018] Figure 3 It shows along Figure 2 The diagram shows a cross-sectional view of the thin-film transistor structure along lines A1-A1' and A2-A2'.

[0019] Figure 4 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure.

[0020] Figure 5 It shows along Figure 4 The diagram shows a cross-sectional view of the thin-film transistor structure along line B-B'.

[0021] Figure 6 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure.

[0022] Figure 7 It shows along Figure 6 The diagram shows a cross-sectional view of the thin-film transistor structure with lines C1-C1' and C2-C2'.

[0023] Figure 8 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure.

[0024] Figure 9 It shows along Figure 8 The diagram shows a cross-sectional view of the thin-film transistor structure along line D-D'.

[0025] Figure 10 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure.

[0026] Figure 11 It shows along Figure 10 The diagram shows a cross-sectional view of the thin-film transistor structure along line E-E'.

[0027] Figure 12 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure.

[0028] Figure 13 It shows along Figure 12 The diagram shows a cross-sectional view of the thin-film transistor structure along line F-F'.

[0029] Figure 14A and Figure 14B This is a graph showing the voltage distribution results of the dual-gate thin-film transistor according to the comparative example and embodiment.

[0030] Figure 15 This is a graph showing the degradation amount of the first thin-film transistor in the dual-gate thin-film transistors according to the comparative example and the embodiment, according to the stress time.

[0031] Figure 16 This is a graph showing the voltage relationship between the first thin-film transistor and the second thin-film transistor in a dual-gate thin-film transistor according to an embodiment of the present disclosure, based on the thickness of the insulating layer of the second thin-film transistor.

[0032] Figure 17 This is an equivalent circuit diagram of a thin-film transistor according to one embodiment of the present disclosure.

[0033] Figure 18 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure.

[0034] Figure 19 It shows along Figure 18 The diagram shows a cross-sectional view of the thin-film transistor structure along line G-G'.

[0035] Figure 20 This is a graph showing the voltage distribution results of the dual-gate thin-film transistor according to the comparative example and embodiment.

[0036] Figure 21 This is an equivalent circuit diagram of a thin-film transistor according to one embodiment of the present disclosure.

[0037] Figure 22 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure.

[0038] Figure 23 It shows along Figure 22 The diagram shows a cross-sectional view of the thin-film transistor structure along line H-H'.

[0039] Figure 24 This is a graph showing the voltage distribution results of the dual-gate thin-film transistor according to the comparative example and embodiment.

[0040] Figure 25 This is a schematic diagram illustrating the configuration of a display device according to one embodiment of the present disclosure.

[0041] Figure 26 This is an equivalent circuit diagram showing the stage configuration of a gate drive circuit according to one embodiment of the present disclosure.

[0042] Figure 27 This is an equivalent circuit diagram illustrating a pixel circuit configuration according to one embodiment of the present disclosure. Detailed Implementation

[0043] The advantages and features of this specification, as well as methods for achieving these advantages and features, will become clearer from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is limited only by the scope of the claims.

[0044] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings used to illustrate embodiments of this specification are illustrative and are not limited to what is shown in this specification. Throughout the specification, the same reference numerals refer to the same parts. Furthermore, in describing this specification, detailed descriptions of related known technologies will be omitted if they are deemed unnecessarily obscuring the spirit of this specification. When terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. When a part is represented in the singular, it includes the plural unless otherwise specified.

[0045] When interpreting a component, it is assumed to include the error range, even if there is no separate explicit description of the error range.

[0046] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "over", "below", "side", etc., one or more other parts may be located between the two parts unless, for example, "exactly" or "directly" is used.

[0047] When describing temporal relationships, if temporal continuity is described as “after,” “continuously,” “next,” or “before,” it can include discontinuous cases, as long as “immediately” or “directly” is not used.

[0048] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the "first" component mentioned below can also be the "second" component within the technical scope of this specification.

[0049] When describing the components of this specification, terms such as first, second, A, B, a, b, etc., may be used. These terms are intended only to distinguish a component from other components, and the nature, order, sequence, or number of components is not limited by these terms. When a component is described as "connected," "coupled," or "attached" to another component, it should be understood that the component may be directly connected or attached to another component, but in the absence of any specific and explicit description, other components may also be "between" each indirectly connected or attached component.

[0050] "At least one" should be understood to include any combination of one or more of the associated components. For example, "at least one of the first component, the second component, and the third component" can be understood to include not only the first component, the second component, or the third component, but also any combination of two or more of the first component, the second component, and the third component.

[0051] Individual features of the various embodiments described herein may be combined in part or in whole, or combined with each other, and may be technically linked and operated in various ways. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0052] Preferred embodiments will be described below with reference to the accompanying drawings. For ease of explanation, the proportions of the components depicted in the drawings differ from actual proportions, and therefore the embodiments are not limited to the proportions depicted in the drawings.

[0053] Figure 1A and Figure 1B This is an equivalent circuit diagram of a thin-film transistor according to one embodiment of the present disclosure.

[0054] Reference Figure 1A and Figure 1BAccording to one embodiment, the thin-film transistor may have a dual-gate structure and include a first thin-film transistor Ta and a second thin-film transistor Tb connected in series.

[0055] The first thin-film transistor Ta may include a gate electrode GE1, a drain electrode DE1, and a source electrode SE1, and the second thin-film transistor Tb may include a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The source electrode SE1 of the first thin-film transistor Ta and the drain electrode DE2 of the second thin-film transistor Tb may be connected in series. The first thin-film transistor Ta and the second thin-film transistor Tb may have a dual-gate structure in which the gate electrodes GE1 and GE2 are connected.

[0056] Reference Figure 1B According to one embodiment, the dual-gate thin-film transistor Ta-Tb may further include light-shielding electrodes LS1 and LS2 overlapping with the gate electrodes GE1 and GE2. The light-shielding electrodes LS1 and LS2 may be connected to the source electrode SE2 of the second thin-film transistor Tb.

[0057] According to one embodiment, the dual-gate thin-film transistor Ta-Tb can have a diode structure, wherein the gate electrodes GE1 and GE2 are connected to the drain electrode DE1 of the first thin-film transistor Ta.

[0058] The dual-gate thin-film transistors Ta and Tb can be driven in the on-state by applying a high-potential power supply voltage VDD as the gate voltage VG and drain voltage VD, and by applying a low-potential power supply voltage VSS as the source voltage VS.

[0059] The drain-source voltage Vds applied to the dual-gate thin-film transistors Ta-Tb is divided into the drain-source voltages Vds1 and Vds2 of the first thin-film transistor Ta and the second thin-film transistor Tb, so that the dual-gate thin-film transistors Ta and Tb can reduce the high drain current stress (HDCS) caused by the application of the high potential power supply voltage VDD.

[0060] By applying a high-potential power supply voltage VDD to the gate electrode GE1 and the drain electrode DE1, the first thin-film transistor Ta can operate in saturation mode (saturation mode, Vgs1=Vds1, Vgs1-Vth < Vds1), and the second thin-film transistor Tb can operate in linear mode (linear mode, Vgs2-Vth > Vds2).

[0061] The distribution of the drain-source voltage Vds1 applied to the first thin-film transistor Ta in saturation mode can be greater than the distribution of the drain-source voltage Vds2 applied to the second thin-film transistor Tb in linear mode. As the drive time (stress time) increases, the degradation (Vth offset) of the first thin-film transistor Ta in saturation mode may become greater than the degradation (Vth offset) of the second thin-film transistor Tb in linear mode, and therefore, the degradation (Vth offset) of the dual-gate thin-film transistor Ta-Tb may become larger.

[0062] To reduce the degradation of the first thin-film transistor Ta, the dual-gate thin-film transistor Ta-Tb according to one embodiment may have a heterogeneous resistor structure. This heterogeneous resistor structure can increase the voltage Vds2 distributed to the second thin-film transistor Tb and decrease the voltage Vds1 distributed to the first thin-film transistor Ta. The dual-gate thin-film transistor Ta-Tb according to one embodiment may have a heterogeneous resistor structure, wherein the gate active capacitance (Cox_b, Figure 3 The gate active capacitance (Cox_a) of the first thin-film transistor Ta is less than that of the first thin-film transistor Ta. Figure 3 This makes the resistance of the second thin-film transistor Tb greater than the resistance of the first thin-film transistor Ta.

[0063] Reference Figures 3 to 13 A heterogeneous resistor structure for a dual-gate thin-film transistor according to an embodiment of the present invention is described in detail.

[0064] Figure 2 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure. Figure 3 It shows along Figure 2 The diagram shows a cross-sectional view of the thin-film transistor structure along lines A1-A1' and A2-A2'. Figure 4 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure, and Figure 5 It shows along Figure 4 The diagram shows a cross-sectional view of the thin-film transistor structure along line B-B'.

[0065] Reference Figures 2 to 5 According to the embodiment, the first thin-film transistor Ta and the second thin-film transistor Tb constituting the dual-gate thin-film transistor can have a heterogeneous capacitor structure, i.e., a heterogeneous resistor structure, wherein the gate electrodes GE1 and GE2 are disposed in different layers, such that the spacing between the gate electrodes GE1 and GE2 and the active layer ACT is different.

[0066] The first thin-film transistor Ta may include a first light-shielding electrode LS1 on a substrate SUB, a buffer layer BF covering the first light-shielding electrode LS1, an active layer ACT on the buffer layer BF, a gate insulating layer GI covering the active layer ACT, a first gate electrode GE1 on the gate insulating layer GI, a first drain electrode DE1 and a first source electrode SE1 disposed on a conductive portion facing each other in a first direction (channel length direction), wherein a first channel portion CA1 in the active layer ACT is located between the first drain electrode DE1 and the first source electrode SE1.

[0067] The second thin-film transistor Tb may include a second light-shielding electrode LS2 on a substrate SUB, a buffer layer BF covering the second light-shielding electrode LS2, an active layer ACT on the buffer layer BF, a gate insulating layer GI covering the active layer ACT, an interlayer insulating layer ILD on the gate insulating layer GI, a gate electrode GE2 on the interlayer insulating layer ILD, a second drain electrode DE2 and a second source electrode SE2 configured to face each other in a first direction (channel length direction), wherein the second channel portion CA2 in the active layer ACT is located between the second drain electrode DE2 and the second source electrode SE2.

[0068] The first gate electrode GE1 of the first thin-film transistor Ta and the second gate electrode GE2 of the second thin-film transistor Tb can be connected through a contact hole CH3 penetrating the interlayer insulating layer (ILD). The first gate electrode GE1 can extend in a first direction (channel length direction) to overlap with the second gate electrode GE2, and the first gate electrode GE1 and the second gate electrode GE2 can be connected through the contact hole CH3 at the overlapping portion.

[0069] The first source electrode SE1 of the first thin-film transistor Ta and the second drain electrode DE2 of the second thin-film transistor Tb can be integrated by sharing the conductive portion of the active layer ACT between the first channel portion CA1 and the second channel portion CA2.

[0070] The dual-gate thin-film transistor Ta-Tb may also include a drain connection electrode SD1 and a source connection electrode SD2. The drain connection electrode SD1 and the source connection electrode SD2 are connected to the first drain electrode DE1 and the second source electrode SE2 through the first contact hole CH1 and the second contact hole CH2 that penetrate the interlayer insulating layer ILD and the gate insulating layer GI, respectively, and are disposed on the interlayer insulating layer ILD.

[0071] Reference Figure 4 and Figure 5The dual-gate thin-film transistor Ta-Tb may also include a connection electrode SD3. The connection electrode SD3 is disposed on the interlayer insulating layer ILD and is connected to the conductive portion of the active layer ACT, which integrates the first source electrode SE1 and the second drain electrode DE2, through a contact hole CH5 that penetrates the interlayer insulating layer ILD and the gate insulating layer GI, thereby reducing the resistance of the conductive portion.

[0072] The active layer ACT can have a structure in which channel portions CA1 and CA2 with semiconductor properties and conductive portions with conductive properties are integrally formed. The conductive portions can be regions in which the active layer ACT is selectively conductive through ion implantation, plasma treatment, heat treatment, or the like. The conductive portions of the active layer ACT can include the first drain electrode DE1 and the first source electrode SE1 of the first thin-film transistor Ta, and the second drain electrode DE2 and the second source electrode SE2 of the second thin-film transistor Tb. The first drain electrode DE1 can be represented as the first conductive portion, the first source electrode SE1 and the second drain electrode DE2 can be represented as the second conductive portion, and the second source electrode SE2 can be represented as the third conductive portion.

[0073] The active layer ACT can have a structure in which the length in the first direction (channel length direction) is longer than the width in the second direction (channel width direction). In the active layer ACT, the first drain electrode DE1, the first channel portion CA1, the first source electrode SE1, the second drain electrode DE2, the second channel portion CA2, and the second source electrode SE2 can be arranged in parallel in the first direction (channel length direction).

[0074] The drain electrode SD1, the first gate electrode GE1, the second gate electrode GE2 and the source electrode SD2 can be spaced apart from each other in a first direction (channel length direction) and arranged in parallel to each other in the first direction.

[0075] Light-shielding electrodes LS1 and LS2 overlap with channel portions CA1 and CA2, respectively, and can protect channel portions CA1 and CA2 by blocking light incident through the substrate SUB. Light-shielding electrodes LS1 and LS2 can overlap with gate electrodes GE1 and GE2, respectively. Channel portions CA1 and CA2 can be integrated and can have a source contact structure that connects to the source connection electrode SD2 through contact holes penetrating multiple insulating layers ILD and GI. Light-shielding electrodes LS1 and LS2 can be omitted.

[0076] The first gate electrode GE1 of the first thin-film transistor Ta can be disposed on the gate insulating layer GI and overlap with the first channel portion CA1, wherein the gate insulating layer GI is located between the first gate electrode GE1 and the first channel portion CA1. The second gate electrode GE2 of the second thin-film transistor Tb can be disposed on the interlayer insulating layer ILD and overlap with the second channel portion CA2, wherein the gate insulating layer GI and the interlayer insulating layer ILD are located between the second gate electrode GE2 and the second channel portion CA2.

[0077] The gate insulating layer GI and the interlayer insulating layer ILD can be represented as the first gate insulating layer and the second gate insulating layer.

[0078] The gate electrode GE1 and active layer ACT of the first thin-film transistor Ta may have a gap d1 corresponding to the thickness of an insulating layer GI, and the gate electrode GE2 and active layer ACT of the second thin-film transistor Tb may have a gap (d2, d2>d1) corresponding to the thickness of the two insulating layers GI and ILD.

[0079] Therefore, in a dual-gate thin-film transistor according to one embodiment, the second capacitance Cox_b between the gate electrode GE2 of the second thin-film transistor Tb and the active layer ACT can be smaller than the first capacitance Cox_a between the gate electrode GE1 of the first thin-film transistor Ta and the active layer ACT. Therefore, the resistance of the second thin-film transistor Tb can be greater than the resistance of the first thin-film transistor Ta.

[0080] Therefore, the voltage Vds2 allocated to the second thin-film transistor Tb increases, and the voltage Vds1 allocated to the first thin-film transistor Ta decreases, so that the difference between the voltages Vds1 and Vds2 allocated to the first thin-film transistor Ta and the second thin-film transistor Tb can be reduced. Thus, the stress and degradation of the first thin-film transistor Ta in saturation mode can be reduced, and the overall stress and degradation of the dual-gate thin-film transistors Ta and Tb can also be reduced.

[0081] The buffer layer (BF), gate insulating layer (GI), and interlayer insulating layer (ILD) can be represented as multiple insulating layers. Each of the multiple insulating layers can have a single layer or multiple layers comprising insulating material. The buffer layer (BF) and gate insulating layer (GI) can be formed of silicon oxide (SiOx) or aluminum oxide (Al2O3) having a low hydrogen content. The interlayer insulating layer (ILD) can have a single layer or multiple layers comprising at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

[0082] The active layer ACT can include any of the following: amorphous silicon semiconductor materials, polycrystalline silicon semiconductor materials, and metal oxide semiconductor materials. For example, the semiconductor layer ACT may include at least one of the following: IGZO (InGaZnO) based metal oxide semiconductor material, IGO (InGaO) based metal oxide semiconductor material, IGZTO (InGaZnSnO) based metal oxide semiconductor material, GZTO (GaZnSnO) based metal oxide semiconductor material, GZO (GaZnO) based metal oxide semiconductor material, GO (GaO) based metal oxide semiconductor material, TO (SnO) based metal oxide semiconductor material, ITO (InSnO) based metal oxide semiconductor material, ITZO (InSnZnO) based metal oxide semiconductor material, IZO based metal oxide semiconductor material, ZO (ZnO) based metal oxide semiconductor material, IO (InO) based metal oxide semiconductor material, InO (InO) based metal oxide semiconductor material, ZnO based metal oxide semiconductor material, and FIZO (FeInZnO) based metal oxide semiconductor material. The active layer ACT can have a single-layer structure or a multilayer structure in which at least two oxide semiconductor layers are stacked.

[0083] The light-shielding electrodes LS1 and LS2 can be formed from a first metal layer (light-shielding metal layer). The gate electrode GE1 can be formed from a second metal layer (gate metal layer). The gate electrode GE2, the drain connection electrode SD1, and the source connection electrode SD2 can be formed from a third metal layer (source / drain metal layer). Each of the first, second, and third metal layers can have a single-layer structure including at least one of aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), copper (Cu), gold (Au), silver (Ag), and alloys thereof, or can have a multilayer structure in which at least two metal layers are stacked.

[0084] Figure 6 This is a plan view illustrating a thin-film transistor structure according to an embodiment of the present disclosure. Figure 7 It shows along Figure 6 The diagram shows a cross-sectional view of the thin-film transistor structure along lines C1-C1' and C2-C2'. Figure 8 This is a plan view illustrating a thin-film transistor structure according to an embodiment of the present disclosure, and Figure 9 It shows along Figure 8 The diagram shows a cross-sectional view of the thin-film transistor structure along line D-D'. Figure 10 This is a plan view illustrating a thin-film transistor structure according to an embodiment of the present disclosure. Figure 11 It shows along Figure 10The diagram shows a cross-sectional view of the thin-film transistor structure along line E-E'. Figure 12 This is a plan view illustrating a thin-film transistor structure according to an embodiment of the present disclosure, and Figure 13 It shows along Figure 12 The diagram shows a cross-sectional view of the thin-film transistor structure along line F-F'.

[0085] According to Figures 2 to 5 Compared to the dual-gate thin-film transistor of one embodiment shown, according to Figures 6 to 9 The dual-gate thin-film transistor shown in one embodiment differs in the arrangement of the gate electrode GE21 of the second thin-film transistor Tb.

[0086] according to Figures 10 to 13 The difference between the dual-gate thin-film transistor of the illustrated embodiment is that the arrangement of the gate electrode GE21, source connection electrode SD21, and connection electrode SD31 of the second thin-film transistor Tb differs from that according to the embodiment... Figures 2 to 5 The dual-gate thin-film transistor of the embodiment shown.

[0087] therefore, Figures 6 to 13 The focus will be on explanation and Figures 2 to 5 Different configurations will be provided, and descriptions of duplicate configurations will be omitted.

[0088] Reference Figures 6 to 13 According to one embodiment, the dual-gate thin-film transistor may further include a planarization layer PLN covering the drain connection electrode SD1 and the source connection electrode SD2 on the interlayer insulating layer ILD, and a passivation layer PAS on the planarization layer PLN. The second gate electrode GE21 of the second thin-film transistor Tb may be disposed on the planarization layer PLN and may be connected to the first gate electrode GE1 of the first thin-film transistor Ta through a contact hole CH31 penetrating the planarization layer PLN and the interlayer insulating layer ILD.

[0089] The planarization layer PLN may include organic insulating materials, and the passivation layer PAS may include inorganic insulating materials.

[0090] Reference Figures 10 to 13 The source connection electrode SD21 of the second thin-film transistor Tb can be disposed on the planarization layer PLN in the same way as the second gate electrode GE21. The source connection electrode SD21 can be connected to the second source electrode SE2 of the active layer ACT through the contact hole CH21 that penetrates the planarization layer PLN, the interlayer insulating layer ILD, and the gate insulating layer GI.

[0091] Reference Figure 12 and Figure 13The connection electrode SD31 can be disposed on the planarization layer PLN in the same manner as the second gate electrode GE2 and the source connection electrode SD21. The connection electrode SD31 can be connected to the first source electrode SE1 and the second drain electrode DE2 of the active layer ACT through the contact hole CH51 that penetrates the planarization layer PLN, the interlayer insulating layer ILD, and the gate insulating layer GI.

[0092] The gate insulating layer GI, the interlayer insulating layer ILD, and the planarization layer PLN can be represented as the first insulating layer, the second insulating layer, and the third insulating layer.

[0093] Reference Figures 6 to 13 The gate electrode GE1 and active layer ACT of the first thin film transistor Ta may have a gap d1 corresponding to the thickness of an insulating layer GI, and the gate electrode GE21 and active layer ACT of the second thin film transistor Tb may have a gap (d3, d3>d1) corresponding to the thickness of the three insulating layers GI, ILD and PLN.

[0094] Therefore, in a dual-gate thin-film transistor according to one embodiment, the second capacitance Cox_b between the gate electrode GE21 of the second thin-film transistor Tb and the active layer ACT can be smaller than the first capacitance Cox_a between the gate electrode GE1 of the first thin-film transistor Ta and the active layer ACT. Therefore, the resistance of the second thin-film transistor Tb can be greater than the resistance of the first thin-film transistor Ta.

[0095] Therefore, the voltage Vds1 allocated to the first thin-film transistor Ta can be reduced, thereby reducing the stress and degradation of the first thin-film transistor Ta, and thus reducing the overall stress and degradation of the dual-gate thin-film transistor Ta-Tb.

[0096] Figure 14A This is a graph showing the voltage distribution results of the dual-gate thin-film transistor according to the comparative example. Figure 14B This is a graph showing the voltage distribution results of the dual-gate thin-film transistor according to an embodiment, and Figure 15 This is a graph showing the degradation amount of the first thin-film transistor in the dual-gate thin-film transistors according to the comparative example and the embodiment, according to the stress time.

[0097] Figure 14A and Figure 14B The potential V varies depending on the position (μm) of the first and second thin-film transistors Ta' / Tb' and Ta / Tb. Figure 15 The degradation of the first thin-film transistor Ta' and Ta (ΔVth, Vth offset) is shown as an increase over stress time.

[0098] Reference Figure 14AAccording to the comparative example, the dual-gate thin-film transistor may include a first thin-film transistor Ta' and a second thin-film transistor Tb' having the same structure, and when a conduction operation is performed by applying a high-potential power supply voltage VDD, it can be seen that the voltage Vds11 allocated to the first thin-film transistor Ta' operating in saturation mode is greater than the voltage Vds12 allocated to the second thin-film transistor Tb' operating in linear mode.

[0099] Reference Figure 14B A dual-gate thin-film transistor according to one embodiment may include having, for example, Figures 2 to 13 The first thin-film transistor Ta and the second thin-film transistor Tb with different gate effective capacitances are shown. When the conduction operation is performed by applying a high-potential power supply voltage VDD, it can be seen that the voltage Vds21 assigned to the first thin-film transistor Ta in saturation mode is reduced compared to the assigned voltage Vds11 of the comparative example, while the drain-source voltage Vds22 assigned to the second thin-film transistor Tb in linear mode is increased compared to the assigned voltage Vds12 of the comparative example.

[0100] Therefore, refer to Figure 15 As can be seen, compared with the stress-time degradation (ΔVth, Vth offset) of the first thin-film transistor Ta' according to the comparative example, the stress-time degradation (ΔVth, Vth offset) of the first thin-film transistor Ta according to the embodiment is reduced. Therefore, compared with the comparative example, the dual-gate thin-film transistor according to the embodiment can reduce overall stress and degradation.

[0101] Figure 16 This is a graph showing the relationship between the distributed voltage of the first and second thin-film transistors in a dual-gate thin-film transistor according to one embodiment of the present disclosure and the thickness of the gate insulating layer.

[0102] Reference Figure 16 It can be seen that as the thickness of the multiple insulating layers INS between the gate electrode GE2 and the active layer ACT of the second thin-film transistor Tb increases, the voltage distributed to the second thin-film transistor Tb increases, while the voltage distributed to the first thin-film transistor Ta decreases. It can be confirmed that when the thickness of the multiple insulating layers INS between the gate electrode GE2 and the active layer ACT of the second thin-film transistor Tb is 7000 Å (the GI thickness of Ta = 1500 Å), the distributed voltage of the second thin-film transistor Tb becomes greater than the distributed voltage of the first thin-film transistor Ta.

[0103] As the thickness of the multiple insulating layers INS between the gate electrode GE2 and the active layer ACT of the second thin-film transistor Tb increases, the capacitance Cox_b between the gate electrode GE2 and the active layer ACT decreases, thereby reducing the current Ids.

[0104] According to one embodiment, the thickness of the plurality of insulating layers INS between the gate electrode GE2 of the second thin-film transistor Tb and the active layer ACT can be greater than the thickness of the gate insulating layer GI of the first thin-film transistor Ta (1500 Å = 0.15 μm), and can be less than the maximum thickness of the first region R1 (3.3 μm, 22 times the thickness of Ta GI), wherein the reliability improvement effect is greater than the reduction of the current Ids of the second thin-film transistor Tb.

[0105] In a dual-gate thin-film transistor according to one embodiment, the first thin-film transistor Ta may have a first thickness d1 corresponding to the gate insulating layer GI between the gate electrode GE1 and the active layer ACT. The second thin-film transistor Tb may have a second thickness d2 including the gate insulating layer GI and the interlayer insulating layer ILD between the gate electrode GE2 and the active layer ACT, or may have a third thickness d3 including the gate insulating layer GI, the interlayer insulating layer ILD, and the planarization layer PLN.

[0106] Even though the second thin-film transistor Tb includes a relatively thick planarization layer PLN of about 2.6 μm between the gate electrode GE2 and the active layer ACT, as well as a gate insulating layer GI and an interlayer insulating layer ILD, it can still operate normally because the third thickness d3 of the three insulating layers is less than the maximum thickness of the first region R1 (3.3 μm).

[0107] Figure 17 This is an equivalent circuit diagram of a thin-film transistor according to one embodiment of the present disclosure. Figure 18 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure. Figure 19 It shows along Figure 18 The cross-sectional view of the thin-film transistor structure along line G-G' is shown, and Figure 20 It is a graph comparing the voltage distribution results of a dual-gate thin-film transistor based on a comparative example and an embodiment.

[0108] Reference Figures 17 to 19 According to one embodiment, a dual-gate thin-film transistor includes a first thin-film transistor Ta_1 and a second thin-film transistor Tb connected in series with shared gate electrodes GE1 and GE2, and may have a heterogeneous resistor structure, wherein the resistance of the first thin-film transistor Ta_1 is less than the resistance of the second thin-film transistor Tb. Descriptions of configurations that are repeated with those of the previously described embodiments will be omitted or briefly mentioned.

[0109] The first thin-film transistor Ta_1 may include a first gate electrode GE1, a first channel portion CA1 of the active layer ACT, a first drain electrode DE1 and a first source electrode SE1 connected to both sides of the first channel portion CA1, respectively. The second thin-film transistor Tb may include a gate electrode GE2, a second channel portion CA2 of the active layer ACT, a second drain electrode DE2 and a second source electrode SE2 connected to both sides of the second channel portion CA2, and a light-shielding electrode LS2 connected to the second source electrode SE2. The first gate electrode GE1 and the second gate electrode GE2 may be disposed on the gate insulating layer GI and may be integrally formed. The first source electrode SE1 and the second drain electrode DE2 may be integrally formed in the conductive portion between the first channel portion CA1 and the second channel portion CA2 of the active layer ACT.

[0110] According to one embodiment, the dual-gate thin-film transistor may have a diode structure, wherein the gate electrodes GE1 and GE2 are connected to the drain electrode DE1 of the first thin-film transistor Ta_1.

[0111] The first thin-film transistor Ta_1 does not include a light-shielding electrode, and the second thin-film transistor Tb includes a light-shielding electrode LS2 with a source contact structure, such that the resistance of the first thin-film transistor Ta_1 can be reduced compared to the resistance of the second thin-film transistor Tb.

[0112] Therefore, the voltage Vds1 allocated to the first thin-film transistor Ta_1 can be reduced, the voltage Vds2 allocated to the second thin-film transistor Tb can be increased, and the difference between the voltages Vds1 and Vds2 allocated to the first thin-film transistor Ta_1 and the second thin-film transistor Tb can be reduced.

[0113] Reference Figure 20 According to the comparative example, the dual-gate thin-film transistor may include a first thin-film transistor Ta' and a second thin-film transistor Tb' having the same structure, and when a conduction operation is performed by applying a high-potential power supply voltage VDD, it can be seen that the voltage Vds11 assigned to the first thin-film transistor Ta' operating in saturation mode is greater than the voltage Vds12 assigned to the second thin-film transistor Tb' operating in linear mode.

[0114] On the other hand, a dual-gate thin-film transistor according to one embodiment may include, for example: Figures 17 to 19The first thin-film transistor Ta_1 and the second thin-film transistor Tb with heterogeneous resistor structures are shown. When a high-potential power supply voltage VDD is applied to perform a conduction operation, it can be seen that the voltage Vds21 assigned to the first thin-film transistor Ta_1 in saturation mode is reduced compared to the assigned voltage Vds11 in the comparative example, while the drain-source voltage Vds22 assigned to the second thin-film transistor Tb in linear mode is increased compared to the assigned voltage Vds12 in the comparative example.

[0115] Therefore, the stress and degradation of the first thin-film transistor Ta_1 in saturation mode can be reduced, and in addition, the overall stress and degradation of the dual-gate thin-film transistor Ta_1-Tb can be reduced.

[0116] Figure 21 This is an equivalent circuit diagram of a thin-film transistor according to one embodiment of the present disclosure. Figure 22 This is a plan view illustrating a thin-film transistor structure according to one embodiment of the present disclosure. Figure 23 It shows along Figure 22 The cross-sectional view of the thin-film transistor structure of lines H1-H1' and H2-H2' is shown, and Figure 24 It is a graph comparing the voltage distribution results of a dual-gate thin-film transistor based on a comparative example and an embodiment.

[0117] According to Figures 17 to 19 Compared to the dual-gate thin-film transistors Ta_1 and Tb in the illustrated embodiment, according to Figures 21 to 23 The difference between the dual-gate thin-film transistor Ta_2-Tb in the illustrated embodiment is that the first thin-film transistor Ta_2 has a dual-gate structure including a light-shielding electrode LS1 connected to the gate electrode GE1. Therefore, descriptions of components that are repeated in the previously described embodiments will be omitted or briefly mentioned.

[0118] The first thin-film transistor Ta_2 may include a first gate electrode GE1, a first drain electrode DE1, a first source electrode SE1, and a first light-shielding electrode LS1 connected to the first gate electrode GE1. The second thin-film transistor Tb may include a gate electrode GE2, a second drain electrode DE2, a second source electrode SE2, and a light-shielding electrode LS2 connected to the second source electrode SE2. The first gate electrode GE1 and the second gate electrode GE2 may be disposed on the gate insulating layer GI and formed integrally.

[0119] The first light-shielding electrode LS1 and the first gate electrode GE1, which overlap with the first channel portion CA1, can extend in the second direction (channel width direction) and can overlap with the gate insulating layer GI and the buffer layer BF in the region that does not overlap with the active layer ACT. The first gate electrode GE1 can be connected to the first light-shielding electrode LS1 through the contact hole CH4 that penetrates the gate insulating layer GI and the buffer layer BF.

[0120] The first thin-film transistor Ta_2 may have a dual-gate structure in which the first light-shielding electrode LS1 and the first gate electrode GE1 are connected, and the second thin-film transistor Tb may have a source contact structure in which the second light-shielding electrode LS2 and the second source electrode SE2 are connected.

[0121] Therefore, the dual-gate thin-film transistor Ta_2-Tb according to one embodiment can have a heterogeneous resistor structure, wherein the resistance of the first thin-film transistor Ta_2 is less than the resistance of the second thin-film transistor Tb. Consequently, the voltage Vds1 allocated to the first thin-film transistor Ta_2 can be reduced, the voltage Vds2 allocated to the second thin-film transistor Tb can be increased, and the difference between the voltages Vds1 and Vds2 allocated to the first thin-film transistor Ta_2 and the second thin-film transistor Tb can be reduced.

[0122] Reference Figure 24 A dual-gate thin-film transistor according to one embodiment may include, for example: Figures 21 to 23 The first thin-film transistor Ta_2 and the second thin-film transistor Tb with heterogeneous resistor structures are shown. When a high-potential power supply voltage VDD is applied to perform a conduction operation, it can be seen that the voltage Vds21 assigned to the first thin-film transistor Ta_2 in saturation mode is reduced compared to the assigned voltage Vds11 in the comparative example, while the drain-source voltage Vds22 assigned to the second thin-film transistor Tb in linear mode is increased compared to the assigned voltage Vds12 in the comparative example.

[0123] Therefore, the stress and degradation of the first thin-film transistor Ta_2 in saturation mode can be reduced, and in addition, the overall stress and degradation of the dual-gate thin-film transistor Ta_2-Tb can be reduced.

[0124] Figure 25 This is a schematic diagram illustrating the configuration of a display device according to one embodiment of the present disclosure, and Figure 26 This is an equivalent circuit diagram showing the configuration of each stage of a gate drive circuit according to one embodiment of the present disclosure.

[0125] According to one embodiment, the display device may be an electroluminescent display. The electroluminescent display device may be any one of an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QD) display device, and an inorganic light-emitting diode (ILD) display device.

[0126] Reference Figure 25 A display device according to one embodiment may include a display panel 100, a gate driving circuit 200 built into the display panel 100, and a data driving circuit 410 connected to the display panel 100. The gate driving circuit 200 and the data driving circuit 410 may be referred to as driving circuits.

[0127] Display panel 100 can be a rigid display panel or a flexible display panel that can change shape, such as a foldable, bendable, rollable, or stretchable display panel.

[0128] The display panel 100 can display images via a pixel array, wherein sub-pixels SP are arranged in a matrix in the display area DA. In one embodiment, the display panel 100 may further include a touch sensor array disposed in the display area DA to sense a user's touch. Sub-pixels P may include red sub-pixels emitting red light, green sub-pixels emitting green light, blue sub-pixels emitting blue light, and may also include white sub-pixels emitting white light. Each sub-pixel P may include a pixel circuit consisting of a light-emitting element and a plurality of thin-film transistors that independently drive the light-emitting element. The display panel 100 may include a plurality of data lines DL, a plurality of gate lines GL, a plurality of power lines VDL, and other signal lines connected to the sub-pixels P.

[0129] According to one embodiment, the display panel 100 may further include a touch sensor screen disposed in the display area DA to sense the user's touch.

[0130] The gate driving circuit 200 may be disposed in at least one of the bezel regions BZ1 to BZ2 located outside the display area DA surrounding the display panel 100. For example, the gate driving circuit 200 may be disposed in at least one of the first bezel regions BZ1 and the second bezel regions BZ2 located between the display area DA and opposite to each other. The gate driving circuit 200 may be integrated into the display panel 100 in the form of a gate in panel (GIP) formed together with the thin-film transistors of the display area DA.

[0131] The gate driving circuit 200 may include a first scan driving circuit 210 and a second scan driving circuit 220 for driving multiple gate lines GL, and a light emission control driving circuit 230. The first scan driving circuit 210 may include multiple first scan stages for supplying a first scan signal to each of a first group of gate lines among the multiple gate lines GL. The second scan driving circuit 220 may include multiple second scan stages for supplying a second scan signal to each of a second group of gate lines among the multiple gate lines GL. The light emission control driving circuit 230 may include multiple light emission control stages for supplying a light emission control signal to each of a third group of gate lines among the multiple gate lines GL.

[0132] The number of gate lines connected to each pixel line, the number of scan drive circuits, and the number of light emission control drive circuits are not limited to the following: Figure 25 The ones shown can vary in various ways depending on the detailed configuration of the pixel circuits that constitute each sub-pixel P.

[0133] The data driving circuit 410 converts digital data supplied from the timing controller into analog data voltage and supplies this data voltage to each of the multiple data lines DL of the display panel 100. The data driving circuit 410 includes one or more ICs (integrated circuits) and can be mounted on each circuit film 420. It can be electrically connected via an anisotropic conductive film (ACF) to pad areas disposed in the bezel area BZ4 of the display panel 100. The circuit film 420 can be any of COF (chip-on-film), FPC (flexible printed circuit), and FFC (flexible flat cable).

[0134] The thin-film transistors included in the driving circuit of the gate driving circuit 200 disposed in the display area DA and the bezel areas BZ1 to BZ4 of the display panel 100 can be any of polycrystalline silicon semiconductor, amorphous silicon semiconductor and oxide semiconductor.

[0135] In one embodiment, the thin-film transistors of the display panel 100 may include at least one of low-temperature polycrystalline silicon (LTPS) transistors and oxide transistors using metal-oxide-semiconductor.

[0136] The thin-film transistor of the display panel 100 according to one embodiment includes a dual-gate thin-film transistor with a heterogeneous resistor structure according to the above embodiment, which makes it possible to reduce the stress and degradation of the dual-gate thin-film transistor.

[0137] Reference Figure 26Each stage of the gate drive circuit may include: a set node 2, to which a start signal VST or a carry output CRY(N-4) from the previous stage is applied as a set signal; a high-potential power line 4, to which a high-potential power voltage VDD is applied; a first gate turn-off voltage line 6, to which a first gate turn-off voltage VGL is applied; a second gate turn-off voltage line 8, to which a second gate turn-off voltage VSS is applied; a clock line 12, to which a clock signal GCLK(N) is applied; a gate output line 14, to which a gate output GOUT(N) is applied; a carry output line 16, to which a carry output CRY(N) is applied; and a reset node 18, to which a reset signal or a carry output CRY(N+4) from the next stage is applied as a reset signal.

[0138] The carry output CRY(N) of each stage can be applied to another stage as a carry signal. The gate output GOUT(N) of each stage can be applied to the gate line GL of the display panel 100 as a scan signal. The second gate turn-off voltage VSS for the carry output CRY(N) can be a voltage lower than the first gate turn-off voltage VGL for the gate output GOUT(N).

[0139] Each stage of a gate drive circuit according to one embodiment may include a first charging unit and a first discharging unit for charging and discharging a first control node Q, a second charging unit and a second discharging unit for charging and discharging a second control node QB, a first output unit for outputting a gate signal GOUT(N), and a second output unit for outputting a carry signal CRY(N).

[0140] The first charging unit may include a 1-1 thin-film transistor T1a and a 1-2 thin-film transistor T1b connected in series between the set node 2 and the first control node Q, and sharing a gate electrode connected to the set node 2. The 1-1 thin-film transistor T1a and the 1-2 thin-film transistor T1b can activate the charging path between the set node 2 and the first control node Q in response to a set signal (start signal or carry output CRY(N-4) from the previous stage) applied to the set node 2. The 1-1 thin-film transistor T1a and the 1-2 thin-film transistor T1b can charge the first control node Q using the gate on-state voltage of the set signal through the activated first charging path. The carry output CRY(N-4) from the previous stage can be applied from the (N-4)th previous stage.

[0141] The first discharge unit may include a 1-1 discharge unit that provides a 1-1 discharge channel for the first control node Q and a 1-2 discharge unit that provides a 1-2 discharge channel for the first control node Q.

[0142] The 1-1 discharge unit may include a 3-1 thin-film transistor T3_a and a 3-2 thin-film transistor T3_b connected in series between the first control node Q and the second gate turn-off voltage line VSS, and sharing a gate electrode connected to the second control node QB. The 3-1 thin-film transistor T3_a and the 3-2 thin-film transistor T3_b can activate the 1-1 discharge path between the first control node Q and the second gate turn-off voltage line VSS in response to control by the second control node QB. The 3-1 thin-film transistor T3_a and the 3-2 thin-film transistor T3_b can then discharge the voltage of the first control node Q to the second gate turn-off voltage line VSS through the activated 1-1 discharge path.

[0143] The 1-2 discharge unit may include a 3-3 thin-film transistor T3n_a and a 3-4 thin-film transistor T3n_b connected in series between the first control node Q and the second gate turn-off voltage line VSS, and sharing a gate electrode connected to the reset node 18. The 3-3 thin-film transistor T3n_a and the 3-4 thin-film transistor T3n_b may activate the 1-2 discharge path between the first control node Q and the second gate turn-off voltage line VSS in response to a reset signal applied to the reset node 14 (a reset signal or a carry output CRY(N+4) from a subsequent stage). The 3-3 thin-film transistor T3n_a and the 3-4 thin-film transistor T3n_b can then discharge the voltage of the first control node Q to the second gate turn-off voltage line VSS through the activated 1-2 discharge path.

[0144] The second charging unit may include a 4-1 thin-film transistor T4a and a 4-2 thin-film transistor T4b connected in series between the high-potential voltage line 4 and the second control node QB, and sharing a gate electrode connected to the high-potential voltage line 4. The 4-1 thin-film transistor T4a and the 4-2 thin-film transistor T4b are activated by a high-potential power supply voltage VDD applied to the high-potential voltage line 4, thereby charging the second control node QB with the high-potential power supply voltage VDD.

[0145] The second discharge unit may include a 2-1 discharge unit that provides a 2-1 discharge path for the second control node QB and a 2-2 discharge unit that provides a 2-2 discharge path for the second control node QB.

[0146] The 2-1 discharge unit may include a 5-1 thin-film transistor T5c having a gate electrode connected to the set node 2 and providing a 2-1 discharge path between the second control node QB and the second gate turn-off voltage line 8. The 5-1 thin-film transistor T5c can activate the 2-1 discharge path between the second control node QB and the second gate turn-off voltage line 8 in response to a set signal (start signal or carry output CRY(N-4) from the preceding stage). The 5-1 thin-film transistor T5c can then discharge the voltage of the second control node QB to the second gate turn-off voltage line VSS through the activated 2-1 discharge path.

[0147] The 2-2 discharge unit may include a 5-2 thin-film transistor T5q having a gate electrode connected to a first control node Q and providing a 2-2 discharge path between a second control node QB and a second gate turn-off voltage line 8. The 5-2 thin-film transistor T5q can activate the 2-2 discharge path between the second control node QB and the second gate turn-off voltage line 8 in response to control by the first control node Q. The 5-2 thin-film transistor T5q can then discharge the voltage of the second control node QB to the second gate turn-off voltage line VSS through the activated 2-2 discharge path.

[0148] The first output unit can share the gate output line 14 and includes a first pull-up thin-film transistor T6 activated by the control of the first control node Q and a first pull-down thin-film transistor T7 activated by the control of the second control node QB. The first pull-up thin-film transistor T6 can be activated in response to the voltage of the first control node Q and can output the clock signal GCLK(N) applied to the clock line 12 as the gate output GOUT(N) to the gate output line 14. The first pull-down thin-film transistor T7 can be activated in response to the voltage of the second control node QB and can output the first gate turn-off voltage VGL applied to the first gate turn-off voltage line 6 as the gate output GOUT(N) to the gate output line 14.

[0149] The second output section can share the carry output line 16 and includes a second pull-up thin-film transistor T6c activated by the control of the first control node Q and a second pull-down thin-film transistor T7c activated by the control of the second control node QB. The second pull-up thin-film transistor T6c can be activated in response to the voltage of the first control node Q and can output the clock signal GCLK(N) applied to the clock line 12 as the carry output CRY(N) to the carry output line 16. The second pull-down thin-film transistor T7c can be activated in response to the voltage of the second control node QB and can output the second gate turn-off voltage VSS applied to the second gate turn-off voltage line 8 as the carry output CRY(N) to the carry output line 16.

[0150] Each stage of the gate drive circuit according to one embodiment may further include an offset transistor T3q connected to the intermediate node of 1-1 thin film transistor T1a and 1-2 thin film transistor T1b and the intermediate node of 3-1 thin film transistor T3_a and 3-2 thin film transistor T3_b.

[0151] Offset transistor T3q can be activated in response to the first control node Q, and the activated offset transistor T3q can apply the high-potential power supply voltage VDD applied to the high-potential voltage line 4 as an offset voltage to the intermediate nodes of thin-film transistors 1-1 T1a and 1-2 T1b, and the intermediate nodes of thin-film transistors 3-1 T3_a and 3-2 T3_b. Each of thin-film transistors 1-1 T1a and 3-1 T3_a can minimize leakage current by having a negative voltage with its gate-source voltage lower than the threshold voltage due to the offset voltage VDD.

[0152] Each stage of the gate drive circuit according to one embodiment may also include a reset transistor T3no, which resets the gate output line 14 in response to the control of the reset node 18.

[0153] The reset transistor T3no can reset the gate output line 14 to the first gate turn-off voltage line VGL in response to the reset signal applied to the reset node 18 or the carry output CRY(N+4) of the subsequent stage.

[0154] In a gate drive circuit according to one embodiment, the 4-1 thin film transistor T4a and 4-2 thin film transistor T4b of the second charging portion for charging the second control node QB can be dual-gate thin film transistors with heterogeneous resistance structures according to the above embodiment.

[0155] According to one embodiment, thin-film transistors T4a (4-1) and T4b (4-2) can be used according to... Figures 2 to 13 Any of the dual-gate thin-film transistors Ta-Tb shown in the various embodiments. Therefore, since the 4-2 thin-film transistor T4b has a heterogeneous structure in which the resistance is greater than that of the 4-1 thin-film transistor T4a, the voltage allocated to the 4-2 thin-film transistor T4b can be increased, and the voltage allocated to the 4-1 thin-film transistor T4a can be decreased.

[0156] According to one embodiment, thin-film transistors T4a (4-1) and T4b (4-2) can be used according to... Figures 17 to 24Any of the dual-gate thin-film transistors Ta_1-Tb and Ta_2-Tb shown in the various embodiments. Therefore, since the 4-1 thin-film transistor T4a has a heterogeneous structure in which the resistance is less than that of the 4-2 thin-film transistor T4b, the voltage allocated to the 4-1 thin-film transistor T4a can be reduced, and the voltage allocated to the 4-2 thin-film transistor T4b can be increased.

[0157] Therefore, the stress and degradation of the 4-1 thin-film transistor T4a operating in saturation mode can be reduced, as can the overall stress and degradation of the dual-gate fourth thin-film transistors T4a and T4b. Thus, the reliability of the gate drive circuit can be improved by preventing multiple outputs of the gate output GOUT(N) and carry output CRY(N) of the gate drive circuit.

[0158] Figure 27 This is an equivalent circuit diagram illustrating a pixel circuit configuration according to one embodiment of the present disclosure.

[0159] Reference Figure 27 According to one embodiment, a sub-pixel P may include a light-emitting element (OLED) and a pixel circuit that independently drives the light-emitting element (OLED), and the pixel circuit may include a driving thin-film transistor DT and a plurality of thin-film transistors T2 to T8 and a storage capacitor Cst.

[0160] Each of the thin-film transistors DT, T2 through T8 in the pixel circuit can be made of any of polycrystalline silicon, amorphous silicon, and oxide semiconductors. In one embodiment, the thin-film transistors DT and T2 through T7 of the pixel circuit can be configured as P-type polycrystalline silicon transistors. In one embodiment, the thin-film transistors DT and T2 through T8 of the pixel circuit can be configured as N-type oxide transistors. In one embodiment, the thin-film transistors DT and T2 through T8 of the pixel circuit can be configured by mixing P-type polycrystalline silicon transistors and N-type oxide transistors.

[0161] In one embodiment, the driving thin-film transistor DT and some of the thin-film transistors T2 and T4 to T8 may be composed of fast-mobility P-type low-temperature polysilicon LTPS transistors, and the third thin-film transistor may be composed of an N-type oxide transistor with a lower off-state current (leakage current) than that of the LTPS transistor.

[0162] The third thin-film transistor (T3, sampling transistor) can be connected to a second node N2, which is controlled by the first gate line 31 and connected to the gate electrode of the driving transistor DT, and to a third node N3, which is connected to the drain electrode (second electrode) of the driving transistor DT. The third transistor T3 is turned on by the gate on-state voltage of the first scan signal Scan1 supplied through the first gate line 31, and can be connected to the gate electrode and drain electrode of the driving transistor DT during the sampling period, thereby connecting the driving transistor DT in a diode structure.

[0163] According to one embodiment, the third transistor T3 may include a 3-1 thin-film transistor T3a and a 3-2 thin-film transistor T3b connected in series between the third node N3 and the second node N2 and sharing a gate electrode. According to the above embodiment, the 3-1 thin-film transistor T3a and the 3-2 thin-film transistor T3b may be dual-gate thin-film transistors with a heterogeneous resistor structure.

[0164] According to one embodiment, thin-film transistors T3a (3-1) and T3b (3-2) can be used according to... Figures 2 to 13 Any of the dual-gate thin-film transistors Ta-Tb shown in the various embodiments. Therefore, since the 3-1 thin-film transistor T3b has a heterogeneous structure in which the resistance is greater than that of the 3-1 thin-film transistor T3a, the voltage allocated to the 3-2 thin-film transistor T3b can be increased, and the voltage allocated to the 3-1 thin-film transistor T3a can be decreased.

[0165] According to one embodiment, thin-film transistors T3a (3-1) and T3b (3-2) can be used according to... Figures 17 to 24 Any of the dual-gate thin-film transistors Ta_1-Tb and Ta_2-Tb shown in the various embodiments. Therefore, since the 3-1 thin-film transistor T3a has a heterogeneous structure in which the resistance is less than that of the 3-2 thin-film transistor T3b, the voltage allocated to the 3-1 thin-film transistor T3a can be reduced, and the voltage allocated to the 3-2 thin-film transistor T3b can be increased.

[0166] Therefore, the stress and degradation of the 3-1 thin-film transistor T3a can be reduced, as can the overall stress and degradation of the dual-gate third thin-film transistor T3. Thus, even if the sampling and compensation time for the threshold voltage Vth of the driving thin-film transistor DT by the third thin-film transistor T3 increases, the degradation of the third thin-film transistor T3 can still be reduced, thereby improving the reliability of the pixel circuit.

[0167] The second thin-film transistor (T2, the switching transistor) is controlled by the second gate line 32 and can be connected to the data line 53 and the first node N1, which is connected to the source electrode (first electrode) of the driving transistor DT. The second thin-film transistor T2 is turned on by the gate on-state voltage of the second scan signal Scan2 supplied through the second gate line 32, and the data voltage Vdata supplied through the data line 53 can be applied to the driving transistor DT during the data programming period.

[0168] The fifth thin-film transistor (T5, the operation control transistor) is controlled by the fifth gate line 35 and can be connected to the first power line 51, which supplies the high-potential power voltage ELVDD, and the first node N1 of the driving transistor DT. The fifth thin-film transistor T5 is turned on by the gate on-state voltage of the light-emitting control signal EM supplied through the fifth gate line 35, and the high-potential power voltage ELVDD supplied through the first power line 51 can be applied to the first node N1 of the driving transistor DT during the light-emitting period.

[0169] The sixth thin-film transistor (T6, light-emitting control transistor) is controlled by the fifth gate line 35 and can be connected to the third node N3 of the driving transistor DT and the fourth node N4 connected to the anode electrode of the light-emitting element (OLED). The sixth thin-film transistor T6 is turned on by the gate on-state voltage of the light-emitting control signal EM supplied through the fifth gate line 35, and can be connected to the third node N3 of the driving transistor DT and the anode electrode of the light-emitting element (OLED) during the light-emitting period.

[0170] The fourth thin-film transistor (T4, the first initialization transistor) is controlled by the fourth gate line 34 and can be connected to the second node N2 of the driving transistor DT and the first initialization voltage line 41. The fourth thin-film transistor T4 is turned on by the gate turn-on voltage of the fourth scan signal Scan4 supplied through the fourth gate line 34, and the first initialization voltage Vinit of the first initialization voltage line 41 can be applied to the second node N2 of the driving transistor DT during the initialization period.

[0171] The seventh thin-film transistor (T7, the second initialization transistor) is controlled by the third gate line 33 and can be connected to the second initialization voltage line 42 and the fourth node N4 connected to the anode of the light-emitting element (OLED). The seventh thin-film transistor T7 is turned on by the gate-on voltage of the third scan signal Scan3 supplied through the third gate line 33, and the second initialization voltage VAR of the second initialization voltage line 42 can be applied to the fourth node N4 connected to the anode electrode of the light-emitting element (OLED) during the initialization period. The second initialization voltage VAR can be represented as the anode reset voltage.

[0172] The eighth thin-film transistor (T8, the third initialization transistor) is controlled by the third gate line 33 and can be connected to the third initialization voltage line 43 and the first node N1 of the driving transistor DT. The eighth thin-film transistor T8 is turned on by the gate turn-on voltage of the third scan signal Scan3 supplied through the third gate line 33, and the third initialization voltage Vobs of the third initialization voltage line 43 can be supplied to the first node N1 of the driving transistor DT during the initialization period. The third initialization voltage Vobs can be expressed as the on-bias stress voltage that suppresses the threshold voltage offset of the driving transistor DT.

[0173] A storage capacitor Cst can be connected between the first power line 51 and the second node N2 of the driving transistor DT. The storage capacitor Cst can charge the voltage difference between the high-potential power voltage ELVDD applied through the first power line 51 and the data voltage Vdata applied to the driving transistor DT and the second node N2. During the sampling period of the driving transistor DT, which is connected in a diode structure via a sampling third thin-film transistor T3, the storage capacitor Cst can sample and store the threshold voltage Vth of the driving transistor DT and provide a data voltage compensated for the threshold voltage to the second node N2 of the driving transistor DT. The storage capacitor Cst can maintain the voltage difference between the high-potential power supply voltage ELVDD and the data voltage (Vdata+Vth) compensated for the threshold voltage of the driving transistor DT by charging to a target voltage, and can provide the maintained target voltage as the driving voltage of the driving transistor DT.

[0174] The driving transistor DT (first thin-film transistor) may have a gate electrode connected to the second node N2, a source electrode (first electrode) connected to the first node N1, and a drain electrode (second electrode) connected to the third node N3. The driving transistor DT can control the amount of current flowing through the sixth thin-film transistor T6 to the light-emitting element (OLED) according to the target voltage of the charging in the storage capacitor Cst, thereby controlling the light emission intensity of the light-emitting element (OLED).

[0175] The light-emitting element (OLED) may include an anode connected to a third node N3 of a driving transistor DT via a sixth thin-film transistor T6, a cathode connected to a second electric field line 52 to which a low-potential electric voltage ELVSS is applied, and an organic light-emitting layer between the anode and the cathode. The light-emitting element (OLED) can generate light with brightness proportional to the amount of driving current supplied from the driving transistor DT via the sixth thin-film transistor T6.

[0176] Reference Figure 25 and Figure 27Gate lines 31, 32, 33 and 34 can be driven by multiple scan drive circuits 210 and 220 in the gate drive circuit 200, and gate line 35 can be driven by the light emission control drive circuit 230 in the gate drive circuit 200.

[0177] As described above, a dual-gate thin-film transistor according to one embodiment of the present disclosure can reduce the voltage distribution difference between the first thin-film transistor and the second thin-film transistor by having a heterostructure in which the first thin-film transistor and the second thin-film transistor have different resistances.

[0178] According to one embodiment of the present disclosure, a dual-gate thin-film transistor has a heterogeneous resistor structure in which the resistance of the second thin-film transistor is greater than the resistance of the first thin-film transistor, thereby increasing the voltage allocated to the second thin-film transistor and decreasing the voltage allocated to the first thin-film transistor.

[0179] According to one embodiment of the present disclosure, a dual-gate thin-film transistor has a heterogeneous resistor structure in which the resistance of a first thin-film transistor is less than the resistance of a second thin-film transistor, thereby reducing the voltage allocated to the first thin-film transistor and increasing the voltage allocated to the second thin-film transistor.

[0180] Therefore, the dual-gate thin-film transistor according to one embodiment of the present disclosure can reduce the difference in voltage distribution between the first thin-film transistor and the second thin-film transistor, thereby reducing the stress and degradation of the first thin-film transistor operating in saturation mode, and thus reducing the overall stress and degradation of the dual-gate thin-film transistor, thereby improving the reliability of the dual-gate thin-film transistor.

[0181] According to one embodiment of the present disclosure, a gate drive circuit including a dual-gate thin-film transistor can improve the reliability of the gate drive circuit by reducing the degradation of the dual-gate thin-film transistor, and can achieve low power consumption.

[0182] A display device including dual-gate thin-film transistors according to one embodiment of the present disclosure can improve the reliability of the pixel circuit by reducing the degradation of the dual-gate thin-film transistors in the pixel circuit, and can achieve low power consumption.

[0183] The display device according to this disclosure can be applied to all electronic devices. For example, the display device according to this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle navigation systems, vehicle display devices, televisions, wallpaper display devices, signage devices, gaming devices, laptop computers, monitors, camera devices, camcorders, and home appliances.

[0184] The features, structures, effects, etc., described in the various examples of this specification are included in at least one example of this specification, and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc., shown in at least one example of this specification can be combined or modified by those skilled in the art to which the technical concept of this specification pertains in other examples. Therefore, the content related to such combinations and modifications should be construed as being included within the technical scope or rights of this specification.

[0185] The foregoing disclosure is not limited to the embodiments and drawings described above, and it will be apparent to those skilled in the art that various substitutions, modifications, and variations can be made within the scope of the technical spirit of this disclosure. Therefore, the scope of this disclosure is indicated by the claims set forth below, and all variations or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as including within the scope of this specification.

Claims

1. A dual-gate thin-film transistor, comprising: A first thin-film transistor, the first thin-film transistor including a first gate electrode, a first drain electrode, a first source electrode, and a first channel portion between the first drain electrode and the first source electrode; as well as The second thin-film transistor includes a second gate electrode connected to the first gate electrode, a second drain electrode connected to the first source electrode, a second source electrode, and a second channel portion between the second drain electrode and the second source electrode. Wherein, the first channel portion and the first gate electrode overlap each other, and the first insulating layer is located between the first channel portion and the first gate electrode, and The second channel portion and the second gate electrode overlap each other, including multiple insulating layers of the first insulating layer and the second insulating layer between the second channel portion and the second gate electrode.

2. The dual-gate thin-film transistor according to claim 1, wherein: The first thin-film transistor and the second thin-film transistor include an active layer, and the first channel portion and the second channel portion are formed in the active layer. The first drain electrode is formed as a first conductive portion of the active layer that contacts the first channel portion. The first source electrode and the second drain electrode are integrally formed between the first channel portion and the second channel portion by a second conductive portion of the active layer that contacts the first channel portion and the second channel portion. The second source electrode is formed as a third conductive portion of the active layer that contacts the second channel portion.

3. The dual-gate thin-film transistor according to claim 2, further comprising: A drain connection electrode is connected to the first drain electrode through a first contact hole that penetrates the plurality of insulating layers; as well as A source electrode is connected to the second source electrode through a second contact hole that penetrates the plurality of insulating layers.

4. The dual-gate thin-film transistor according to claim 3, wherein: The first gate electrode is disposed on the first insulating layer. The second gate electrode, the drain connection electrode, and the source connection electrode are disposed on the second insulating layer, and The first gate electrode and the second gate electrode are connected to each other through a third contact hole that penetrates the second insulating layer.

5. The dual-gate thin-film transistor according to claim 4, further comprising: A connecting electrode is provided, which is connected to the second conductive portion through a fourth contact hole that penetrates the plurality of insulating layers.

6. The dual-gate thin-film transistor according to claim 3, further comprising: A first light-shielding electrode overlaps with the first channel portion, wherein a buffer layer is located between the first light-shielding electrode and the first channel portion; as well as The second light-shielding electrode overlaps with the second channel portion, wherein the buffer layer is located between the second light-shielding electrode and the second channel portion.

7. The dual-gate thin-film transistor according to claim 6, in, The first light-shielding electrode and the second light-shielding electrode are connected to the source electrode connection electrode.

8. The dual-gate thin-film transistor according to claim 3, in, The plurality of insulating layers further includes a third insulating layer disposed on the second insulating layer between the second channel portion and the second gate electrode.

9. The dual-gate thin-film transistor according to claim 8, wherein: The first gate electrode is disposed on the first insulating layer. The second gate electrode is disposed on the third insulating layer, and The first gate electrode and the second gate electrode are connected to each other through a third contact hole that penetrates the second insulating layer and the third insulating layer.

10. The dual-gate thin-film transistor according to claim 9, wherein: The drain electrode is disposed on the second insulating layer and is connected to the first drain electrode through the first contact hole penetrating the first and second insulating layers. The source electrode is disposed on the second insulating layer and is connected to the second source electrode through the second contact hole that penetrates the first and second insulating layers, or The source electrode is disposed on the third insulating layer and is connected to the second source electrode through the second contact hole that penetrates the first insulating layer to the third insulating layer.

11. The dual-gate thin-film transistor according to claim 5, wherein, The connection electrode is disposed on the second insulating layer and is connected to the second conductive portion through the fourth contact hole penetrating the first and second insulating layers, or The connecting electrode is disposed on the third insulating layer and is connected to the second conductive portion through the fourth contact hole that penetrates the first insulating layer to the third insulating layer.

12. The dual-gate thin-film transistor according to claim 1, in, The second capacitance between the second gate electrode and the second channel portion of the second thin-film transistor is less than the first capacitance between the first gate electrode and the first channel portion of the first thin-film transistor.

13. The dual-gate thin-film transistor according to claim 1, in, The second resistance of the second thin-film transistor is greater than the first resistance of the first thin-film transistor.

14. A dual-gate thin-film transistor, comprising: A first thin-film transistor, the first thin-film transistor including a first gate electrode, a first drain electrode, a first source electrode, and a first channel portion between the first drain electrode and the first source electrode; as well as The second thin-film transistor includes a second gate electrode connected to the first gate electrode, a second drain electrode connected to the first source electrode, a second source electrode, and a second channel portion between the second drain electrode and the second source electrode. The second thin-film transistor further includes a second light-shielding electrode overlapping the second channel portion, and The first gate electrode and the second gate electrode are disposed in the same layer and are integrally formed as a continuous structure.

15. The dual-gate thin-film transistor according to claim 14, wherein: The first thin-film transistor and the second thin-film transistor include an active layer, and the first channel portion and the second channel portion are formed in the active layer. The first drain electrode is formed as a first conductive portion of the active layer that contacts the first channel portion. The first source electrode and the second drain electrode are integrally formed between the first channel portion and the second channel portion by a second conductive portion of the active layer that contacts the first channel portion and the second channel portion. The second source electrode is formed as a third conductive portion of the active layer that contacts the second channel portion.

16. The dual-gate thin-film transistor of claim 15, further comprising: A drain connection electrode is connected to the first drain electrode through a first contact hole that penetrates multiple insulating layers; as well as A source electrode is connected to the second source electrode through a second contact hole that penetrates the plurality of insulating layers.

17. The dual-gate thin-film transistor according to claim 16, in, The second light-shielding electrode is connected to the source electrode.

18. The dual-gate thin-film transistor of claim 17, wherein: The first thin-film transistor further includes a first light-shielding electrode overlapping the first channel portion, wherein a buffer layer is located between the first light-shielding electrode and the first channel portion. The first gate electrode and the second gate electrode are disposed on the gate insulating layer covering the active layer, and The first gate electrode is connected to the first light-shielding electrode through a third contact hole that penetrates the gate insulating layer and the buffer layer.

19. The dual-gate thin-film transistor according to claim 14, in, The second resistance of the second thin-film transistor is greater than the first resistance of the first thin-film transistor.

20. A display device, comprising: Display panel; as well as Gate driving circuit for driving the gate lines of the display panel. The gate driving circuit includes a stage circuit that outputs a gate signal to each of the gate lines. The stage circuit includes: An output unit is configured to output the gate signal via a gate output line in response to the control of the first control node and the first control node. The first charging unit is used to charge the first control node; The first discharge unit is used to discharge the first control node; The second charging unit is used to charge the second control node; and The second discharge unit is used to discharge the second control node. The second charging unit includes a dual-gate thin-film transistor according to any one of claims 1 to 19, the dual-gate thin-film transistor being connected between a high-potential power supply line supplied with a high-potential power voltage and the second control node. The first gate electrode, the second gate electrode, and the first drain electrode of the dual-gate thin-film transistor are connected to the high-potential power supply line, and the second source electrode is connected to the second control node.

21. A display device, comprising: Multiple subpixels set in the display area of ​​the display panel. Each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for independently driving the light-emitting element. The pixel circuit includes: A driving transistor for driving the light-emitting element; and A sampling thin-film transistor connecting the gate and drain electrodes of the driving transistor. The sampling thin-film transistor includes a dual-gate thin-film transistor according to any one of claims 1 to 19.

22. The display device according to claim 21, wherein: The first drain electrode of the dual-gate thin-film transistor is connected to the drain electrode of the driving transistor. The first gate electrode and the second gate electrode are connected to the gate line that controls the sampling thin-film transistor, and The second source electrode is connected to the gate electrode of the driving transistor.

23. A dual-gate thin-film transistor, comprising: A first thin-film transistor, the first thin-film transistor including a first gate electrode, a first drain electrode, a first source electrode, and a first channel portion between the first drain electrode and the first source electrode; as well as The second thin-film transistor includes a second gate electrode connected to the first gate electrode, a second drain electrode connected to the first source electrode, a second source electrode, and a second channel portion between the second drain electrode and the second source electrode. The first channel portion and the second channel portion are formed on the same layer, and Wherein, the first distance between the first channel portion and the first gate electrode is less than the second distance between the second channel portion and the second gate electrode.

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