A trench gate device and a method of manufacturing the same
By forming first and second lead-out layers in the trench gate device and burying the second lead-out layer in the gate conductive layer, the problem of increased gate resistance is solved, and the high-frequency performance of the device is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD
- Filing Date
- 2024-12-25
- Publication Date
- 2026-06-26
AI Technical Summary
In the prior art, while trench gate devices reduce cell size, the gate resistance increases, affecting the high-frequency performance of the device.
By forming first and second lead-out layers on the semiconductor structure and burying the gate conductive layer at the bottom of the second lead-out layer, the contact area between the lead-out layer and the gate conductive layer is increased, thereby reducing the gate resistance.
This effectively reduces gate resistance, decreases switching losses, and improves the high-frequency performance of the device.
Smart Images
Figure CN122294560A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a trench gate device and its fabrication method. Background Technology
[0002] Shielded gate trench power MOS (SGT MOS) devices are widely used in low-to-medium voltage applications below 250V due to their advantages such as low specific on-resistance, low Miller capacitance, low power loss, small parasitic capacitance, high switching speed, and good high-frequency characteristics. Figure 1 The diagram shows a cross-sectional structure of an SGT MOS device, including a substrate 01, a drift region 011, a P-type well region 012, an N-type source region 013, a P-type contact region 014, a gate structure 02, a trench 021, an insulating layer 022, a shielding gate layer 023, an isolation dielectric layer 024, a gate dielectric layer 025, a polysilicon gate 026, an interlayer dielectric layer 03, a source 04, and a drain 05. In high-frequency, high-efficiency applications, lower switching losses are required, but excessively high gate resistance will increase these losses. Currently, high-frequency performance is typically improved by reducing the device's cell size (pitch). However, reducing the cell size inevitably leads to an increase in gate resistance, which in turn increases switching losses, affecting device performance.
[0003] Therefore, there is an urgent need to find a method for fabricating trench gate devices that can reduce device size while lowering gate resistance. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench gate device and its fabrication method, which solves the problem that the gate resistance increases while the cell size of the trench gate device is reduced in the prior art.
[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a trench gate device, comprising the following steps:
[0006] A semiconductor structure is provided, the semiconductor structure including a semiconductor layer and at least one trench gate structure extending along the X direction, the semiconductor layer including a source region of a first conductivity type, a drift region of a first conductivity type and a well region of a second conductivity type, the well region being located on the upper surface layer of the drift region, the source region being located on the upper surface layer of the well region, the trench gate structure penetrating the source region and the well region and extending its bottom surface into the drift region, the trench gate structure including a trench, a gate dielectric layer and a gate conductive layer;
[0007] A first interlayer dielectric layer is formed covering the upper surface of the semiconductor structure;
[0008] A first lead-out layer is formed that penetrates the first interlayer dielectric layer and is electrically connected to the source region, and a second lead-out layer is formed that penetrates the first interlayer dielectric layer and extends to the gate conductive layer at the bottom.
[0009] A second interlayer dielectric layer is formed covering the upper surfaces of the first interlayer dielectric layer, the first lead-out layer, and the second lead-out layer;
[0010] A source electrode is formed that penetrates the second interlayer dielectric layer and is electrically connected to the first lead-out layer, a gate electrode that penetrates the second interlayer dielectric layer and is electrically connected to the second lead-out layer, and a drain electrode that is electrically connected to the bottom surface of the semiconductor layer. The dimension of the second lead-out layer in the X direction is not less than the dimension of the source electrode.
[0011] Optionally, the semiconductor layer further includes a first conductivity type substrate, and the drift region is located on the upper surface of the substrate.
[0012] Optionally, the gate dielectric layer covers the inner wall and bottom surface of the trench, the gate conductive layer fills the trench, and the gate dielectric layer wraps around the sidewall and bottom surface of the gate conductive layer.
[0013] Optionally, the trench gate structure further includes an insulating layer, an isolation dielectric layer, and a shielding gate layer. The insulating layer is located below the gate dielectric layer and covers the inner wall and bottom surface of the trench. The shielding gate layer fills the bottom of the trench. The insulating layer wraps the sidewalls and bottom surface of the shielding gate layer. The isolation dielectric layer covers the upper surface of the insulating layer and the shielding gate layer. The gate dielectric layer covers the inner wall of the trench above the isolation dielectric layer. The gate conductive layer fills the trench above the isolation dielectric layer.
[0014] Optionally, the second lead-out layer extends through the gate conductive layer.
[0015] Optionally, the material of the second lead-out layer includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, and platinum.
[0016] Optionally, the semiconductor layer further includes a second conductivity type contact region located in the well region, and the first lead-out layer is electrically connected to the contact region.
[0017] Optionally, the gate is located on both sides of the source in the X direction.
[0018] Optionally, after forming the first interlayer dielectric layer and before forming the first lead-out layer and the second lead-out layer, the method further includes forming a first contact hole and a second contact hole, wherein the first contact hole penetrates the first interlayer dielectric layer and the source region, and the second contact hole penetrates the first interlayer dielectric layer and exposes the gate conductive layer at its bottom.
[0019] The present invention also provides a trench gate device, comprising:
[0020] A semiconductor structure includes a semiconductor layer and at least one trench gate structure extending along the X direction. The semiconductor layer includes a source region of a first conductivity type, a drift region of a first conductivity type, and a well region of a second conductivity type. The well region is located on the upper surface of the drift region, and the source region is located on the upper surface of the well region. The trench gate structure penetrates the source region and the well region and extends its bottom surface into the drift region. The trench gate structure includes a trench, a gate dielectric layer, and a gate conductive layer.
[0021] The first interlayer dielectric layer covers the upper surface of the semiconductor structure;
[0022] The first lead-out layer penetrates the first interlayer dielectric layer and is electrically connected to the source region;
[0023] The second lead-out layer penetrates the first interlayer dielectric layer and is electrically connected to the gate conductive layer.
[0024] The second interlayer dielectric layer covers the upper surfaces of the first interlayer dielectric layer, the first lead-out layer, and the second lead-out layer;
[0025] The source electrode penetrates the second interlayer dielectric layer and is electrically connected to the first lead-out layer, wherein the dimension of the second lead-out layer in the X direction is not less than the dimension of the source electrode;
[0026] The gate penetrates the second interlayer dielectric layer and is electrically connected to the second lead-out layer;
[0027] The drain is electrically connected to the bottom surface of the semiconductor layer.
[0028] As described above, the trench gate device and its fabrication method of the present invention form a first interlayer dielectric layer on the upper surface of a semiconductor structure, and form a first lead-out layer and a second lead-out layer penetrating the first interlayer dielectric layer. Then, a second interlayer dielectric layer is formed covering the first interlayer dielectric layer, the first lead-out layer, and the second lead-out layer, exposing the upper surface, along with a source and a gate penetrating the second interlayer dielectric layer. The source is electrically connected to the first lead-out layer, and the gate is electrically connected to the second lead-out layer. The bottom of the second lead-out layer is buried in the gate conductive layer, increasing the area between the second lead-out layer and the gate conductive layer. This reduces the contact resistance between the second lead-out layer and the gate conductive layer, while also reducing the gate resistance of the device. This avoids the problem of increased gate resistance caused by the reduction in device size. Simultaneously, it reduces the switching losses of the device and improves its performance, thus possessing high industrial application value. Attached Figure Description
[0029] Figure 1 The diagram shows a cross-sectional structure of an SGT MOS device.
[0030] Figure 2 The diagram shows a process flow chart of the method for fabricating the trench gate device of the present invention.
[0031] Figure 3 The diagram shows a cross-sectional structure after the formation of the shielding gate layer in the fabrication method of the trench gate device of the present invention.
[0032] Figure 4 The diagram shows a cross-sectional structure after the formation of the insulating layer in the method for fabricating the trench gate device of the present invention.
[0033] Figure 5 The diagram shows a cross-sectional structure after the isolation material layer in the fabrication method of the trench gate device of the present invention.
[0034] Figure 6 The diagram shows a cross-sectional structure after the formation of the isolation dielectric layer in the fabrication method of the trench gate device of the present invention.
[0035] Figure 7 The diagram shows a cross-sectional structure after the formation of the gate conductive layer in the fabrication method of the trench gate device of the present invention.
[0036] Figure 8 The diagram shown is a cross-sectional view of the trench gate device fabrication method of the present invention after the formation of the first interlayer dielectric layer.
[0037] Figure 9 The diagram shows a cross-sectional structure after forming the first lead-out layer and the second lead-out layer, which is a method for fabricating the trench gate device of the present invention.
[0038] Figure 10 The diagram shows a cross-sectional structure after the formation of the second interlayer dielectric layer in the fabrication method of the trench gate device of the present invention.
[0039] Figure 11 The diagram shows a cross-sectional structure after the formation of the third contact hole in the method for fabricating the trench gate device of the present invention.
[0040] Figure 12 The diagram shown is a cross-sectional view of the trench gate device fabrication method of the present invention after the source electrode is formed.
[0041] Figure 13 The diagram shows the top surface structure after the source and gate are formed in the method for fabricating the trench gate device of the present invention.
[0042] Figure 14 The diagram shows a cross-sectional structure after the drain electrode is formed, which is a method for fabricating the trench gate device of the present invention.
[0043] Figure 15 This is a schematic diagram of another cross-sectional structure after the drain electrode is formed, which is a method for fabricating the trench gate device of the present invention.
[0044] Explanation of icon numbers
[0045] 01 Substrate
[0046] 011 Drift Zone
[0047] 012 P-type well region
[0048] 013 N-type source region
[0049] 014 P-type contact area
[0050] 02 Grid Structure
[0051] 021 Trench
[0052] 022 Insulation layer
[0053] 023 Shielding Grid Layer
[0054] 024 Isolation Dielectric Layer
[0055] 025 Gate dielectric layer
[0056] 026 Polysilicon gate
[0057] 03 Interlayer Dielectric Layer
[0058] 04 Source
[0059] 05 Drain
[0060] 1. Semiconductor Structure
[0061] 11 Semiconductor layer
[0062] 12 Substrates
[0063] 13 Drift Zone
[0064] 14 Tunnel Area
[0065] 15 source regions
[0066] 16 Contact Area
[0067] 17. Groove grid structure
[0068] 171 Trench
[0069] 172 Gate dielectric layer
[0070] 173 Gate conductive layer
[0071] 174 Insulation layer
[0072] 175 Shielding layer
[0073] 176 Isolation Dielectric Layer
[0074] 177mm thick insulation material layer
[0075] 178. Insulation material layer
[0076] 2 First interlayer dielectric layer
[0077] 21 First extraction layer
[0078] 22 Second extraction layer
[0079] 3 Second interlayer dielectric layer
[0080] 31 Third contact hole
[0081] 4 Source
[0082] 41 First plug
[0083] 42 First Interconnect Layer
[0084] 5 Drain
[0085] 6 gates
[0086] 61 Second Interconnect Layer Detailed Implementation
[0087] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0088] Please see Figures 2 to 15 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0089] Example 1
[0090] This embodiment provides a method for fabricating a trench gate device, such as... Figure 2 The diagram shown is a process flow chart of the fabrication method of the trench gate device, including the following steps:
[0091] S1: A semiconductor structure is provided, the semiconductor structure including a semiconductor layer and at least one trench gate structure extending along the X direction, the semiconductor layer including a source region of a first conductivity type, a drift region of a first conductivity type and a well region of a second conductivity type, the well region being located on the upper surface layer of the drift region, the source region being located on the upper surface layer of the well region, the trench gate structure penetrating the source region and the well region and extending to the drift region from the bottom surface, the trench gate structure including a trench, a gate dielectric layer and a gate conductive layer;
[0092] S2: Form a first interlayer dielectric layer covering the upper surface of the semiconductor structure;
[0093] S3: Form a first lead-out layer that penetrates the first interlayer dielectric layer and is electrically connected to the source region, and a second lead-out layer that penetrates the first interlayer dielectric layer and extends to the gate conductive layer at the bottom;
[0094] S4: Form a second interlayer dielectric layer covering the upper surfaces of the first interlayer dielectric layer, the first lead-out layer, and the second lead-out layer;
[0095] S5: Form a source electrode that penetrates the second interlayer dielectric layer and is electrically connected to the first lead-out layer, a gate electrode that penetrates the second interlayer dielectric layer and is electrically connected to the second lead-out layer, and a drain electrode that is electrically connected to the bottom surface of the semiconductor layer, wherein the dimension of the second lead-out layer in the X direction is not less than the dimension of the source electrode.
[0096] Please see Figures 3 to 9 Steps S1, S2, and S3 are executed as follows: A semiconductor structure 1 is provided, which includes a semiconductor layer 11 and at least one trench gate structure 17 extending along the X direction. The semiconductor layer 11 includes a source region 15 of a first conductivity type, a drift region 13 of a first conductivity type, and a well region 14 of a second conductivity type. The well region 14 is located on the upper surface of the drift region 13, and the source region 15 is located on the upper surface of the well region 14. The trench gate structure 17 penetrates the source region 15 and the well region 14 and extends to the drift region 13 at its bottom. The trench gate structure 17 includes a trench 171, a gate dielectric layer 172, and a gate conductive layer 173. A first interlayer dielectric layer 2 is formed covering the upper surface of the semiconductor structure 1. A first lead-out layer 21 is formed penetrating the first interlayer dielectric layer 2 and electrically connected to the source region 15, and a second lead-out layer 22 is formed penetrating the first interlayer dielectric layer 2 and extending to the gate conductive layer 173 at its bottom.
[0097] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.
[0098] Specifically, semiconductor structure 1 is usually the source and gate structure of the device to be fabricated, and its specific size, shape, thickness and construction can be selected according to the actual situation.
[0099] As an example, the semiconductor layer 11 also includes a first conductivity type substrate 12, and the drift region 13 is located on the upper surface of the substrate 12.
[0100] Specifically, substrate 12 is usually the process platform for fabricating drift region 13. In the later stages of device fabrication, substrate 12 is usually thinned and then electrically connected to the drain of the subsequently formed device. While ensuring device performance, the size, shape and doping concentration of substrate 12 can be selected according to the actual situation.
[0101] Specifically, the drift region 13 is usually used to ensure the withstand voltage of the device, and its doping concentration is generally lower than that of the substrate 12. Under the premise of ensuring device performance, the doping concentration of the drift region 13 can be selected according to the actual situation.
[0102] It should be noted that the drift region 13 is usually formed by epitaxial processes, such as chemical vapor deposition or physical vapor deposition. The specific formation method is selected according to the actual situation and is not limited here.
[0103] Specifically, well region 14 is typically a normally doped region. While ensuring device performance, the doping concentration of well region 14 can be selected based on actual conditions. Here, "normal doping" refers to doping relative to heavy or light doping.
[0104] Specifically, the methods for forming the trap region 14 include ion implantation or other suitable methods.
[0105] Specifically, the source region 15 is typically a heavily doped region to form an ohmic contact with the subsequently formed first lead-out layer. While ensuring device performance, the size, shape, and doping concentration of the source region 15 can be selected according to actual conditions. In this embodiment, the source region 15 is formed on the upper surface of the entire well region 14.
[0106] Specifically, the methods for forming source region 15 include ion implantation or other suitable methods.
[0107] As an example, the gate dielectric layer 172 covers the inner wall and bottom surface of the trench 171, the gate conductive layer 173 fills the trench 171, and the gate dielectric layer 172 wraps the side wall and bottom surface of the gate conductive layer 173, that is, the device to be fabricated is a general trench gate device.
[0108] It should be noted that the trench gate structure 17 can typically be formed before or after the formation of the well region 14 and the source region 15. Here, the trench gate structure 17 is formed before the formation of the well region 14.
[0109] Specifically, the device to be fabricated is a conventional trench gate device. The formation of the trench gate structure 17 includes the following steps: forming a patterned first masking layer on the upper surface of the semiconductor layer 11; etching the drift region 13 based on the patterned first masking layer to form a trench 171 of a preset depth; forming a gate dielectric layer 172 covering the inner wall and bottom surface of the trench 171; and forming a gate conductive layer 173 filling the trench 171.
[0110] Specifically, the first masking layer includes a photoresist layer, a hard mask layer, or a stacked film layer composed of a hard mask layer and a photoresist layer. Preferably, a hard mask layer or a stacked film layer composed of a hard mask layer and a photoresist layer is used as the first masking layer.
[0111] Specifically, the methods for patterning the first masking layer are the photoresist patterning process or the hard mask layer patterning process commonly used in photolithography, which will not be elaborated here.
[0112] Specifically, after forming the trench 171 and before forming the gate dielectric layer 172, there is also a step of removing the first masking layer. The method for removing the first masking layer is usually the same as the method for removing the photoresist layer or the hard mask layer, which will not be described in detail here.
[0113] As an example, the trench gate structure 17 also includes an insulating layer 174, an isolation dielectric layer 176, and a shielding gate layer 175. The insulating layer 174 is located below the gate dielectric layer 172 and covers the inner wall and bottom surface of the bottom of the trench 171. The shielding gate layer 175 fills the bottom of the trench 171. The insulating layer 174 wraps the side walls and bottom surface of the shielding gate layer 175. The isolation dielectric layer 176 covers the upper surfaces of the insulating layer 174 and the shielding gate layer 175. The gate dielectric layer 172 covers the inner wall of the trench 171 above the isolation dielectric layer 176. The gate conductive layer 173 fills the trench 171 above the isolation dielectric layer 176. That is, the device to be fabricated is a shielding gate device.
[0114] Specifically, the device to be fabricated is a shielding gate device. The formation of the trench gate structure 17 includes the following steps: forming a patterned second shielding layer on the upper surface of the drift region 13; forming a trench 171 of a preset depth based on the patterned second shielding layer; sequentially forming a thick insulating material layer 177 covering the inner wall and bottom surface of the trench 171 and a trench-filling shielding gate material layer, and etching back the shielding gate material layer and the thick insulating material layer 177 to obtain a shielding gate layer 175 of a preset height and an insulating layer 174 whose upper surface is not higher than the upper surface of the shielding gate layer; forming an isolation material layer 178 filling the remaining part of the trench 171 and etching back the isolation material layer 178 to obtain an isolation dielectric layer 176 covering the insulating layer 174 and the upper surface of the shielding gate layer 175; forming a gate dielectric layer 172 covering at least the upper part of the inner wall of the trench 171 above the isolation dielectric layer 176 and a gate conductive layer 173 filling the upper part of the trench 171 above the isolation dielectric layer 176.
[0115] Specifically, the second masking layer includes a photoresist layer, a hard mask layer, or a stacked film layer composed of a hard mask layer and a photoresist layer. Preferably, a hard mask layer or a stacked film layer composed of a hard mask layer and a photoresist layer is used as the second masking layer.
[0116] Specifically, the methods for patterning the second masking layer are the photoresist patterning process or the hard mask layer patterning process commonly used in photolithography, which will not be elaborated here.
[0117] Specifically, the methods for forming the trench 171 include dry etching, wet etching, or other suitable methods.
[0118] Specifically, after forming the trench 171 and before forming the thick insulating material layer 177, there is also a step of removing the second masking layer. The method for removing the second masking layer is usually the same as the method for removing photoresist layers or hard mask layers, which will not be described in detail here.
[0119] Specifically, the methods for forming the thick insulating material layer 177 include chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods; the methods for forming the shielding grid material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, the thick insulating material layer 177 is formed using a thermal oxidation process.
[0120] Specifically, such as Figure 3 The diagram shows a cross-sectional view of the shielding gate layer 175 after its formation. Methods for etching back the shielding gate material layer include chemical mechanical polishing, dry etching, wet etching, or other suitable methods. Preferably, a combination of chemical mechanical polishing and wet etching processes is used to etch back the shielding gate material layer.
[0121] Specifically, such as Figure 4The diagram shows a cross-sectional structure after the insulating layer 174 is formed. The methods for etching back the thick insulating material layer 177 include dry etching, wet etching, or other suitable methods.
[0122] Specifically, such as Figure 5 The diagram shown is a cross-sectional view of the structure after the formation of the isolation material layer 178. The method for forming the isolation material layer 178 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, a high-density plasma chemical vapor deposition process is used to form the isolation material layer 178.
[0123] Specifically, the methods for etching back the isolation material layer 178 include chemical mechanical polishing, dry etching, wet etching, or other suitable methods. Preferably, a wet process is used to etch back the isolation material layer 178 to obtain the isolation dielectric layer 176.
[0124] Specifically, the method for forming the gate dielectric layer 172 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods. Preferably, when the device to be fabricated is a shielded gate device, a thermal oxidation process is used to form the gate dielectric layer 172 covering the inner wall of the trench 171 above the isolation dielectric layer 176 and the exposed upper surface of the semiconductor layer 11; when the device is a conventional trench gate device, a thermal oxidation process is used to form the gate dielectric layer 172 covering the inner wall and bottom surface of the trench 171 and the exposed upper surface of the semiconductor layer 11.
[0125] Specifically, such as Figure 7 The diagram shown is a cross-sectional view of the gate conductive layer 173 after it has been formed. The methods for forming the gate conductive layer 173 include chemical vapor deposition, physical vapor deposition, or other suitable methods.
[0126] It should be noted that after the gate conductive layer 173 is formed using the deposition process, since the gate conductive layer 173 also covers the semiconductor layer 11, it is necessary to remove the gate conductive layer 173 covering the semiconductor layer 11 after the deposition process is completed, leaving only the portion filling the trench 171 as the gate conductive layer 173 of the device. Chemical mechanical polishing (CMP) can be used to remove the gate conductive layer 173 covering the semiconductor layer 11, or a combination of CMP and dry etching or wet etching can be used to remove the gate conductive layer 173 covering the semiconductor layer 11, or other suitable methods can be used to remove the gate conductive layer 173 covering the semiconductor layer 11.
[0127] Specifically, such as Figure 8 The diagram shown is a cross-sectional view of the structure after the formation of the first interlayer dielectric layer 2. The methods for forming the first interlayer dielectric layer 2 include chemical vapor deposition, physical vapor deposition, or other suitable methods.
[0128] As an example, after forming the first interlayer dielectric layer 2 and before forming the first lead-out layer 21 and the second lead-out layer 22, the method further includes forming a first contact hole and a second contact hole. The first contact hole penetrates the first interlayer dielectric layer 2 and the source region 15, and the second contact hole penetrates the first interlayer dielectric layer 5 and exposes the gate conductive layer 173 at the bottom.
[0129] Specifically, the first contact hole and the second contact hole can be formed simultaneously or in stages. Compared with making the first contact hole and the second contact hole in stages, forming the first contact hole and the second contact hole simultaneously can simplify the process steps and reduce the manufacturing cost.
[0130] Specifically, taking the simultaneous formation of the first contact hole and the second contact hole as an example, the formation of the first contact hole and the second contact hole includes the following steps: forming a patterned third shielding layer on the upper surface of the first interlayer dielectric layer 2; and simultaneously forming the first contact hole and the second contact hole based on the patterned third shielding layer.
[0131] Specifically, the third masking layer includes a photoresist layer, a hard mask layer, or a stacked film layer composed of a hard mask layer and a photoresist layer. Preferably, a hard mask layer or a stacked film layer composed of a hard mask layer and a photoresist layer is used as the third masking layer.
[0132] Specifically, the methods for simultaneously forming the first contact hole and the second contact hole include dry etching, wet etching, or other suitable methods. Preferably, dry etching is used to form the first contact hole and the second contact hole.
[0133] It should be noted that when simultaneously forming the first and second contact holes, compared to the manufacturing process of ordinary shielding gate devices, it is necessary to add a step of making a mask for forming the first and second contact holes, and then patterning the third shielding layer based on the mask. When forming the first and second contact holes in stages, it is necessary to make the shielding layer for forming the first contact hole and the shielding layer for forming the second contact hole separately. It is also necessary to make two corresponding masks to pattern the shielding layer for forming the first contact hole and the shielding layer for forming the second contact hole, respectively. Furthermore, the depths of the first and second contact holes formed in stages can be the same or different. Here, depth refers to the distance between the bottom surface of the first contact hole (second contact hole) and the opening of the first contact hole (second contact hole).
[0134] Specifically, after the first contact hole and the second contact hole are formed simultaneously, and before the second interlayer dielectric layer 3 is formed, there is also a step of removing the third masking layer. The method for removing the third masking layer is usually the same as the method for removing photoresist layer or hard mask layer, which will not be described in detail here.
[0135] Specifically, the groove 171 extends along the X direction, and the first end and the second end of the groove 171 are arranged sequentially along the X direction (here, the first end and the second end are the two ends of the groove 171 in the X direction). The distance between the end of the first contact hole adjacent to the first end and the first end is greater than the distance between the end of the second contact hole adjacent to the first end and the first end. The distance between the end of the first contact hole adjacent to the second end and the second end is greater than the distance between the end of the second contact hole adjacent to the second end and the second end.
[0136] Specifically, while ensuring device performance, the distance between the first contact hole and the first end of the trench 171 in the X direction can be selected according to actual conditions; the distance between the first contact hole and the second end of the trench 171 can be selected according to actual conditions; the distance between the second contact hole and the first end of the trench 171 can be selected according to actual conditions; and the distance between the second contact hole and the second end of the trench 171 can be selected according to actual conditions. Preferably, the dimension of the first contact hole in the X direction is not less than the dimension of the opening of the trench 171 in the X direction. While ensuring the contact performance between the first lead-out layer 21 and the well region 14, the size of the first contact hole in the X direction can also be smaller than the size of the trench 171 opening in the X direction.
[0137] As an example, the semiconductor layer 11 also includes a second conductivity type contact region 16, which is located in the well region 14, and the first lead-out layer 21 is electrically connected to the contact region 16.
[0138] Specifically, the contact area 16 is used to form an ohmic contact between the trap area 14 and the first lead-out layer 21. The contact area 16 can be formed after the formation of the first contact hole and before the formation of the first lead-out layer 21 that fills the first contact hole, or it can be formed before the formation of the first interlayer dielectric layer 2. If the contact area 16 is formed before the formation of the first interlayer dielectric layer 2, then the bottom of the formed first contact hole will expose the contact area 16.
[0139] Specifically, the method for forming the contact region 16 includes ion implantation or other suitable methods. In this embodiment, after forming the first contact hole and before forming the first lead-out layer 21, the contact region 16 is formed by ion implantation into the well region 14 exposed at the bottom of the first contact hole.
[0140] It should be noted that the first and second contact holes are formed in steps. Regardless of whether the first or second contact hole is formed first, before forming the next contact hole, the shielding layer of the previous contact hole must be removed and the lead-out layer that fills the previous contact hole must be formed. Similarly, before forming the second interlayer dielectric layer, the shielding layer of the next contact hole must be removed and the lead-out layer that fills the next contact hole must be formed.
[0141] Specifically, such as Figure 9 The diagram shown is a cross-sectional view of the structure after the formation of the first take-off layer 21 and the second take-off layer 22. The method for forming the first take-off layer 21 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The method for forming the second take-off layer 22 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
[0142] It should be noted that when the source region 15 is located on the upper surface of the entire well region 14, the first contact hole needs to penetrate the source region 15. The first lead-out layer 21 is electrically connected to the source region 15 and simultaneously forms an electrical connection with the well region 14 through the contact area 16 at the bottom of the first contact hole. When the source region 15 and the contact area 16 on the upper surface of the well region 14 are alternately arranged along the arrangement direction of the trench grid structure 17, the first contact hole does not need to penetrate the source region 15. The first lead-out layer 21 is electrically connected to the source region 15 and simultaneously forms an electrical connection with the well region 14 through the contact area 16 at the bottom of the first contact hole.
[0143] Specifically, the material of the first lead-out layer 21 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials. Preferably, a composite structure consisting of a titanium layer, a titanium nitride layer, and a tungsten layer is used as the first lead-out layer 21.
[0144] As an example, the second lead-out layer 22 penetrates the gate conductive layer 173. That is, when the device is a shielded gate device, the second lead-out layer 22 penetrates the gate conductive layer 173, and the bottom surface of the second lead-out layer 22 is flush with the upper surface of the isolation dielectric layer 176.
[0145] Specifically, when the bottom surface of the second lead-out layer 22 is flush with the upper surface of the isolation dielectric layer 176, since the upper surface of the isolation dielectric layer 176 is lower than the bottom surface of the well region 14, in order to ensure the performance of the device, the first contact hole and the second contact hole need to be formed in stages. Therefore, the first lead-out layer 21 and the second lead-out layer 22 usually also need to be formed in stages.
[0146] Specifically, while ensuring good contact performance between the gate conductive layer 173 and the second lead-out layer 22, the bottom surface of the second lead-out layer 22 can be flush with the upper surface of the gate conductive layer 173, or it can be located within the gate conductive layer 173. Preferably, the bottom of the second lead-out layer 22 is embedded in the gate conductive layer 173.
[0147] Specifically, by extending the bottom surface of the second contact hole into the gate conductive layer 173, the area of the contact region between the second lead-out layer 22 and the gate conductive layer 173 is increased. The resistivity of the gate conductive layer 173 is greater than that of the second lead-out layer 22, thereby reducing the contact resistance between the second lead-out layer 22 and the gate conductive layer 173, and thus reducing the gate resistance of the device. It should be noted that when polysilicon and tungsten are used as the gate conductive layer 173 and the second lead-out layer 22, respectively, the resistivity of polysilicon is typically 0.01–1 Ω·m, and the resistivity of tungsten is 4.9 × 10⁻⁶. -8 Ω.m can greatly reduce gate resistance.
[0148] As an example, the material of the second lead-out layer 22 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials. Preferably, a composite layer structure consisting of a titanium layer, a titanium nitride layer, and a tungsten layer is used as the second lead-out layer 22.
[0149] Please see Figures 10 to 15 Steps S4 and S5 are executed: a second interlayer dielectric layer 3 is formed covering the upper surfaces of the first interlayer dielectric layer 2, the first lead-out layer 21 and the second lead-out layer 22; a source 4 is formed that penetrates the second interlayer dielectric layer 3 and is electrically connected to the first lead-out layer 21, a gate 6 is formed that penetrates the second interlayer dielectric layer 3 and is electrically connected to the second lead-out layer 22, and a drain 5 is formed that is electrically connected to the bottom surface of the semiconductor layer 11, wherein the size of the second lead-out layer 22 in the X direction is not less than the size of the source 4.
[0150] Specifically, such as Figure 10 The diagram shown is a cross-sectional view of the structure after the formation of the second interlayer dielectric layer 3. The methods for forming the second interlayer dielectric layer 3 include chemical vapor deposition, physical vapor deposition, or other suitable methods.
[0151] Specifically, such as Figure 11 The diagram shows a cross-sectional structure after the formation of the third contact hole 31. After the formation of the second interlayer dielectric layer 3 and before the formation of the gate 6 and the source 4, the process also includes the steps of forming the third contact hole 31 and the fourth contact hole. The third contact hole 31 penetrates the second interlayer dielectric layer 3 and exposes the first lead-out layer 21 on its bottom surface. The fourth contact hole penetrates the second interlayer dielectric layer 3 and exposes the second lead-out layer 22 on its bottom surface.
[0152] Specifically, the third contact hole 31 and the fourth contact hole are usually formed simultaneously, or they can be formed in steps. Preferably, the third contact hole 31 and the fourth contact hole are formed simultaneously to reduce process steps and lower the manufacturing cost of the device.
[0153] Specifically, methods for simultaneously forming the third contact hole 31 and the fourth contact hole include dry etching, wet etching, or other suitable methods.
[0154] As an example, such as Figure 12 and Figure 13 The figures show a cross-sectional view of the source 4 and gate 6 after their formation and a top view of the source 4 and gate 6 after their formation. The gate 6 is located on both sides of the source 4 in the X direction. That is, in the X direction, the gate 6 is formed at intervals on both sides of the source 4 and electrically connected to the second lead-out layer 22 below it.
[0155] Specifically, the source 4 includes a first plug 41 filling the third contact hole 31 and a first interconnect layer 42 located on the upper surface of the second interlayer dielectric layer 3, and the gate 6 includes a second plug filling the fourth contact hole and a second interconnect layer 61 located on the upper surface of the second interlayer dielectric layer 3.
[0156] Specifically, the methods for forming the first plug 41 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the methods for forming the second plug include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the methods for forming the first interconnect layer 42 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; and the methods for forming the second interconnect layer 61 include having the gate located on both sides of the source in the X direction. In this embodiment, a filler metal layer is formed simultaneously to fill the third contact hole 31 and the fourth contact hole, and the filler metal layer covering the upper surface of the second interlayer dielectric layer 3 is removed to obtain the first plug 41 and the second plug. Then, an interconnect metal layer covering the upper surface of the second interlayer dielectric layer 3 is formed simultaneously, and the interconnect metal layer is etched to obtain the first interconnect layer 42 electrically connected to the first plug 41 and the second interconnect layer 61 electrically connected to the second plug.
[0157] Specifically, such as Figure 14 and 15 The figures show two cross-sectional structural diagrams after the formation of drain 5, one for one cross-section and the other for the other. Drain 5 is electrically connected to the bottom surface of substrate 12. The methods for forming drain 5 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
[0158] Specifically, before forming the gate 4 and source 6 of the device, a first interlayer dielectric layer 2 is first formed, and a first lead-out layer 21 and a second lead-out layer 22 are formed through the first interlayer dielectric layer 2. The second lead-out layer 22 is buried in the gate conductive layer 173, and then the gate 6 is electrically connected to the second lead-out layer 22 to realize the electrical connection between the gate 6 and the gate conductive layer 173. This increases the area of the contact region between the second lead-out layer 22 and the gate conductive layer 173, reduces the contact resistance between the gate conductive layer 173 and the second lead-out layer 22, and reduces the gate resistance of the device. This avoids the increase in gate resistance caused by the reduction of device size, and facilitates the reduction of device size.
[0159] Specifically, by embedding the second lead-out layer 22 into the gate conductive layer 173, the gate resistance of the device is reduced, the switching loss of the device is reduced, and the performance of the device is improved.
[0160] The trench gate device fabrication method of this embodiment improves the device fabrication process by adding the steps of forming a first interlayer dielectric layer 2, a first lead-out layer 21 penetrating the first interlayer dielectric layer 2, and a second lead-out layer 22 before forming the source 4 and gate 6 of the device. The first lead-out layer 21 is electrically connected to the well region 14 and the source region 15, and the second lead-out layer 22 is buried in the gate conductive layer 173. Then, the gate 6, which is electrically connected to the second lead-out layer 22, is fabricated. This increases the area of the region where the second lead-out layer 22 contacts the gate conductive layer 173, reduces the contact resistance between the gate 6 and the gate conductive layer 173, and thus reduces the gate resistance of the device, reduces the switching loss of the device, avoids the problem of increased gate resistance while shrinking the device size, facilitates the shrinkage of the device size, and improves the performance of the device.
[0161] Example 2
[0162] This embodiment also provides a trench gate device, such as Figure 14 and Figure 15The diagrams shown are schematic cross-sectional views of several trench gate devices, including a semiconductor structure 1, a first interlayer dielectric layer 2, a first lead-out layer 21, a second lead-out layer 22, a second interlayer dielectric layer 3, a source 4, a gate 6, and a drain 5. The semiconductor structure 1 includes a semiconductor layer 11 and at least one trench gate structure 17 extending along the X-direction. The semiconductor layer 11 includes a first conductivity type source region 15, a first conductivity type drift region 13, and a second conductivity type well region 14. The well region 14 is located on the upper surface of the drift region 13, and the source region 15 is located on the upper surface of the well region 14. The trench gate structure 17 penetrates the source region 15 and the well region 14 and extends its bottom surface into the drift region 13. The trench gate structure 17 includes a trench 17. 1. Gate dielectric layer 172 and gate conductive layer 173; First interlayer dielectric layer 2 covers the upper surface of semiconductor structure 1; First lead-out layer 21 penetrates the first interlayer dielectric layer 2 and is electrically connected to source region 15; Second lead-out layer 22 penetrates the first interlayer dielectric layer 2 and extends to the gate conductive layer 173 at its bottom; Second interlayer dielectric layer 3 covers the exposed upper surfaces of the first interlayer dielectric layer 2, first lead-out layer 21 and second lead-out layer 22; Source 4 penetrates the second interlayer dielectric layer 3 and is electrically connected to the first lead-out layer 21, and the size of the second lead-out layer 22 in the X direction is not less than the size of the source 4; Gate 6 penetrates the second interlayer dielectric layer 3 and is electrically connected to the second lead-out layer 22; Drain 5 is electrically connected to the bottom surface of semiconductor layer 11.
[0163] Specifically, the semiconductor structure 1 is a structure for fabricating the source electrode 4 and the gate electrode 6. The semiconductor layer 11 of the semiconductor structure 1 also includes a first conductivity type substrate 12, and the drift region 13 is located on the upper surface of the substrate 12.
[0164] Specifically, the substrate 12 may be made of silicon, silicon germanium, silicon carbide, diamond, or other suitable semiconductor materials. Preferably, a silicon wafer is used as the substrate 12.
[0165] Specifically, while ensuring device performance, the thickness of substrate 12 can be selected according to actual conditions; the thickness of drift region 13 can be selected according to actual conditions; the thickness of well region 14 can be selected according to actual conditions; and the thickness of source region 15 can be selected according to actual conditions.
[0166] Specifically, while ensuring device performance, the opening size, shape, and depth of trench 171 can be selected according to actual conditions. Here, depth refers to the distance between the bottom surface of trench 171 and the opening of the trench.
[0167] Specifically, the gate dielectric layer 172 covers the inner wall and bottom surface of the trench 171, the gate conductive layer 173 fills the trench 171, and the gate dielectric layer 172 wraps the side wall and bottom surface of the gate conductive layer 173, that is, the device to be fabricated is a common trench gate device.
[0168] It should be noted that the trench gate device can also be a shielded gate device. When it is a shielded gate device, the trench gate structure 17 further includes an insulating layer 174, an isolation dielectric layer 176, and a shielding gate layer 175. The insulating layer 174 is located below the gate dielectric layer 172 and covers the inner wall and bottom surface of the bottom of the trench 171. The shielding gate layer 175 fills the bottom of the trench 171. The insulating layer 174 wraps the side walls and bottom surface of the shielding gate layer 174. The isolation dielectric layer 176 covers the upper surface of the insulating layer 174 and the shielding gate layer 175. The gate dielectric layer 172 covers the inner wall of the trench 171 above the isolation dielectric layer 176. The gate conductive layer 173 fills the trench 171 above the isolation dielectric layer 176.
[0169] Specifically, the insulating layer 174 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the gate dielectric layer 172 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the shielding gate layer 175 is made of polysilicon or other suitable conductive materials; the gate conductive layer 173 is made of polysilicon or other suitable conductive materials; and the isolation dielectric layer 176 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
[0170] Specifically, while ensuring device performance, the thickness of the insulating layer 174 can be selected according to the actual situation; the thickness of the isolation dielectric layer can be selected according to the actual situation; and the thickness of the gate dielectric layer 172 can be selected according to the actual situation.
[0171] Specifically, the well region 14 is also provided with a second conductive contact region 16 with its bottom surface spaced at a preset distance from the bottom surface of the well region 14. The thickness of the contact region 16 can be selected according to the actual situation while ensuring the performance of the device.
[0172] Specifically, the first interlayer dielectric layer 2 is further provided with a first contact hole and a second contact hole that penetrate the first interlayer dielectric layer 2. The bottom of the first contact hole exposes the source region 15 and the contact region 16, and the bottom of the second contact hole exposes the gate conductive layer 173.
[0173] Specifically, the first end and the second end of the groove 171 are arranged sequentially along the X direction (here, the first end and the second end are the two ends of the groove 171 in the X direction). The distance between the end of the first contact hole adjacent to the first end and the first end is greater than the distance between the end of the second contact hole adjacent to the first end and the first end. The distance between the end of the first contact hole adjacent to the second end and the second end is greater than the distance between the end of the second contact hole adjacent to the second end and the second end.
[0174] Specifically, while ensuring device performance, the opening size and shape of the first contact hole can be selected according to the actual situation; the opening shape and size of the second contact hole can be selected according to the actual situation.
[0175] Specifically, while ensuring device performance, the thickness of the first interlayer dielectric layer 2 can be selected according to the actual situation.
[0176] Specifically, the material of the first interlayer dielectric layer 2 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
[0177] Specifically, while ensuring device performance, the material of the first lead-out layer 21 can be the same as or different from the material of the second lead-out layer 22. Preferably, the material of the first lead-out layer 21 is the same as the material of the second lead-out layer 22.
[0178] Specifically, the material of the second interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
[0179] Specifically, the second interlayer dielectric layer 3 is further provided with a third contact hole 31 and a fourth contact hole that penetrate the second interlayer dielectric layer 3. The bottom surface of the third contact hole 31 exposes the first lead-out layer 21, and the bottom surface of the fourth contact hole exposes the second lead-out layer 22.
[0180] Specifically, while ensuring device performance, the opening size and shape of the third contact hole 31 can be selected according to the actual situation; the opening size and shape of the fourth contact hole can be selected according to the actual situation.
[0181] Specifically, in the X direction, the gate 6 is spaced on both sides of the source 4 and electrically connected to the second lead-out layer 22 below it. The source 4 includes a first plug 41 filling the third contact hole 31 and a first interconnect layer 42 located on the upper surface of the second interlayer dielectric layer 3. The gate 6 includes a second plug filling the fourth contact hole and a second interconnect layer 61 located on the upper surface of the second interlayer dielectric layer 3.
[0182] Specifically, the first plug 41 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials; the second plug is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials. Preferably, the first plug 41, the second plug, the first lead-out layer 21, and the second lead-out layer 22 are made of the same material.
[0183] Specifically, the material of the first interconnect layer 42 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the second interconnect layer 61 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; and the material of the drain electrode 5 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.
[0184] Specifically, by providing a second lead-out layer 22 with its two ends electrically connected to the gate 6 and the gate conductive layer 173 respectively between the gate 6 and the gate conductive layer 173, and the bottom of the second lead-out layer 22 being buried in the gate conductive layer 173, the contact resistance between the second lead-out layer 22 and the gate conductive layer 173 is reduced, and the gate resistance of the device is also reduced.
[0185] Specifically, by embedding the second lead-out layer 22 in the gate conductive layer 173, the area of the contact region between the gate conductive layer 173 and the second lead-out layer 22 is increased, thereby further reducing the contact resistance between the second lead-out layer 22 and the gate conductive layer 173, reducing the gate resistance and switching loss of the device, and improving the performance of the device.
[0186] The trench gate device of this embodiment improves the device structure by forming a second lead-out layer 22 between the gate 6 and the gate conductive layer 173, and the bottom of the second lead-out layer 22 is buried in the gate conductive layer 173. This reduces the contact resistance between the second lead-out layer 22 and the gate conductive layer 173, while also reducing the gate resistance of the device, thereby reducing the switching loss of the device and improving the performance of the device.
[0187] In summary, the trench gate device and its fabrication method of the present invention improve the fabrication process of the trench gate device by forming a second lead-out layer penetrating the first interlayer dielectric layer before forming the source and gate electrodes. The bottom of the second lead-out layer is buried in the gate conductive layer, which increases the contact area between the second lead-out layer and the gate conductive layer, reduces the contact resistance between the two layers, and simultaneously reduces the gate resistance of the device. This, in turn, reduces the switching losses of the device and avoids the problem of increased gate resistance caused by shrinking the device size, facilitating device miniaturization and improving device performance. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0188] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a trench gate device, characterized in that, Includes the following steps: A semiconductor structure is provided, the semiconductor structure including a semiconductor layer and at least one trench gate structure extending along the X direction, the semiconductor layer including a source region of a first conductivity type, a drift region of a first conductivity type and a well region of a second conductivity type, the well region being located on the upper surface layer of the drift region, the source region being located on the upper surface layer of the well region, the trench gate structure penetrating the source region and the well region and extending its bottom surface into the drift region, the trench gate structure including a trench, a gate dielectric layer and a gate conductive layer; A first interlayer dielectric layer is formed covering the upper surface of the semiconductor structure; A first lead-out layer is formed that penetrates the first interlayer dielectric layer and is electrically connected to the source region, and a second lead-out layer is formed that penetrates the first interlayer dielectric layer and extends to the gate conductive layer at the bottom. A second interlayer dielectric layer is formed covering the upper surfaces of the first interlayer dielectric layer, the first lead-out layer, and the second lead-out layer; A source electrode is formed that penetrates the second interlayer dielectric layer and is electrically connected to the first lead-out layer, a gate electrode that penetrates the second interlayer dielectric layer and is electrically connected to the second lead-out layer, and a drain electrode that is electrically connected to the bottom surface of the semiconductor layer. The dimension of the second lead-out layer in the X direction is not less than the dimension of the source electrode.
2. The method for fabricating a trench gate device according to claim 1, characterized in that: The semiconductor layer also includes a first conductivity type substrate, and the drift region is located on the upper surface of the substrate.
3. The method for fabricating a trench gate device according to claim 1, characterized in that: The gate dielectric layer covers the inner wall and bottom surface of the trench, the gate conductive layer fills the trench, and the gate dielectric layer wraps around the sidewalls and bottom surface of the gate conductive layer.
4. The method for fabricating a trench gate device according to claim 1, characterized in that: The trench gate structure further includes an insulating layer, an isolation dielectric layer, and a shielding gate layer. The insulating layer is located below the gate dielectric layer and covers the inner wall and bottom surface of the trench. The shielding gate layer fills the bottom of the trench. The insulating layer wraps the sidewalls and bottom surface of the shielding gate layer. The isolation dielectric layer covers the upper surface of the insulating layer and the shielding gate layer. The gate dielectric layer covers the inner wall of the trench above the isolation dielectric layer. The gate conductive layer fills the trench above the isolation dielectric layer.
5. The method for fabricating a trench gate device according to claim 4, characterized in that: The second lead-out layer penetrates the gate conductive layer.
6. The method for fabricating a trench gate device according to claim 1, characterized in that: The materials of the second lead-out layer include titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, and platinum.
7. The method for fabricating a trench gate device according to claim 1, characterized in that: The semiconductor layer further includes a second conductivity type contact region located in the well region, and the first lead-out layer is electrically connected to the contact region.
8. The method for fabricating a trench gate device according to claim 1, characterized in that: The gate is located on both sides of the source in the X direction.
9. The method for fabricating a trench gate device according to claim 1, characterized in that: After forming the first interlayer dielectric layer and before forming the first lead-out layer and the second lead-out layer, the method further includes forming a first contact hole and a second contact hole. The first contact hole penetrates the first interlayer dielectric layer and the source region, and the second contact hole penetrates the first interlayer dielectric layer and exposes the gate conductive layer at its bottom.
10. A trench gate device, characterized in that, include: A semiconductor structure includes a semiconductor layer and at least one trench gate structure extending along the X direction. The semiconductor layer includes a source region of a first conductivity type, a drift region of a first conductivity type, and a well region of a second conductivity type. The well region is located on the upper surface of the drift region, and the source region is located on the upper surface of the well region. The trench gate structure penetrates the source region and the well region and extends its bottom surface into the drift region. The trench gate structure includes a trench, a gate dielectric layer, and a gate conductive layer. The first interlayer dielectric layer covers the upper surface of the semiconductor structure; The first lead-out layer penetrates the first interlayer dielectric layer and is electrically connected to the source region; The second lead-out layer extends through the bottom of the first interlayer dielectric layer into the gate conductive layer; The second interlayer dielectric layer covers the upper surfaces of the first interlayer dielectric layer, the first lead-out layer, and the second lead-out layer; The source electrode penetrates the second interlayer dielectric layer and is electrically connected to the first lead-out layer, wherein the dimension of the second lead-out layer in the X direction is not less than the dimension of the source electrode; The gate penetrates the second interlayer dielectric layer and is electrically connected to the second lead-out layer; The drain is electrically connected to the bottom surface of the semiconductor layer.