integrated circuit

Abstract

An integrated circuit enables power to flow stably within cell boundaries and includes a back-side wiring layer capable of reducing coupling interference between devices, comprising: a back-side wiring layer including a plurality of back-side metal lines each extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a field-effect transistor (FET) disposed above the back-side wiring layer; and a front-side wiring layer disposed above the FET and including a plurality of front-side metal lines extending in the first direction and spaced apart from each other in the second direction, wherein n number of front-side metal lines are arranged in the cell in the second direction at a first spacing, and m number of back-side metal lines are arranged in the cell in the second direction at a second spacing.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0196074, filed on December 24, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to integrated circuits. Background Technology

[0003] Recently, as integrated circuits have become more advanced in scale, back-side power delivery networks (BSPDNs) have been adopted. BSPDN literally means the technology used to apply PDN to the back side. Here, a network can refer to a set of interconnects, and interconnects can generally refer to metal interconnects. Furthermore, depending on the application, networks can be classified as signal networks and power supply networks. A signal network represents a set of interconnects used to exchange signals between transistors or with external devices. On the other hand, a power supply network represents a set of interconnects used to supply power to operate transistors. According to existing technology, power is delivered via the front side; however, recently, power can also be delivered via the back side using BSPDNs. Summary of the Invention

[0004] In general, this disclosure relates to an integrated circuit that enables stable power flow within cell boundaries and includes a back-side wiring layer capable of reducing coupling interference between devices.

[0005] According to some embodiments, this disclosure relates to an integrated circuit, the integrated circuit comprising: a back-side wiring layer including a plurality of back-side metal lines each extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a field-effect transistor (FET) disposed above the back-side wiring layer; and a front-side wiring layer disposed above the FET and including a plurality of front-side metal lines extending in the first direction and spaced apart from each other in the second direction, wherein n front-side metal lines are arranged in a cell in the second direction at a first spacing (where n is an integer greater than or equal to 1), and m back-side metal lines are arranged in the cell in the second direction at a second spacing (where m is an integer greater than or equal to 1).

[0006] According to some embodiments, this disclosure relates to an integrated circuit, the integrated circuit comprising: a back-side wiring layer including a plurality of back-side metal lines each extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a cell region disposed above the back-side wiring layer and including: an active region extending in the first direction and spaced apart from each other in the second direction, and a gate line extending in the second direction and spaced apart from each other in the first direction; and a front-side wiring layer disposed above the cell region and including a plurality of front-side metal lines extending in the first direction and spaced apart from each other in the second direction, wherein a first front-side power line and a second front-side power line among the plurality of front-side metal lines are aligned with cell boundaries (CB) on both sides of the cell in the cell region in the second direction, the first back-side power line and the second back-side power line among the plurality of back-side metal lines are aligned with the CB on both sides of the cell in the second direction, n front-side metal lines are arranged in the second direction at a first spacing inside the cell (where n is an integer greater than or equal to 1), and m back-side metal lines are arranged in the second direction at a second spacing inside the cell (where m is an integer greater than or equal to 1).

[0007] According to some embodiments, this disclosure relates to an integrated circuit, the integrated circuit comprising: a back-side wiring layer including a plurality of back-side metal lines each extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a FET disposed above the back-side wiring layer; and a front-side wiring layer disposed above the FET and including a plurality of front-side metal lines extending in the first direction and spaced apart from each other in the second direction, wherein a first front-side power line and a second front-side power line among the plurality of front-side metal lines are aligned with the CB of a cell in the second direction, and power is applied to the first front-side power line and the second front-side power line; a first back-side power line and a second back-side power line among the plurality of back-side metal lines are aligned with the CB of the cell on both sides in the second direction, and power is applied to the first back-side power line and the second back-side power line; n front-side metal lines are arranged in the cell in the second direction at a first spacing (where n is an integer greater than or equal to 1), and m back-side metal lines are arranged in the cell in the second direction at a second spacing (where m is an integer greater than or equal to 1). Attached Figure Description

[0008] The exemplary embodiments will be more clearly understood from the following detailed explanation in conjunction with the accompanying drawings.

[0009] Figure 1A and Figure 1B These are layout and cross-sectional views of examples of integrated circuits including a back-side wiring layer according to some implementation methods.

[0010] Figure 2This is a graph illustrating examples of coupling effects between devices when current is supplied to the M1 metal line at the cell boundary or when no current is supplied to the M1 metal line at the cell boundary, according to some embodiments.

[0011] Figure 3A and Figure 3B These are example layout diagrams of an integrated circuit according to some implementations within a single unit and an integrated circuit according to a comparative example.

[0012] Figure 4A and Figure 4B These are examples illustrating different implementations. Figure 3A and Figure 3B A conceptual diagram illustrating an example of the vertical positional relationship between the back-side wiring layer and the front-side wiring layer in an integrated circuit.

[0013] Figures 5A to 5D A layout diagram illustrating examples of various ratios between the spacing of the front metal lines of the front wiring layer and the spacing of the back metal lines of the back wiring layer within a cell according to some embodiments.

[0014] Figures 6A to 6D This is a perspective view illustrating example structures of various FETs that can be included in an integrated circuit according to some embodiments. Detailed Implementation

[0015] In the following text, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0016] Figure 1A This is a layout diagram of an example integrated circuit 100 including a back-side wiring layer according to some embodiments, and Figure 1B It is based on some implementation methods along Figure 1A A cross-sectional view of integrated circuit 100 taken by line I-I'. Figure 2 This is a graph illustrating examples of coupling effects between devices when current is supplied to the M1 metal line at the cell boundary or when no current is supplied to the M1 metal line at the cell boundary, according to some embodiments.

[0017] exist Figure 1A and Figure 1B In this configuration, integrated circuit 100 may include a back-side wiring layer 110, a field-effect transistor (FET), and a front-side wiring layer 120. Here, the back-side (BS) may represent the lower side in the z-direction, and the front-side (FS) may represent the upper side in the z-direction. For example, in... Figure 1B In this configuration, the back-side wiring layer 110, the FET, and the front-side wiring layer 120 can be arranged in this order along the z-direction. For reference, in... Figure 1AIn the diagram, the top layout corresponds to a plan view of the integrated circuit 100 when viewed from the front, and the bottom layout corresponds to a plan view of the integrated circuit 100 when viewed from the back. Furthermore, Figure 1B The cross-sectional view corresponding to integrated circuit 100 shows two cells cut in the y-direction.

[0018] The back-side wiring layer 110 may include multiple back-side metal lines extending in the x-direction and spaced apart from each other in the y-direction. The back-side metal lines may include a first back-side power line 110P-1, a second back-side power line 110P-2, and a back-side signal line 110S. The first back-side power line 110P-1 may provide a first power VDD (e.g., a positive potential power) to the FET. The second back-side power line 110P-2 may be spaced apart from the first back-side power line 110P-1 in the y-direction and provide a second power VSS (e.g., a negative potential or ground potential power) to the FET. The first back-side power line 110P-1 and the second back-side power line 110P-2 may be connected to the active region ACT via a back-side contact 150 in a power tap cell (PTC). The back-side signal line 110S may be located in the y-direction between the first back-side power line 110P-1 and the second back-side power line 110P-2. The back-side signal line 110S may be connected to the source / drain of the FET. Signals can be input to and output from the FET via back-side signal lines 110S. In some embodiments, back-side signal lines 110S may be omitted. In some embodiments, multiple back-side signal lines 110S may be arranged between the first back-side power line 110P-1 and the second back-side power line 110P-2.

[0019] In integrated circuit 100, the back-side wiring layer 110 may correspond to the uppermost metal wiring layer among the multilayer metal wiring layers arranged on the back side of integrated circuit 100. In other words, the back-side wiring layer 110 may correspond to the metal wiring layer closest to the FET on the back side (e.g., the back-side M1 metal wiring layer). Furthermore, the first back-side power line 110P-1 and the second back-side power line 110P-2 of the back-side wiring layer 110 may be aligned with the cell boundaries CB on both sides of a cell in the y-direction. Furthermore, the first back-side power line 110P-1 and the second back-side power line 110P-2 may be arranged alternately in the y-direction.

[0020] When describing the cell in more detail, according to some embodiments, the cell region may be located between the back wiring layer 110 and the front wiring layer 120 in the integrated circuit 100. Furthermore, a plurality of active regions ACT and gate lines 140 may be arranged in the cell region. The active regions ACT may each extend in the x-direction and be spaced apart from each other in the y-direction. The gate lines 140 may each extend in the y-direction and be spaced apart from each other in the x-direction. A cell may include two active regions ACT in the y-direction (e.g., a first active region ACT1 and a second active region ACT2). Additionally, a cell may include source / drain electrodes 132 arranged on both sides of a gate line 140 in the x-direction (see...). Figure 6C ).

[0021] Furthermore, the element height CH can represent the width of an element in the y-direction and corresponds to the distance between the element boundaries CB on both sides of an element in the y-direction. Here, the element boundary CB can be defined at the midpoint between two adjacent active regions ACT in two adjacent elements in the y-direction. For example, when Figure 1A The unit shown (i.e., Figure 1B The cell on the right side of the image is the first cell, Cell1, and the cell below the first cell, Cell1, in the y-direction (i.e., Figure 1B When the cell on the left is the second cell (Cell2), the midpoint between the first active region ACT1 of the first cell (Cell1) and the second active region ACT2 of the second cell (Cell2) can correspond to the cell boundary CB on the lower side of the first cell (Cell1). Furthermore, when the cell located above the first cell (Cell1) in the y-direction is called the third cell, the midpoint between the second active region ACT2 of the first cell (Cell1) and the first active region ACT1 of the third cell can correspond to the cell boundary CB on the upper side of the first cell (Cell1).

[0022] exist Figure 1A and Figure 1B In integrated circuit 100, the first back-side power line 110P-1 and the second back-side power line 110P-2 can be aligned with the cell boundaries CB on both sides of a cell in the y-direction, respectively. (Refer to...) Figure 5A and Figure 5B The arrangement of the back wiring layer 110 in the y direction is described in more detail.

[0023] The front-side wiring layer 120 may include multiple front-side metal lines extending in the x-direction and spaced apart from each other in the y-direction. The front-side metal lines may include a first front-side power line 120P-1, a second front-side power line 120P-2, and a front-side signal line 120S. The first front-side power line 120P-1 may provide a first power VDD (e.g., a positive potential power) to the FET. The second front-side power line 120P-2 may be spaced apart from the first front-side power line 120P-1 in the y-direction and provide a second power VSS (e.g., a negative potential or ground potential power) to the FET. The first front-side power line 120P-1 and the second front-side power line 120P-2 may be connected to the active region ACT via a contact 160 in the power tap unit PTC. The front-side signal line 120S may be located in the y-direction between the first front-side power line 120P-1 and the second front-side power line 120P-2. The front-side signal line 120S may be connected to the source / drain of the FET. Signals can be input to and output from the FET via front-side signal lines 120S. Multiple front-side signal lines 120S can be spaced apart from each other in the y-direction between the first front-side power line 120P-1 and the second front-side power line 120P-2.

[0024] In integrated circuit 100, the front wiring layer 120 may correspond to the lowest metal wiring layer among the multilayer metal wiring layers arranged on the front side of integrated circuit 100. In other words, the front wiring layer 120 may correspond to the metal wiring layer closest to the FET on the front side (e.g., the front M1 metal wiring layer). Furthermore, the first front power line 120P-1 and the second front power line 120P-2 of the front wiring layer 120 may be aligned with the cell boundaries CB on both sides of a cell in the y-direction. In some embodiments, the first front power line 120P-1 or the second front power line 120P-2 may be located between two adjacent cells in the y-direction. Additionally, the first front power line 120P-1 and the second front power line 120P-2 may be arranged alternately in the y-direction.

[0025] The FET can be located in the z-direction between the back wiring layer 110 and the front wiring layer 120. Two FETs can be arranged within a single cell. For example, a first FET FET1 including a first active region ACT1 and a second FET FET2 including a second active region ACT2 can be arranged within a single cell. In integrated circuit 100, the first FET FET1 may include a p-channel metal-oxide-semiconductor (PMOS) FET, and the second FET FET2 may include an n-channel metal-oxide-semiconductor (NMOS) FET. However, in some embodiments, the first FET FET1 may include an NMOS FET, and the second FET FET2 may include a PMOSFET. The first FET FET1 and the second FET FET2 may each include a gate line 140 and an active pattern 130 (see [link to documentation]). Figure 6C The active pattern 130 may have an active region ACT and may include source / drain electrodes 132 disposed on both sides of the gate line 140 in the x-direction and a channel 134 located between the source and drain (see...). Figure 6C ).like Figure 1A As shown, the first FET FET1 and the second FET FET2 may share gate line 140.

[0026] Gate line 140 may extend in the y-direction. Gate line 140 may surround channel 134 in various structures. For example, in integrated circuit 100, gate line 140 may surround channel 134 in a gate all-around (GAA) structure. However, the structure of gate line 140 is not limited to a GAA structure.

[0027] Gate line 140 may include a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include, for example, silicon oxide, silicon nitride, a high-k dielectric material, other dielectric materials, and / or combinations thereof, and may include one or more dielectric materials. In some embodiments, the gate dielectric layer may include an interface layer formed between the channel and the dielectric material. In some embodiments, the gate dielectric layer may be formed using an atomic layer deposition (ALD) process to ensure a consistent thickness around each channel. However, the method of forming the gate dielectric layer is not limited to the ALD process.

[0028] A gate electrode layer may be formed on the gate dielectric layer to surround the channel 134. The gate electrode layer may include polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other conductive materials and / or combinations thereof, and may include one or more conductive materials.

[0029] The active region ACT may include semiconductor materials (such as Si, SiGe, Ge, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP). In integrated circuit 100, the active region ACT may include Si or SiGe. As described above, multiple active regions ACT may extend in the x-direction and be spaced apart from each other in the y-direction. The active regions ACT within a cell may include a first active region ACT1 in the lower region and a second active region ACT2 in the upper region in the y-direction. The active pattern 130 of the first active region ACT1 may form the source / drain 132 and channel 134 of the first FET FET1, and the active pattern 130 of the second active region ACT2 may form the source / drain 132 and channel 134 of the second FET FET2. The first active region ACT1 and the second active region ACT2 may be electrically isolated from each other through a dielectric layer.

[0030] Furthermore, the channels 134 of the first FET FET1 and the second FET FET2 may each have a multi-bridge channel (MBC) structure, and the four surfaces of the channel 134 may be surrounded by gate lines 140. Here, the four surfaces of the channel 134 may include two surfaces in the y-direction and two surfaces in the z-direction. In some embodiments, the channels 134 of the first FET FET1 and the second FET FET2 may each include at least two nanosheets. However, in some embodiments, at least one of the channels 134 of the first FET FET1 and the second FET FET2 may include only one nanosheet. In the integrated circuit 100, the structure of the channels 134 of the first FET FET1 and the second FET FET2 is not limited to an MBC structure. (Refer to...) Figures 6A to 6D The FET, including gate line 140 and channel 134 in other structures, is described in more detail.

[0031] Contact 160 and back contact 150 can be arranged in the power tap unit PTC as described above. A first front power line 120P-1 can be connected to a first back power line 110P-1 via contact 160, a first active region ACT1, and back contact 150. Furthermore, a second front power line 120P-2 can be connected to a second back power line 110P-2 via contact 160, a second active region ACT2, and back contact 150. One power tap unit PTC can be arranged every tens to hundreds of contacted poly pitches (CPPs) in the x-direction. For example, in integrated circuit 100, one power tap unit PTC can be arranged, for example, at approximately 60 contacted poly pitches (CPPs). However, the arrangement spacing of the power tap units PTCs is not limited to the values ​​described above.

[0032] Here, the contact polysilicon pitch CPP can represent the spacing between gate lines 140 in the x-direction. For example... Figure 1A As shown, in integrated circuit 100, the size of the power tap unit PTC is set to the dimensions of two contact polysilicon pitches CPP in the x-direction and one cell height CH. However, the size of the power tap unit PTC is not limited to this. For example, the size of the power tap unit PTC may be set to one or more contact polysilicon pitches CPP in the x-direction and one or more cell heights CH in the y-direction.

[0033] For reference, the active region ACT in the power tap cell PTC may include a dummy active pattern 130D. Furthermore, the dummy active pattern 130D may include a dummy source / drain 132D and a dummy channel 134D. A dummy gate line 140D may be located in the power tap cell PTC, and the dummy gate line 140D may have a single diffusion break (SDB) structure. Therefore, in the power tap cell PTC, the dummy active pattern 130D may not operate as a component of the FET. However, the dummy source / drain 132D of the dummy active pattern 130D may include power paths between the first front-side power line 120P-1 and the first back-side power line 110P-1, and between the second front-side power line 120P-2 and the second back-side power line 110P-2.

[0034] For reference, the SDB may have substantially the same width in the x-direction as the gate line 140. For example, the SDB may have an insulating layer with substantially the same width as the gate extending into the semiconductor substrate and separating the active region ACT. Unlike the double diffusion break (DDB), the SDB does not have a separate dummy gate, and the upper portion of the insulating layer forming the SDB corresponding to the gate may protrude from the substrate.

[0035] On the other hand, DDB and SDB have different active region ACT separation structures and can be formed across two gates. For example, DDB can be formed by arranging an insulating layer in a buried structure under two adjacent gates in the x-direction. Therefore, DDB has a spacing between gates in the x-direction (e.g., the width corresponding to the contact polysilicon spacing CPP), and in DDB, the two upper gates can correspond to dummy gates.

[0036] Furthermore, considering the cell size, two cells including the DDB can be larger in the x-direction by one contact polysilicon pitch (CPP) than two cells including the SDB. Therefore, cells including the SDB may be advantageous in terms of size. Additionally, the insulating layers forming the DDB and SDB can include compressive stress materials and / or tensile stress materials. Here, compressive stress materials include materials capable of applying compressive stress to the active region, and tensile stress materials include materials capable of applying tensile stress to the active region. For example, the insulating layer of the SDB can include silicon nitride, and the insulating layer of the DDB can include oxides (such as tetraethyl orthosilicate (TEOS)). However, the materials of the insulating layers of the DDB and SDB are not limited to those described above.

[0037] In the power tap cell (PTC) of integrated circuit 100, the connection relationships between the back-side wiring layer 110 and the front-side wiring layer 120 and the dummy active pattern 130D (e.g., dummy source / drain 132D) are as follows. The first back-side power line 110P-1 and the second back-side power line 110P-2 of the back-side wiring layer 110 can be connected to the dummy source / drain 132D via the back-side contact 150, the metal plate via 152, and the back-side via 155. For example... Figure 1B As shown, the back-side contact 150 can contact its corresponding dummy source / drain 132D, and the metal plate via 152 can be contacted by both back-side contacts 150, which in turn contact two dummy source / drain 132Ds adjacent to each other in the y-direction. Furthermore, the first front-side power line 120P-1 and the second front-side power line 120P-2 of the front-side wiring layer 120 can be connected to the dummy source / drain 132D via contact 160 and via 165. Figure 1B As shown, contact 160 can be contacted by two dummy source / drain electrodes 132D in the y direction.

[0038] For reference, in integrated circuit 100, a cell may correspond to, for example, a standard cell, and therefore, a basic layout can be used when designing an integrated circuit. When describing standard cells in more detail, with the increasing integration of semiconductor devices in recent years, a significant amount of time and money is spent on designing the layout of integrated circuits (especially device regions). Therefore, to reduce the above, a layout design technique based on standard cells can be used. This technique reduces the time required for layout design by pre-designing logic devices (such as OR and AND gates) that are repeatedly used as standard cells, storing the logic devices in the computer system, and arranging and routing the logic devices in the necessary locations.

[0039] For example, standard units may include basic units (such as AND, OR, NOR, INVERTER and NAND), complex units (such as OR / AND / INVERTER (OAI) and AND / OR / INVERTER (AOI)), and storage elements (such as simple master-slave flip-flops and latches).

[0040] The standard cell approach involves pre-preparing logic circuit blocks (i.e., cells) with multiple functions and arbitrarily combining these cells to design application-specific large-scale integrated circuits (LSIs) tailored to the needs of customers or users. Cells can be pre-designed and verified, and then registered in a computer. Logic design, placement, and interconnection can be performed by combining the registered cells using computer-aided design (CAD).

[0041] Specifically, in the design / manufacturing of LSIs, when a certain number of standardized logic circuit blocks (i.e., standard cells) are already stored in a library, standard cells that meet the current design objectives can be retrieved from the library and arranged as multiple cells on the chip. The entire circuit can be designed to achieve the shortest interconnect length by performing optimal interconnection in the interconnect space between cells. As the types of cells stored in the library become more diverse, the design becomes more flexible, and therefore, the possibility of optimal chip design increases.

[0042] In integrated circuit 100, n front-side metal lines of front-side wiring layer 120 can be arranged in the y-direction within a single cell with a first spacing P1 (where n is an integer greater than or equal to 1). Furthermore, m back-side metal lines of back-side wiring layer 110 can be arranged in the same cell with a second spacing P2 (where m is an integer greater than or equal to 1). Therefore, the front-side metal lines of front-side wiring layer 120 and the back-side metal lines of back-side wiring layer 110 can have a spacing in the y-direction with an integer ratio. Specifically, when the cell height CH is 1, n is 5, and m is 3, the first spacing P1 between the front-side metal lines in front-side wiring layer 120 is 1 / 5, and the second spacing P2 between the back-side metal lines in back-side wiring layer 110 is 1 / 3. Therefore, the ratio of first spacing P1 to second spacing P2 can be 3:5. Furthermore, instead of spacing, the ratio can be defined by the number of front-side metal lines of front-side wiring layer 120 and the number of back-side metal lines of back-side wiring layer 110 arranged within a single cell. In this case, the ratio of the number of front metal wires (n) to the number of back metal wires (m) can be 5:3. Here, m can be less than or equal to n. However, the relationship between m and n is not limited to the one described above.

[0043] In integrated circuit 100, the first front power line 120P-1 and the second front power line 120P-2 of the front wiring layer 120 can be aligned with the cell boundaries CB on both sides of a cell in the y-direction. Similarly, the first back power line 110P-1 and the second back power line 110P-2 of the back wiring layer 110 can be aligned with the cell boundaries CB on both sides of a cell in the y-direction.

[0044] In the front wiring layer 120, the first front power line 120P-1 and the second front power line 120P-2 can each reside in two cells, and half of each can be allocated to one cell. Therefore, n-1 front signal lines 120S can be arranged within one cell. Specifically, for example, when n is 5, the first front power line 120P-1 and the second front power line 120P-2 are aligned with the cell boundary CB in the y-direction of one cell, and four front signal lines 120S can be arranged between the first front power line 120P-1 and the second front power line 120P-2. The same concept can also be applied to the back wiring layer 110. (Refer to...) Figures 5A to 5D The structure of the front wiring layer 120 and the back wiring layer 110 arranged in other ratios of n and m is described in more detail.

[0045] In integrated circuit 100, the first back-side power line 110P-1, the second back-side power line 110P-2, the first front-side power line 120P-1, and the second front-side power line 120P-2 (hereinafter referred to as power lines 110P-1, 110P-2, 120P-1, and 120P-2) of the front wiring layer 120 and the back wiring layer 110 are aligned with the cell boundary CB. This allows power supply current to flow stably in the cell boundary CB via power lines 110P-1, 110P-2, 120P-1, and 120P-2, thereby preventing coupling interference between adjacent devices. More specifically, in the case of front and back-side M1 metal lines, when there is no power supply current in the cell boundary CB, coupling interference between adjacent devices may cause the device to become unusable.

[0046] Figure 2 An example of coupling effect is shown. The x-axis represents the cell boundary CB with spacing of 0, 128, and 512 contact polysilicon pitch CPPs, and shows the signal delay when power current is supplied to the cell boundary (track) and when no power current is supplied (trackless). The y-axis represents the signal delay, and its units are normalized. As can be seen from the graph, a large signal delay occurs when no power current is supplied to the cell boundary CB (trackless), and the signal delay increases with the spacing of the contact polysilicon pitch CPPs.

[0047] In integrated circuit 100, the power lines 110P-1, 110P-2, 120P-1, and 120P-2 of the front wiring layer 120 and the back wiring layer 110 are aligned with the cell boundary CB, and power supply current is allowed to flow, thereby preventing coupling interference between adjacent devices. Furthermore, the front metal lines of the front wiring layer 120 and the back metal lines of the back wiring layer 110 can be arranged within the cell at a specific integer ratio, thereby enabling various operations of the back signal lines 110S of the back wiring layer 110.

[0048] Figure 3A and Figure 3B Example layout diagrams of an integrated circuit 100 according to some embodiments and an integrated circuit COM according to a comparative example are shown respectively within a cell. Figure 4A and Figure 4B They are shown respectively Figure 3A Integrated circuit 100 and Figure 3B This is a conceptual diagram illustrating the vertical positioning relationship between the back-side wiring layer and the front-side wiring layer in an integrated circuit (COM). See below for reference. Figure 1A and Figure 1B A description is provided, and simplifications or omissions have been referenced. Figures 1A to 3B The given description.

[0049] exist Figure 3A and Figure 4A In the integrated circuit 100, n front-side metal lines of the front wiring layer 120 can be arranged in the y-direction within a single cell, and m back-side metal lines of the back wiring layer 110 can be arranged. Furthermore, the first front-side power line 120P-1 and the second front-side power line 120P-2 of the front wiring layer 120 can be aligned with the cell boundaries CB on both sides in the y-direction, and the first back-side power line 110P-1 and the second back-side power line 110P-2 of the back wiring layer 110 can be aligned with the cell boundaries CB on both sides in the y-direction. Therefore, connections between the corresponding power lines 110P-1, 110P-2, 120P-1, and 120P-2 can be easily made in the power tap cell PTC. Furthermore, when the power lines 110P-1, 110P-2, 120P-1, and 120P-2 are aligned with the cell boundary CB, the power supply current can flow through the power lines 110P-1, 110P-2, 120P-1, and 120P-2 within the cell boundary CB. Therefore, the effect of preventing coupling interference can be maximized.

[0050] exist Figure 3B and Figure 4BIn the integrated circuit COM according to the comparative example, a number of front-side wiring layers FM (e.g., five) of front-side metal lines can be arranged in the cell in the y-direction, and two back-side metal lines of the back-side wiring layer BM can be arranged. Furthermore, the first front-side power line FM1 and the second front-side power line FM2 of the front-side wiring layer FM can be aligned with the cell boundaries CB on both sides in the y-direction. However, as in... Figure 3B and Figure 4B As can be seen, the first back-side power line BM1 and the second back-side power line BM2 of the back-side wiring layer BM are not aligned with the cell boundary CB. Therefore, in the power tap cell PTC, it is not easy to establish connections between the corresponding power lines 110P-1, 110P-2, 120P-1, and 120P-2, and additional contacts or vias may be required. Furthermore, the misalignment of the first back-side power line BM1 and the second back-side power line BM2 with the cell boundary CB reduces the effectiveness of preventing coupling interference. Additionally, the back-side wiring layer BM may not include back-side signal lines or may include only one back-side signal line, which prevents or limits the use of back-side signal lines.

[0051] Figures 5A to 5D A layout diagram illustrating various example ratios between the spacing of the front metal lines of the front wiring layer and the spacing of the back metal lines of the back wiring layer within a cell, according to some embodiments, is shown below. (See below for reference.) Figure 1A and Figure 1B A description is provided, and simplifications or omissions have been referenced. Figures 1A to 4B The given description.

[0052] exist Figure 5A The diagram shows an integrated circuit 100a. In the integrated circuit 100a, the ratio of the number of front metal lines in the front wiring layer 120 in the y-direction within a cell to the number of back metal lines in the back wiring layer 110a is 5:1. Therefore, five front metal lines of the front wiring layer 120 can be arranged in the y-direction within a cell, and one back metal line of the back wiring layer 110a can be arranged in the y-direction within a cell. Furthermore, the first front power line 120P-1 and the second front power line 120P-2 of the front wiring layer 120 can be aligned with the cell boundaries CB on both sides in the y-direction, and the first back power line 110Pa-1 and the second back power line 110Pa-2 of the back wiring layer 110a can be aligned with the cell boundaries CB on both sides in the y-direction. In this case, the back wiring layer 110a may not include back signal lines.

[0053] exist Figure 5BThe diagram shows an integrated circuit 100b. In the integrated circuit 100b, the ratio of the number of front metal lines in the front wiring layer 120 in the y-direction within a cell to the number of back metal lines in the back wiring layer 110b is 5:2. Therefore, the five front metal lines of the front wiring layer 120 can be arranged in the y-direction within a single cell, and the two back metal lines of the back wiring layer 110b can be arranged in the y-direction within a single cell. Furthermore, the first front power line 120P-1 and the second front power line 120P-2 of the front wiring layer 120 can be aligned with the cell boundaries CB on both sides in the y-direction, and the first back power line 110Pb-1 and the second back power line 110Pb-2 of the back wiring layer 110b can be aligned with the cell boundaries CB on both sides in the y-direction. In this case, the back wiring layer 110b may include a back signal line 110Sb.

[0054] exist Figure 5C The diagram shows an integrated circuit 100c. In the integrated circuit 100c, the ratio of the number of front-side metal lines in the front wiring layer 120 in the y-direction within a cell to the number of back-side metal lines in the back wiring layer 110c is 5:3. Therefore, the five front-side metal lines of the front wiring layer 120 can be arranged in the y-direction within one cell, and the three back-side metal lines of the back wiring layer 110c can be arranged in the y-direction within one cell. Furthermore, the first front-side power line 120P-1 and the second front-side power line 120P-2 of the front wiring layer 120 can be aligned with the cell boundaries CB on both sides in the y-direction, and the first back-side power line 110Pc-1 and the second back-side power line 110Pc-2 of the back wiring layer 110c can be aligned with the cell boundaries CB on both sides in the y-direction. In this case, the back wiring layer 110c may include two back-side signal lines 110Sc.

[0055] exist Figure 5D The diagram shows an integrated circuit 100d. In the integrated circuit 100d, the ratio of the number of front-side metal lines in the front wiring layer 120 in the y-direction to the number of back-side metal lines in the back wiring layer 110d is 5:4. Therefore, the five front-side metal lines of the front wiring layer 120 can be arranged in one cell in the y-direction, and the four back-side metal lines of the back wiring layer 110d can be arranged in one cell in the y-direction. Furthermore, the first front-side power line 120P-1 and the second front-side power line 120P-2 of the front wiring layer 120 can be aligned with the cell boundaries CB on both sides in the y-direction, and the first back-side power line 110Pd-1 and the second back-side power line 110Pd-2 of the back wiring layer 110d can be aligned with the cell boundaries CB on both sides in the y-direction. In this case, the back wiring layer 110d may include three back-side signal lines 110Sd.

[0056] Figures 6A to 6D This is a perspective view illustrating example structures of various FETs that can be included in an integrated circuit according to some embodiments. For ease of illustration, Figures 6A to 6C This shows the state where one of the two source / drain regions has been removed, and Figure 6D This shows a cross-section of the VFET taken along a plane that passes through the channel of the VFET and is perpendicular to the x-direction. See below for reference. Figure 1A and Figure 1B A description is provided, and simplifications or omissions have been referenced. Figures 1A to 5D The given description.

[0057] exist Figure 6A In this context, integrated circuit 100e may include, for example, a fin field-effect transistor (finFET). For example... Figure 1A As shown in the integrated circuit 100, the finFET may be located between the back-side wiring layer 110 and the front-side wiring layer 120. When describing the finFET in more detail, it may be formed from an active pattern 130a having a fin shape extending in the x-direction between a shallow trench isolation (STI) and a gate line 140 extending in the y-direction. The active pattern 130a may include a source / drain 132 and a channel 134a. The source / drain 132 may be formed on both sides of the gate line 140, and the source and drain may be spaced apart from each other in the x-direction. An insulating layer may be formed between the channel 134a and the gate line 140. In some embodiments, the finFET may be formed from a plurality of active patterns 130a spaced apart from each other in the y-direction and the gate line 140.

[0058] exist Figure 6B In this context, integrated circuit 100f may include, for example, a gate-all-around field-effect transistor (GAAFET). For example... Figure 1A As shown in the integrated circuit 100, the GAAFET may be located between the back wiring layer 110 and the front wiring layer 120. The GAAFET may be formed by an active pattern 130b extending in the x-direction and a gate line 140 extending in the y-direction. The active pattern 130b may include source / drain 132 and a channel 134b. The channel 134b may include, for example, nanowires spaced apart from each other in the z-direction. The source / drain 132 may be formed on both sides of the gate line 140, and thus the source and drain may be spaced apart from each other in the x-direction. An insulating layer may be formed between the channel 134b and the gate line 140. Figure 6B The diagram shows that a GAAFET includes three nanowires, but the number of nanowires in a GAAFET is not limited to three.

[0059] exist Figure 6CIn this context, integrated circuit 100 may include, for example, a multi-bridge channel field-effect transistor (MBCFET). MBCFET may correspond to... Figure 1A The integrated circuit 100 contains a FET, and therefore, the MBCFET can be disposed between the back wiring layer 110 and the front wiring layer 120. The MBCFET can be formed by an active pattern 130 extending in the x-direction and a gate line 140 extending in the y-direction. The active pattern 130 may include source / drain 132 and a channel 134. The channel 134 may include, for example, nanosheets spaced apart from each other in the z-direction. The source / drain 132 can be formed on both sides of the gate line 140, and therefore, the source and drain can be spaced apart from each other in the x-direction. An insulating layer can be formed between the channel 134 and the gate line 140. Figure 6C The MBCFET is shown to include three nanosheets, but the number of nanosheets in an MBCFET is not limited to three.

[0060] exist Figure 6D In this context, the integrated circuit 100g may include, for example, a VFET. (e.g., ...) Figure 1A As shown in the integrated circuit 100, the VFET may be located between the back wiring layer 110 and the front wiring layer 120. The VFET may be formed by an active pattern 130c and a gate line 140a. The active pattern 130c may include a source / drain 132a and a channel 134c. Specifically, the VFET may include a top source / drain 132a-T and a bottom source / drain 132a-B spaced apart from each other in the z-direction, and the channel 134c is located between the top source / drain 132a-T and the bottom source / drain 132a-B. The VFET may include a gate line 140a surrounding the channel 134c between the top source / drain 132a-T and the bottom source / drain 132a-B. An insulating layer may be formed between the channel 134c and the gate line 140a.

[0061] So far, various FET structures have been described. However, integrated circuits according to some embodiments are not limited to the structures described above. For example, in some embodiments, the integrated circuit may include a forkFET, in which dielectric walls isolate nanosheets of P-type transistors and nanosheets of N-type transistors, thereby forming a structure in which N-type transistors are close to P-type transistors. In addition, in some embodiments, the integrated circuit may include FETs (such as complementary FETs (CFETs), negative capacitance CFETs (NC-CFETs), and carbon nanotube FETs (CNT-FETs)), and may also include bipolar junction transistors.

[0062] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims, their equivalents, and the appended claims. Specific features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features derived from the combination may be removed from the combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

Claims

1. An integrated circuit, comprising: The back-side wiring layer includes a plurality of back-side metal lines extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; Field-effect transistor, along the third direction above the back-side wiring layer; as well as A front wiring layer, extending in a third direction above the field-effect transistor, includes multiple front metal lines extending in a first direction and spaced apart from each other in a second direction. Wherein, n front-side metal wires are arranged in at least one cell in the second direction at a first spacing, where n is an integer greater than or equal to 1, and Wherein, m back-side metal wires are arranged in the at least one unit in the second direction at a second spacing, where m is an integer greater than or equal to 1.

2. The integrated circuit according to claim 1, further comprising: The active regions extend in a first direction and are spaced apart from each other in a second direction. Wherein, the at least one unit includes a first unit, The first unit comprises two active regions spaced apart in the second direction. The first unit includes a first unit boundary on a first side of the first unit, and a second unit boundary on a second side of the first unit. The boundaries of the first and second units are spaced apart from each other along the second direction. Among the plurality of front-side metal lines, the first front-side electric field line and the second front-side electric field line are aligned with the first unit boundary and the second unit boundary, respectively, and Among the plurality of back-side metal lines, the first back-side electric field line and the second back-side electric field line are aligned with the first unit boundary and the second unit boundary, respectively.

3. The integrated circuit according to claim 2, in, The first front power line is configured to receive a first power source, and the second front power line is configured to receive a second power source different from the first power source. The first back-side power line is configured to receive a first power, and the second back-side power line is configured to receive a second power.

4. The integrated circuit according to claim 2, further comprising: A power tapping unit, wherein the power tapping unit includes: Contacts are configured to connect a first front-side power line and a second front-side power line to the two active regions of the first unit; and The back-side contact is configured to connect the first back-side power line and the second back-side power line to the two active regions of the first unit.

5. The integrated circuit according to claim 4, further comprising: Gate lines extend in a second direction and are arranged with a third spacing in a first direction. The power tap unit has a width of one unit or more in the second direction and a width of a third spacing or more in the first direction.

6. The integrated circuit according to claim 4, in, The contact is connected to the first front power line or the second front power line via a via, and The back-side contact is connected to the first back-side power line or the second back-side power line through a back-side via.

7. The integrated circuit according to claim 6, in, The first front power line or the second front power line is located between the first unit and the second unit adjacent to the first unit in the second direction. The second unit includes two additional active regions spaced apart from each other in the second direction, and The active region of the first unit and the additional active region of the second unit are connected together to the contact element.

8. The integrated circuit according to claim 2, in, A field-effect transistor includes a gate line, a source and a drain of first active regions on both sides of the gate line in a first direction, and a channel located between the source and the drain. The front wiring layer includes a metal wiring layer on the front side of the integrated circuit that is closest to the field-effect transistor, and The back-side wiring layer includes a metal wiring layer on the back side of the integrated circuit that is closest to the field-effect transistor.

9. The integrated circuit according to claim 8, in, The trench includes a multi-bridge trench structure, and The gate line includes a fully encircling gate structure.

10. The integrated circuit according to claim 2, wherein, The midpoint between two adjacent active regions in two adjacent cells in the second direction is defined as the cell boundary.

11. The integrated circuit according to claim 2, wherein, The width of the first unit in the second direction is defined as the first width. The number n of the plurality of front-side metal lines is based on a first width or a first spacing. The number m of the plurality of back-side metal lines is based on a first width or a second spacing, and The number n of the plurality of front-side metal wires is greater than or equal to the number m of the plurality of back-side metal wires.

12. An integrated circuit, comprising: The back-side wiring layer includes a plurality of back-side metal lines extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; A cell region, above a back-side wiring layer, includes an active region and a gate line, the active regions extending in a first direction and spaced apart from each other in a second direction, and the gate lines extending in the second direction and spaced apart from each other in the first direction. as well as A front wiring layer, located above the cell region, includes a plurality of front metal lines extending in a first direction, wherein the plurality of front metal lines are spaced apart from each other in a second direction. Among the plurality of front-side metal lines, the first front-side electric field line and the second front-side electric field line are respectively aligned with the unit boundaries of the first and second sides in the unit region of the first unit, wherein the first side and the second side are spaced apart in the second direction. Among the plurality of back-side metal lines, the first back-side electric field line and the second back-side electric field line are aligned with the unit boundaries of the first and second sides of the first unit, respectively. Among them, n front metal wires are arranged at a first spacing in the second direction inside the first unit, where n is an integer greater than or equal to 1, and Among them, m back-side metal wires are arranged in the second direction at a second spacing inside the first unit, where m is an integer greater than or equal to 1.

13. The integrated circuit according to claim 12, further comprising: A power tap unit, wherein the power tap unit includes contacts configured to connect a first front-side power line and a second front-side power line to an active region, and rear-side contacts configured to connect a first rear-side power line and a second rear-side power line to an active region. Wherein, the gate lines are arranged with a third spacing in the first direction, and The power tap unit has a width equal to or greater than the width of a unit in the second direction, and a length equal to or greater than the length of a third spacing in the first direction.

14. The integrated circuit according to claim 13, in, Between two adjacent units in the second direction, the first front electric line or the second front electric line and... In this configuration, the active regions of two adjacent units are connected together to the contact element.

15. The integrated circuit according to claim 12, in, A first gate line, a source, a drain, and a channel located between the source and drain form a field-effect transistor in the cell region. The trench includes a multi-bridge trench structure, and The first gate line includes a fully encircling gate structure.

16. The integrated circuit according to claim 12, wherein, The width of the first unit in the second direction is defined as the first width. The number n of the plurality of front-side metal lines is based on a first width or a first spacing. The number m of the plurality of back-side metal lines is based on a first width or a second spacing, and The number n of the plurality of front-side metal wires is greater than or equal to the number m of the plurality of back-side metal wires.

17. An integrated circuit, comprising: The back-side wiring layer includes a plurality of back-side metal lines extending in a first direction, the plurality of back-side metal lines being spaced apart from each other in a second direction perpendicular to the first direction; Field-effect transistor, above the back-side wiring layer; as well as A front wiring layer, located above the field-effect transistor, comprises a plurality of front metal lines extending in a first direction and spaced apart from each other in a second direction. The first and second front-side electric field lines of the plurality of front-side metal wires are aligned with the unit boundary of the unit in the second direction, and the first and second front-side electric field lines are configured to receive power. The first and second back-side electric field lines of the plurality of back-side metal wires are aligned with the unit boundary of the unit in the second direction, and the first and second back-side electric field lines are configured to receive power. Wherein, n front-side metal wires are arranged in the unit at a first spacing in the second direction, where n is an integer greater than or equal to 1, and In this unit, m back-side metal wires are arranged in the second direction at a second spacing, where m is an integer greater than or equal to 1.

18. The integrated circuit of claim 17, further comprising: Gate lines extend in a second direction and are arranged at a third spacing in a first direction; as well as The power tap unit includes contacts configured to connect a first front-side power line and a second front-side power line to an active region, and rear-side contacts configured to connect a first rear-side power line and a second rear-side power line to an active region. The power tap unit has a width equal to or greater than the width of a unit in the second direction, and a length equal to or greater than the length of a third spacing in the first direction.

19. The integrated circuit according to claim 18, in, The first or second front power line is located between two adjacent units in the second direction. In this configuration, the active regions in the two adjacent units are connected to the contact element. The contact element is connected to the first front power line or the second front power line via a through-hole, and The back-side contact is connected to the first back-side power line or the second back-side power line through a back-side via.

20. The integrated circuit according to claim 17, wherein, The width of the unit in the second direction is defined as the first width. The number n of the plurality of front-side metal lines is based on a first width or a first spacing. The number m of the plurality of back-side metal lines is based on a first width or a second spacing, and The number n of the plurality of front-side metal wires is greater than or equal to the number m of the plurality of back-side metal wires.

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