Probe card and testing apparatus
By designing the first probe and the second probe in the probe card with opposite current directions, parasitic inductance is reduced, the problem of insufficient test accuracy in the prior art is solved, and higher test accuracy and signal transmission efficiency are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHROMA ATE (SUZHOU) CO LTD
- Filing Date
- 2024-12-31
- Publication Date
- 2026-06-30
Smart Images
Figure CN122307163A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to testing techniques, and in particular to a probe card and testing apparatus. Background Technology
[0002] In semiconductor testing, a probe card is a device used to perform electrical tests on wafers. A probe card contains multiple precisely arranged tiny probes that make electrical contact with the wafer; therefore, the structure and arrangement of the probes directly affect the accuracy of the electrical tests. Summary of the Invention
[0003] This disclosure relates to a probe card, comprising a substrate, at least one first probe, and a plurality of second probes. The first probe is disposed in a first region on the substrate. The second probes are disposed in a plurality of second regions on the substrate, corresponding to a first side and a second side of the first region. When the first probe and the plurality of second probes are used to transmit a test signal, the first current direction on the first probe is opposite to the second current direction on the plurality of second probes.
[0004] In one embodiment, the first side and the second side of the first region include two corresponding sides of the first region.
[0005] In one embodiment, the plurality of second regions surround the first region.
[0006] In one embodiment, at least one first probe includes a plurality of first probes, and the number of probes in the first region is greater than the number of probes in any of the plurality of second regions.
[0007] In one embodiment, at least one first probe is used to apply at least one first test signal to the wafer, and the plurality of second probes are used to receive a plurality of second test signals output by the wafer.
[0008] This disclosure also relates to a testing apparatus, comprising a processor, a stage, and a probe card. The processor provides at least one test signal. The stage carries a wafer. The probe card is coupled to the processor and is used to receive the test signal. The probe card includes at least one first probe and a plurality of second probes. The first probe is disposed in a first region on the probe card. The second probes are disposed in a plurality of second regions on the probe card, corresponding to a first side and a second side of the first region. When the first probe and the plurality of second probes are used to transmit the test signal, a first current direction on the first probe is opposite to a second current direction on the plurality of second probes.
[0009] In one embodiment, the first side and the second side of the first region include two corresponding sides of the first region.
[0010] In one embodiment, the plurality of second regions surround the first region.
[0011] In one embodiment, at least one first probe includes a plurality of first probes, and the number of probes in the first region is greater than the number of probes in any of the plurality of second regions.
[0012] In one embodiment, at least one first probe is used to apply at least one first test signal to the wafer, and the plurality of second probes are used to receive a plurality of second test signals output by the wafer.
[0013] Therefore, by designing the configuration and arrangement of the first and second probes, the parasitic inductance of the probes can be reduced by utilizing the opposite current characteristics between the first and second probes, thereby improving the accuracy of wafer testing. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of a test apparatus according to some embodiments of the present disclosure;
[0015] Figure 2 This is a schematic diagram of a probe card according to some embodiments of the present disclosure;
[0016] Figure 3 This is a schematic diagram of the magnetic field when a probe card transmits test signals according to a portion of the embodiments of this disclosure;
[0017] Figure 4A This is a schematic diagram illustrating the configuration of the first probe and the second probe according to one embodiment of the present disclosure;
[0018] Figure 4B This is a schematic diagram illustrating the configuration of the first probe and the second probe according to one embodiment of the present disclosure;
[0019] Figure 4C This is a schematic diagram illustrating the configuration of the first probe and the second probe according to one embodiment of the present disclosure;
[0020] Figure 4D This is a schematic diagram illustrating the configuration of the first probe and the second probe according to one embodiment of the present disclosure.
[0021] [Symbol Explanation]
[0022] 100: Testing equipment
[0023] 110: Processor
[0024] 120: Support platform
[0025] 200: Probe Card
[0026] 210: First probe
[0027] 220: Second probe
[0028] 230:Substrate
[0029] 231: Area 1
[0030] 232A: Second Area
[0031] 232B: Second Area
[0032] 232C: Second Region
[0033] 232D: Second Region
[0034] 410: Second Area
[0035] 420: Second Zone
[0036] 430: Second Area
[0037] 440: Second Area
[0038] D: Wafer
[0039] I21: Current
[0040] I22: Current
[0041] P: Probe Detailed Implementation
[0042] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.
[0043] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terminology. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.
[0044] Figure 1 A schematic diagram of a testing apparatus 100 according to a partial embodiment of this disclosure. Before wafer D is diced, the testing apparatus 100 is used to test each wafer cell on wafer D to determine whether the electrical characteristics of the wafer cell meet expectations, for example, to determine whether it is a good or defective product.
[0045] The testing apparatus 100 includes a processor 110, a stage 120, and a probe card 200. In one embodiment, the processor 110, the stage 120, and the probe card 200 are mounted on the same machine, but they can be mounted on different devices. For example, the stage 120 and the probe card 200 are mounted on the testing machine, while the processor 110 is mounted on an external control host and electrically coupled to the stage 120 and the probe card 200.
[0046] The processor 110 controls the stage 120 and the probe card 200, and provides one or more test signals to determine whether the performance of the chip unit is qualified based on the signals returned by the probe card 200. The "test signal" is a signal with specific electrical characteristics (e.g., voltage, current) or a specific waveform, which can be stored in advance in the internal memory of the processor 110 or the test device 100, or obtained from an external server via a network connection. The testing method will be described in subsequent paragraphs.
[0047] A stage 120 is coupled to a processor 110 and is used to support a wafer D, which contains multiple die cells to be tested. A probe card 200 includes multiple probes P positioned corresponding to the stage 120 to transmit test signals. For example, the probe card 200 is positioned on the stage 120 directly above the wafer D, and the probes P are positioned corresponding to the contacts (e.g., pads or bumps) of the multiple die cells.
[0048] The probe card 200 is coupled to the processor 110 to receive test signals and to transmit the test signals to the wafer cell, or to receive test signals after they have passed through the wafer cell. The probe card 200 sends the test signals after they have passed through the wafer cell back to the processor 110 so that the processor 110 can determine whether the electrical characteristics of the wafer cell meet expectations. Since those skilled in the art will understand how the test signals are generated, further details are omitted here.
[0049] In some embodiments, the stage 120 and the probe card 200 can move relative to each other. For example, the stage 120 can be displaced vertically to bring the wafer D into contact with the probe P on the probe card 200, or to move the wafer D away from the probe card 200. However, this disclosure is not limited thereto; in other embodiments, the probe card 200 can also be displaced vertically to contact or move away from the wafer D (wafer cell). Since those skilled in the art will understand the configuration of the displacement mechanism in the test apparatus 100, it will not be described in detail here.
[0050] Figure 2This is a schematic diagram of a probe card 200 according to a partial embodiment of the present disclosure. Referring to Figures 1 and 2, the probe card 200 includes a substrate 230 and a plurality of probes 210 and 220. The substrate 230 is a fixing plate for fixing the probes 210 and 220, and the probes 210 and 220 can be equivalent to... Figure 1 The probe P is shown. In other words, depending on the configuration location, Figure 1 The probe P shown can be divided into at least one first probe 210 and multiple second probes 220. For example... Figure 2 As shown, the location of the first probe 210 on the substrate 230 is referred to as "first region 231". Similarly, the multiple locations of the second probe 220 on the substrate 230 are referred to as "second regions 232A to 232D".
[0051] During the testing process, the test signals provided by the processor 110 are transmitted by a portion of the plurality of probes 210 and 220. For example, the first probe 210 applies one or more test signals (referred to herein as "first test signals") to the corresponding wafer cell. After the first test signal passes through the wafer cell, one or more second probes 220 receive one or more test signals (referred to herein as "second test signals") output by the wafer cell and transmit the second test signals back to the processor 110. The processor 110 can analyze the second test signals (e.g., determine voltage, current, or waveform, or determine signal transmission time) to determine whether the performance of the wafer cell meets expectations. In other embodiments, the processor 110 may also transmit the first test signal through one or more second probes 220 and receive the second test signal output by the wafer cell through one or more first probes 210.
[0052] As previously described, in the testing procedure, each first probe 210 corresponds to one second probe 220 to form a test loop. Multiple first probes 210 can transmit multiple test signals and form multiple test loops with multiple second probes 220 respectively. However, this disclosure is not limited thereto; in other embodiments, each first probe 210 may also correspond to multiple second probes 220 to form a test loop, or multiple first probes 210 may form a test loop with one second probe 220.
[0053] The aforementioned test procedure, due to the structural characteristics of the probe card 200, results may not be as accurate as ideal. Specifically, because the probes on the probe card 200 are small, numerous, and densely packed, they generate parasitic inductance. This parasitic inductance not only causes signal transmission loss, but also releases energy in the parasitic inductance as oscillations or voltage pulses when the current changes, thus affecting the accuracy of the test. Therefore, this disclosure describes a design and improvement of the probe arrangement to reduce parasitic inductance and thus avoid undesirable energy loss.
[0054] Here, the second and... Figure 3 This disclosure explains the arrangement of the probes and the principle behind its improvement. Figure 3 This is a schematic diagram of the magnetic field when the probe card 200 transmits a test signal according to a partial embodiment of this disclosure. As previously described, the first probe 210 and the second probe 220 are used to perform different transmission actions; for example, the first probe 210 is used to "apply" a first test signal, and the second probe 220 is used to "receive" a second test signal. In other words, when the first probe 210 and the second probe 220 transmit test signals, the direction of the first current on the first probe 210 is opposite to the direction of the second current on the second probe 220. According to Ampere's law, the current in a conductor generates a magnetic field, and the direction of the magnetic field is determined by the direction of the current. Therefore, the direction of the magnetic field formed by the current I21 in the first probe 210 (e.g., ...) is... Figure 3 As shown, (counterclockwise) the direction of the magnetic field formed by the current I22 of the second probe 220 (as shown) will be opposite to the direction of the magnetic field formed by the current I22 of the second probe 220 (e.g.) Figure 3 As shown, the clockwise direction is the opposite.
[0055] As mentioned above, the parasitic inductance on the probes can be divided into two parts: "self-inductance" and "mutual inductance." Self-inductance depends on the structure and volume of the probes 210 / 220 themselves, while mutual inductance depends on the mutual magnetic field influence between the probes 210 / 220. According to the mutual inductance formula, when the magnetic fields generated by the first probe 210 and the second probe 220 are in opposite directions, the self-inductance of the probes themselves will cancel out the mutual inductance in response to adjacent probes. Therefore, by changing the placement, arrangement, and spacing of the probes 210 / 220, the mutual inductance generated between the first probe 210 and the second probe 220 due to the magnetic field can cancel out the self-inductance of the probes themselves, thereby improving the total parasitic inductance. With reduced parasitic inductance, the testing capability of the testing device 100 will be more accurate.
[0056] like Figure 2As shown, in one embodiment, the second probe 220 and its corresponding second regions 232A-232D correspond to at least two sides of the first probe 210 / first region 231. In other words, the second probe 220 is adjacent to the first and second sides of the first probe 210, for example, located in the second regions 232A-232B. Each second region 232A-232D is spaced from the first region 231 to provide the same magnetic field cancellation effect. For example, the cross-sectional diameter of probes 210 / 220 may be between 10 and 200 micrometers, and the spacing between the first region 231 and each second region 232A-232D may be 2 to 10 times the cross-sectional diameter of the probe, for example, between 20 and 2000 micrometers. However, this disclosure is not limited to this; in other embodiments, the spacing may be more than 10 times the cross-sectional diameter of the probe. Since the strength of the magnetic field is related to the distance between the wires, by arranging the second probes 220 in different second regions 232A to 232D, each second probe 220 can exert a similar cancellation capability to improve their parasitic inductance.
[0057] Please see Figure 2 As shown, in one embodiment, the number of probes of the first probe 210 in the first region 231 is greater than the number of probes of the second probe 220 in any of the second regions 232A-232D. In other words, the first area of the first region 231 is greater than the second area of any of the second regions 232A-232D.
[0058] Figures 4A to 4D The diagram shows the configuration of the first probe 210 and the second probe 220 in different embodiments of this disclosure. Figures 4A to 4D In, with Figure 2 Similar elements related to the embodiments are denoted by the same reference numerals for ease of understanding, and the specific principles of the similar elements have been described in detail in the preceding paragraphs. Figures 4A to 4D The components that work together in a coordinated manner will not be elaborated upon here.
[0059] Please see Figure 4A As shown, in this embodiment, the second region 410 where the second probe 220 is located is two adjacent sides corresponding to the first probe 210 (first region 231), and the two second regions 410 are spaced at the same interval as the first region 231, thus providing the same parasitic inductance cancellation effect to reduce the total value of parasitic inductance.
[0060] Please see Figure 4BAs shown, in this embodiment, the second region 420 where the second probe 220 is located has two adjacent sides corresponding to the first probe 210 (first region 231), and the spacing of the multiple second probes 220 in the second region 420 is also the same, so as to surround the upper right corner of the first region 231.
[0061] Please see Figure 4C As shown, in this embodiment, the second region 430 where the second probe 220 is located corresponds to two corresponding sides of the first probe 210 (first region 231) so as to provide the same parasitic inductance cancellation effect in different directions (e.g., left and right) to reduce the total value of parasitic inductance.
[0062] Please see Figure 4D As shown, in this embodiment, the second region 440 where the second probe 220 is located surrounds the first region 231 where the first probe 210 is located, so as to provide opposite magnetic fields from each direction around the first region 231 to reduce the total value of the parasitic inductance of probes 210 / 220.
[0063] It is worth mentioning here that, although in Figure 4D In the illustrated embodiment, the second probes 220 are located within the same second region 440 (i.e., the spacing between each second probe 220 is substantially the same). However, this disclosure is not limited thereto; in other embodiments, the second probes 220 may be located in multiple second regions 440 and may similarly surround the first region 231 (i.e., the spacing between each second probe 220 may not be the same). For example, Figure 2 The second regions 232A to 232D shown correspond to all the sides of the first region 2 respectively. This arrangement can also be considered as the "surround" configuration described in this disclosure.
[0064] The components, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of textual description or the order of presentation of the drawings in this disclosure.
[0065] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.
Claims
1. A probe card, characterized by, Include: One substrate; At least one first probe is disposed in a first region on the substrate; and Multiple second probes are disposed on multiple second regions on the substrate and correspond to a first side and a second side of the first region; When the at least one first probe and the plurality of second probes are used to transmit at least one test signal, the direction of a first current on the at least one first probe is opposite to the direction of a second current on the plurality of second probes.
2. The probe card of claim 1, wherein, The first side and the second side of the first region include two corresponding sides of the first region.
3. The probe card of claim 1, wherein, The plurality of second regions surround the first region.
4. The probe card of claim 1, wherein, The at least one first probe includes a plurality of first probes, and the number of probes in the first region is greater than the number of probes in any of the plurality of second regions.
5. The probe card of claim 1, wherein, The at least one first probe is used to apply at least one first test signal to a wafer, and the plurality of second probes are used to receive the plurality of second test signals output by the wafer.
6. A test device characterized by, Include: A processor for providing at least one test signal; A support stage for holding a wafer; and A probe card, coupled to the processor and used to receive the test signal, wherein the probe card includes: At least one first probe is disposed in a first region on the probe card; and Multiple second probes are disposed in multiple second regions on the probe card, and correspond to a first side and a second side of the first region; When the at least one first probe and the plurality of second probes are used to transmit at least one test signal, the direction of a first current on the at least one first probe is opposite to the direction of a second current on the plurality of second probes.
7. The test device of claim 6, wherein, The first side and the second side of the first region include two corresponding sides of the first region.
8. The test device of claim 6, wherein, The plurality of second regions surround the first region.
9. The test device of claim 6, wherein, The at least one first probe includes a plurality of first probes, and the number of probes in the first region is greater than the number of probes in any of the plurality of second regions.
10. The testing apparatus as described in claim 6, characterized in that, The at least one first probe is used to apply at least one first test signal to the wafer, and the plurality of second probes are used to receive the plurality of second test signals output by the wafer.