Low dropout voltage regulator circuit

Abstract

This application provides a low-dropout regulator circuit, including: a circuit input terminal, a circuit output terminal, a ground terminal, a power supply circuit, a reference voltage circuit, an error amplifier, a power transistor, and voltage divider resistors. The voltage divider resistors are connected to the circuit output terminal and the ground terminal. The inverting input terminal of the error amplifier is connected to the output terminal of the reference voltage circuit, and the non-inverting input terminal of the error amplifier is connected between the first and second voltage divider resistors. The power supply circuit is connected to the error amplifier. The reference voltage circuit includes a reference voltage circuit, a startup circuit, and an external filter capacitor. The output terminal of the reference voltage circuit is connected to the input terminal of the startup circuit, the external filter capacitor is connected to the output terminal of the startup circuit and the ground terminal, and the output terminal of the startup circuit is connected to the inverting input terminal of the error amplifier. The startup circuit is used to ensure that the voltage at the inverting input terminal reaches the reference voltage output by the reference voltage circuit within a time threshold. This application can improve the response speed of the low-dropout regulator circuit and reduce ripple.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a low dropout voltage regulator circuit. Background Technology

[0002] In modern electronic systems, low-dropout regulators (LDOs) play a crucial role. They provide a stable power supply voltage, ensuring the proper functioning of various electronic components and subsystems under varying power conditions. The core function of an LDO is to maintain a very small voltage difference between the input and output voltages while simultaneously delivering a stable output voltage. This characteristic makes LDOs ideal for battery-powered devices, portable electronic products, and systems requiring efficient power management.

[0003] However, traditional LDO circuits have certain limitations in terms of response speed and output voltage ripple suppression. Response speed refers to the speed at which the LDO adjusts its output voltage to reach a new steady state after detecting a change in input voltage or load current. A slow response speed can lead to voltage fluctuations in the system during transient load changes, thus affecting system stability and performance. Output voltage ripple refers to periodic fluctuations in the output voltage, which can be caused by factors such as input power supply noise, internal circuit noise, non-ideal effects of internal components, or switching actions of the power supply. The presence of ripple not only affects the accuracy of the system but can also damage sensitive circuits. Summary of the Invention

[0004] This application provides a low-dropout regulator circuit with fast response speed and low ripple.

[0005] This application provides a low dropout voltage regulator circuit, including: a circuit input terminal, a circuit output terminal, a ground terminal, a power supply circuit, a reference voltage circuit, an error amplifier, a power transistor, and a voltage divider resistor;

[0006] The power transistor includes a first terminal, a second terminal, and a controllable terminal; the first terminal is connected to the circuit input terminal, the second terminal is connected to the circuit output terminal, and the controllable terminal is connected to the output terminal of the error amplifier.

[0007] The voltage divider resistor is connected between the circuit output terminal and the ground terminal; the voltage divider resistor includes a first voltage divider resistor and a second voltage divider resistor connected in series;

[0008] The inverting input of the error amplifier is connected to the output of the reference voltage circuit; the non-inverting input of the error amplifier is connected between the first voltage divider resistor and the second voltage divider resistor.

[0009] The power supply circuit is connected to the error amplifier and is used to supply power to the error amplifier;

[0010] The reference voltage circuit includes a reference voltage circuit, a startup circuit, and an external filter capacitor; the output terminal of the reference voltage circuit is connected to the input terminal of the startup circuit, the external filter capacitor is connected to the output terminal of the startup circuit and the ground terminal, and the output terminal of the startup circuit is connected to the inverting input terminal of the error amplifier; the startup circuit is used to make the voltage at the inverting input terminal reach the reference voltage output by the reference voltage circuit within a time threshold.

[0011] Optionally, the startup circuit includes a comparator circuit and a charging circuit; the reference voltage circuit is used to output a first reference voltage and a second reference voltage; the comparator circuit is used to compare the output voltage of the startup circuit with the first reference voltage; when the output voltage of the startup circuit does not reach the first reference voltage, the charging circuit is turned on, and the reference voltage circuit charges the external filter capacitor through the charging circuit; when the output voltage of the startup circuit reaches the first reference voltage, the charging circuit is turned off, and the reference voltage circuit directly charges the external filter capacitor until the voltage at the inverting input terminal reaches the second reference voltage.

[0012] Optionally, the comparison circuit includes a first operational amplifier, a first inverter, and a second inverter; the charging circuit includes a second operational amplifier, a first switching transistor, and a second switching transistor; the first input terminal of the first operational amplifier is used to receive the first reference voltage, the second input terminal of the first operational amplifier is connected to the second terminal of the first switching transistor, the output terminal of the first operational amplifier is connected to the controllable terminal of the first switching transistor through the first inverter, and is connected to the controllable terminal of the second switching transistor through the first inverter and the second inverter connected in series; the first input terminal of the second operational amplifier is used to receive the second reference voltage, the second input terminal of the second operational amplifier is connected to the second terminal of the first switching transistor, and the output terminal of the second operational amplifier is connected to the first terminal of the second switching transistor; the first terminal of the first switching transistor is used to receive the second reference voltage, and the second terminal of the second switching transistor is connected to the output terminal of the startup circuit; when the output voltage of the startup circuit does not reach the first reference voltage, the first switching transistor is turned off and the second switching transistor is turned on; when the output voltage of the startup circuit reaches the first reference voltage, the first switching transistor is turned on and the second switching transistor is turned off.

[0013] Optionally, the startup circuit further includes a first resistor, a second resistor, and a filter capacitor; the first resistor is connected to the first switching transistor and the external filter capacitor; the second resistor is connected to the second switching transistor and the external filter capacitor; one end of the filter capacitor is connected between the first resistor and the second resistor, and the other end is connected to the ground terminal.

[0014] Optionally, the power supply circuit includes a voltage detection circuit and a voltage amplification circuit; the voltage detection circuit is connected to the circuit input terminal and is used to detect whether the input voltage at the circuit input terminal is greater than a threshold voltage; the voltage amplification circuit is used to amplify the input voltage when the input voltage at the circuit input terminal is less than the threshold voltage.

[0015] Optionally, the voltage amplification circuit includes at least two cascaded charge pump circuits. The voltage amplification circuit is used to: when the input voltage at the circuit input terminal is less than a threshold voltage, control the number of the at least two cascaded charge pump circuits turned on according to the different magnitudes of the input voltage, so as to adjust the different amplification factors of the input voltage.

[0016] Optionally, the voltage detection circuit includes at least two detection resistors connected in series between the circuit input terminal and the ground terminal, and the output terminal of each charge pump circuit is connected to a different detection resistor. The voltage detection circuit is used to detect the voltage of each detection resistor and control the operating state of the at least two cascaded charge pump circuits according to the detection results.

[0017] Optionally, when the voltage of a certain sensing resistor is not greater than the threshold voltage, the charge pump circuit connected to the sensing resistor is connected to the voltage amplification circuit; when the voltage of a certain sensing resistor is greater than the threshold voltage, the charge pump circuit connected to the sensing resistor is in a short-circuit state.

[0018] Optionally, the charge pump circuit includes a switch, and the output terminal of the charge pump circuit is connected to the detection resistor through the switch; when the voltage of a certain detection resistor is not greater than the threshold voltage, the switch corresponding to the detection resistor is open, and when the voltage of a certain detection resistor is greater than the threshold voltage, the switch corresponding to the detection resistor is closed.

[0019] Optionally, the power transistor includes an NMOS transistor, and the low dropout regulator circuit further includes a power supply voltage amplifier circuit connected to the power supply circuit and the NMOS transistor, used to amplify the output voltage of the power supply circuit to power the NMOS transistor.

[0020] In some embodiments, the low-dropout regulator circuit includes: a circuit input terminal, a circuit output terminal, a ground terminal, a power supply circuit, a reference voltage circuit, an error amplifier, a power transistor, and voltage divider resistors. The inverting input terminal of the error amplifier is connected to the output terminal of the reference voltage circuit, and the non-inverting input terminal of the error amplifier is connected between the first and second voltage divider resistors. The reference voltage circuit includes a reference voltage circuit, a startup circuit, and an external filter capacitor. The output terminal of the reference voltage circuit is connected to the input terminal of the startup circuit, the external filter capacitor is connected to the output terminal of the startup circuit and the ground terminal, and the output terminal of the startup circuit is connected to the inverting input terminal of the error amplifier. The startup circuit is used to ensure that the voltage at the inverting input terminal reaches the reference voltage output of the reference voltage circuit within a time threshold, thereby improving the response speed of the low-dropout regulator circuit. The external filter capacitor can reduce the voltage ripple at the circuit output terminal and improve the anti-interference capability.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] Figure 1 The diagram shown is a circuit diagram of one embodiment of the low dropout regulator circuit of this application.

[0024] Figure 2 for Figure 1 A partial circuit diagram of one embodiment of the reference voltage circuit shown.

[0025] Figure 3 for Figure 1 The circuit diagram shown is an embodiment of the power supply circuit. Detailed Implementation

[0026] This application provides a low dropout voltage regulator circuit. The low dropout voltage regulator circuit of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0027] Figure 1 The diagram shown is a circuit diagram of one embodiment of the low dropout regulator circuit 10 of this application. Figure 1 As shown, the low dropout regulator circuit 10 includes: circuit input terminal VIN, circuit output terminal VOUT, ground terminal GND, power supply circuit 11, reference voltage circuit 12, error amplifier 13, power transistor T, and voltage divider resistor R.

[0028] The power transistor T includes a first terminal T1, a second terminal T2, and a controllable terminal TC. The first terminal T1 is connected to the circuit input terminal VIN, the second terminal T2 is connected to the circuit output terminal VOUT, and the controllable terminal TC is connected to the output terminal of the error amplifier 13.

[0029] The voltage divider resistor R is connected between the circuit output terminal VOUT and the ground terminal GND. The voltage divider resistor R includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series.

[0030] The inverting input of error amplifier 13 is connected to the output of reference voltage circuit 12. The non-inverting input of error amplifier 13 is connected between the first voltage divider resistor R1 and the second voltage divider resistor R2.

[0031] The power supply circuit 11 is connected to the error amplifier 13 and is used to supply power to the error amplifier 13.

[0032] The first voltage divider resistor R1 and the second voltage divider resistor R2 are used to collect the output voltage of the circuit output terminal VOUT, obtain the feedback voltage, and feed the feedback voltage back to the error amplifier 13.

[0033] The reference voltage circuit 12 is used to generate a reference voltage. The reference voltage circuit 12 includes a bandgap reference voltage circuit, which can minimize the impact of temperature changes on the reference voltage.

[0034] According to the virtual short and virtual open principle of error amplifier 13, the feedback voltage of the voltage divider resistor R at the non-inverting input terminal of error amplifier 13 is consistent with the reference voltage at the inverting input terminal.

[0035] The signal amplified by error amplifier 13 is output to the controllable terminal TC of power transistor T, thereby controlling the conduction voltage of power transistor T and adjusting the output voltage VOUT of the circuit.

[0036] When the output voltage decreases, the feedback voltage decreases, causing the voltage at the non-inverting input of error amplifier 13 to decrease. The output voltage of error amplifier 13 increases, which increases the voltage at the controllable terminal TC of power transistor T, thereby decreasing the voltage between the first terminal T1 and the second terminal T2 of power transistor T. This leads to an increase in the output current and voltage of power transistor T, which in turn increases the output voltage at the circuit output terminal VOUT, forming a negative feedback system.

[0037] When the output voltage increases, the feedback voltage increases, causing the voltage at the non-inverting input of error amplifier 13 to increase. The output voltage of error amplifier 13 decreases, causing the voltage at the controllable terminal TC of power transistor T to decrease, which in turn increases the voltage between the first terminal T1 and the second terminal T2 of power transistor T. This results in a decrease in the output current and voltage of power transistor T, thereby reducing the output voltage at the circuit output terminal VOUT, forming a negative feedback system.

[0038] By adjusting the resistance values ​​of the first voltage divider resistor R1 and the second voltage divider resistor R2, the voltage division ratio of the voltage divider resistor R can be adjusted, thereby adjusting the output voltage of the circuit output terminal VOUT.

[0039] The low dropout regulator circuit 10 also includes a buffer stage 16, which connects the output of the error amplifier 13 and the controllable terminal TC of the power transistor T. The buffer stage 16 can amplify the output signal connected to the error amplifier 13, so that the power transistor T can obtain a larger driving voltage and improve the current output capability of the power transistor T.

[0040] The reference voltage circuit 12 includes a reference voltage circuit 14, a startup circuit 15, and an external filter capacitor C1. The output of the reference voltage circuit 14 is connected to the input of the startup circuit 15. The external filter capacitor C1 is connected to the output of the startup circuit 15 and the ground terminal GND. The output of the startup circuit 15 is connected to the inverting input of the error amplifier 13. The startup circuit 15 is used to ensure that the voltage at the inverting input reaches the reference voltage output by the reference voltage circuit 14 within a time threshold.

[0041] Reference voltage circuit 14 is used to generate a reference voltage. Reference voltage circuit 14 includes a bandgap reference voltage circuit. The reference voltage generated by reference voltage circuit 14 includes noise, which causes ripple in the output voltage at circuit output terminal VOUT.

[0042] The external filter capacitor C1 can filter the reference voltage of the reference voltage circuit 14, thereby reducing the voltage ripple at the circuit output terminal VOUT.

[0043] If the external filter capacitor C1 is directly connected to the reference voltage circuit 14 and the ground terminal GND, the circuit will start up slowly. The voltage at the inverting input terminal of the error amplifier 13 will take a long time to reach the reference voltage, which will increase the response time of the output voltage VOUT of the circuit to the reference voltage and affect the working performance of the low dropout regulator circuit 10.

[0044] Therefore, this application includes a startup circuit 15, which connects the reference voltage circuit 14 and the inverting input of the error amplifier 13. An external filter capacitor C1 is connected to the output of the startup circuit 15 and the ground terminal GND. The startup circuit 15 ensures that the voltage at the inverting input reaches the reference voltage output by the reference voltage circuit 14 within a specified time threshold, thereby improving the circuit's response speed. The time threshold can be set based on experimentation or experience. Different startup circuits 15 can be configured according to specific time thresholds.

[0045] In some embodiments, the low-dropout regulator circuit includes: a circuit input terminal VIN, a circuit output terminal VOUT, a ground terminal GND, a power supply circuit 11, a reference voltage circuit 12, an error amplifier 13, a power transistor T, and voltage divider resistors R. The inverting input terminal of the error amplifier 13 is connected to the output terminal of the reference voltage circuit 12, and the non-inverting input terminal of the error amplifier 13 is connected between the first voltage divider resistor R1 and the second voltage divider resistor R2. The reference voltage circuit 12 includes a reference voltage circuit 14, a startup circuit 15, and an external filter capacitor C1. The output terminal of the reference voltage circuit 14 is connected to the input terminal of the startup circuit 15, the external filter capacitor C1 is connected to the output terminal of the startup circuit 15 and the ground terminal GND, and the output terminal of the startup circuit 15 is connected to the inverting input terminal of the error amplifier 13. The startup circuit 15 is used to ensure that the voltage at the inverting input terminal reaches the reference voltage output of the reference voltage circuit 14 within a time threshold, thereby improving the response speed of the low-dropout regulator circuit 10. The external filter capacitor C1 can reduce the voltage ripple at the circuit output terminal VOUT and improve the anti-interference capability.

[0046] The power transistor T includes an NMOS transistor. The low dropout regulator circuit 10 also includes a power supply voltage amplifier circuit 19, which connects the power supply circuit 11 and the NMOS transistor to amplify the output voltage of the power supply circuit 11 and supply power to the NMOS transistor.

[0047] Compared to PMOS transistors, NMOS transistors have a smaller device area, which can improve circuit response speed, reduce voltage drop, and reduce losses.

[0048] exist Figure 1 In the illustrated embodiment, the power supply circuit outputs voltage VDD1 to power the error amplifier 13. The power supply voltage amplification circuit 19 amplifies voltage VDD1 to voltage VDD2, which is then supplied to the buffer stage 16 to power the power transistor T. By setting the power supply voltage amplification circuit 19, a suitable driving voltage can be provided to the power transistor T, reducing the voltage drop of the power transistor T, increasing the output voltage VOUT at the circuit output terminal, and simultaneously increasing the output current to enhance the current driving capability.

[0049] In some embodiments, the power supply voltage amplification circuit 19 includes a charge pump circuit.

[0050] Figure 2 for Figure 1 A partial circuit diagram of one embodiment of the reference voltage circuit 12 shown.

[0051] The startup circuit 15 includes a comparator circuit 17 and a charging circuit 18. The reference voltage circuit 14 is used to output a first reference voltage Vref1 and a second reference voltage Vref2. Through resistor voltage division, the reference voltage circuit 14 can output different first reference voltages Vref1 and second reference voltages Vref2.

[0052] Comparator circuit 17 compares the output voltage of startup circuit 15 with the first reference voltage Vref1. When the output voltage of startup circuit 15 fails to reach the first reference voltage Vref1, charging circuit 18 is turned on, and reference voltage circuit 14 charges external filter capacitor C1 through charging circuit 18. By designing a specific charging circuit 18, reference voltage circuit 14 can quickly charge external filter capacitor C1, so that the voltage at the output of startup circuit 15 (i.e., the voltage at the inverting input of error amplifier 13) reaches the first reference voltage within a set time threshold.

[0053] When the output voltage of the startup circuit 15 reaches the first reference voltage Vref1, the charging circuit 18 is disconnected, and the reference voltage circuit 14 directly charges the external filter capacitor C1 until the voltage at the inverting input reaches the second reference voltage Vref2.

[0054] During the process of the reference voltage circuit 14 directly charging the external filter capacitor C1, the external filter capacitor C1 plays a filtering role.

[0055] In this way, the error amplifier 13 can respond quickly to the reference voltage, and the ripple of the reference voltage can be eliminated.

[0056] The comparator circuit 17 includes a first operational amplifier A1, a first inverter I1, and a second inverter I2. The charging circuit 18 includes a second operational amplifier A2, a first switching transistor M1, and a second switching transistor M2. The first input terminal of the first operational amplifier A1 is used to receive a first reference voltage Vref1. The second input terminal of the first operational amplifier A1 is connected to the second terminal of the first switching transistor M1. The output terminal of the first operational amplifier A1 is connected to the controllable terminal of the first switching transistor M1 through the first inverter I1, and is connected to the controllable terminal of the second switching transistor M2 through the first inverter I1 and the second inverter I2 connected in series.

[0057] The first input terminal of the second operational amplifier A2 is used to receive the second reference voltage Vref2. The second input terminal of the second operational amplifier A2 is connected to the second terminal of the first switching transistor M1. The output terminal of the second operational amplifier A2 is connected to the first terminal of the second switching transistor M2. The first terminal of the first switching transistor M1 is used to receive the second reference voltage Vref2. The second terminal of the second switching transistor M2 is connected to the output terminal of the startup circuit 15.

[0058] When the output voltage of the startup circuit 15 does not reach the first reference voltage Vref1, the first switch M1 is turned off and the second switch M2 is turned on. When the output voltage of the startup circuit 15 reaches the first reference voltage Vref1, the first switch M1 is turned on and the second switch M2 is turned off.

[0059] In this embodiment, both the first switch M1 and the second switch M2 are NMOS transistors.

[0060] The first operational amplifier A1 has a first input terminal that is positive and a second input terminal that is negative. The second operational amplifier A2 has a first input terminal that is positive and a second input terminal that is negative.

[0061] When the startup circuit 15 is connected to the reference voltage, due to the external filter capacitor C1, the output terminal of the startup circuit 15 will not immediately generate an output voltage, and the output voltage of the startup circuit 15 will be low. The voltage at the inverting input terminal of the first operational amplifier A1 is lower than the voltage at the non-inverting input terminal, so the first operational amplifier A1 outputs a high-level signal. After passing through the first inverter I1, the controllable terminal of the first switch M1 receives a low-level signal, and the first switch M1 is turned off. After passing through the first inverter I1 and the second inverter I2, the controllable terminal of the second switch M2 receives a high-level signal, and the second switch M2 is turned on. The second reference voltage Vref2 charges the external filter capacitor C1 through the second operational amplifier A2, and the second operational amplifier A2 and the second switch M2 form a unity negative feedback circuit, allowing the second reference voltage Vref2 to quickly charge the external filter capacitor C1.

[0062] When the output voltage of the startup circuit 15 reaches the first reference voltage Vref1, the voltage at the inverting input terminal of the first operational amplifier A1 is higher than the voltage at the non-inverting input terminal. The first operational amplifier A1 outputs a low-level signal. After passing through the first inverter I1, the controllable terminal of the first switch M1 receives a high-level signal, and the first switch M1 is turned on. After passing through the first inverter I1 and the second inverter I2, the controllable terminal of the second switch M2 receives a low-level signal, and the second switch M2 is turned off. The second reference voltage Vref2 directly charges the external filter capacitor C1. At this time, the circuit has a filtering effect, and the voltage of the external filter capacitor C1 will slowly rise to the second reference voltage Vref2.

[0063] In some embodiments, the first reference voltage Vref1 is 0.45V and the second reference voltage Vref2 is 0.5V. The output voltage of the startup circuit 15 first reaches 0.45V at a relatively fast rate, and then slowly rises to 0.5V.

[0064] The startup circuit 15 also includes a first resistor R11, a second resistor R12, and a filter capacitor C2. The first resistor R11 is connected to the first switching transistor M1 and the external filter capacitor C1. The second resistor R12 is connected to the second switching transistor M2 and the external filter capacitor C1. One end of the filter capacitor C1 is connected between the first resistor R11 and the second resistor R12, and the other end is connected to the ground terminal GND.

[0065] When the output voltage of the startup circuit 15 does not reach the first reference voltage Vref1, the second reference voltage Vref2 charges the external filter capacitor C1 through the second operational amplifier A2. The second operational amplifier A2, the second resistor R12, and the second switch M2 form a unity negative feedback circuit, so that the second reference voltage Vref2 can quickly charge the external filter capacitor C1.

[0066] When the output voltage of the startup circuit 15 reaches the first reference voltage Vref1, the second reference voltage Vref2 charges the external filter capacitor C1 through the first resistor R11. The first resistor R11 and the external filter capacitor C1 together perform filtering. The filter capacitor C2 further performs filtering.

[0067] Figure 3 for Figure 1 A circuit diagram of one embodiment of the power supply circuit 11 shown.

[0068] The power supply circuit 11 includes a voltage detection circuit 21 and a voltage amplification circuit 22. The voltage detection circuit 21 is connected to the circuit input terminal VIN and is used to detect whether the input voltage at the circuit input terminal VIN is greater than the threshold voltage. The voltage amplification circuit 22 is used to amplify the input voltage when the input voltage at the circuit input terminal VIN is less than the threshold voltage.

[0069] The threshold voltage can include multiple threshold voltage levels. The voltage detection circuit 21 can detect whether the input voltage at the circuit input terminal VIN is greater than a certain threshold voltage in the multiple threshold voltage levels. Based on the relationship between the input voltage at the circuit input terminal VIN and the threshold voltage, the voltage detection circuit 21 outputs a corresponding detection signal. The voltage amplification circuit 22 is used to receive the detection signal and amplify the input voltage at the circuit input terminal VIN. Specifically, the voltage amplification circuit 22 can amplify the input voltage in multiple stages and output multiple output voltages. The voltage amplified by the voltage amplification circuit 22 is used to power the error amplifier 13.

[0070] By setting up voltage detection circuit 21 and voltage amplification circuit 22, an appropriate power supply voltage can be provided to error amplifier 13 according to the input voltage at circuit input terminal VIN, ensuring the normal operation of error amplifier 13. When the input voltage at circuit input terminal VIN is low, a suitable power supply voltage can also be provided to error amplifier 13, making low dropout regulator circuit 10 suitable for low input voltage conditions.

[0071] The voltage amplifier circuit 22 includes at least two cascaded charge pump circuits 23. The voltage amplifier circuit 22 is used to: when the input voltage at the circuit input terminal VIN is less than the threshold voltage, control the number of the at least two cascaded charge pump circuits 23 that are turned on according to different magnitudes of the input voltage, so as to adjust different amplification factors of the input voltage.

[0072] The charge pump circuit 23 amplifies the input voltage, with each stage amplifying the input voltage by the same factor. Under the influence of clock signals CLK and CLKB, the charge pump circuit 23 amplifies the input voltage. By controlling the number of charge pump circuits 23 that are activated, the voltage amplifier circuit 22 amplifies the input voltage by different factors. In this embodiment, the voltage amplifier circuit 22 includes two cascaded charge pump circuits 23. Activating one charge pump circuit 23 amplifies the input voltage by one time, while activating two charge pump circuits amplifies the input voltage by two times. If the input voltage is high, fewer charge pump circuits 23 can be activated; if the input voltage is low, more charge pump circuits 23 can be activated. By using at least two cascaded charge pump circuits 23, the amplification factor of the voltage amplifier circuit 22 can be adjusted according to different input voltages, providing a suitable power supply voltage for the error amplifier 13, which can drive the internal circuitry without damaging the circuit components.

[0073] The voltage detection circuit 21 includes at least two detection resistors R0 connected in series between the circuit input terminal VIN and the ground terminal GND. The output terminal of each charge pump circuit 23 is connected to a different detection resistor R0. The voltage detection circuit 21 is used to detect the voltage of each detection resistor R0 and control the working state of at least two cascaded charge pump circuits 23 according to the detection results.

[0074] In this embodiment, the voltage detection circuit 21 includes four series-connected detection resistors R0, forming three voltage divider nodes A, B, and C. The voltage detection module VDET is connected to one detection resistor R0 respectively to detect the voltage at voltage divider nodes A, B, and C. The threshold voltage is set to 0.7V.

[0075] Based on the detection results of each voltage detection module VDET, the input voltage of the circuit input terminal VIN can be determined. Based on the detection results, the working state of each charge pump circuit 23 is controlled. According to the required amplification factor, the number of charge pump circuits 23 that are turned on is controlled, thereby accurately amplifying the input voltage and obtaining the required power supply voltage.

[0076] The output terminal of each charge pump circuit 23 is connected to a different detection resistor R0. The operating state of each charge pump circuit 23 is controlled according to the electrical signal of each detection resistor R0. In this way, the magnitude of the input voltage at the circuit input terminal VIN can be flexibly detected, and the operating state of each charge pump circuit 23 can be flexibly controlled according to the magnitude of the input voltage.

[0077] When the voltage of a certain sensing resistor R0 is not greater than the threshold voltage, the charge pump circuit 23 connected to the sensing resistor R0 is connected to the voltage amplifier circuit 22; when the voltage of a certain sensing resistor R0 is greater than the threshold voltage, the charge pump circuit 23 connected to the sensing resistor R0 is in a short-circuit state.

[0078] exist Figure 3 In the illustrated embodiment, the voltage detection module VDET, connected to voltage divider node A, outputs an enable signal EN based on the relationship between voltage divider node A and the threshold voltage. When the voltage at voltage divider node A is less than the threshold voltage, it indicates that the input voltage at the circuit input terminal VIN is less than the circuit's startup voltage, and the enable signal EN is low, disconnecting the low-dropout amplifier circuit 10. When the voltage at voltage divider node A is greater than the threshold voltage, the enable signal EN is high, activating the low-dropout amplifier circuit 10.

[0079] The voltage detection modules VDET, connected to voltage divider nodes B and C, respectively output corresponding signals Switch1 and Switch2 to the charge pump circuit 23 based on the relationship between the voltages at voltage divider nodes B and C and the threshold voltage, controlling the number of charge pump circuits 23 that are activated. When the voltage at voltage divider node B is lower than the threshold voltage, the charge pump circuit 23 connected to voltage divider node B is activated, connecting to the voltage amplifier circuit 22 to amplify the input voltage. When the voltage at voltage divider node C is lower than the threshold voltage, the charge pump circuit 23 connected to voltage divider node C is activated, connecting to the voltage amplifier circuit 22, and the two charge pump circuits 23 together amplify the input voltage. When the voltage at voltage divider node B is higher than the threshold voltage, the charge pump circuit 23 connected to voltage divider node B is disconnected, in a short-circuit state, and does not amplify the input voltage. In this way, it is possible to flexibly control whether each charge pump circuit 23 amplifies the input voltage.

[0080] The charge pump circuit 23 includes a switch S, and the output terminal of the charge pump circuit 23 is connected to the detection resistor R0 through the switch S. When the voltage of a certain detection resistor R0 is not greater than the threshold voltage, the switch S corresponding to the detection resistor R0 is open; when the voltage of a certain detection resistor R0 is greater than the threshold voltage, the switch S corresponding to the detection resistor R0 is closed.

[0081] The voltage detection module VDET outputs signals Switch1 and Switch2, which are respectively connected to switches S of a charge pump circuit 23, controlling the on / off state of switch S. When the voltage across a detection resistor R0 is not greater than a threshold voltage, the voltage detection module VDET connected to the detection resistor R0 outputs a low-level signal, the switch S corresponding to the detection resistor R0 is opened, and the charge pump circuit 23 connected to the switch S is connected to the voltage amplifier circuit 22 and is in operation. When the voltage across a detection resistor R0 is greater than the threshold voltage, the voltage detection module VDET connected to the detection resistor R0 outputs a high-level signal, the switch S corresponding to the detection resistor R0 is closed, and the charge pump circuit 23 connected to the switch S is disconnected from the voltage amplifier circuit 22, and is in a short-circuit state.

Claims

1. A low dropout voltage regulator circuit, characterized by, include: Circuit input terminal, circuit output terminal, ground terminal, power supply circuit, reference voltage circuit, error amplifier, power transistor and voltage divider resistor; The power transistor includes a first terminal, a second terminal, and a controllable terminal; the first terminal is connected to the circuit input terminal, the second terminal is connected to the circuit output terminal, and the controllable terminal is connected to the output terminal of the error amplifier. The voltage divider resistor is connected between the circuit output terminal and the ground terminal; the voltage divider resistor includes a first voltage divider resistor and a second voltage divider resistor connected in series; The inverting input of the error amplifier is connected to the output of the reference voltage circuit; the non-inverting input of the error amplifier is connected between the first voltage divider resistor and the second voltage divider resistor. The power supply circuit is connected to the error amplifier and is used to supply power to the error amplifier; The reference voltage circuit includes a reference voltage circuit, a startup circuit, and an off-chip filter capacitor; The output terminal of the reference voltage circuit is connected to the input terminal of the startup circuit. The external filter capacitor is connected to the output terminal of the startup circuit and the ground terminal. The output terminal of the startup circuit is connected to the inverting input terminal of the error amplifier. The startup circuit is used to make the voltage at the inverting input terminal reach the reference voltage output by the reference voltage circuit within a time threshold.

2. The low dropout voltage regulator circuit of claim 1, wherein, The startup circuit includes a comparator circuit and a charging circuit; the reference voltage circuit is used to output a first reference voltage and a second reference voltage; the comparator circuit is used to compare the output voltage of the startup circuit with the first reference voltage; When the output voltage of the startup circuit does not reach the first reference voltage, the charging circuit is turned on, and the reference voltage circuit charges the external filter capacitor through the charging circuit; when the output voltage of the startup circuit reaches the first reference voltage, the charging circuit is turned off, and the reference voltage circuit directly charges the external filter capacitor until the voltage at the inverting input terminal reaches the second reference voltage.

3. The low dropout voltage regulator circuit of claim 2, wherein, The comparator circuit includes a first operational amplifier, a first inverter, and a second inverter; the charging circuit includes a second operational amplifier, a first switching transistor, and a second switching transistor; the first input terminal of the first operational amplifier is used to receive the first reference voltage, the second input terminal of the first operational amplifier is connected to the second terminal of the first switching transistor, the output terminal of the first operational amplifier is connected to the controllable terminal of the first switching transistor through the first inverter, and is connected to the controllable terminal of the second switching transistor through the first inverter and the second inverter connected in series; the first input terminal of the second operational amplifier is used to receive the second reference voltage, the second input terminal of the second operational amplifier is connected to the second terminal of the first switching transistor, and the output terminal of the second operational amplifier is connected to the first terminal of the second switching transistor; the first terminal of the first switching transistor is used to receive the second reference voltage, and the second terminal of the second switching transistor is connected to the output terminal of the startup circuit; when the output voltage of the startup circuit does not reach the first reference voltage, the first switching transistor is turned off and the second switching transistor is turned on; when the output voltage of the startup circuit reaches the first reference voltage, the first switching transistor is turned on and the second switching transistor is turned off.

4. The low dropout voltage regulator circuit of claim 3, wherein, The startup circuit further includes a first resistor, a second resistor, and a filter capacitor; the first resistor is connected to the first switching transistor and the external filter capacitor; the second resistor is connected to the second switching transistor and the external filter capacitor; one end of the filter capacitor is connected between the first resistor and the second resistor, and the other end is connected to the ground terminal.

5. The low dropout regulator circuit of claim 1, wherein, The power supply circuit includes a voltage detection circuit and a voltage amplification circuit; the voltage detection circuit is connected to the circuit input terminal and is used to detect whether the input voltage at the circuit input terminal is greater than a threshold voltage; the voltage amplification circuit is used to amplify the input voltage when the input voltage at the circuit input terminal is less than the threshold voltage.

6. The low dropout regulator circuit of claim 5, wherein, The voltage amplification circuit includes at least two cascaded charge pump circuits. The voltage amplification circuit is used to: when the input voltage at the circuit input terminal is less than a threshold voltage, control the number of the at least two cascaded charge pump circuits turned on according to the different magnitudes of the input voltage, so as to adjust the different amplification factors of the input voltage.

7. The low dropout voltage regulator circuit of claim 6, wherein, The voltage detection circuit includes at least two detection resistors connected in series between the circuit input terminal and the ground terminal. The output terminal of each charge pump circuit is connected to a different detection resistor. The voltage detection circuit is used to detect the voltage of each detection resistor and control the operating state of the at least two cascaded charge pump circuits based on the detection results.

8. The low dropout regulator circuit of claim 7, wherein, When the voltage of a certain sensing resistor is not greater than the threshold voltage, the charge pump circuit connected to the sensing resistor is connected to the voltage amplification circuit; when the voltage of a certain sensing resistor is greater than the threshold voltage, the charge pump circuit connected to the sensing resistor is in a short-circuit state.

9. The low dropout voltage regulator circuit of claim 8, wherein, The charge pump circuit includes a switch, and the output terminal of the charge pump circuit is connected to the detection resistor through the switch; when the voltage of a certain detection resistor is not greater than the threshold voltage, the switch corresponding to the detection resistor is open, and when the voltage of a certain detection resistor is greater than the threshold voltage, the switch corresponding to the detection resistor is closed.

10. The low dropout regulator circuit of claim 1, wherein, The power transistor includes an NMOS transistor, and the low dropout regulator circuit also includes a power supply voltage amplifier circuit connected to the power supply circuit and the NMOS transistor, used to amplify the output voltage of the power supply circuit to power the NMOS transistor.

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