Current source circuit and methods for generating zero temperature coefficient current

Abstract

This invention provides a current source circuit and a method for generating a zero-temperature-coefficient current. The circuit includes a current mirror, a bias resistor, a first transistor, a second transistor, and a first current source. The current mirror is coupled between a supply voltage terminal, a first node, and a second node, and is configured to output a first current and a second current to the first node and the second node, respectively. The bias resistor is coupled between the first node and a third node to control the first current based on the voltage difference between the first node and the third node. The first transistor is coupled between the third node and a reference voltage terminal. The second transistor is coupled between the second node and the reference voltage terminal. The first current source is configured to output a third current to the second node to generate a fourth current. The third current has a negative temperature coefficient.

Description

Technical Field

[0001] This invention relates to a current source circuit, and more particularly to a current source circuit and method capable of generating current with zero temperature coefficient or positive temperature coefficient. Background Technology

[0002] Current-current circuits are typically affected by temperature (e.g., output current increases or decreases due to rising temperature). When a precise and stable current source is required, these variations can lead to unpredictable errors or inaccuracies in circuit operation. To eliminate or reduce the effects of temperature, an additional resistor is usually added to the current-current circuit. However, with increasing circuit design and manufacturing costs, circuit area has become a significant concern, and the area required for the additional resistor is substantial. Therefore, a solution is needed that simultaneously achieves space savings and stable output current. Summary of the Invention

[0003] According to one embodiment, this disclosure provides a current source circuit including a current mirror, a bias resistor, a first transistor, a second transistor, and a first current source. The current mirror is coupled between a supply voltage terminal, a first node, and a second node, and is configured to output a first current to the first node and a second current to the second node. The bias resistor is coupled between the first node and a third node to control the first current based on the voltage difference between the first and third nodes. The first transistor has a first terminal coupled to the third node, a second terminal coupled to a reference voltage terminal, and a first control terminal. The second transistor has a third terminal coupled to the second node, a fourth terminal coupled to the reference voltage terminal, and a second control terminal. The first current source is configured to output a third current to the second node to generate a fourth current.

[0004] The third current has a negative temperature coefficient. The fourth current is the sum of the second and third currents.

[0005] In one embodiment, the current source circuit further includes a second current source configured to draw a fifth current from the third node to generate a sixth current flowing through the first transistor, wherein the fifth current has a negative temperature coefficient and the sixth current is the first current minus the fifth current.

[0006] The first current source further includes a fifth transistor, a sixth transistor, and a seventh transistor. The fifth transistor has a ninth terminal coupled to the second node, a tenth terminal coupled to the supply voltage terminal, and a fifth control terminal. The sixth transistor has an eleventh terminal and a sixth control terminal coupled to each other, and a twelfth terminal coupled to the supply voltage terminal. The seventh transistor has a thirteenth terminal coupled to the eleventh terminal of the sixth transistor, a seventh control terminal coupled to the third node, and a fourteenth terminal coupled to the reference voltage terminal. The fifth control terminal of the fifth transistor is coupled to the sixth control terminal of the sixth transistor.

[0007] The second current source further includes an eighth transistor having a fifteenth terminal and an eighth control terminal coupled to the third node, and a sixteenth terminal coupled to the reference voltage terminal.

[0008] According to another embodiment, the current source circuit further includes a first switch and a second switch. The first switch is coupled between the first current source and the first node. The second switch is coupled between the second current source and the third node.

[0009] The first switch and the second switch are configured to be turned on in a zero temperature coefficient mode and to be turned off in a positive temperature coefficient mode.

[0010] According to one embodiment, this disclosure provides a method for generating a zero-temperature coefficient current, comprising: outputting a first current and a second current to a first node and a second node respectively via a current mirror; outputting a third current to the second node via a first current source to generate a fourth current flowing out of the second node, wherein the third current has a negative temperature coefficient and the fourth current is the second current plus the third current; and drawing a fifth current from a third node via a second current source to generate a sixth current, wherein the fifth current has a negative temperature coefficient and the sixth current is the first current minus the fifth current.

[0011] In this method, a bias resistor is used to control the first current, and the bias resistor is coupled between the first node and the third node.

[0012] Since the current source used in this disclosure consists only of transistors, it achieves a greater effect of saving circuit area compared to the traditional method of reducing current by using additional resistors. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a current source circuit described according to an embodiment of the present invention.

[0014] Figure 2 This is a circuit diagram of a current source circuit described according to an embodiment of this case.

[0015] Figure 3This is a schematic diagram of a current source circuit with switching function according to an embodiment of the present invention.

[0016] Symbol Explanation

[0017] 100, 200, 300: Current source circuit

[0018] 110: Current Mirror

[0019] 115: Operational amplifier

[0020] 120: Bias resistor

[0021] M1, M2, M3, M4, M5, M6, Q1, Q2: Transistors

[0022] N1, N2, N3: Nodes

[0023] I0, I1, I2, I3, I4, I5: Current

[0024] IS1, IS2, 230, 240: Current Sources

[0025] VDD: Supply voltage terminal

[0026] VSS: Reference voltage terminal

[0027] S1, S2: Switches Detailed Implementation

[0028] To make the above and other objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings:

[0029] The following outlines some embodiments to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. However, these embodiments are merely exemplary and not intended to limit the scope of the present invention. It is understood that those skilled in the art can modify the embodiments described below as needed, for example, by changing the process sequence and / or including more or fewer steps than described herein, and these modifications do not exceed the scope of the embodiments of the present invention.

[0030] Figure 1This is a schematic diagram of a current source circuit 100 according to an embodiment of the present invention. The current source circuit 100 includes a current mirror 110, a bias resistor 120, transistors Q1 and Q2, and a current source IS2. The current mirror 110 is coupled to a supply voltage terminal VDD and outputs a current I0 and a current I3 to a node N1 and a node N2, respectively. The bias resistor 120 is coupled between node N1 and a node N3. The first terminal of transistor Q1 is coupled to node N3, and the second terminal and control terminal of transistor Q1 are coupled to a reference voltage terminal VSS. The first terminal of transistor Q2 is coupled to node N2, and the second terminal and control terminal of transistor Q2 are coupled to the reference voltage terminal VSS. That is, the control terminals of transistors Q1 and Q2 are coupled to each other. Current source IS2 has a negative temperature coefficient (i.e., it decreases as temperature increases) and is configured to output a current I2 to node N2 to generate a current I4 flowing through transistor Q1, where current I4 is the sum of currents I2 and I3.

[0031] The current mirror 110 includes transistors M1 and M2, and an operational amplifier 115. The first terminal of transistor M1 is coupled to the supply voltage terminal VDD, the second terminal of transistor M1 is coupled to node N1, and the control terminal of transistor M1 is coupled to the output terminal of operational amplifier 115. The first terminal of transistor M2 is coupled to the supply voltage terminal VDD, the second terminal of transistor M2 is coupled to node N2, and the control terminal of transistor M2 is coupled to the output terminal of operational amplifier 115. That is, the control terminals of both transistors M1 and M2 are coupled to the output terminal of operational amplifier 115. Operational amplifier 115 further has a first input terminal (labeled "+") and a second input terminal (labeled "-"), respectively coupled to nodes N1 and N2.

[0032] There is a first voltage difference VBE1 between the first terminal and the control terminal of transistor Q1, and a second voltage difference VBE2 between the first terminal and the control terminal of transistor Q2. When a virtual short circuit is formed between the first and second input terminals of operational amplifier 115, the voltage at node N2 will approach the second voltage difference VBE2, making the voltage across bias resistor 120 equivalent to VBE2 - VBE1. Assuming that bias resistor 120 has a resistance value Rbias, the current I0 can be derived from the following formula:

[0033]

[0034] That is, the bias resistor 120 can be used to control the current value of I0. Furthermore, as... Figure 1As shown, transistors Q1 and Q2 are bipolar junction transistors (BJTs), therefore the first voltage difference VBE1 and the second voltage difference VBE2 decrease with increasing temperature. However, generally, the first voltage difference VBE1 is configured to have a larger decrease than the second voltage difference VBE2, so the voltage across the bias resistor 120 increases with increasing temperature, which in turn causes the current I0 to increase with increasing temperature. Therefore, the current I0 has a positive temperature coefficient.

[0035] To reduce or offset the increase in current I0 with rising temperature, current source IS2 outputs a current I2 with a negative temperature coefficient to node N2. This ensures that the second voltage difference VBE2 of transistor Q2 decreases by the same amount as the first voltage difference VBE1 of transistor Q1 as the temperature rises, thus achieving temperature compensation and eliminating or reducing the increase in current I0 with rising temperature. However, the design of current source IS2 requires consideration of current mirror 110, transistors Q1 and Q2, bias resistor 120, and any components present in current source circuit 100, which may increase the design complexity and difficulty of current source IS2. Therefore, as... Figure 1 As shown, a current source IS1 with a negative temperature coefficient is added to the current source circuit 100 to effectively design a current source IS2 that meets the requirements of the current source circuit 100.

[0036] Current source IS1 is configured to draw a current I1 from node N3 to generate a current I5 flowing through transistor Q1, where current I5 is current I0 minus current I1. By appropriately configuring the ratio of currents I1 and I2 (e.g., configuring the current value of current I2 as a multiple of the current value of current I1), a current source IS2 that can eliminate or reduce the influence of temperature on current I0 can be designed effectively and easily.

[0037] It should be noted that, although Figure 1 As shown, the current mirror 110 includes transistors M1 and M2, which are P-type metal-oxide-semiconductor transistors (PMOS), and transistors Q1 and Q2, which are PNP type BJTs. However, transistors M1 and M2 can also be N-type MOS, and transistors Q1 and Q2 can also be NPN type BJTs.

[0038] Figure 2This is a circuit diagram of a current source circuit 200 described according to an embodiment of the present invention. Similar to current source circuit 100, current source circuit 200 includes a current mirror 110, transistors Q1 and Q2, and a bias resistor 120. Current source circuit 200 further includes current sources 230 and 240, which are examples of current sources IS1 and IS2, respectively.

[0039] Current source 230 includes a transistor M5, having a first terminal coupled to node N3 and a control terminal, and a second terminal coupled to a reference voltage terminal VSS. Current source 240 includes transistors M3, M4, and M6, wherein transistor M3 has a first terminal coupled to node N2 and a second terminal coupled to a supply voltage terminal VDD. Transistor M4 has a first terminal coupled to the control terminal of transistor M3 and a control terminal coupled to the supply voltage terminal VDD. Transistor M6 has a first terminal coupled to the first terminal of transistor M4, a second terminal coupled to the reference voltage terminal VSS, and a control terminal coupled to the control terminal of transistor M5.

[0040] The following details how the configuration of currents I0, I1, and I2 can be used to eliminate or reduce the increase in current I0 with rising temperature. Assuming the current ratio between transistors M1 and M2 is 1:M, the relationship between currents I3 and I0 can be deduced as I3 = M × I0. Therefore, the relationship between currents I0, I2, I3, and I4 can be deduced as follows:

[0041] I4=I2+I3=I2+M×I0 (2)

[0042] At this point, the voltage across the bias resistor 120 can be expressed as:

[0043]

[0044] Where V T The thermal voltage is (kT / q).

[0045] Next, formula (3) is rewritten using Taylor series as follows to calculate the magnitude of the temperature compensation current at a temperature of S degrees:

[0046]

[0047] Where α is V T The slope with respect to temperature, β1 is the slope of current I1 with respect to temperature, and r is the multiple of current I2 with respect to I1. Furthermore, I0 >> I1 and I0 >> I2. In this case, the coefficient of ΔT obtained from formula (4) If it is zero, then V can be eliminated. T The temperature effect is determined and the generated VBE2-VBE1 is confirmed to be a voltage with zero temperature coefficient. Based on this voltage and referring to formula (1), the current I0 with zero temperature coefficient can be obtained.

[0048] At this time, refer to Figure 2 Assuming the current ratio of transistors M5 and M6 is 1:K, and the current ratio of transistors M4 and M3 is 1:N, then the relationship between currents I2 and I1 can be derived as I2 = N × K × I1. A portion of formula (4) can be rewritten as:

[0049]

[0050] Therefore, in the design process, it is only necessary to consider the characteristics of currents I0 and I1 and the current I1 at the current temperature of S degrees to find the value of r, so as to eliminate or reduce the increase of current I0 when the temperature rises. At the same time, by adding current sources IS1 and 230 to current source circuits 100 and 200 respectively, the design of current sources IS2 and 240 can be achieved effectively and simply.

[0051] It should be noted that, although Figure 2 As shown, transistor M5 in current source 230 and transistor M6 in current source 240 are NMOS transistors, while transistors M3 and M4 in current source 240 are PMOS transistors. However, transistors M5 and M6 can also be PMOS transistors, and transistors M3 and M4 can also be NMOS transistors.

[0052] Figure 3 This is a schematic diagram of a current source circuit 300 with switching functionality according to an embodiment of this invention. Similar to current source circuit 100, current source circuit 300 includes a current mirror 110, transistors Q1 and Q2, a bias resistor 120, and current sources IS1 and IS2. The difference between current source circuit 300 and current source circuit 100 is that current source circuit 300 further includes switches S1 and S2. Switch S1 is coupled between current source IS1 and node N3, while switch S2 is coupled between current source IS2 and node N2.

[0053] When switches S1 and S2 are on, current source circuit 300 can have the same function as current source circuit 100, that is, generate a current I0 with zero temperature coefficient (i.e., unaffected by temperature) or a very small temperature coefficient (i.e., minimally affected by temperature). In this case, current source circuit 300 can be considered to be in a zero temperature coefficient mode. Conversely, when switches S1 and S2 are off, since current source IS1 no longer draws current I1 from node N3 and current source IS2 no longer outputs current I2 to node N2, current source circuit 300 will generate a current I0 with a positive temperature coefficient. In this case, current source circuit 300 can be considered to be in a positive temperature coefficient mode.

[0054] Switches S1 and S2 can be controlled by a controller (not shown), such as a microcontroller or microprocessor, switching between a zero-temperature coefficient mode and a positive temperature coefficient mode. In one embodiment, in response to the need for a stable current source, the controller can control switches S1 and S2 to be turned on, so that currents I1 and I2 compensate for current I0 to offset or reduce the increase in current I0 as the temperature rises. In another embodiment, in response to temperature-related needs (e.g., as part of a thermometer circuit), the controller can control switches S1 and S2 to be turned off, so that currents I1 and I2 cannot compensate for current I0, in order to perform positive temperature coefficient or other temperature-related operations.

[0055] This disclosure provides a current source circuit including a current mirror, multiple transistors, and one or more current sources with a negative temperature coefficient, including a bias resistor. The current mirror generates currents I0 and I3 and outputs them to nodes N1 and N2, respectively, where the ratio of currents I0 to I3 is 1:M, i.e., I3 = M × I0. Current source IS2 outputs current I2 to node N2 to generate a current I4 output from node N2, i.e., I4 = M × I0 + I2. The bias resistor is used to control the magnitude of current I0. Current source IS1 draws current I1 from node N3 to generate a current I5 flowing through transistor Q1, i.e., I5 = I0 - I1.

[0056] Furthermore, by configuring multiple transistors in current sources IS1 and IS2 such that the current value of I2 is a multiple of the current value of I1, it is possible to effectively and easily eliminate or reduce the increase in current I0 as the temperature rises by using current sources with negative temperature coefficients to add and / or extract current. At the same time, since the current sources used in this disclosure consist only of transistors, compared to the traditional method of reducing current using additional resistors, it achieves a greater saving in circuit area.

Claims

1. A current source circuit, characterized by, include: A current mirror is coupled between a supply voltage terminal, a first node and a second node, wherein the current mirror is configured to output a first current to the first node and a second current to the second node; A bias resistor is coupled between the first node and a third node to control the first current based on the voltage difference between the first node and the third node. A first transistor has a first terminal coupled to the third node, a second terminal coupled to a reference voltage terminal, and a first control terminal; A second transistor having a third terminal coupled to the second node, a fourth terminal coupled to the reference voltage terminal, and a second control terminal; and A first current source is configured to output a third current to the second node to generate a fourth current, wherein the third current has a negative temperature coefficient. The fourth current is the sum of the second current and the third current.

2. The current source circuit of claim 1, wherein, The aforementioned current mirrors include: A third transistor has a fifth terminal coupled to the first node and a sixth terminal coupled to the supply voltage terminal; A fourth transistor having a seventh terminal coupled to the second node and an eighth terminal coupled to the supply voltage terminal; and An operational amplifier, wherein an output terminal of the operational amplifier is coupled to a third control terminal of the third transistor and a fourth control terminal of the fourth transistor, a first input terminal of the operational amplifier is coupled to the first node, and a second input terminal of the operational amplifier is coupled to the second node.

3. The current source circuit of claim 1, wherein, It further includes a second current source configured to draw a fifth current from the third node to generate a sixth current flowing through the first transistor, wherein the fifth current has a negative temperature coefficient and the sixth current is the first current minus the fifth current.

4. The current source circuit of claim 3, wherein, The aforementioned first current source further includes: A fifth transistor has a ninth terminal coupled to the second node, a tenth terminal coupled to the supply voltage terminal, and a fifth control terminal; A sixth transistor has an eleventh terminal and a sixth control terminal coupled to each other, and a twelfth terminal coupled to the aforementioned supply voltage terminal; and A seventh transistor has a thirteenth terminal coupled to the eleventh terminal of the sixth transistor, a seventh control terminal coupled to the third node, and a fourteenth terminal coupled to the reference voltage terminal. The fifth control terminal of the fifth transistor is coupled to the sixth control terminal of the sixth transistor.

5. The current source circuit of claim 4, wherein, The aforementioned second current source further includes: An eighth transistor has a fifteenth terminal and an eighth control terminal coupled to the third node, and a sixteenth terminal coupled to the reference voltage terminal.

6. The current source circuit as described in claim 5, characterized in that: The current flowing through the fifth transistor is a first multiple of the current flowing through the sixth transistor. The current flowing through the seventh transistor is a second multiple of the current flowing through the eighth transistor. as well as The aforementioned third current is a third multiple of the aforementioned fifth current, wherein the aforementioned third multiple is the product of the aforementioned first multiple and the aforementioned second multiple.

7. The current source circuit of claim 1, wherein, Including: A first switch is coupled between the first current source and the first node, wherein the first switch is configured to be turned on in a zero temperature coefficient mode and to be turned off in a positive temperature coefficient mode.

8. The current source circuit of claim 3, wherein, Including: A first switch is coupled between the first current source and the first node; and A second switch is coupled between the second current source and the third node. The first switch and the second switch are configured to be turned on in a zero temperature coefficient mode and to be turned off in a positive temperature coefficient mode.

9. A method of generating a zero-temperature coefficient current, characterized by, include: Using a current mirror, a first current and a second current are output to a first node and a second node, respectively; A third current is output to the second node via a first current source to generate a fourth current flowing out of the second node, wherein the third current has a negative temperature coefficient and the fourth current is the second current plus the third current. as well as A fifth current is drawn from a third node via a second current source to generate a sixth current, wherein the fifth current has a negative temperature coefficient and the sixth current is the first current minus the fifth current. Specifically, a bias resistor is used to control the first current, and the bias resistor is coupled between the first node and the third node.

10. The method for generating a zero temperature coefficient current as described in claim 9, characterized in that, Including: In a zero temperature coefficient mode, a first switch and a second switch are turned on; as well as In a positive temperature coefficient mode, disconnect the first switch and the second switch. The first switch is coupled between the first current source and the second node, and the second switch is coupled between the second current source and the third node.

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