JTAG system of the chip

Abstract

This application provides a chip-based JTAG system. The chip includes: a first JTAG interface forming a first JTAG chain, a first CPU core group, and a first JTAG-bus conversion unit; the first JTAG-bus also couples to at least one hardware resource within the chip that needs to be accessed by the first JTAG interface, the hardware resource not being linked to the first JTAG chain; the first JTAG interface accesses the first CPU core group and the first JTAG-bus conversion unit in a chained manner; the first JTAG-bus conversion unit, in response to recognizing a first access request received through the first JTAG link indicating access to the hardware resource, accesses the hardware resource, and sends the access result to the first JTAG interface through the first JTAG chain.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and more particularly to JTAG systems for chips. Background Technology

[0002] Figure 1A A block diagram of a solid-state storage device (SSD) is shown. The SSD 102 is coupled to a host computer to provide storage capabilities. The host computer and the SSD 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Solid-state storage device 102 (hereinafter referred to as storage device) includes interface 103, control unit 104, one or more NVM chips 105 and DRAM (Dynamic Random Access Memory) 110.

[0003] The aforementioned NVM chip 105 includes common storage media such as NAND flash memory, phase-change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), and RRAM (Resistive Random Access Memory). The NVM chip 105 includes one or more logic units (LUNs). A logic unit (LUN) is the smallest unit in the NVM chip that independently executes commands and reports its status.

[0004] The aforementioned interface 103 can be adapted to exchange data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The aforementioned control unit 104 is used to control data transmission between interface 103, NVM chip 105, and DRAM 110, and is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. Control unit 104 can be implemented in various ways, including software, hardware, firmware, or combinations thereof. For example, control unit 104 can be in the form of an FPGA (Field-programmable gate array), ASIC (Application Specific Integrated Circuit), or a combination thereof. Control unit 104 may also include a processor or controller, in which software is executed to manipulate the hardware of control unit 104 to process I / O (Input / Output) commands. Control unit 104 can also be coupled to DRAM 110 and can access data in DRAM 110. FTL tables and / or cached I / O command data can be stored in DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] The host accesses storage device 102 using I / O commands that conform to the storage protocol. The control unit 104 generates one or more media interface commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that conform to the interface protocol of the NVM chip based on the media interface commands. The control unit also tracks the completion of all media interface commands generated from an I / O command and indicates the processing results of the I / O commands to the host.

[0008] Figure 1B A schematic diagram of the control components of the storage device is shown. (For example...) Figure 1BThe control unit 104 includes, for example, a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a media interface controller 1045, and a storage media management unit 1044. The host interface 1041 receives I / O commands from the host and generates storage commands, which are then provided to the storage command processing unit 1042. Storage commands may access storage space of the same size, such as 4KB. The storage media management unit 1044 maintains a logical address to physical address translation for each storage command. For example, the storage media management unit 1044 includes an FTL table. For read commands, the storage media management unit 1044 outputs the physical address corresponding to the logical address accessed by the storage command; for write commands, the storage media management unit 1044 allocates an available physical address and records the mapping between the accessed logical address and the allocated physical address. The storage media management unit 1044 also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0009] The storage command processing unit 1043, based on the physical address provided by the storage media management unit 1044, operates the media interface controller 1045 to issue a storage media access command to the NVM chip. For clarity, the command sent from the host to the storage device is called an IO command; the command sent from the host command processing unit 1042 to the storage command processing unit 1043 is called a storage command; the command sent from the storage command processing unit 1043 to the media interface controller 1045 is called a media interface command; and the command sent from the media interface controller 1045 to the NVM chip is called a storage media access command. The storage media access command conforms to the NVM chip's interface protocol.

[0010] Figure 1C A detailed block diagram of the control components is shown. (For example...) Figure 1C As shown, the control components include: a host interface (PCIe interface), a host command processing unit, a storage media management unit, a storage command processing unit, a media interface controller, a DDR interface, and a JTAG interface.

[0011] The host interface is, for example, a PCIe interface based on the PCIe protocol. The host command processing unit includes an NVMe protocol processor and multiple CPU cores (referred to as CPU core group 0). The NVMe protocol processor can be referenced in Chinese patents 2023107884483, 2023107884549, 201510887865.9, 201610505459.6, and 201510997494X. The storage command processing unit and storage media management unit are implemented by multiple CPU cores (referred to as CPU core group 1). Some CPU cores in CPU core group 0 and CPU core group 1 can be shared. The media interface controller includes multiple CPU cores (referred to as CPU core group 2) and multiple LUN controllers (referred to as LUN controller group). The DDR (Double Data Rate) interface is used to access DDR memory external to the control unit. PCIe interfaces, DDR interfaces, and media interface controllers that connect to NVM chips (such as the ONFI interface) are all high-speed interfaces, with data transfer rates in the hundreds of megahertz (MHz) or even higher. These interfaces include PHY circuitry (called physical layer modules) used to generate the signal waveforms required for the protocols followed by each interface, clock synchronization, delay jitter control, etc. The PHY circuitry for these interfaces is referred to as the PCIe PHY, DDR PHY, and media interface PHY, respectively.

[0012] A JTAG interface refers to an interface that supports the JTAG protocol. The JTAG (Joint Test Action Group) protocol is used for debugging electronic devices. Figure 1C As shown, the control unit connects to the debugger via a JTAG interface. The debugger generates JTAG commands compliant with the JTAG protocol to access data within the control unit and can optionally operate various hardware units within the control unit.

[0013] For ease of debugging, JTAG connects the various hardware units within the control unit via a link (hereinafter referred to as the JTAG chain) independent of the control unit's internal bus. To reduce hardware resource consumption, the JTAG chain typically connects the hardware units (such as...) in a serial manner. Figure 1C (As shown by the red dashed line in the diagram). Because each hardware unit is linked together via a JTAG chain, when accessing each hardware unit through the JTAG interface, the data to be accessed needs to be moved from the data source to the JTAG interface via the JTAG chain before it can be obtained by the debugger, resulting in a relatively slow access speed.

[0014] As control units grow in size and complexity, the number of hardware resources requiring JTAG access increases rapidly, causing a significant performance degradation when the chained JTAG architecture is applied to new control units. For example, access latency to a single hardware resource increases significantly, slowing down the JTAG debugging process and severely impacting chip development efficiency. On the other hand, while the JTAG chain provides a pathway to access the internal hardware resources of the control unit, facilitating the debugging process, some resources within the control unit are sensitive. For instance, control registers in the DDR-PHY and PCIe-PHY may cause communication failures between the control unit and the host or DDR memory, leading to serious malfunctions. Therefore, it is necessary to improve the security of sensitive resources within the control unit during debugging and to prevent users from accessing them via JTAG after debugging is complete and the unit is provided to the user. Summary of the Invention

[0015] To solve the above-mentioned technical problems, or at least partially solve the above-mentioned technical problems, embodiments of this application provide a JTAG system for a storage control chip.

[0016] In a first aspect, embodiments of this application provide a chip, including: a first JTAG interface, a first CPU core group, and a first JTAG-bus conversion unit; the first JTAG interface, the first CPU core group, and the first JTAG-bus conversion unit form a first JTAG chain;

[0017] On the first JTAG chain, the first JTAG interface is coupled to the first CPU core group, the first CPU core group is coupled to the first JTAG-bus conversion unit, and the first JTAG-bus conversion unit is coupled to the first JTAG interface.

[0018] The first JTAG-bus conversion unit is also coupled to at least one hardware resource within the chip. The at least one hardware resource is not linked to the first JTAG chain. The hardware resource is a hardware resource within the chip that needs to be accessed by the first JTAG interface.

[0019] The first JTAG interface accesses the first CPU core group and the first JTAG-bus conversion unit in a chained manner;

[0020] The first JTAG-bus conversion unit responds to recognizing a first access request received through the first JTAG link indicating access to the hardware resource, accesses the hardware resource, and sends the access result to the first JTAG interface through the first JTAG chain.

[0021] Optionally, the first JTAG-bus conversion unit is coupled to the at least one hardware resource via a first bus;

[0022] The first JTAG-bus conversion unit responds to the recognition of the first access request indicating access to the hardware resource by accessing the hardware resource through the first bus and sends the access result to the first JTAG interface through the first JTAG chain.

[0023] Optionally, there may be multiple hardware resources, and these multiple hardware resources may occupy different address spaces on the first bus; the first JTAG-bus translation unit accesses the hardware resources according to their addresses on the first bus.

[0024] Optionally, the first JTAG-bus conversion unit is a JTAG bridge, and the chip further includes a first multiplexer, the JTAG bridge being coupled to the first multiplexer, and the first multiplexer being coupled to each of the at least one hardware resource through a path following the JTAG protocol.

[0025] The first multiplexer receives a first selection signal and connects the first JTAG chain to the hardware resource indicated by the first selection signal via the JTAG bridge.

[0026] Optionally, in response to recognizing that the second access request indicates access to a hardware resource coupled to the first multiplexer, the JTAG bridge generates a first selection signal and provides the first selection signal to the first multiplexer, the first selection signal indicating that the first JTAG chain is connected to the hardware resource.

[0027] Optionally, the hardware resources include one or more of a hardware accelerator, an NVMe protocol processor, and a LUN controller group.

[0028] Optionally, the first JTAG interface may exclusively occupy multiple pins of the chip for transmitting JTAG signals.

[0029] Optionally, the first JTAG interface exclusively occupies four pins of the chip to transmit the mode selection signal, clock signal, data input signal, and data output signal in the JTAG signal.

[0030] Optionally, the chip further includes a second JTAG interface and a second multiplexer, wherein the second JTAG interface is coupled to the second multiplexer, and the second multiplexer is coupled to multiple sensitive hardware resources within the chip;

[0031] The second multiplexer connects the JTAG signal of the second JTAG interface to one of the sensitive hardware resources.

[0032] Optionally, the second multiplexer directly couples the plurality of sensitive hardware resources. The second multiplexer receives a second selection signal, provides the third access request to the sensitive hardware resource indicated by the second selection signal, and connects the sensitive hardware resource to the JTAG signal of the second JTAG interface.

[0033] Optionally, the second multiplexer couples the sensitive hardware resources through a second JTAG-bus conversion unit; the second JTAG-bus conversion unit couples the sensitive hardware resources through a third bus.

[0034] The second JTAG-bus conversion unit, in response to receiving a second access request from the second multiplexer, accesses the sensitive hardware resource indicated by the second access request via the third bus.

[0035] Optionally, the number of the second JTAG-bus conversion units is the same as the number of the sensitive hardware resources, and the plurality of sensitive hardware resources are coupled to the second multiplexer through different second JTAG-bus conversion units.

[0036] Optionally, the number of the second JTAG-bus conversion units is less than the number of the sensitive hardware resources. Some of the sensitive hardware resources are coupled to the second multiplexer through the second JTAG-bus conversion units, and the remaining sensitive hardware resources are directly coupled to the second multiplexer.

[0037] Optionally, the chip may also include a PICe interface, a DDR controller, a media interface controller, and a cross-chip interface unit;

[0038] The sensitive hardware resources include one or more of the following: the physical layer module of the PICe interface, the physical layer module of the DDR controller, the physical layer module of the media interface controller, and the physical layer module of the cross-chip interface unit.

[0039] Optionally, the second JTAG interface occupies multiple pins of the chip to transmit JTAG signals; the second JTAG interface multiplexes multiple pins of the chip with the general purpose input / output unit, and the second JTAG interface can be disabled.

[0040] Optionally, in response to receiving a configuration command, the chip configures the plurality of pins to connect to a general-purpose input / output unit.

[0041] Optionally, the second JTAG interface may exclusively use multiple pins of the chip to transmit JTAG commands.

[0042] Optionally, the hardware resources accessed through the first JTAG interface are the same as those accessed through the second JTAG interface.

[0043] Optionally, the chip may further include a second CPU core group and a third CPU core group;

[0044] On the first JTAG chain, the first CPU core group is coupled to the second CPU core group, the second CPU core group is coupled to the third CPU core group, and the third CPU core group is coupled to the first JTAG-bus conversion unit;

[0045] The first JTAG interface accesses the second CPU core group and the third CPU core group in a chained manner.

[0046] Optionally, the chip further includes a JTAG signal switching unit, which couples the first JTAG interface to the first JTAG chain and the first JTAG interface to the first CPU core group.

[0047] The JTAG signal switching unit is used to switch the operating mode of accessing the first CPU core group through the first JTAG interface.

[0048] Optionally, the operating modes for accessing the first CPU core group through the first JTAG interface include chained mode and exclusive mode.

[0049] When the working mode of accessing the first CPU core group through the first JTAG interface is the chain mode, the first JTAG interface, the JTAG signal switching unit, the first CPU core group, the second CPU core group, the third CPU core group and the first JTAG-bus conversion unit form the first JTAG chain.

[0050] When the operating mode of accessing the first CPU core group through the first JTAG interface is exclusive mode, the JTAG signal switching unit connects the JTAG signal of the first JTAG interface to the first CPU core group, but not to the first JTAG chain.

[0051] Optionally, the first JTAG interface is coupled to the JTAG signal switching unit through four pins to transmit the mode selection signal, clock signal, data input signal and data output signal in the JTAG signal;

[0052] The second CPU core group, the third CPU core group and the first JTAG-bus conversion unit each include a set of JTAG ports, the JTAG signal switching unit includes two sets of JTAG ports, and the first CPU core group includes two sets of JTAG ports. Each set of JTAG ports is used to transmit the mode selection signal, clock signal, data input signal and data output signal in the JTAG signal.

[0053] The two sets of JTAG ports included in the JTAG signal switching unit are respectively designated as the first JTAG port and the second JTAG port, and the two sets of JTAG ports included in the first CPU core group are respectively designated as the third JTAG port and the fourth JTAG port.

[0054] The pins of the first JTAG port used for transmitting the mode selection signal, clock signal, data input signal, and data output signal in the JTAG signal are coupled to the pins of the third JTAG port used for transmitting the mode selection signal, clock signal, data input signal, and data output signal in the JTAG signal, respectively, so that the first JTAG interface can access the first CPU core group in exclusive mode.

[0055] Optionally, the pins in the second JTAG port used for transmitting the mode selection signal and clock signal in the JTAG signals are coupled to the pins in the second CPU core group, the third CPU core group, the first JTAG-bus conversion unit, and the fourth JTAG port used for transmitting the mode selection signal and clock signal in the JTAG signals, respectively. The pins in the second JTAG port used for transmitting the data input signal are coupled to the pins in the fourth JTAG port used for transmitting the data input signal. The pins in the second JTAG port used for transmitting the data output signal are coupled to the pins in the first JTAG-bus conversion unit used for transmitting the data output signal, so that the first JTAG interface can access the first CPU core group, the second CPU core group, the third CPU core group, and the first JTAG-bus conversion unit in a chained mode.

[0056] Optionally, the first CPU core group is coupled to the at least one hardware resource via a second bus;

[0057] The second bus is a bus with a faster information transmission rate than the first bus.

[0058] Secondly, embodiments of this application provide an electronic device, including a chip provided in any embodiment of this application.

[0059] The chip provided in this application embodiment includes: a first JTAG interface, a first CPU core group, and a JTAG-bus conversion unit; the first JTAG interface, the first CPU core group, and the JTAG-bus conversion unit form a first JTAG chain; on the first JTAG chain, the first JTAG interface is coupled to the first CPU core group, the first CPU core group is coupled to the JTAG-bus conversion unit, and the JTAG-bus conversion unit is coupled to the first JTAG interface; the JTAG-bus conversion unit also couples to at least one hardware resource within the chip, the at least one hardware resource not linked to the first JTAG chain, and the hardware resource being a hardware resource within the chip that needs to be accessed by the first JTAG interface. The first JTAG interface accesses the first CPU core group and the JTAG-bus conversion unit in a chained manner. When the first JTAG interface accesses the first CPU core group and the JTAG-bus conversion unit, because other hardware resources are not linked to the first JTAG chain, the length of the first JTAG chain is relatively short, allowing the debugger coupled to the first JTAG interface to access the first CPU core group and the JTAG-bus conversion unit at a relatively fast speed. When accessing other hardware resources through the first JTAG interface, since the hardware resource is not linked to the first JTAG chain, data does not need to be relayed through other hardware resources, making it faster than accessing via the first JTAG chain. Compared to existing schemes that chain all hardware resources together, this also shortens the length of the first JTAG chain, thereby reducing access latency. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0061] Figure 1A A block diagram of a solid-state storage device is shown.

[0062] Figure 1B A schematic diagram of the control components of the storage device is shown.

[0063] Figure 1C A detailed block diagram of the control components is shown;

[0064] Figure 2 A schematic diagram of the structure of a control component according to an embodiment of this application is shown;

[0065] Figure 3 A schematic diagram of the structure of a control component provided in another embodiment of this application is shown;

[0066] Figure 4 A schematic diagram of the structure of a control component provided in another embodiment of this application is shown;

[0067] Figure 5 A schematic diagram of the structure of a control component provided in another embodiment of this application is shown;

[0068] Figure 6 This paper shows a schematic diagram of the JTAG circuit connection of the control component provided in an embodiment of this application;

[0069] Figure 7 A schematic diagram of the structure of a control component provided in yet another embodiment of this application is shown;

[0070] Figure 8A , Figure 8B , Figure 8C , Figure 8D The methods for coupling the same bus from a device to two independent low-speed buses are shown respectively;

[0071] Figure 9A , Figure 9B Each of the following diagrams shows a structural schematic of a slave device bus multiplexer. Detailed Implementation

[0072] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0073] Figure 2 A schematic diagram of the structure of a control component according to an embodiment of this application is shown.

[0074] like Figure 2 As shown, the control components include: a PCIe interface ( Figure 2 (Not shown), host command processing unit, media interface controller, CPU core group 1, hardware accelerator, two JTAG interfaces (denoted as JTAG interface 1 and JTAG interface 2 respectively), JTAG-bus conversion unit, multiplexer, PICe PHY, DDR PHY, ONFIPHY, and cross-chip interface unit PHY. The PICe PHY, DDR PHY, ONFIPHY, and cross-chip interface unit PHY are the physical layer modules of the PICe interface, DDR controller, media interface controller, and cross-chip interface unit, respectively. For ease of understanding, they are drawn independently and not within their respective hardware units. Optionally, there may be one or more hardware accelerators.

[0075] The host command processing unit, media interface controller, CPU core group 1, PICe interface, DDR controller, and media interface controller in this embodiment are related to... Figure 1C The embodiments shown are the same, and will not be repeated here to avoid repetition. The cross-chip interface unit can be found in Chinese patents 2023112407535 / 2023112408006 / 2023112408218, which provide chip-to-chip interconnection technology. Compared to... Figure 1C In this embodiment, the control components include JTAG interface 1, JTAG interface 2, JTAG-bus conversion unit, and multiplexer.

[0076] like Figure 2 As shown, JTAG interface 1, CPU core group 1, CPU core group 2, CPU core group 0, and JTAG-bus conversion unit form a JTAG chain ( Figure 2 (Represented by red dashed lines). For example, in a JTAG chain, JTAG interface 1 is coupled to CPU core group 1, CPU core group 1 is coupled to CPU core group 2, CPU core group 0 is coupled to CPU core group 2, the JTAG-bus translation unit is coupled to CPU core group 0, and the JTAG-bus translation unit is coupled to JTAG interface 1. JTAG interface 1 accesses CPU core group 1, CPU core group 2, CPU core group 0, and the JTAG-bus translation unit in a JTAG chain manner. On the JTAG chain formed by JTAG interface 1, CPU core group 0, CPU core group 1, CPU core group 2, and the JTAG-bus translation unit, the method of accessing CPU core group 0, CPU core group 1, and CPU core group 2 through JTAG interface 1 is the same as the method of accessing via the JTAG protocol in prior art. For example, when accessing CPU core group 1 through JTAG interface 1, the command to access CPU core group 1 is passed from JTAG interface 1 to CPU core group 1. The result of accessing CPU core group 1 is passed sequentially through the JTAG chain to CPU core group 2, CPU core group 0 and JTAG-bus translation unit, and then passed to JTAG interface 1 by the JTAG-bus translation unit.

[0077] like Figure 2 As shown, the JTAG-bus conversion unit is also connected to a low-speed bus ( Figure 2 (Represented by the green dashed line in the middle), and coupled via a low-speed bus to hardware resources that need to be accessed by JTAG interface 1, such as the NVMe protocol processor, LUN controller group, and hardware accelerator. The JTAG-bus translation unit, NVMe protocol processor, LUN controller group, and hardware accelerator occupy different address spaces on the low-speed bus.

[0078] When accessing hardware resources (NVMe protocol processors, LUN controller groups, hardware accelerators) coupled to the low-speed bus via JTAG interface 1, the JTAG-bus translation unit assists in the process. The JTAG-bus translation unit, in response to recognizing that the accessed hardware resource is coupled to the low-speed bus, accesses the hardware resource in a manner similar to accessing a device on the low-speed bus. Based on the address of the accessed hardware resource on the low-speed bus, the JTAG-bus translation unit generates an access request for that hardware resource and sends it to the hardware resource via the low-speed bus. The accessed hardware resource provides an access result on the low-speed bus. The JTAG-bus translation unit retrieves this access result from the low-speed bus and then provides it to JTAG interface 1 via the JTAG chain. Therefore, from the perspective of JTAG interface 1, it appears to be accessing hardware resources linked in the JTAG chain, allowing debugger 1 to access hardware resources coupled to the low-speed bus according to the existing JTAG protocol without requiring any modifications.

[0079] For example, when accessing the hardware resources of an NVMe protocol processor from JTAG interface 1, the command to access the NVMe protocol processor (denoted as command 1) is sequentially passed from JTAG interface 1 to CPU core group 1, CPU core group 2, CPU core group 0, and the JTAG-bus translation unit. The JTAG-bus translation unit recognizes that the hardware resource accessed by command 1 is an NVMe protocol processor coupled to a low-speed bus. Based on the address of the NVMe protocol processor on the low-speed bus, it generates an access request and sends this request to the NVMe protocol processor via the low-speed bus to access its hardware resources. The access result for the NVMe protocol processor is sent to the JTAG-bus translation unit via the low-speed bus. The JTAG-bus translation unit then passes the access result back to JTAG interface 1 via the JTAG chain. For debugger 1, the NVMe protocol processor accessed through JTAG interface 1 is connected to the JTAG chain and can be accessed according to the existing JTAG protocol.

[0080] In this embodiment, when accessing CPU core group 0, CPU core group 1, or CPU core group 2 through JTAG interface 1, the JTAG chain is relatively short because hardware resources such as the NVMe protocol processor are not linked to the JTAG chain. This allows debugger 1 to access CPU core group 0, CPU core group 1, or CPU core group 2 at a faster speed through JTAG interface 1. The hardware resources connected to the low-speed bus do not physically form a chain. The low-speed bus connects each hardware resource individually; when accessing a hardware resource through the low-speed bus, data does not need to be relayed through other hardware resources, making it faster than accessing via a JTAG chain. While the JTAG chain is relatively long when accessing hardware resources coupled to the low-speed bus through JTAG interface 1, it is still shorter than the prior art scheme that chains all hardware resources, thus reducing access latency. Furthermore, the hardware resources coupled to the low-speed bus do not need to provide circuitry for implementing JTAG functionality, reducing the complexity of the control chip.

[0081] Optionally, JTAG interface 1 may exclusively use, for example, four pins of the control unit to connect to the four signal lines (TMS, TCK, TDI, TDO) required by the JTAG protocol.

[0082] like Figure 2 As shown, JTAG interface 2 is used to connect debugger 2. JTAG interface 2 is connected to PICe PHY, DDR PHY, ONFIPHY and cross-chip interface unit PHY via a multiplexer. Figure 2 (Represented by a purple dashed line).

[0083] The multiplexer receives selection signal 1 and connects the hardware unit indicated by selection signal 1 to JTAG interface 2. For example, the multiplexer receives an access request from debugger 2 from JTAG interface 2 and, according to selection signal 1, passes the access request to one of the PICe PHY, DDR PHY, ONFIPHY, or cross-chip interface unit PHY. JTAG interface 2 forms direct connections with PICePHY, DDR PHY, ONFIPHY, and cross-chip interface unit PHY through the multiplexer, eliminating the need to form a JTAG chain for these hardware resources. Therefore, when accessing these hardware resources through JTAG interface 2, data does not need to be transferred between all hardware resources, reducing the length of the JTAG chain, shortening the time required to access hardware resources through JTAG interface 2, and without significantly increasing the hardware resources required to implement JTAG functionality. It is worth noting that... Figure 2 The schematic illustration shows hardware units accessible via JTAG interface 2, including DDR PHY, PCIe PHY, ONFIPHY, and cross-chip interface unit PHY. In other alternative embodiments, more or fewer hardware units may be accessible via JTAG interface 2.

[0084] Optionally, JTAG interface 2 includes four pins for connecting the four signal lines (TMS, TCK, TDI, TDO) required by the JTAG protocol. The DDR PHY, PCIe PHY, ONFI PHY, and cross-chip interface unit PHY are all connected to these four pins via a multiplexer. These four pins are shared in a time-sharing manner to prevent different hardware units from being connected to them simultaneously. The multiplexer connects the hardware unit indicated by selection signal 1 to the four pins of JTAG interface 2 according to selection signal 1.

[0085] Optionally, JTAG interface 2 shares four pins with GPIO (General Purpose Input / Output). During the development and debugging phase of the control unit, JTAG interface 2 is enabled. These four pins connect to the four signal lines required by the JTAG protocol (TMS, TCK, TDI, TDO). Sensitive hardware resources, such as PICe PHY, DDR PHY, ONFIPHY, and cross-chip interface unit PHY, are debugged through JTAG interface 2. After development and debugging are completed, JTAG interface 2 is disabled, and the four pins used by JTAG interface 2 are configured as GPIOs for user use. This prevents users from accidentally malfunctioning the control unit due to misoperation of sensitive hardware resources through JTAG interface 2. Optionally, select signal 1 can indicate the hardware unit connected to JTAG interface 2, or it can indicate that the four pins of JTAG interface 2 are used as GPIOs.

[0086] Alternatively, JTAG interface 2 can exclusively use 4 pins of the control component. These 4 pins are enabled during the development and debugging phase of the control component to enable JTAG interface 2. After the development and debugging are completed, these 4 pins are disabled.

[0087] like Figure 2 As shown, CPU core group 0, CPU core group 1, CPU core group 2, NVMe protocol processor, LUN controller group, and one or more hardware accelerators are interconnected via a high-speed bus. The low-speed bus provided in this embodiment differs from the high-speed bus. In some cases of using storage devices, one or more hardware resources within the control unit may fail. The failed component may occupy the high-speed bus for an extended period, preventing the high-speed bus from processing other bus transactions. Additionally, the high-speed bus itself may also fail. This embodiment provides a low-speed bus, different from the high-speed bus, connecting the JTAG-bus conversion unit to the required hardware resources. This provides a reliable path for accessing hardware resources when the control unit fails. Even if the high-speed bus fails, these hardware resources can still be accessed through JTAG interface 1 and the low-speed bus.

[0088] Optionally, in this embodiment of the application, hardware resources such as CPU core group 0, CPU core group 1, CPU core group 2, NVMe protocol processor, LUN controller group, and one or more hardware accelerators accessed through JTAG interface 1, and hardware resources such as PICe PHY, DDR PHY, ONFIPHY, and cross-chip interface unit PHY accessed through JTAG interface 2, are registers. JTAG interface 1 and JTAG interface 2 can work simultaneously and access hardware resources on different JTAG chains respectively.

[0089] In an optional embodiment, the multiplexer coupled to JTAG interface 2 can be connected to the DDR PHY, PCIe PHY, ONFIPHY, and cross-chip interface unit PHY via multiple JTAG-bus conversion units. The path between the multiplexer and the multiple JTAG-bus conversion units is a JTAG chain, and the multiple JTAG-bus units are connected via low-speed buses (different from the JTAG bus conversion units). Figure 2 The low-speed bus (indicated by the green line) is coupled to each hardware unit.

[0090] Figure 3 A schematic diagram of the structure of a control component provided in another embodiment of this application is shown. For example... Figure 3 As shown, different from Figure 2 The control components shown Figure 3 In the control unit shown, the multiplexer is connected to the DDR PHY, PCIe PHY, ONFIPHY, and cross-chip interface unit PHY via JTAG-bus conversion units 2-1, 2-2, 2-3, and 2-4, respectively. The paths between the multiplexer and JTAG-bus conversion units 2-1, 2-2, 2-3, and 2-4 are all JTAG chains (e.g., ...). Figure 3 (As shown by the purple dashed line in the middle). JTAG-bus conversion unit 2-1 is coupled to the DDR PHY via a low-speed bus (e.g., Figure 3 (As shown by the green dashed line in the middle), the JTAG-bus conversion unit 2-2 is coupled to the PCIe PHY via a low-speed bus (such as...). Figure 3 (As shown by the green dashed line in the middle), JTAG-bus conversion unit 2-3 is coupled to ONFI PHY via a low-speed bus (such as...). Figure 3 (As shown by the green dashed line in the middle), the TAG-bus conversion unit 2-4 is coupled to the cross-chip interface unit PHY via a low-speed bus (e.g., Figure 3 (As shown by the green dashed line).

[0091] Optionally, the paths between the multiplexer and the DDR PHY, PCIe PHY, ONFIPHY, and cross-chip interface unit PHY can be different. For example, the multiplexer can be connected to the DDR PHY and PCIe PHY (see reference) via JTAG-bus conversion unit 2-1 and JTAG-bus conversion unit 2-2. Figure 3 It connects directly to the ONFIPHY and the cross-chip interface unit PHY via the JTAG chain (see reference). Figure 2 ).

[0092] Figure 4 A schematic diagram of the structure of a control component provided in another embodiment of this application is shown. For example... Figure 4 As shown, the control components include: a PCIe interface ( Figure 2 (Not shown), host command processing unit, media interface controller, CPU core group 1, hardware accelerator, two JTAG interfaces (referred to as JTAG interface 1 and JTAG interface 2 respectively), JTAG bridge, multiplexer 1, multiplexer 2, PICePHY, DDR PHY, ONFIPHY and cross-chip interface unit PHY. Figure 4 The multiplexer 1, PICe PHY, DDR PHY, ONFIPHY, and cross-chip interface unit PHY shown are... Figure 2 The embodiments shown are the same, and will not be repeated here to avoid repetition.

[0093] CPU core group 1, CPU core group 2, CPU core group 0 form a JTAG chain with the JTAG bridge (e.g., Figure 4 (As shown by the red dashed line in the middle). JTAG interface 1 accesses CPU core group 1, CPU core group 2, CPU core group 0, and the JTAG bridge via a JTAG chain. The JTAG bridge is also coupled to the NVMe protocol processor, LUN controller group, and hardware accelerator (e.g., through multiplexer 2) via multiplexer 2. Figure 4 (As shown by the green dashed line). Multiplexer 2 transmits the JTAG signal from the JTAG bridge to one of the NVMe protocol processor, LUN controller group, or hardware accelerator, and sends the access result back to the JTAG bridge, which then transmits it to JTAG interface 1 via a JTAG chain. For example, based on the access request received from the JTAG chain, the JTAG bridge identifies the hardware unit to be accessed coupled to multiplexer 2 (the hardware unit to be accessed is one of the NVMe protocol processor, LUN controller group, or hardware accelerator) and generates a corresponding selection signal 2. Multiplexer 2 then transmits the access request to the hardware unit to be accessed based on the selection signal 2.

[0094] When debugger 1 accesses, for example, a hardware accelerator through JTAG interface 1, the access request is sequentially passed from JTAG interface 1 to CPU core group 1, CPU core group 2, CPU core group 0, JTAG bridge, and hardware accelerator. The access result is sequentially passed from the hardware accelerator to multiplexer 2, JTAG bridge, and JTAG interface 1. When debugger 1 accesses the hardware accelerator through JTAG interface 1, the path from multiplexer 2 to the hardware accelerator forms part of the JTAG chain, and the path from the hardware accelerator to multiplexer 2 forms another part of the JTAG chain. Similarly, when debugger 1 accesses the NVMe protocol processor through JTAG interface 1, the path from multiplexer 2 to the NVMe protocol processor and the path from the NVMe protocol processor back to multiplexer 2 also become part of the JTAG chain. When debugger 1 accesses the LUN controller group through JTAG interface 1, the path from multiplexer 2 to the LUN controller group and the path from the LUN controller group back to multiplexer 2 also become part of the JTAG chain. Thus, multiplexer 2 and each accessed hardware resource form multiple JTAG chains. Multiplexer 2 can determine, based on selection signal 2, to connect a certain JTAG chain to the JTAG chain formed by JTAG interface 1, CPU core group 1, CPU core group 2, CPU core group 0 and JTAG-bus conversion unit.

[0095] In this embodiment, the hardware resources connected to the multiplexer 2 form a JTAG chain at different times. When accessing one of the hardware resources through the multiplexer 2, the data does not need to be relayed through other hardware resources connected to the multiplexer 2. Compared with the prior art scheme of chaining all hardware resources, the length of the JTAG chain is shortened, thereby reducing the access latency.

[0096] During the research and development and use of the control component, it was found that most of the control component's software runs on CPU core group 1. In the development and debugging of the control component, the situation with the highest demand for JTAG performance (the situation requiring the most JTAG usage) occurs when debugging the software of CPU core group 1. In order to further improve the chip development efficiency, it is necessary to further reduce the latency of accessing the hardware resources of CPU core group 1 using JTAG.

[0097] Figure 5 A schematic diagram of the structure of a control component provided in another embodiment of this application is shown.

[0098] like Figure 5 As shown, in Figure 2Based on the control components shown, the control components provided in this embodiment further include a JTAG signal switching unit. The JTAG signal switching unit is coupled to both the JTAG interface 1 and the CPU core group 1. The JTAG signal switching unit is used to switch the operating mode of accessing the CPU core group 1 through the JTAG interface 1, for example, switching the operating mode of accessing the CPU core group 1 through the JTAG interface 1 from the serial mode to the exclusive mode, or switching the operating mode of accessing the CPU core group 1 through the JTAG interface 1 from the exclusive mode to the serial mode.

[0099] When accessing CPU core group 1 via JTAG interface 1 in chained mode, JTAG interface 1, JTAG signal switching unit, CPU core group 1, CPU core group 2, CPU core group 0, and JTAG-bus conversion unit form a JTAG chain. JTAG interface 1 accesses CPU core group 1, CPU core group 2, CPU core group 0, and JTAG-bus conversion unit via this JTAG chain. Accessing CPU core group 0, CPU core group 1, and CPU core group 2 via JTAG interface 1 within this JTAG chain is the same as accessing it via the JTAG protocol in prior art. For example, when accessing CPU core group 2 via JTAG interface 1, the command to access CPU core group 2 is sequentially passed from JTAG interface 1 to JTAG signal switching unit, CPU core group 1, and CPU core group 2. The result of accessing CPU core group 2 is passed sequentially through the JTAG chain to CPU core group 0 and the JTAG-bus translation unit, which then passes it to JTAG interface 1.

[0100] When accessing CPU core group 1 via JTAG interface 1 in exclusive mode, JTAG interface 1, JTAG signal switching unit, and CPU core group 1 form a JTAG chain. This JTAG chain does not include CPU core group 0, CPU core group 2, or other components. Only CPU core group 1 can be accessed through JTAG interface 1; CPU core group 2, CPU core group 0, and the JTAG-bus conversion unit cannot be accessed. Because the JTAG chain only includes CPU core group 1, the JTAG chain is shortened to the minimum, allowing JTAG interface 1 to access CPU core group 1 with optimal performance. Furthermore, in exclusive mode, CPU core group 1 does not need to process JTAG commands to access other hardware units, simplifying the circuit implementation of the JTAG chain and contributing to improved performance.

[0101] The JTAG interface communicates with external test equipment (such as debugger 1) through a standardized set of pins, such as TMS (mode select), TCK (clock), TDI (data input), and TDO (data output). Optionally, common JTAG interfaces may also include pins for power and ground. A simplified JTAG interface requires only two pins, TDI and TDO. The following example, using a JTAG interface including TMS, TCK, TDI, and TDO, illustrates the connection method of the JTAG circuit in this embodiment.

[0102] Figure 6 A schematic diagram of the JTAG circuit connection of the control component provided in an embodiment of this application is shown.

[0103] like Figure 6 As shown, JTAG interface 1 is connected to the JTAG signal switching unit through 4 pins, which are respectively used as TMS pin, TCK pin, TDI pin and TDO pin.

[0104] Figure 6 The diagram shows two CPU core groups 1, representing the same CPU core group 1, but connected to the JTAG signal switching unit via different JTAG circuits to support JTAG interface 1 accessing CPU core group 1 in either chained or exclusive mode. It is important to understand that these two different JTAG circuits are hardware circuits that coexist within the control unit.

[0105] The JTAG signal switching unit includes two sets of JTAG ports.

[0106] For the first group of JTAG ports, the TMS, TCK, TDI, and TDO of the JTAG signal switching unit are respectively connected to CPU core group 1 ( Figure 6 The TMS, TCK, TDI, and TDO of CPU core group 1 are connected within the dashed box. The paths between the TDI of the JTAG signal switching unit and the TDI of CPU core group 1, and between the TDO of the JTAG signal switching unit and the TDO of CPU core group 1, form a JTAG chain. Under this connection method, the operating mode of JTAG interface 1 accessing CPU core group 1 is exclusive mode.

[0107] For the second group of JTAG ports, the TMS and TCK of the JTAG signal switching unit are simultaneously connected to the TMS and TCK of CPU core group 1, CPU core group 2, CPU core group 0, and the JTAG-bus conversion unit. The TDI of the JTAG signal switching unit is connected to the TDI of CPU core group 1, the TDO of CPU core group 1 is connected to the TDI of CPU core group 2, the TDO of CPU core group 2 is connected to the TDI of CPU core group 0, and the TDO of CPU core group 0 is connected to the TDO of the JTAG-bus conversion unit, thus forming another JTAG chain. In this connection mode, CPU core group 1 operates in chained mode.

[0108] Registers are widely used in integrated circuit chips. Besides storing data, each circuit unit uses numerous registers as interfaces for interacting with other circuits, transmitting the internal state of the circuit (referred to as status registers), and controlling the circuit's operation and processes (referred to as control registers). For ease of design and use, multiple registers are organized into a register file (called RegFile), and the RegFile can be coupled to a bus so that external circuits can access it via the bus. RegFile is also a hardware resource that needs to be accessed through the JTAG interface; accessing RegFile through the JTAG interface allows observation of the internal state of the circuit. When the number of registers in a RegFile is large, accessing RegFile via JTAG requires chaining the registers together in a JTAG chain, making the JTAG chain very long. This not only increases the complexity of the JTAG circuit but also severely affects the operating speed of the JTAG chain, and may even affect the overall maximum operating speed of the chip.

[0109] Figure 7 A schematic diagram of the structure of a control component provided in yet another embodiment of this application is shown. Figure 7 The host command processing unit, media interface controller, CPU core group 1, hardware accelerator, JTAG interface 1, JTAG interface 2, JTAG-bus conversion unit, multiplexer, PICe PHY, DDR PHY, ONFIPHY and cross-chip interface unit PHY shown are... Figure 2 The embodiments shown are the same and will not be described again here.

[0110] like Figure 7As shown, the hardware resources of the NVMe protocol processor, LUN controller, and hardware accelerator include register files. These register files are coupled to CPU core group 1 via low-speed bus 2. CPU core group 1 accesses each register file through low-speed bus 2, thereby controlling the NVMe protocol processor, LUN controller, and hardware accelerator to which each register file belongs. For example, CPU core group 1 provides configuration information and controls resets for the NVMe protocol processor, LUN controller, and hardware accelerator via low-speed bus 2. To be coupled to low-speed bus 2, each register file in the NVMe protocol processor, LUN controller, and hardware accelerator has a low-speed bus interface capable of processing bus protocols, receiving accesses to registers in the register file from the low-speed bus, and providing access results.

[0111] The register files in the NVMe protocol processor, LUN controller, and hardware accelerator are coupled to the JTAG-bus conversion unit via low-speed bus 1. The hardware resources of the NVMe protocol processor, LUN controller, and hardware accelerator accessed through JTAG interface 1 are the register files.

[0112] Optionally, low-speed bus 1 and low-speed bus 2 share the same bus protocol. JTAG interface 1 accesses the register files of the NVMe protocol processor, LUN controller, and hardware accelerator via low-speed bus 1, also through the respective low-speed bus interfaces of the NVMe protocol processor, LUN controller, and hardware accelerator. Therefore, each register file does not require separate circuitry for processing the JTAG protocol, nor does it require connecting the registers of the register files to the JTAG chain. Low-speed bus 1 and low-speed bus 2 are independent of each other. Even if low-speed bus 2 fails, it does not affect JTAG interface 1's access to the register files in the NVMe protocol processor, LUN controller, and hardware accelerator via low-speed bus 1.

[0113] Optionally, the register files in the NVMe protocol processor, LUN controller, and hardware accelerator prioritize responding to accesses from low-speed bus 1, so that even if low-speed bus 2 continues to generate access requests to each register file due to a fault, each register file can still be accessed through JTAG interface 1 and the low-speed bus.

[0114] exist Figure 7 In this context, the JTAG-bus translation unit can access the low-speed bus interface of the NVMe protocol processor, LUN controller, and hardware accelerator register files via low-speed bus 1. CPU core group 1 can also access the low-speed bus interface of the NVMe protocol processor, LUN controller, and hardware accelerator register files via low-speed bus 2. Figure 7In this context, different bus master devices need to access the same bus slave devices through multiple independent low-speed buses.

[0115] Figure 8A This demonstrates a method of coupling the same bus from a device to two independent low-speed buses.

[0116] like Figure 8A As shown, JTAG interface 1 accesses low-speed bus 1 through a JTAG-bus conversion unit. The JTAG-bus conversion unit acts as the master device on low-speed bus 1, where only slave device 1 is coupled. The CPU is the master device on low-speed bus 2, which is coupled to slave devices 1, 2, 3, and 4. Slave device 1 is coupled to low-speed bus 2 via a slave device bus multiplexer. Slave devices 1, 2, 3, and 4 are coupled to low-speed bus 2 via a bus decoder. Slave device 1 is, for example, a... Figure 7 The register file shown is located in the NVMe protocol processor, LUN controller, or hardware accelerator.

[0117] The address space of low-speed bus 1 is independent of the address space of low-speed bus 2. Slave device 1 occupies a portion of the address space on low-speed bus 1. Slave device 1, slave device 2, slave device 3, and slave device 4 each occupy a portion of the address space on low-speed bus 2. The address of slave device 1 on low-speed bus 1 can be the same as or different from the address of slave device 1 on low-speed bus 2.

[0118] The CPU sends a bus access request on low-speed bus 2, which carries an address. The bus decoder generates a selection signal for a slave device based on the address carried in the bus access request. The selected slave device responds to the bus access request, while the unselected slave device does not respond to the access request.

[0119] The slave bus multiplexer is used to select which low-speed bus 1 or low-speed bus 2 should be connected to slave device 1 at different times. Taking the example where low-speed bus 1 has higher priority than low-speed bus 2: When there is a bus access request on low-speed bus 1, the slave bus multiplexer connects low-speed bus 1 to slave device 1 and disconnects low-speed bus 2 from slave device 1. When there is a bus access request on low-speed bus 2 but no access request on low-speed bus 1, the slave bus multiplexer connects low-speed bus 2 to slave device 1. When there are bus access requests on both low-speed bus 1 and low-speed bus 2, the slave bus multiplexer connects low-speed bus 1 to slave device 1 and disconnects low-speed bus 2 from slave device 1. Slave device 1 operates in a manner conforming to the low-speed bus protocol without being aware of the slave bus multiplexer's presence.

[0120] Optionally, the slave bus multiplexer identifies whether a bus access request exists on low-speed bus 2 based on the selection signal for slave device 1 from the bus decoder. Thus, when the CPU accesses, for example, slave device 3 via low-speed bus 2, the slave bus multiplexer assumes there is no access request on low-speed bus 2. In other words, the slave bus multiplexer is only used to select whether to connect low-speed bus 1 or low-speed bus 2 to slave device 1 at different times, without providing a path between low-speed bus 1 and slave devices 2-4.

[0121] Figure 8B This demonstrates another way to couple the same bus from a device to two independent low-speed buses.

[0122] like Figure 8B As shown, JTAG interface 1 accesses low-speed bus 1 through a JTAG-bus conversion unit. The JTAG-bus conversion unit acts as the master device on low-speed bus 1, and slave device 1 and slave device 5 are coupled to low-speed bus 1. Slave device 1 and slave device 5 are, for example, Figure 7 The register file shown is located in the NVMe protocol processor, LUN controller, or hardware accelerator. The CPU is the master device on low-speed bus 2, which is coupled to slave devices 5, 2, 3, and 4. Slave device 1 is coupled to low-speed bus 2 via slave bus multiplexer 1. Slave device 5 is coupled to low-speed bus 2 via slave bus multiplexer 2. Slave devices 1 and 5 are coupled to low-speed bus 1 via bus decoder 1. Slave devices 2, 3, and 4 are coupled to low-speed bus 2 via bus decoder 2.

[0123] The address space of low-speed bus 1 is independent of the address space of low-speed bus 2. Slave device 1 and slave device 5 each occupy a portion of the address space on low-speed bus 1. Slave device 5, slave device 2, slave device 3, and slave device 4 each occupy a portion of the address space on low-speed bus 2. The address of slave device 1 on low-speed bus 1 can be the same as or different from the address of slave device 1 on low-speed bus 2.

[0124] The CPU sends a bus access request on low-speed bus 2, which carries an address. Bus decoder 2 generates a selection signal for a slave device based on the address carried in the bus access request. The selected slave device responds to the bus access request, while the unselected slave device does not respond to the access request.

[0125] Slave bus multiplexer 1 is used to select which low-speed bus 1 or low-speed bus 2 is connected to slave device 1 at different times. This is illustrated by the example where low-speed bus 1 has a higher priority than low-speed bus 2. For instance, when there is a bus access request on low-speed bus 1, slave bus multiplexer 1 connects low-speed bus 1 to slave device 1 and disconnects low-speed bus 2 from slave device 1. When there is a bus access request on low-speed bus 2 but no access request on low-speed bus 1, slave bus multiplexer 1 connects low-speed bus 2 to slave device 1. When there are bus access requests on both low-speed bus 1 and low-speed bus 2, slave bus multiplexer 1 connects low-speed bus 1 to slave device 1 and disconnects low-speed bus 2 from slave device 1. Slave device 1 operates in a manner conforming to the low-speed bus protocol without being aware of the existence of slave bus multiplexer 1.

[0126] Slave bus multiplexer 2 is used to select which low-speed bus 1 or low-speed bus 2 should be connected to slave device 5 at different times. This is illustrated by the example where low-speed bus 1 has a higher priority than low-speed bus 2. For instance, when there is a bus access request on low-speed bus 2, slave bus multiplexer 2 connects low-speed bus 1 to slave device 5 and disconnects low-speed bus 2 from slave device 5. When there is a bus access request on low-speed bus 2 but no access request on low-speed bus 1, slave bus multiplexer 2 connects low-speed bus 2 to slave device 5. When there are bus access requests on both low-speed bus 1 and low-speed bus 2, slave bus multiplexer 2 connects low-speed bus 1 to slave device 5 and disconnects low-speed bus 2 from slave device 5. Slave device 5 operates in a manner conforming to the low-speed bus protocol without being aware of the presence of slave bus multiplexer 2.

[0127] Optionally, the slave device bus multiplexer 1 identifies whether there is a bus access request on the low-speed bus 2 based on the selection signal of the slave device 1 by the bus decoder 1, and the slave device bus multiplexer 2 identifies whether there is a bus access request on the low-speed bus 2 based on the selection signal of the slave device 5 by the bus decoder 2.

[0128] Figure 8C This demonstrates yet another way to couple the same bus from a device to two independent, low-speed buses. Figure 8B On this basis, Figure 8C The illustrated embodiment also includes a low-speed bus 3, a JTAG-bus conversion unit 2, and a slave device bus multiplexer 3. The JTAG interface 2 accesses the low-speed bus 3 through the JTAG-bus conversion unit 2. The JTAG-bus conversion unit 2 acts as the master device on the low-speed bus 3, and a slave device 1 is coupled to the low-speed bus 3.

[0129] Slave bus multiplexer 3 is coupled to slave bus multiplexer 1 and bus decoder 1. Slave bus multiplexer 3 is used to select whether to connect low-speed bus 3 or low-speed bus 1 to slave bus multiplexer 1 at different times.

[0130] Slave bus multiplexer 1 is coupled to slave bus multiplexer 3 and bus decoder 2. Slave bus multiplexer 1 is used to select one of the low-speed bus and low-speed bus 2 selected by slave bus multiplexer 3 to be connected to slave device 1 at different times.

[0131] The slave device bus multiplexer 2 is coupled to bus decoder 1 and bus decoder 2. The slave device bus multiplexer 2 is used to select one of the low-speed buses 1 and 2 coupled to bus decoder 1 at different times to be connected to the slave device 5.

[0132] like Figure 8C As shown, embodiments of this application connect multiple low-speed buses to the same slave device through cascaded slave bus multiplexers. The slave bus multiplexers can provide priority. For example, slave bus multiplexer 3 preferentially connects low-speed bus 2 (rather than low-speed bus 1) to slave bus multiplexer 1. Meanwhile, slave bus multiplexer 1 preferentially connects the selection result of slave bus multiplexer 3, rather than low-speed bus 2, to slave device 1.

[0133] exist Figure 8C In this embodiment, JTAG interface 2 can only access slave device 1 and not other slave devices, thus providing security. JTAG interface 1 can access slave device 1 and slave device 5, but not slave devices 2-4. The CPU can access slave devices 1-5 via low-speed bus 2.

[0134] Optionally, during the development and debugging phase of the control components, slave device 1 can be accessed via JTAG interface 2. Before delivery to the customer, slave device bus multiplexer 3 can be configured via JTAG interface 2 to allow it to selectively connect low-speed bus 1 to slave device bus multiplexer 1. Additionally, JTAG interface 2 can be configured as GPIO, thereby preventing access to slave device 1 via JTAG interface 2, while allowing access to slave device 1 via JTAG interface 1.

[0135] Figure 8D This demonstrates yet another way to couple the same bus from a device to two independent, low-speed buses. Figure 8C On this basis, Figure 8D The illustrated embodiment also includes a switch for connecting the low-speed bus 1 and the slave bus multiplexer 3.

[0136] When JTAG interface 2 is operational (e.g., during the development and debugging phase of control components), the switch is disconnected via JTAG interface 2. Alternatively, the switch's default state is off. When the switch is off, slave device 1 cannot be accessed via JTAG interface 1; access to slave device 1 is made via JTAG interface 2, thus ensuring security.

[0137] After JTAG interface 2 has finished operating, close the switch via JTAG interface 2. Also, configure JTAG interface 2 as a GPIO to prevent access to slave device 1 via JTAG interface 2, while allowing access to slave device 1 via JTAG interface 1. Alternatively, for safety reasons, the switch can be kept in the open state.

[0138] exist Figures 8A-8D The diagram illustrates various methods for different bus masters to access the same bus slave device via multiple independent low-speed buses using a slave device multiplexer. Optionally, Figures 8A-8D Low-speed bus 1 and low-speed bus 2 in the configuration are both APB buses. The APB (Advanced Peripheral Bus) is a bus for low-power peripherals, suitable for low-bandwidth peripherals that do not require high-performance pipelines. The APB bus interface includes the following signals: PENABLE (enable signal), PWRITE (transfer direction, 1-write, 0-read), PWDATA (write data bus), PADDR (address bus), PSEL (peripheral select signal), PREADY (ready signal), and PRDATA (read data signal). The APB bus supports multiple master devices accessing multiple slave devices on a single APB bus.

[0139] Therefore, embodiments of this application require that the same slave device be accessed by master devices on different APB buses on two or more APB buses, and that the slave device has a single APB bus interface.

[0140] Figure 9A A schematic diagram of a device bus multiplexer is shown.

[0141] like Figure 9A As shown, the slave bus multiplexer includes three APB bus interfaces (denoted as APB interface 1, APB interface 2 and APB interface 3 respectively), an arbitrator, a master-slave multiplexer, and a slave-master multiplexer.

[0142] APB interface 1 connects to APB bus 1, APB interface 2 connects to APB bus 2, and APB interface 3 connects to slave devices shared by APB bus 1 and APB bus 2. The JTAG-bus conversion unit is the master device of APB bus 1, and the CPU is the master device of APB bus 2.

[0143] The arbitrator identifies bus access requests from APB bus 1 and APB bus 2 based on the PSEL signals of APB interface 1 and APB interface 2. A valid PSEL signal indicates that an access request exists on its corresponding APB bus. For example, if the PSEL signal on APB bus 2 is valid and the PSEL signal on APB bus 1 is invalid, it means that an access request exists on APB bus 2 and no access request exists on APB bus 1.

[0144] Optionally, the arbitrator prioritizes responding to access requests from APB bus 1. When the PSEL signal of APB bus 1 is active, the arbitrator processes access requests from APB bus 1 first. Only when the PSEL signal of APB bus 1 is inactive does the arbitrator process access requests from APB bus 2. The arbitration result of the arbitrator is expressed by setting the selection signal (…). Figure 9A (represented by dashed lines) is provided to master-slave multiplexers and slave-master multiplexers.

[0145] The PADDR, PWDATA, PSEL, and PENABLE signals of the APB interface 1 and APB interface 2 of the slave device bus multiplexer are respectively connected to the master-slave multiplexer. The master-slave multiplexer selects one set of signals to be transmitted to APB interface 3 based on the selection signal from the arbitrator, so as to provide it to slave device 1.

[0146] When the arbitrator selects to handle an access request for APB bus 1, the selection signal instructs the master-slave multiplexer to provide the PADDR, PWDATA, PSEL, and PENABLE signals from APB interface 1 corresponding to APB bus 1 to APB interface 3. When the arbitrator selects to handle an access request for APB bus 2, the selection signal instructs the master-slave multiplexer to provide the PADDR, PWDATA, PSEL, and PENABLE signals from APB interface 2 corresponding to APB bus 2 to APB interface 3.

[0147] The slave-master multiplexer connects to the PRDATA and PREADY signals of APB interface 3. Based on the selection signal from the arbitrator, the slave-master multiplexer selects whether to connect the PRDATA and PREADY signals of APB interface 3 to APB interface 1 or APB interface 2 to provide power to APB bus 1 or APB bus 2.

[0148] When the arbitrator selects to handle an access request for APB bus 1, the selection signal instructs the master selector to connect the PRDATA and PREADY signals of APB interface 3 to APB interface 1 of APB bus 1. When the arbitrator selects to handle an access request for APB bus 2, the selection signal instructs the master selector to connect the PRDATA and PREADY signals of APB interface 3 to APB interface 2 of APB bus 2.

[0149] Optionally, when the arbitration of an access request to APB bus 2 fails, the arbitrator generates an invalid PREADY signal and transmits it to the CPU via APB bus 2 to indicate to the CPU that the access request it sent has failed to arbitrate. For example, when the PSEL signals of APB bus 1 and APB bus 2 are both valid, the arbitrator generates an invalid PREADY signal for APB bus 2, so that APB bus 2 knows that the current slave device 1 cannot respond to its bus access request, and postpones the bus access request or waits for the slave device 1 to respond to its bus access request. The arbitrator does not need to generate a PREADY signal for APB bus 1, but instead provides the PREADY signal of APB interface 3 to APB interface 1 connected to APB bus 1 through a slave-master multiplexer. When the arbitrator chooses to process the access request of APB bus 2, it provides the PREADY signal from APB interface 3 to APB interface 2 connected to APB bus 2 through a slave-master multiplexer.

[0150] The master devices on APB bus 1 and APB bus 2 each access the slave devices according to the APB protocol, and the APB slave devices also respond to the bus access requests according to the APB bus protocol. These devices do not need to modify the circuits related to handling the APB bus protocol.

[0151] Figure 9B This diagram illustrates another structural schematic of a device bus multiplexer.

[0152] like Figure 9B As shown, the slave device bus multiplexer includes three APB bus interfaces (denoted as APB interface 1, APB interface 2 and APB interface 3 respectively), an arbitrator, multiplexer 1, and multiplexer 2.

[0153] APB interface 1 connects to APB bus 1, APB interface 2 connects to APB bus 2, and APB interface 3 connects to slave devices shared by APB bus 1 and APB bus 2. The JTAG-bus conversion unit is the master device of APB bus 1, and the CPU is the master device of APB bus 2.

[0154] The arbitrator identifies bus access requests from APB bus 1 and APB bus 2 based on the PSEL signals of APB interface 1 and APB interface 2. A valid PSEL signal indicates that an access request exists on its corresponding APB bus. For example, if the PSEL signal on APB bus 2 is valid and the PSEL signal on APB bus 1 is invalid, it means that an access request exists on APB bus 2 and no access request exists on APB bus 1. When the PSEL signal of either APB interface 1 or APB interface 2 is valid, the arbitrator outputs a valid PSEL signal to the slave device through APB interface 3.

[0155] The arbitration result of the arbitrator is manifested in the control signal ( Figure 9B (represented by dashed lines) is provided to multiplexer 1 and multiplexer 2.

[0156] Multiplexer 1 connects PADDR / PWDATA / PRDATA of APB interface 1 and APB interface 2. Figure 9B (Represented by thick solid green and red lines) and the PENABLE signal. Among them, PADDR / PWDATA / PENABLE are signals generated by the master device of the APB bus and provided to the slave device. Multiplexer 1 provides the PADDR, PWDATA, PRDATA, and PENABLE signals of APB interface 1 or APB interface 2 to APB interface 3 according to the control signal.

[0157] PRDATA is a signal generated by the slave device on the APB bus and provided to the master device. Multiplexer 1 selects, based on the control signal, to provide the PRDATA signal from APB interface 3 to either APB interface 1 or APB interface 2. When only one of APB buses 1 or APB bus 2 has an APB bus request, and only one PSEL signal is valid in either APB interface 1 or APB interface 2, the arbitrator outputs a control signal, controlling multiplexers 1 and 2 to connect the PADDR, PWDATA, PRDATA, and PENABLE signal lines of the APB interface corresponding to the valid PSEL signal to APB interface 3.

[0158] Multiplexer 2 is used to process the PREADY signal. The PREADY signal is generated by the slave device on the APB bus and provided to the master device to inform the master device whether the slave device can currently process the APB bus access request. Multiplexer 2 selects to provide the PREADY signal of APB interface 3 to either APB interface 1 or APB interface 2 based on the control signal.

[0159] The arbitrator also outputs a PREADY signal to APB interface 2.

[0160] When an APB bus request exists on APB bus 1 or APB bus 2, and only one PSEL signal is valid in APB interface 1 or APB interface 2, the arbitrator outputs a control signal to indicate that the PREADY signal of APB interface 3 will be provided to the APB interface corresponding to the valid PSEL signal in the future.

[0161] When both APB bus 1 and APB bus 2 have APB bus requests, and the PSEL signals of both APB interface 1 and APB interface 2 are valid, the slave device bus multiplexer prioritizes processing the access request from APB bus 1. For this purpose, the arbitrator generates an invalid PREADY signal to APB interface 2 connected to APB bus 2 to inform APB bus 2 that its current access request will not be processed temporarily. The arbitrator also generates control signals for multiplexer 1 and multiplexer 2, instructing multiplexer 1 to provide the PADDR / PWDATA / PRDATA and PENABLE signals of APB interface 1 to the slave device, and instructing multiplexer 2 to provide the PREADY signal of APB interface 3 to APB interface 1 connected to APB bus 1. After the access request of APB bus 1 is processed, the PSEL signal of APB bus 1 becomes invalid, and the arbitrator cancels the invalid PREADY signal provided to APB bus 2. If the PSEL signal of APB bus 2 is still valid at this time, the arbitrator controls multiplexer 1 and multiplexer 2 to connect the PADDR / PWDATA / PENALBE and PREADY signal lines of APB interface 2 to APB interface 3 by outputting control signals.

[0162] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A chip, characterized in that, include: The first JTAG interface, the first CPU core group, and the first JTAG-bus conversion unit; The first JTAG interface, the first CPU core group, and the first JTAG-bus conversion unit form the first JTAG chain; On the first JTAG chain, the first JTAG interface is coupled to the first CPU core group, the first CPU core group is coupled to the first JTAG-bus conversion unit, and the first JTAG-bus conversion unit is coupled to the first JTAG interface. The first JTAG-bus conversion unit is also coupled to at least one hardware resource within the chip. The at least one hardware resource is not linked to the first JTAG chain. The hardware resource is a hardware resource within the chip that needs to be accessed by the first JTAG interface. The first JTAG interface accesses the first CPU core group and the first JTAG-bus conversion unit in a chained manner; The first JTAG-bus conversion unit responds to recognizing a first access request received through the first JTAG link indicating access to the hardware resource, accesses the hardware resource, and sends the access result to the first JTAG interface through the first JTAG chain.

2. The chip according to claim 1, wherein the first JTAG-bus conversion unit is coupled to the at least one hardware resource via a first bus; The first JTAG-bus conversion unit responds to the recognition of the first access request indicating access to the hardware resource by accessing the hardware resource through the first bus and sends the access result to the first JTAG interface through the first JTAG chain.

3. The chip according to claim 1, characterized in that, The JTAG-bus conversion unit is a JTAG bridge, and the chip also includes a first multiplexer. The JTAG bridge is coupled to the first multiplexer, and the first multiplexer is coupled to each of the at least one hardware resource through a path that follows the JTAG protocol. The first multiplexer receives a first selection signal and connects the first JTAG chain to the hardware resource indicated by the first selection signal via the JTAG bridge.

4. The chip according to claim 3, characterized in that, In response to recognizing a second access request indicating access to a hardware resource coupled to the first multiplexer, the JTAG bridge generates a first selection signal and provides the first selection signal to the first multiplexer, the first selection signal indicating that the first JTAG chain is connected to the hardware resource.

5. The chip according to any one of claims 1-4, characterized in that, The chip also includes a second JTAG interface and a second multiplexer, the second JTAG interface being coupled to the second multiplexer, and the second multiplexer being coupled to multiple sensitive hardware resources within the chip. The second multiplexer connects the JTAG signal of the second JTAG interface to one of the sensitive hardware resources.

6. The chip according to claim 5, characterized in that, The second JTAG interface uses multiple pins of the chip to transmit JTAG signals; the second JTAG interface multiplexes multiple pins of the chip with the general purpose input / output unit, and the second JTAG interface can be disabled.

7. The chip according to any one of claims 1-6, characterized in that, The chip also includes a second CPU core group and a third CPU core group; On the first JTAG chain, the first CPU core group is coupled to the second CPU core group, the second CPU core group is coupled to the third CPU core group, and the third CPU core group is coupled to the first JTAG-bus conversion unit; The first JTAG interface accesses the second CPU core group and the third CPU core group in a chained manner.

8. The chip according to claim 7, characterized in that, The chip also includes a JTAG signal switching unit, which couples the first JTAG interface to the first JTAG chain and the first JTAG interface to the first CPU core group. The JTAG signal switching unit is used to switch the operating mode of accessing the first CPU core group through the first JTAG interface.

9. The chip according to claim 8, characterized in that, The operating modes for accessing the first CPU core group through the first JTAG interface include chained mode and exclusive mode. When the working mode of accessing the first CPU core group through the first JTAG interface is the chain mode, the first JTAG interface, the JTAG signal switching unit, the first CPU core group, the second CPU core group, the third CPU core group and the first JTAG-bus conversion unit form the first JTAG chain. When the operating mode of accessing the first CPU core group through the first JTAG interface is exclusive mode, the JTAG signal switching unit connects the JTAG signal of the first JTAG interface to the first CPU core group, but not to the first JTAG chain.

10. An electronic device, characterized in that, Includes the chip as described in any one of claims 1-9.

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