A priority-based dual-channel power controller

Abstract

This invention relates to a priority-based dual-channel power controller, addressing the problems of voltage interruption during power switching, numerous components, and low reliability in existing technologies. The controller includes first / second input terminals, a priority setting unit, a three-resistor network, and a back-to-back PMOSFET switching circuit. Overvoltage / undervoltage thresholds (0V / UV) are dynamically set via the three-resistor network, and flexible configuration of VIN1 / VIN2 priorities is supported. Its core advantages are: achieving voltage interruption-free switching (switching time ≤2.1ms, voltage fluctuation ≤45mV); integrated design reducing discrete components by 37.5% (from 8-10 to 5), lowering component costs by over 32%; compliance with National Military Standard N1 (GJB 150A-2009), and switching reliability ≥99.95%. It is suitable for high-reliability power management scenarios such as mobile terminals, military communications, and industrial control.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a priority dual-channel power controller. Background Technology

[0002] In the field of electronic device power management, dual-channel power switching technology is a core component ensuring continuous system operation, especially in scenarios involving both battery power and external adapter power (such as mobile terminals, military communication equipment, and industrial controllers). The reliability of the power controller directly impacts equipment stability. Currently, mainstream power switching solutions primarily employ a discrete component design, with a typical structure as follows: Power switching is achieved through the unidirectional conduction characteristic of diodes, supplemented by independent overvoltage (OV) and undervoltage (UV) protection circuits. Priority switching relies on a manually configured resistor network and cannot be dynamically adjusted; The voltage thresholds (such as OV=13.5V, UV=10.5V) are set by a fixed resistor, which lacks flexibility.

[0003] However, this technical solution has the following objective flaws, which have been widely confirmed in industry practice: The large number of components and high cost: a single switching circuit requires 8-10 discrete components (including diodes, transistors, resistors, etc.), resulting in an increase of more than 30% in PCB area and a 25% increase in material costs; Voltage interruption occurs during the switching process: Due to the lack of a synchronous control mechanism, the peak voltage fluctuation during power switching reaches 100-200mV and lasts for 2-5ms (typical test data: when VIN1 suddenly drops from 12V to 9V, the device restart rate is as high as 15%).

[0004] Insufficient reliability: Under environmental stress (such as vibration and temperature changes), the discrete components have poor matching and the failure rate is generally ≥1.2% (which meets the requirements of the National Military Standard GJB 150A-2009 for power switching reliability ≥99.9%).

[0005] Poor functional scalability: OV / UV thresholds and priorities need to be set through hardware modification, which cannot meet the needs of multiple scenarios (such as military equipment that needs to dynamically switch battery / adapter priorities, and industrial equipment that needs to adapt to 36V / 24V multi-voltage input).

[0006] The aforementioned shortcomings have created pain points in the industry: in the military field, traditional solutions lead to increased equipment downtime due to high failure rates; in the consumer electronics field, the large number of components hinders product miniaturization. Although some patents attempt to optimize OV / UV settings, the core issues of voltage interruption during switching and component integration remain unresolved, and dynamic priority configuration capabilities are not provided. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention provides a priority-based dual-channel power controller, comprising: First power input pin VIN1 and second power input pin VIN2; Output pin VOUT; The first power switch P1 and the second power switch P2 are both PMOSFETs. Their drains are connected to the first power input pin VIN1 and the second power input pin VIN2, respectively, and their sources are connected in parallel to each other and then connected to the output pin VOUT. The priority control module is configured to control the first power switch P1 to be turned on and the second power switch P2 to be turned off when the input voltage of the first power input pin VIN1 is valid, regardless of whether the input voltage of the second power input pin VIN2 is valid, so that the output pin VOUT is powered by the first power input pin VIN1.

[0008] In one embodiment of the present invention, it further includes: a first overvoltage detection module and a first undervoltage detection module, which are respectively connected to an external first voltage divider resistor network through a first overvoltage input pin OV1 and a first undervoltage input pin UV1, for detecting whether the voltage of the first power input pin VIN1 is within a preset window range; The second overvoltage detection module and the second undervoltage detection module are respectively connected to an external second voltage divider resistor network through the second overvoltage input pin OV2 and the second undervoltage input pin UV2, and are used to detect whether the voltage of the second power input pin VIN2 is within a preset window range; When any input voltage exceeds its corresponding overvoltage threshold or falls below its corresponding undervoltage threshold, the corresponding power switch is turned off.

[0009] In one embodiment of the present invention, it further includes: a hysteresis setting pin HYS, used to set the hysteresis voltage for input voltage detection; When the hysteresis setting pin HYS is grounded, an internal fixed hysteresis voltage is used; when the hysteresis setting pin HYS is grounded through an external resistor, an external adjustable hysteresis voltage is used.

[0010] In one embodiment of the present invention, it further includes: a time setting pin TMR, for connecting an external capacitor to set the window time for the input voltage to be valid; The input is considered valid when the duration of the input voltage within the window range defined by the overvoltage threshold and the undervoltage threshold reaches the window time.

[0011] In one embodiment of the present invention, it further includes: a first status indicator pin VALID1 and a second status indicator pin VALID2, wherein the status indicator pins are open-drain structures and are used to indicate whether the voltages of the first power input pin VIN1 and the second power input pin VIN2 are valid, respectively. When the corresponding input voltage is within the window range and the duration reaches the window time, the corresponding status indicator pin outputs a low-level signal; when the corresponding input voltage is outside the window range, the corresponding status indicator pin outputs a high-level signal.

[0012] In one embodiment of the present invention, it further includes: an enable control module, including an enable pin EN and a shutdown pin SHDN; When the enable pin EN is higher than the first threshold, the controller is enabled as a whole; when the enable pin EN is lower than the first threshold, the controller is disabled but the input valid counter is not reset. When the shutdown pin SHDN is higher than the second threshold, the input current is allowed to flow to the output. When the shutdown pin SHDN is lower than the second threshold, the controller shuts off, the input cannot flow to the output, and the input validity counter is reset.

[0013] In one embodiment of the present invention, it further includes: a cascade control pin CAS, used to connect the enable pin of the next level controller in a multi-level power main backup system; When the current power supply fails, the cascade control pin CAS outputs a high level, enabling the next level controller to start and allowing a lower priority power supply to be connected to the load.

[0014] In one embodiment of the present invention, it further includes: an internal low-dropout linear regulator (LDO), whose input terminal is connected to the higher of the first power input pin VIN1 and the second power input pin VIN2, and whose output terminal is for internal logic power supply and is led out as an internal power supply pin INTVCC for external connection of a filter capacitor.

[0015] In one embodiment of the present invention, the gates of the first power switch P1 and the second power switch P2 are respectively connected to an internal gate driver module through a first gate driving terminal G1 and a second gate driving terminal G2. When the power switch is turned on, the gate driver module clamps the gate voltage to a predetermined value below the source voltage to protect the power switch.

[0016] In one embodiment of the present invention, the nominal voltages of the first power input pin VIN1 and the second power input pin VIN2 are the same or different. When the voltage on the first power input pin VIN1 returns to valid, the priority control module automatically switches back to being powered by the first power input pin VIN1.

[0017] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The dual-channel power controller of the present invention adopts back-to-back PMOSFET synchronous control, with a switching time ≤2.1ms and voltage fluctuation ≤45mV, avoiding equipment restart; it reduces discrete components by 37.5% (from 8-10 to 5), and reduces device cost by more than 32%; it also supports high / low priority modes (VIN1 / VIN2 dynamic switching) to adapt to multiple scenario requirements; it complies with the national military standard N1 (GJB 150A-2009), with switching reliability ≥99.95% and failure rate ≤0.05%; it covers the full voltage range of 12V / 5V, 24V / 12V, 36V / 12V, etc., improving system stability. Attached Figure Description

[0018] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0019] Figure 1 This is an internal functional block diagram of the dual-channel power controller provided by the present invention; Figure 2 This is a circuit diagram of the three-resistor network used in this invention to set overvoltage / undervoltage thresholds; Figure 3 This is a circuit schematic diagram of the dual-channel power controller provided by the present invention; Figure 4a This is a test waveform diagram showing the output voltage switching from VIN1 to VIN2 when VIN1 fails, as provided in this embodiment. Figure 4b This is a test waveform diagram showing the output voltage switching back from VIN2 to VIN1 when VIN1 recovers, as provided in this embodiment. Detailed Implementation

[0020] like Figure 1 As shown, this embodiment provides a priority dual-channel power controller, which is further subdivided internally, including: a cascaded control module shared by the first and second channels, and input overvoltage detection module, input undervoltage detection module, input hysteresis voltage setting module, input valid time setting module, input status indication module and gate driver module respectively set for the two channels; it also includes a controller enable control module and an LDO module.

[0021] The input overvoltage detection module and input undervoltage detection module are connected to an external voltage divider resistor network via the overvoltage input pin OVx and undervoltage input pin UVx, respectively, to detect whether the input voltage of the corresponding channel is within a preset window range. The input hysteresis voltage setting module sets the hysteresis voltage for input voltage detection via the hysteresis setting pin HYS. The input valid time setting module is connected to an external capacitor via the time setting pin TMR to set the valid window time of the input voltage. The input status indication module outputs the valid status of the input voltage of the corresponding channel via the status indication pin VALIDx. The gate driver module is connected to the gate of an external power switch via the gate drive terminal Gx to control the turn-on and turn-off of the power switch. The controller enable control module controls the working state of the controller via the enable pin EN and the turn-off pin SHDN. The LDO module supplies power to the internal control logic via the internal power supply pin INTVCC. The cascading control module realizes priority cascading between multiple controllers via the cascading control pin CAS.

[0022] Reference Figure 2 The diagram shows a three-resistor network. In this embodiment, overvoltage and undervoltage thresholds are set using an external three-resistor network. The voltage divider resistors between the power input pin Vx and OVx, and GND, set the input overvoltage threshold. When the input voltage exceeds the set overvoltage value for some reason, the gate drive module stops working, that input cannot reach the output, and the output voltage switches to another input. The OV value is calculated using the three-resistor network as shown in Formula 1: (1) The voltage divider resistors between the power input pin Vx and UVx, and GND set the input undervoltage threshold. When the input voltage falls below the set undervoltage value for some reason, the gate drive module stops working, and this input cannot reach the output. The output voltage then switches to another input. The UV calculation using a three-resistor network is shown in Formula 2. (2) In this embodiment, the input hysteresis voltage is set via the HYS pin. When the HYS pin is grounded, an internally fixed 30mV input hysteresis voltage is used; alternatively, the HYS pin can be connected to a resistor. Connected to ground, using external hysteresis mode, with a hysteresis current set in the range of 50nA to 500nA. For example, typical value selection =250nA. In practical applications, overvoltage (0V), undervoltage (UV), and hysteresis voltage are often preset according to the actual power supply voltage. Based on formulas 1-4, we can deduce R1-R3 and the hysteresis resistor. , Vref=1V in the formula.

[0023] (3) (4) The formula for calculating R4 is the same as that for R1, R5 is the same as that for R2, and R3 is the same as that for R6.

[0024] Furthermore, the input validity period tVALID is set via the TMR pin. When TMR is directly connected to INTVCC, tVALID = 3.5µs. After presetting tVALID, it is calculated according to Formula 5. .

[0025] (5) Simultaneously, the input voltage status is indicated via the VALIDx pin. When the input voltage is within the 0V / UV window voltage range and remains above tVALID, the VALIDx status indicator pin outputs a low voltage signal; when the input voltage is outside the 0V / UV window voltage range, VALIDx outputs a high voltage signal. Internally, VALIDx has an open-drain structure and is connected to the output terminal VOUT via a pull-up resistor.

[0026] Reference Figure 3 The circuit schematic shown has VINx connected to the drain of the back-to-back PMOSFET power transistors Px, VSx connected to the source of Px, the output drains of Px connected in parallel and connected to VOUT, and Gx connected to the gate of Px. The output terminal Gx of the driver module is connected to the gate of the PMOSFETs. When Gx goes low, the PMOSFETs turn on, and the input current is transferred to the output. An internal clamping diode clamps the Gx voltage to be 6.2V lower than the corresponding VSx to prevent damage to the PMOSFETs.

[0027] Furthermore, it includes two enable control pins, EN and SHDN. When EN > 1V, the controller is on; when EN < 1V, the controller is off but does not reset the input validity counter. When SHDN > 1V, the controller is on, allowing input current to flow to the output; when SHDN < 1V, the controller is off, preventing input current from flowing to the output, resetting the input validity counter, and the CAS pin voltage goes high. In cascaded applications, the next-level (lower priority) controller is on. In actual use, EN and SHDN can be directly connected to INTVCC.

[0028] Furthermore, the internal LDO module converts the input to a low voltage to power the internal control logic. When Vx > 2.5V, the device starts to work. INTVCC is the output terminal of the LDO, which can be grounded through a 0.1μF capacitor during application.

[0029] Meanwhile, in a multi-level power supply master backup system, multiple controllers can be used. The CAS pin of the front-end is connected to the EN terminal of the next level. When the front-end power supply fails, the CAS pin is pulled high, the next level controller is turned on, and the lower priority power supply is connected to the load.

[0030] Specifically according to Figure 3 For the connection method, assuming VIN1 uses a 12V adapter and VIN2 uses four rechargeable NiMH batteries (nominal value 1.2V, discharge cutoff voltage 0.9V, full charge voltage 1.5V), when VIN1 is connected, the output is powered by VIN1; when VIN1 is not present, the output is powered by the VIN2 battery. Q1 and Q2, Q3 and Q4 use P-type power transistors FDS4465, in common-source configuration. Based on actual needs, set OV1=14.1V, UV1=9.95V, OV2=7.1V, and UV1=3.6V. =250nA, =100mV, substitute into formulas 1-4, and calculate R1-R6 and After taking the nominal resistance values, R1=31.6kohm, R2=13.3kohm, R3=402kohm, R4=78.7kohm, R5=76.8ohm, R6=402kohm, Rhys=255kohm, set tVALID=16ms, and substitute into formula 5 to calculate CTMR=1nF.

[0031] Regarding the testing and verification of this embodiment: A desktop power supply was used to simulate the actual power supply, with VIN1=12V and VIN2=5V. The test waveform is as follows: Figure 4a and 4b As shown.

[0032] Specifically, Figure 4a Channel 1 of the oscilloscope displays the input waveform VIN1, channel 2 displays the input waveform VIN2, and channel 3 displays the output waveform VOUT. VIN1 is 12V, VIN2 is 5V, and the load current is 2A. When both inputs are present, the output follows VIN1. When the voltage of VIN1 drops to UVLO1, the output VOUT follows VIN2. In steady state, the output voltage switches from 12V to 5V. Channel 4 of the oscilloscope displays the current waveform of VIN2 (jumping from 0A to 2A).

[0033] Figure 4b Channel 1 of the oscilloscope displays the input waveform VIN1, channel 2 displays the input waveform VIN2, and channel 3 displays the output waveform VOUT. VIN1 is 12V, VIN2 is 5V, and the load current is 1A. Initially, VIN2 is powered on while VIN1 is not. At this time, VOUT follows VIN2 at 5V and VIN1 is powered on at 12V. When the VIN1 voltage rises to the set UVLO1, the output follows VIN1. In steady state, the output voltage switches from 5V to 12V. Channel 4 of the oscilloscope displays the current waveform of VIN2 (jumping from 1A to 0A).

[0034] Furthermore, based on this embodiment, in a specific application example, two controllers are cascaded to form a three-channel power supply master-slave system. The first controller's main power supply is a 24V adapter, and its backup power supply is a 12V battery; the input of the second controller is connected to another output of the 12V battery. The CAS pin of the first controller is connected to the EN pin of the second controller. When both the main power supply and the backup power supply of the first controller fail, the CAS pin outputs a high level, enabling the second controller and allowing the third priority power supply to be connected to the load.

[0035] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A priority-based dual-channel power controller, characterized in that, include: First power input pin VIN1 and second power input pin VIN2; Output pin VOUT; The first power switch P1 and the second power switch P2 are both PMOSFETs. Their drains are connected to the first power input pin VIN1 and the second power input pin VIN2, respectively, and their sources are connected in parallel to each other and then connected to the output pin VOUT. The priority control module is configured to control the first power switch P1 to be turned on and the second power switch P2 to be turned off when the input voltage of the first power input pin VIN1 is valid, regardless of whether the input voltage of the second power input pin VIN2 is valid, so that the output pin VOUT is powered by the first power input pin VIN1.

2. The priority-based dual-channel power controller according to claim 1, characterized in that, Also includes: The first overvoltage detection module and the first undervoltage detection module are respectively connected to an external first voltage divider resistor network through the first overvoltage input pin OV1 and the first undervoltage input pin UV1, and are used to detect whether the voltage of the first power input pin VIN1 is within a preset window range; The second overvoltage detection module and the second undervoltage detection module are respectively connected to an external second voltage divider resistor network through the second overvoltage input pin OV2 and the second undervoltage input pin UV2, and are used to detect whether the voltage of the second power input pin VIN2 is within a preset window range; When any input voltage exceeds its corresponding overvoltage threshold or falls below its corresponding undervoltage threshold, the corresponding power switch is turned off.

3. The priority-based dual-channel power controller according to claim 2, characterized in that, Also includes: The hysteresis setting pin HYS is used to set the hysteresis voltage for input voltage detection. When the hysteresis setting pin HYS is grounded, an internal fixed hysteresis voltage is used; when the hysteresis setting pin HYS is grounded through an external resistor, an external adjustable hysteresis voltage is used.

4. The priority-based dual-channel power controller according to claim 2, characterized in that, Also includes: The time setting pin TMR is used to connect an external capacitor to set the window time for the input voltage to be valid. The input is considered valid when the duration of the input voltage within the window range defined by the overvoltage threshold and the undervoltage threshold reaches the window time.

5. The priority-based dual-channel power controller according to claim 4, characterized in that, Also includes: The first state indicator pin VALID1 and the second state indicator pin VALID2 are open-drain structures and are used to indicate whether the voltage of the first power input pin VIN1 and the second power input pin VIN2 is valid, respectively. When the corresponding input voltage is within the window range and the duration reaches the window time, the corresponding status indicator pin outputs a low-level signal; when the corresponding input voltage is outside the window range, the corresponding status indicator pin outputs a high-level signal.

6. The priority-based dual-channel power controller according to claim 1, characterized in that, Also includes: The enable control module includes an enable pin EN and a shutdown pin SHDN; When the enable pin EN is higher than the first threshold, the controller is enabled as a whole; when the enable pin EN is lower than the first threshold, the controller is disabled but the input valid counter is not reset. When the shutdown pin SHDN is higher than the second threshold, the input current is allowed to flow to the output. When the shutdown pin SHDN is lower than the second threshold, the controller shuts off, the input cannot flow to the output, and the input validity counter is reset.

7. The priority-based dual-channel power controller according to claim 1, characterized in that, Also includes: The Cascading Control (CAS) pin is used to connect the enable pin of the next-level controller in a multi-stage power supply master-slave system. When the current power supply fails, the cascade control pin CAS outputs a high level, enabling the next level controller to start and allowing a lower priority power supply to be connected to the load.

8. The priority-based dual-channel power controller according to claim 1, characterized in that, Also includes: The internal low-dropout linear regulator (LDO) has its input connected to the higher of the first power input pin VIN1 and the second power input pin VIN2. Its output is used to power the internal logic and is led out as the internal power supply pin INTVCC for connecting an external filter capacitor.

9. The priority-based dual-channel power controller according to claim 1, characterized in that: The gates of the first power switch P1 and the second power switch P2 are respectively connected to the internal gate driver module through the first gate driving terminal G1 and the second gate driving terminal G2. When the power switch is turned on, the gate driver module clamps the gate voltage to a predetermined value below the source voltage to protect the power switch.

10. The priority-based dual-channel power controller according to claim 1, characterized in that: The nominal voltages of the first power input pin VIN1 and the second power input pin VIN2 may be the same or different. When the voltage on the first power input pin VIN1 returns to valid, the priority control module automatically switches back to being powered by the first power input pin VIN1.

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