Negative pressure generating circuit and circuitry

Abstract

This invention provides a negative voltage generating circuit and circuit system. The negative voltage generating circuit includes: a frequency control module, which delays a clock signal according to a selected voltage level and generates a charging frequency control signal by performing logical operations on the clock signal and its delayed signal; a negative voltage driving module, including first and second driving units, which generate first and second charging voltages respectively based on the charging frequency control signal when the pre-charging signal is invalid; a negative voltage generating module, including first and second capacitors, which charge the first and second capacitors respectively based on the first and second charging voltages to generate a negative voltage; a completion monitoring module, which generates a negative voltage completion signal when the value of the negative voltage is less than a first set value; and a pre-charging module, which generates a pre-charging signal when the negative voltage completion signal is invalid and pre-charges the first and second capacitors based on the pre-charging signal. This invention solves the problem that existing negative voltage generating circuits do not have a voltage level selection function.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a negative voltage generating circuit and circuit system. Background Technology

[0002] In electronic circuit systems, especially memory systems, negative voltages are frequently required; however, existing circuits can only generate a single negative voltage and lack voltage range selection functionality. As system complexity continues to increase, existing circuits can no longer meet current application demands; therefore, how to provide a negative voltage generation circuit with voltage range selection functionality has become a pressing technical problem that those skilled in the art urgently want to solve.

[0003] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a negative pressure generating circuit and circuit system to solve the problem that the existing negative pressure generating circuit does not have a voltage range selection function.

[0005] To achieve the above and other related objectives, the present invention provides a negative pressure generating circuit, the negative pressure generating circuit comprising:

[0006] The frequency control module delays the clock signal according to the selected voltage level and generates a charging frequency control signal by performing logical operations on the clock signal and its delayed signal.

[0007] The negative pressure drive module, connected to the frequency control module, includes a first drive unit and a second drive unit. When the pre-charge signal is invalid, it generates a first charging voltage and a second charging voltage based on the charging frequency control signal.

[0008] A negative voltage generating module, connected to the negative voltage driving module, includes a first capacitor and a second capacitor, which charge the first capacitor and the second capacitor based on the first charging voltage and the second charging voltage respectively to generate a negative voltage;

[0009] The monitoring module is connected to the negative pressure generating module and generates a negative pressure completion signal when the value of the negative voltage is less than a first set value.

[0010] The pre-charge module is connected to the negative pressure generation module and the completion monitoring module. When the negative pressure completion signal is invalid, it generates a pre-charge signal and pre-charges the first capacitor and the second capacitor based on the pre-charge signal.

[0011] Optionally, the frequency control module includes a delay setting unit, a first NAND gate, a first delay unit, a first NOR gate, a second NOR gate, a first inverter, and an OR gate; wherein, the delay setting unit receives the clock signal and performs corresponding level delay processing on the clock signal based on a selected voltage level to generate a delayed signal; the first input terminal of the first NAND gate receives a first enable signal, the second input terminal of the first NAND gate receives the clock signal, the output terminal of the first NAND gate is connected to the input terminal of the first delay unit, the output terminal of the first delay unit is connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate receives the clock signal, the output terminal of the first NOR gate is connected to the first input terminal of the OR gate, the second input terminal of the OR gate is connected to the output terminal of the second NOR gate, the output terminal of the OR gate outputs the charging frequency control signal via the first inverter, the first input terminal of the second NOR gate receives the clock signal, and the second input terminal of the second NOR gate receives the delayed signal.

[0012] Optionally, the negative voltage generating circuit has two voltage levels, including a first voltage level and a second voltage level, wherein the negative voltage value corresponding to the first voltage level is greater than the negative voltage value corresponding to the second voltage level; in this case, the delay setting unit performs one-level delay or two-level delay on the clock signal based on the level selection signal and thereby generates the delayed signal.

[0013] Optionally, the delay setting unit includes a second inverter, a third inverter, an odd number of fourth inverters, a fifth inverter, a second delay unit, a third delay unit, a third NOR gate, a fourth NOR gate, and a level converter; wherein, the input terminal of the second inverter receives the clock signal, the output terminal of the second inverter is connected to the input terminal of the second delay unit, the output terminal of the second delay unit is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the input terminal of the third delay unit and the first input terminal of the third NOR gate, the output terminal of the third delay unit is connected to the first input terminal of the fourth NOR gate, the output terminal of the third delay unit is also connected to the second input terminal of the fourth NOR gate via the odd number of fourth inverters, the third input terminal of the fourth NOR gate receives the gear selection signal via the fifth inverter, the output terminal of the fourth NOR gate is connected to the second input terminal of the third NOR gate, the output terminal of the third NOR gate is connected to the level converter, and the level converter outputs the delay signal by level-raising the input signal.

[0014] Optionally, there are five fourth inverters, which are cascaded between the output of the third delay and the second input of the fourth NOR gate. The second fourth inverter is implemented using a NAND gate, and the fourth fourth inverter is implemented using a NOR gate.

[0015] Optionally, the first driving unit includes a buffer, a fifth NOR gate, a sixth inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; wherein, the first input terminal of the fifth NOR gate receives the charging frequency control signal via the buffer, the second input terminal of the fifth NOR gate receives the pre-charge signal, the output terminal of the fifth NOR gate is connected to the gate of the first PMOS transistor via the sixth inverter, and the gate of the first PMOS transistor is also connected to the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor. The gate of the S-channel transistor is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the third PMOS transistor, and the drain of the second NMOS transistor. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the source of the second NMOS transistor, and the gate of the third NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and outputs the first charging voltage. The sources of the first NMOS transistor and the third NMOS transistor are connected to reference ground.

[0016] Optionally, the second driving unit includes a second NAND gate, a seventh inverter, an eighth inverter, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; wherein, the first input terminal of the second NAND gate receives the charging frequency control signal, the second input terminal of the second NAND gate receives the inverted signal of the pre-charge signal, the output terminal of the second NAND gate is connected to the gate of the fourth PMOS transistor via the seventh inverter and the eighth inverter in sequence, and the gate of the fourth PMOS transistor is also connected to the gate of the fifth PMOS transistor, the gate of the fourth NMOS transistor, and the sixth NMOS transistor. The gate of the fifth NMOS transistor is connected to the power supply voltage. The drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the gate of the sixth PMOS transistor, and the drain of the fifth NMOS transistor. The drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fifth NMOS transistor, and the gate of the sixth NMOS transistor. The source of the sixth PMOS transistor is connected to the power supply voltage. The drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor and outputs the second charging voltage. The sources of the fourth NMOS transistor and the sixth NMOS transistor are connected to reference ground.

[0017] Optionally, the negative voltage generating module further includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; wherein, the first terminal of the first capacitor receives the first charging voltage, the second terminal of the first capacitor is connected to the drain of the seventh PMOS transistor, the first terminal of the second capacitor receives the second charging voltage, the second terminal of the second capacitor is connected to the drain of the ninth PMOS transistor, the gate of the seventh PMOS transistor is connected to the gate of the ninth PMOS transistor, the gate of the seventh NMOS transistor, and the gate of the ninth NMOS transistor and receives the inverted signal of the pre-charge signal, the source of the seventh PMOS transistor is connected to reference ground, and the drain of the seventh PMOS transistor is connected to the reference ground. The drain of the eighth PMOS transistor, the gate of the tenth PMOS transistor, the drain of the seventh NMOS transistor, and the gate of the tenth NMOS transistor are described. The gate of the eighth PMOS transistor is connected to the drain of the ninth PMOS transistor and the gate of the eighth NMOS transistor. The source of the eighth PMOS transistor is connected to reference ground. The source of the ninth PMOS transistor is connected to reference ground. The drain of the ninth PMOS transistor is connected to the drain of the tenth PMOS transistor and the drain of the ninth NMOS transistor. The source of the tenth PMOS transistor is connected to reference ground. The source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is connected to the source of the tenth NMOS transistor and outputs the negative voltage. The source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor.

[0018] Optionally, the pre-charge module includes a pre-charge control unit, an eleventh PMOS transistor, and a twelfth PMOS transistor; wherein, the pre-charge control unit is connected to the completion monitoring module and generates the pre-charge signal when the negative voltage completion signal is invalid; the gates of the eleventh PMOS transistor and the twelfth PMOS transistor receive the pre-charge signal, the sources of the eleventh PMOS transistor and the twelfth PMOS transistor are connected to reference ground, the drain of the eleventh PMOS transistor is connected to the end of the first capacitor away from the first charging voltage, and the drain of the twelfth PMOS transistor is connected to the end of the second capacitor away from the second charging voltage.

[0019] Optionally, the negative pressure generating circuit further includes:

[0020] A voltage clamping module, connected to the negative voltage generating module, clamps the value of the negative voltage to the second set value when the value of the negative voltage is less than the second set value;

[0021] An overvoltage monitoring module, connected to the negative voltage generating module, generates an overvoltage signal when the value of the negative voltage is less than a third set value;

[0022] A discharge control module is connected to the negative voltage generation module and the overvoltage monitoring module. It generates a discharge signal based on the overvoltage signal and discharges the negative voltage based on the discharge signal.

[0023] The third setting value is greater than the second setting value and less than the first setting value.

[0024] Optionally, the voltage clamping module includes a plurality of first diodes, wherein each first diode is connected in series between a reference ground and a negative voltage.

[0025] Optionally, the overvoltage monitoring module includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a ninth inverter, a second diode, a third diode, a fourth diode, and a resistor; wherein the gate of the thirteenth PMOS transistor is connected to its drain and to the gate of the fourteenth PMOS transistor, the source of the thirteenth PMOS transistor is connected to the power supply voltage, the drain of the thirteenth PMOS transistor is connected to the source of the fifteenth PMOS transistor, the source of the fourteenth PMOS transistor is connected to the power supply voltage, the drain of the fourteenth PMOS transistor is connected to a reference ground sequentially via the resistor, the second diode, and the third diode, and the drain of the fourteenth PMOS transistor is also connected to the gate of the sixteenth PMOS transistor, the gate of the twelfth NMOS transistor, and the thirteenth NMOS transistor. The gate of the OS transistor, the gate of the fifteenth PMOS transistor receives the second enable signal, the drain of the fifteenth PMOS transistor is connected to the drain of the eleventh NMOS transistor, the source of the sixteenth PMOS transistor is connected to the power supply voltage, the drain of the sixteenth PMOS transistor is connected to the drain of the seventeenth PMOS transistor and the drain of the fourteenth NMOS transistor and outputs the overvoltage signal through the ninth inverter, the gate of the seventeenth PMOS transistor is connected to the gate of the fourteenth NMOS transistor and receives the negative voltage completion signal, the source of the seventeenth PMOS transistor is connected to the power supply voltage, the gate of the eleventh NMOS transistor is connected to the reference ground, the source of the eleventh NMOS transistor receives the negative voltage through the fourth diode, the drain of the twelfth NMOS transistor is connected to the source of the fourteenth NMOS transistor, the source of the twelfth NMOS transistor is connected to the drain of the thirteenth NMOS transistor, and the source of the thirteenth NMOS transistor is connected to the reference ground.

[0026] Optionally, the discharge control module includes a discharge control unit and a fifteenth NMOS transistor; wherein the discharge control unit is connected to the overvoltage monitoring module and generates the discharge signal based on the overvoltage signal; the gate of the fifteenth NMOS transistor receives the discharge signal, the source of the fifteenth NMOS transistor receives the negative voltage, and the drain of the fifteenth NMOS transistor is connected to reference ground.

[0027] The present invention also provides a circuit system comprising: a negative pressure generating circuit as described in any of the above claims.

[0028] Optionally, the circuit system is a memory system.

[0029] As described above, the negative voltage generating circuit and circuit system of the present invention achieve configurable voltage levels through the design of a frequency control module, a negative voltage driving module, a negative voltage generating module, and a completion monitoring module; achieve rapid establishment of negative voltage through the design of a pre-charging module; achieve voltage range control through the design of a voltage clamping module, an overvoltage monitoring module, and a discharge control module; and, the present invention has low power consumption. Attached Figure Description

[0030] Figure 1 The diagram shown is a schematic diagram of the negative pressure generating circuit in an embodiment of the present invention.

[0031] Figure 2 The diagram shown is a structural schematic of the frequency control module in an embodiment of the present invention.

[0032] Figure 3 The diagram shown is a structural schematic of the negative pressure drive module in an embodiment of the present invention.

[0033] Figure 4 The diagram shown is a structural schematic of the negative pressure generating module in an embodiment of the present invention.

[0034] Figure 5 The diagram shown is a structural schematic of the pre-charging module in an embodiment of the present invention.

[0035] Figure 6 The diagram shows the structure of the voltage clamping module and the discharge control module in an embodiment of the present invention.

[0036] Figure 7 The diagram shown is a schematic of the overvoltage monitoring module in an embodiment of the present invention.

[0037] Component designation explanation

[0038] 10 Negative Voltage Generating Circuit

[0039] 100 Frequency Control Module

[0040] 110 Delay Setting Unit

[0041] 111 Second Delay Unit

[0042] 112 Third Delay Unit

[0043] 113 Level Shifter

[0044] 120 First Delay Unit

[0045] 200 Negative Pressure Drive Module

[0046] 210 First Drive Unit

[0047] 220 Second Drive Unit

[0048] 300 Negative Pressure Generating Unit

[0049] 400 Monitoring module completed

[0050] 500 pre-charge module

[0051] 510 Precharge Control Unit

[0052] 600 Voltage Clamping Module

[0053] 700 Overvoltage Monitoring Module

[0054] 800 Discharge Control Module

[0055] 810 Discharge Control Unit Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] like Figure 1As shown, this embodiment provides a negative pressure generating circuit 10, including a frequency control module 100, a negative pressure driving module 200, a negative pressure generating module 300, a completion monitoring module 400, and a pre-charging module 500; further, it also includes a voltage clamping module 600, an overvoltage monitoring module 700, and a discharge control module 800.

[0059] The frequency control module 100 delays the clock signal CLK according to the selected voltage level, and generates a charging frequency control signal CTL_CF by performing logical operations on the clock signal CLK and its delayed signal. Furthermore, the frequency control module 100 is controlled by a first enable signal VNEG_EN to start and stop working. The first enable signal VNEG_EN is related to the negative voltage completion signal VNEG_OK. Thus, the frequency control module 100 can start working when the negative voltage completion signal VNEG_OK is invalid in order to start outputting the charging frequency control signal CTL_CF, and stop working when the negative voltage completion signal VNEG_OK is valid in order to stop outputting the charging frequency control signal CTL_CF.

[0060] In one example, such as Figure 2 As shown, the frequency control module 100 includes a delay setting unit 110, a first NAND gate (NAND1), a first delay unit 120, a first NOR gate (NOR1), a second NOR gate (NOR2), a first inverter (INV1), and an OR gate (OR). Wherein:

[0061] The delay setting unit 110 receives the clock signal CLK and performs corresponding level delay processing on the clock signal CLK based on the selected voltage level to generate the delay signal DELAY. In practical applications, the negative voltage generation circuit 10 of this embodiment typically has two voltage levels, including a first voltage level and a second voltage level. The negative voltage value corresponding to the first voltage level is greater than the negative voltage value corresponding to the second voltage level. For example, the negative voltage value corresponding to the first voltage level is -1V, and the negative voltage value corresponding to the second voltage level is -1.5V. At this time, the delay setting unit 110 performs one-level delay or two-level delay on the clock signal CLK based on the level selection signal SEL to generate the delay signal DELYA. For example, when the level selection signal SEL is "0", it means that the first voltage level is selected, so the delay setting unit 110 performs one-level delay on the clock signal CLK to generate the delay signal DELAY. When the level selection signal SEL is "1", it means that the second voltage level is selected, so the delay setting unit 110 performs two-level delay on the clock signal CLK to generate the delay signal DELAY. It should be noted that the delay signal DELAY here refers to a delay-related signal, not just the delayed clock signal CLK. It can also refer to the signal after performing corresponding logical operations on the delayed clock signal CLK.

[0062] In one embodiment, the delay setting unit 110 includes a second inverter INV2, a third inverter INV3, an odd number of fourth inverters INV4, a fifth inverter INV5, a second delay unit 111, a third delay unit 112, a third NOR gate NOR3, a fourth NOR gate NOR4, and a level converter 113; wherein, the input terminal of the second inverter INV2 receives the clock signal CLK, the output terminal of the second inverter INV2 is connected to the input terminal of the second delay unit 111, the output terminal of the second delay unit 111 is connected to the input terminal of the third inverter INV3, the output terminal of the third inverter INV3 is connected to the input terminal of the third delay unit 112, and the output terminal of the third inverter INV3 is also connected to the first input terminal of the third NOR gate NOR3. The output of the third delay unit 112 is connected to the first input of the fourth NOR gate 4. The output of the third delay unit 112 is also connected to the second input of the fourth NOR gate 4 via an odd number of fourth inverters. The third input of the fourth NOR gate 4 receives the range selection signal SEL via a fifth inverter INV5 (i.e., the input of the fifth inverter INV5 receives the range selection signal SEL, and the output of the fifth inverter INV5 is connected to the third input of the fourth NOR gate 4). The output of the fourth NOR gate 4 is connected to the second input of the third NOR gate 3. The output of the third NOR gate 3 is connected to a level converter 113. The level converter 113 outputs a delayed signal DELAY by level-raising the input signal. It should be noted that the level converter 113 can be implemented using existing known level conversion structures, and there are no restrictions on this.

[0063] In the above embodiments, the number of fourth inverters is an odd number, such as 1, 3, 5, 7, or 9. As an optional solution, there are five fourth inverters cascaded between the output of the third delay unit 112 and the second input of the fourth NOR gate 4. By using an odd number of fourth inverters, signal matching to the input to the third NOR gate 3 is achieved. In practical applications, the first fourth inverter INV41, the third fourth inverter INV43, and the fifth fourth inverter INV45 are implemented using conventional structures. The second fourth inverter INV42 is implemented using NAND gates (i.e., the inputs of the NAND gates are connected to each other as the inputs of the inverters, and the outputs of the NAND gates are the outputs of the inverters). The fourth fourth inverter INV44 is implemented using NOR gates (i.e., the inputs of the NOR gates are connected to each other as the inputs of the inverters, and the outputs of the NOR gates are the outputs of the inverters). The use of NAND and NOR gates to implement the inversion function facilitates fast signal matching through a large delay.

[0064] The first input of the first NAND gate NAND1 receives the first enable signal VNEG_EN. The second input of the first NAND gate NAND1 receives the clock signal CLK. The output of the first NAND gate NAND1 is connected to the input of the first delay unit 120. The output of the first delay unit 120 is connected to the first input of the first NOR gate NOR1. The second input of the first NOR gate NOR1 receives the clock signal CLK. The output of the first NOR gate NOR1 is connected to the first input of the OR gate OR. The second input of the OR gate OR is connected to the output of the second NOR gate NOR2. The output of the OR gate OR outputs the charging frequency control signal CTL_CF through the first inverter INV1. The first input of the second NOR gate NOR2 receives the clock signal CLK. The second input of the second NOR gate NOR2 receives the delay signal DELAY.

[0065] In the above example, the first delay unit 120, the second delay unit 111, and the third delay unit 112 are, as their names suggest, used for signal delay. The signal delay time of the first delay unit 120 is greater than that of the third delay unit 112, and the signal delay time of the third delay unit 112 is greater than that of the second delay unit 111. Taking the negative voltage generating circuit 10 of this embodiment as having two voltage levels, with the first voltage level corresponding to a negative voltage value of -1V and the second voltage level corresponding to a negative voltage value of -1.5V as an example, the clock signal CLK is delayed by 5ns after passing through the second inverter INV2, the second delay unit 111, and the third inverter INV3, and then by 10ns after passing through the third delay unit 112. Typically, the delay time after passing through five fourth inverters is 20ns, while the delay time of the first delay unit 120 is generally greater than 20ns.

[0066] In this embodiment, the frequency control module 100 sets different charging frequencies based on different voltage levels to output different negative voltages VNEG, thus enabling configurable voltage levels. Taking a negative voltage generation circuit 10 with two voltage levels, where the first voltage level corresponds to a negative voltage of -1V and the second voltage level corresponds to a negative voltage of -1.5V as an example: If the first voltage level is selected, the frequency control module 100 performs logical operations on the clock signal CLK and its delay signal to generate a single-pulse charging frequency control signal CTL_CF, which is denoted as the first signal. If the second voltage level is selected, the frequency control module 100 performs logical operations on the clock signal CLK and its delay signal to generate a double-pulse charging frequency control signal CTL_CF, which is denoted as the second signal. The duty cycle of the second signal is greater than that of the first signal but less than that of the clock signal CLK. It should be noted that the single pulse or double pulse here refers to one signal cycle; a single pulse means one pulse is generated per signal cycle, and a double pulse means two pulses are generated per signal cycle.

[0067] The negative pressure drive module 200 is connected to the frequency control module 100 and includes a first drive unit 210 and a second drive unit 220. When the precharge signal PRECHG is invalid, the first drive unit 210 and the second drive unit 220 generate a first charging voltage VTN and a second charging voltage VTP based on the charging frequency control signal CTL_CF, respectively.

[0068] In one implementation, such as Figure 3 As shown, the first driving unit 210 includes a buffer BUF, a fifth NOR gate NOR5, a sixth inverter INV6, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3. Wherein:

[0069] The first input of the fifth NOR gate NOR5 receives the charging frequency control signal CTL_CF via buffer BUF. The second input of the fifth NOR gate NOR5 receives the pre-charge signal PRECHG. The output of the fifth NOR gate NOR5 is connected to the gate of the first PMOS transistor PM1 via the sixth inverter INV6. The gate of the first PMOS transistor PM1 is also connected to the gate of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1, and the gate of the second NMOS transistor NM2. The source of the first PMOS transistor PM1 is connected to the power supply voltage VDD, and the drain of the first PMOS transistor PM1... The source of the second PMOS transistor PM2, the gate of the third PMOS transistor PM3, and the drain of the second NMOS transistor NM2 are connected. The drain of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM1, the source of the second NMOS transistor NM2, and the gate of the third NMOS transistor NM3. The source of the third PMOS transistor PM3 is connected to the power supply voltage VDD, and the drain of the third PMOS transistor PM3 is connected to the drain of the third NMOS transistor NM3, outputting the first charging voltage VTN. The sources of the first NMOS transistor NM1 and the third NMOS transistor NM3 are connected to the reference ground VSS. The first PMOS transistor PM1, the third PMOS transistor PM3, the first NMOS transistor NM1, and the third NMOS transistor NM3 constitute a two-stage driving structure to generate the first charging voltage VTN based on the charging frequency control signal CTL_CF. The second PMOS transistor PM2 and the second NMOS transistor NM2 are used as intermediate transistors to avoid the final driving transistors (the third PMOS transistor PM3 and the third NMOS transistor NM3) from being turned on simultaneously, thus reducing leakage loss.

[0070] In one implementation, such as Figure 3 As shown, the second driving unit 220 includes a second NAND gate NAND2, a seventh inverter INV7, an eighth inverter INV8, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6. Wherein:

[0071] The first input of the second NAND gate NAND2 receives the charging frequency control signal CTL_CF, and the second input receives the inverted pre-charge signal PRECHGB. The output of the second NAND gate NAND2 is connected to the gate of the fourth PMOS transistor PM4 via the seventh inverter INV7 and the eighth inverter INV8. The gate of the fourth PMOS transistor PM4 is also connected to the gate of the fifth PMOS transistor PM5, the gate of the fourth NMOS transistor NM4, and the gate of the fifth NMOS transistor NM5. The source of the fourth PMOS transistor PM4 is connected to the power supply voltage VDD. The drain of transistor PM4 is connected to the source of the fifth PMOS transistor PM5, the gate of the sixth PMOS transistor PM6, and the drain of the fifth NMOS transistor NM5. The drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4, the source of the fifth NMOS transistor NM5, and the gate of the sixth NMOS transistor NM6. The source of the sixth PMOS transistor PM6 is connected to the power supply voltage VDD. The drain of the sixth PMOS transistor PM6 is connected to the drain of the sixth NMOS transistor NM6 and outputs the second charging voltage VTP. The sources of the fourth NMOS transistor NM4 and the sixth NMOS transistor NM6 are connected to the reference ground VSS. The fourth PMOS transistor PM4, the sixth PMOS transistor PM6, the fourth NMOS transistor NM4, and the sixth NMOS transistor NM6 form a two-stage driving structure to generate the second charging voltage VTP based on the charging frequency control signal CTL_CF; the fifth PMOS transistor PM5 and the fifth NMOS transistor NM5 are used as intermediate transistors to avoid the final stage driving transistors (the sixth PMOS transistor PM6 and the sixth NMOS transistor NM6) from being turned on at the same time, thereby reducing leakage loss.

[0072] The negative voltage generating module 300 is connected to the negative voltage driving module 200 and includes a first capacitor C1 and a second capacitor C2; wherein, the negative voltage generating module 300 charges the first capacitor C1 and the second capacitor C2 based on the first charging voltage VTN and the second charging voltage VTP respectively to generate a negative voltage VNEG.

[0073] In one implementation, such as Figure 4 As shown, the negative voltage generating module 300 includes, in addition to the first capacitor C1 and the second capacitor C2, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, and a tenth NMOS transistor NM10. Wherein:

[0074] The first terminal of the first capacitor C1 receives the first charging voltage VTN, and the second terminal of the first capacitor C1 is connected to the drain of the seventh PMOS transistor PM7. The first terminal of the second capacitor C2 receives the second charging voltage VTP, and the second terminal of the second capacitor C2 is connected to the drain of the ninth PMOS transistor PM9. The gate of the seventh PMOS transistor PM7 is connected to the gate of the ninth PMOS transistor PM9, the gate of the seventh NMOS transistor NM7, and the gate of the ninth NMOS transistor NM9, and receives the inverted precharge signal PRECHGB. The source of the seventh PMOS transistor PM7 is connected to the reference ground VSS. The drain of the seventh PMOS transistor PM7 is connected to the drain of the eighth PMOS transistor PM8, the gate of the tenth PMOS transistor PM10, the drain of the seventh NMOS transistor NM7, and the gate of the tenth NMOS transistor PM10. The gate of NM10 is connected to the gate of the eighth PMOS transistor PM8, which is connected to the drain of the ninth PMOS transistor PM9 and the gate of the eighth NMOS transistor NM8. The source of the eighth PMOS transistor PM8 is connected to the reference ground VSS. The source of the ninth PMOS transistor PM9 is connected to the reference ground VSS. The drain of the ninth PMOS transistor PM9 is connected to the drain of the tenth PMOS transistor PM10 and the drain of the ninth NMOS transistor NM9. The source of the tenth PMOS transistor PM10 is connected to the reference ground VSS. The source of the seventh NMOS transistor NM7 is connected to the drain of the eighth NMOS transistor NM8. The source of the eighth NMOS transistor NM8 is connected to the source of the tenth NMOS transistor NM10 and outputs a negative voltage VNEG. The source of the ninth NMOS transistor NM9 is connected to the drain of the tenth NMOS transistor NM10. During capacitor charging, the charging path is adjusted by the alternating conduction of the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, and the tenth NMOS transistor NM10, thereby generating a negative voltage VNEG. The values ​​of the first capacitor C1 and the second capacitor C2 determine the effective power supply capability of the negative voltage generating circuit 10 to the load in this embodiment. Therefore, the capacitor values ​​should be designed according to the load size.

[0075] The monitoring module 400 is connected to the negative voltage generation module 300 to monitor the value of the negative voltage VNEG and generate a negative voltage completion signal VNEG_OK when the value of the negative voltage VNEG is less than a first set value. In practical applications, the first set value is usually the negative voltage value corresponding to the selected voltage level.

[0076] In one embodiment, the monitoring module 400 includes a selector switch and a comparator. The control terminal of the selector switch receives a range selection signal SEL. The first terminal of the selector switch receives the negative voltage value corresponding to a first voltage range. The second terminal of the selector switch receives the negative voltage value corresponding to a second voltage range. The output terminal of the selector switch is connected to the non-inverting input terminal of the comparator. The inverting input terminal of the comparator receives the negative voltage VNEG. The output terminal of the comparator outputs a negative voltage completion signal VNEG_OK. When the first voltage range is selected, the negative voltage value corresponding to the first voltage range is used as a first set value. When the second voltage range is selected, the negative voltage value corresponding to the second voltage range is used as the first set value. A negative voltage completion signal VNEG_OK is generated when the negative voltage value is less than the first set value. The negative voltage completion signal VNEG_OK is active high.

[0077] The pre-charge module 500 is connected to the negative voltage generation module 300 and the completion monitoring module 400. It is used to generate a pre-charge signal PRECHG when the negative voltage completion signal VNEG_OK is invalid, and to pre-charge the first capacitor C1 and the second capacitor C2 based on the pre-charge signal PRECHG so that the negative voltage VNEG reaches the target value more quickly.

[0078] In one example, such as Figure 5 As shown, the pre-charge module 500 includes a pre-charge control unit 510, an eleventh PMOS transistor PM11, and a twelfth PMOS transistor PM12. The pre-charge control unit 510 is connected to the completion monitoring module 400 and generates a pre-charge signal PRECHG when the negative voltage completion signal VNEG_OK is invalid. The pre-charge signal PRECHG is active low. The gates of the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 receive the precharge signal PRECHG. The sources of the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 are connected to the reference ground VSS. The drain of the eleventh PMOS transistor PM11 is connected to the end of the first capacitor C1 away from the first charging voltage VTN (i.e., the second end of the first capacitor C1, i.e., at node J1). The drain of the twelfth PMOS transistor PM12 is connected to the end of the second capacitor C2 away from the second charging voltage VTP (i.e., the second end of the second capacitor C2, i.e., at node J2). When the precharge signal PRECHG is low, the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 are turned on, precharging the first capacitor C1 and the second capacitor C2 respectively, thereby completing the precharging of the corresponding capacitors before the corresponding charging voltage arrives.

[0079] The voltage clamping module 600 is connected to the negative voltage generating module 300 and is used to clamp the value of the negative voltage VNEG to the second set value when the value of the negative voltage VNEG is less than the second set value, wherein the second set value is less than the first set value.

[0080] In one implementation, such as Figure 6 As shown, the voltage clamping module 600 includes several first diodes, each of which is connected in series between the reference ground VSS and the negative voltage VNEG. In practical applications, each first diode is usually implemented using an NMOS transistor, that is, the gate and source of the NMOS transistor are connected together as the anode of the diode, and the drain of the NMOS transistor is used as the cathode of the diode. Furthermore, the number of first diodes is determined by the magnitude of a second set value, which should be determined by specific requirements and is not limited thereto. Taking a second set value of -3.3V as an example, the voltage clamping module 600 includes three first diodes, where the anode of the first first diode D11 is connected to the reference ground, the cathode of the first first diode D11 is connected to the anode of the second first diode D12, the cathode of the second first diode D12 is connected to the anode of the third first diode D13, and the cathode of the third first diode D13 receives the negative voltage VNEG. Thus, when the value of the negative voltage VNEG is less than -3.3V, the value of the negative voltage VNEG can be clamped at -3.3V.

[0081] The overvoltage monitoring module 700 is connected to the negative voltage generation module 300 and is used to generate an overvoltage signal VNEG_OV when the value of the negative voltage VNEG is less than a third set value. The third set value is greater than the second set value and less than the first set value. In addition, the overvoltage signal VNEG_OV is active high.

[0082] In one implementation, such as Figure 7 As shown, the overvoltage monitoring module 700 includes a thirteenth PMOS transistor PM13, a fourteenth PMOS transistor PM14, a fifteenth PMOS transistor PM15, a sixteenth PMOS transistor PM16, a seventeenth PMOS transistor PM17, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a thirteenth NMOS transistor NM13, a fourteenth NMOS transistor NM14, a ninth inverter INV9, a second diode D2, a third diode D3, a fourth diode D4, and a resistor R. In practical applications, each diode is implemented using an NMOS transistor; that is, the gate and source of the NMOS transistor are connected together as the anode of the diode, and the drain of the NMOS transistor is used as the cathode of the diode. Wherein:

[0083] The gate of the thirteenth PMOS transistor PM13 is connected to its drain and then to the gate of the fourteenth PMOS transistor PM14. The source of the thirteenth PMOS transistor PM13 is connected to the power supply voltage VDD. The drain of the thirteenth PMOS transistor PM13 is connected to the source of the fifteenth PMOS transistor PM15. The source of the fourteenth PMOS transistor PM14 is connected to the power supply voltage VDD. The drain of the fourteenth PMOS transistor PM14 is connected to the reference ground VSS via resistor R, the second diode D2, and the third diode D3. The drain of the fourteenth PMOS transistor PM14 is also connected to the gate of the sixteenth PMOS transistor PM16, the gate of the twelfth NMOS transistor NM12, and the gate of the thirteenth NMOS transistor NM13. The gate of the fifteenth PMOS transistor PM15 is connected to the second enable signal WL_EN. The drain of the fifteenth PMOS transistor PM15 is connected to the drain of the eleventh NMOS transistor NM11. The sixteenth PMOS transistor PM16... The source of transistor 6 is connected to the power supply voltage VDD. The drain of the sixteenth PMOS transistor PM16 is connected to the drain of the seventeenth PMOS transistor PM17 and the drain of the fourteenth NMOS transistor NM14, and outputs an overvoltage signal VNEG_OV through the ninth inverter INV9. The gate of the seventeenth PMOS transistor PM17 is connected to the gate of the fourteenth NMOS transistor NM14 and receives the negative voltage completion signal VNEG_OK. The source of the seventeenth PMOS transistor PM17 is connected to the power supply voltage VDD. The gate of the eleventh NMOS transistor NM11 is connected to the reference ground VSS. The source of the eleventh NMOS transistor NM11 receives the negative voltage VNEG through the fourth diode D4. The drain of the twelfth NMOS transistor NM12 is connected to the source of the fourteenth NMOS transistor NM14. The source of the twelfth NMOS transistor NM12 is connected to the drain of the thirteenth NMOS transistor NM13. The source of the thirteenth NMOS transistor NM13 is connected to the reference ground VSS.

[0084] When the negative voltage is greater than the third set value, the eleventh NMOS transistor NM11 is not overdriven, the current source path formed by the thirteenth PMOS transistor PM13 and the fourteenth PMOS transistor PM14 is not conducting, the gate voltage of the sixteenth PMOS transistor PM16 is low, the sixteenth PMOS transistor PM16 is conducting, and the overvoltage signal VNEG_OV is low. When the negative voltage is less than the third set value, the eleventh NMOS transistor NM11 is overdriven and conducts, the current source path formed by the thirteenth PMOS transistor PM13 and the fourteenth PMOS transistor PM14 is conducting, the gate voltage of the sixteenth PMOS transistor PM16 is high, the sixteenth PMOS transistor PM16 is off, the twelfth NMOS transistor NM12 and the thirteenth NMOS transistor NM13 are conducting, and the overvoltage signal VNEG_OV is high, that is, the overvoltage signal VNEG_OV is generated. In practical applications, the second enable signal WL_EN is the enable signal for the entire circuit system, and the first enable signal VENG_EN is the enable signal for the negative voltage generating circuit 10. The rising edge of the second enable signal WL_EN is located before the rising edge of the first enable signal VENG_EN, and the falling edge of the second enable signal WL_EN is located after the falling edge of the first enable signal VENG_EN.

[0085] The discharge control module 800 is connected to the negative voltage generation module 300 and the overvoltage monitoring module 700. It generates a discharge signal DISCHG based on the overvoltage signal VNEG_OV and discharges the negative voltage VNEG based on the discharge signal DISCHG.

[0086] In one example, such as Figure 6 As shown, the discharge control module 800 includes a discharge control unit 810 and a fifteenth NMOS transistor NM15. The discharge control unit 810 is connected to the overvoltage monitoring module 700 and generates a discharge signal DISCHG based on the overvoltage signal VNEG_OV, where the discharge signal DISCHG is active high. The gate of the fifteenth NMOS transistor NM15 receives the discharge signal DISCHG, the source of the fifteenth NMOS transistor NM15 receives the negative voltage VNEG, and the drain of the fifteenth NMOS transistor NM15 is connected to the reference ground VSS. When the discharge signal DISCHG is high, the fifteenth NMOS transistor NM15 is turned on, causing the negative voltage VNEG to discharge to ground.

[0087] In the negative voltage generating circuit 10 of this embodiment, the design of the frequency control module 100, negative voltage driving module 200, negative voltage generating module 300, and completion monitoring module 400 enables the setting of different charging frequencies based on different voltage levels, thereby outputting different negative voltages. The design of the pre-charging module 500 allows the negative voltage to be quickly established and reach the target value. The design of the voltage clamping module 600, overvoltage monitoring module 700, and discharge control module 800 ensures that the negative voltage value is between a first set value and a third set value, thus maintaining it at the target value after being applied to a load. Taking a first set value of -1.5V, a second set value of -3.3V, and a third set value of -2V as an example, the specific process is as follows:

[0088] Based on the charging frequency corresponding to the selected voltage level, the first capacitor C1 and the second capacitor C2 are charged to generate a negative voltage VNEG until the value of the negative voltage is less than -1.5V. Then, the monitoring module 400 generates a negative voltage completion signal VNEG_OK to stop charging. However, due to signal transmission delay, the capacitors are overcharged, making the value of the negative voltage much smaller than -1.5V.

[0089] When the negative voltage value is less than -3.3V, the voltage clamping module 600 works and clamps the negative voltage value at -3.3V. At the same time, the overvoltage monitoring module 700 works and generates an overvoltage signal VNEG_OV, which causes the discharge control module 800 to control the negative voltage VNEG to discharge to ground until the negative voltage value is adjusted to between -2V and -1.5V.

[0090] When the negative voltage value is between -3.3V and -2V, the voltage clamping module 600 does not work, the overvoltage monitoring module 700 works and generates an overvoltage signal VNEG_OV, which causes the discharge control module 800 to control the negative voltage VNEG to discharge to ground until the negative voltage value is adjusted to between -2V and -1.5V.

[0091] When the negative voltage value is greater than -2V, the voltage clamping module 600, the overvoltage monitoring module 700, and the discharge control module 800 will not work, and the negative voltage value will be between -2V and -1.5V.

[0092] Correspondingly, this embodiment also provides a circuit system, including a negative voltage generating circuit 10; wherein, the negative voltage generating circuit 10 is implemented using the circuit structure described above; of course, it may also include other functional circuits, and there are no limitations on this. In practical applications, the circuit system is a memory system, wherein the negative voltage generating circuit 10 provides a negative voltage to the bit lines in the memory system.

[0093] In summary, the negative voltage generating circuit and circuit system of the present invention, through the design of a frequency control module, a negative voltage driving module, a negative voltage generating module, and a completion monitoring module, achieves configurable voltage levels; through the design of a pre-charging module, it achieves rapid establishment of negative voltage; through the design of a voltage clamping module, an overvoltage monitoring module, and a discharge control module, it achieves voltage range control; moreover, the present invention has low power consumption. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A negative voltage generating circuit characterized by comprising: The negative pressure generating circuit includes: The frequency control module delays the clock signal according to the selected voltage level and generates a charging frequency control signal by performing logical operations on the clock signal and its delayed signal. The negative pressure drive module, connected to the frequency control module, includes a first drive unit and a second drive unit. When the pre-charge signal is invalid, it generates a first charging voltage and a second charging voltage based on the charging frequency control signal. A negative voltage generating module, connected to the negative voltage driving module, includes a first capacitor and a second capacitor, which charge the first capacitor and the second capacitor based on the first charging voltage and the second charging voltage respectively to generate a negative voltage; The monitoring module is connected to the negative pressure generating module and generates a negative pressure completion signal when the value of the negative voltage is less than a first set value. The pre-charge module is connected to the negative pressure generation module and the completion monitoring module. When the negative pressure completion signal is invalid, it generates a pre-charge signal and pre-charges the first capacitor and the second capacitor based on the pre-charge signal.

2. The negative voltage generating circuit according to claim 1, wherein The frequency control module includes a delay setting unit, a first NAND gate, a first delay unit, a first NOR gate, a second NOR gate, a first inverter, and an OR gate. The delay setting unit receives the clock signal and performs corresponding level delay processing on the clock signal based on a selected voltage level to generate a delayed signal. The first input of the first NAND gate receives a first enable signal, the second input of the first NAND gate receives the clock signal, the output of the first NAND gate is connected to the input of the first delay unit, the output of the first delay unit is connected to the first input of the first NOR gate, the second input of the first NOR gate receives the clock signal, the output of the first NOR gate is connected to the first input of the OR gate, the second input of the OR gate is connected to the output of the second NOR gate, the output of the OR gate outputs the charging frequency control signal via the first inverter, the first input of the second NOR gate receives the clock signal, and the second input of the second NOR gate receives the delayed signal.

3. The negative voltage generating circuit according to claim 2, wherein The negative voltage generating circuit has two voltage levels, including a first voltage level and a second voltage level, wherein the negative voltage value corresponding to the first voltage level is greater than the negative voltage value corresponding to the second voltage level; at this time, the delay setting unit performs one-level delay or two-level delay on the clock signal based on the level selection signal and generates the delayed signal accordingly.

4. The negative voltage generating circuit according to claim 3, wherein The delay setting unit includes a second inverter, a third inverter, an odd number of fourth inverters, a fifth inverter, a second delay unit, a third delay unit, a third NOR gate, a fourth NOR gate, and a level converter. The input of the second inverter receives the clock signal; the output of the second inverter is connected to the input of the second delay unit; the output of the second delay unit is connected to the input of the third inverter; the output of the third inverter is connected to the input of the third delay unit and the first input of the third NOR gate; the output of the third delay unit is connected to the first input of the fourth NOR gate; the output of the third delay unit is also connected to the second input of the fourth NOR gate via the odd number of fourth inverters; the third input of the fourth NOR gate receives the gear selection signal via the fifth inverter; the output of the fourth NOR gate is connected to the second input of the third NOR gate; and the output of the third NOR gate is connected to the level converter, which outputs the delayed signal by level-raising the input signal.

5. The negative voltage generating circuit according to claim 4, wherein The number of fourth inverters is five, and the five fourth inverters are cascaded between the output of the third delay and the second input of the fourth NOR gate. The second fourth inverter is implemented using a NAND gate, and the fourth fourth inverter is implemented using a NOR gate.

6. The negative voltage generating circuit according to claim 1, wherein The first driving unit includes a buffer, a fifth NOR gate, a sixth inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The first input terminal of the fifth NOR gate receives the charging frequency control signal via the buffer, the second input terminal of the fifth NOR gate receives the pre-charge signal, and the output terminal of the fifth NOR gate is connected to the gate of the first PMOS transistor via the sixth inverter. The gate of the first PMOS transistor is also connected to the gates of the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor. The gate of the first PMOS transistor is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the third PMOS transistor, and the drain of the second NMOS transistor. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the source of the second NMOS transistor, and the gate of the third NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and outputs the first charging voltage. The source of the first NMOS transistor and the source of the third NMOS transistor are connected to reference ground.

7. The negative voltage generating circuit according to claim 1, wherein The second driving unit includes a second NAND gate, a seventh inverter, an eighth inverter, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The first input of the second NAND gate receives the charging frequency control signal, and the second input of the second NAND gate receives the inverted signal of the pre-charge signal. The output of the second NAND gate is connected to the gate of the fourth PMOS transistor via the seventh inverter and the eighth inverter. The gate of the fourth PMOS transistor is also connected to the gate of the fifth PMOS transistor, the gate of the fourth NMOS transistor, and the gate of the fifth NMOS transistor. The gate of the MOS transistor, the source of the fourth PMOS transistor is connected to the power supply voltage, the drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the gate of the sixth PMOS transistor and the drain of the fifth NMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fifth NMOS transistor and the gate of the sixth NMOS transistor, the source of the sixth PMOS transistor is connected to the power supply voltage, the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor and outputs the second charging voltage, and the source of the fourth NMOS transistor and the source of the sixth NMOS transistor are connected to reference ground.

8. The negative voltage generating circuit according to claim 1, wherein The negative voltage generating module further includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; wherein, the first terminal of the first capacitor receives the first charging voltage, the second terminal of the first capacitor is connected to the drain of the seventh PMOS transistor, the first terminal of the second capacitor receives the second charging voltage, the second terminal of the second capacitor is connected to the drain of the ninth PMOS transistor, the gate of the seventh PMOS transistor is connected to the gate of the ninth PMOS transistor, the gate of the seventh NMOS transistor, and the gate of the ninth NMOS transistor and receives the inverted signal of the pre-charge signal, the source of the seventh PMOS transistor is connected to reference ground, and the drain of the seventh PMOS transistor is connected to the seventh PMOS transistor. The drain of the eighth PMOS transistor, the gate of the tenth PMOS transistor, the drain of the seventh NMOS transistor, and the gate of the tenth NMOS transistor are connected. The gate of the eighth PMOS transistor is connected to the drain of the ninth PMOS transistor and the gate of the eighth NMOS transistor. The source of the eighth PMOS transistor is connected to reference ground. The source of the ninth PMOS transistor is connected to reference ground. The drain of the ninth PMOS transistor is connected to the drain of the tenth PMOS transistor and the drain of the ninth NMOS transistor. The source of the tenth PMOS transistor is connected to reference ground. The source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is connected to the source of the tenth NMOS transistor and outputs the negative voltage. The source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor.

9. The negative voltage generating circuit according to claim 1, wherein The pre-charge module includes a pre-charge control unit, an eleventh PMOS transistor, and a twelfth PMOS transistor. The pre-charge control unit is connected to the completion monitoring module and generates the pre-charge signal when the negative voltage completion signal is invalid. The gates of the eleventh and twelfth PMOS transistors receive the pre-charge signal. The sources of the eleventh and twelfth PMOS transistors are connected to reference ground. The drain of the eleventh PMOS transistor is connected to the end of the first capacitor furthest from the first charging voltage, and the drain of the twelfth PMOS transistor is connected to the end of the second capacitor furthest from the second charging voltage.

10. The negative voltage generating circuit according to any one of claims 1 to 9, wherein The negative pressure generating circuit also includes: A voltage clamping module, connected to the negative voltage generating module, clamps the value of the negative voltage to the second set value when the value of the negative voltage is less than the second set value; An overvoltage monitoring module, connected to the negative voltage generating module, generates an overvoltage signal when the value of the negative voltage is less than a third set value; A discharge control module is connected to the negative voltage generation module and the overvoltage monitoring module. It generates a discharge signal based on the overvoltage signal and discharges the negative voltage based on the discharge signal. The third setting value is greater than the second setting value and less than the first setting value.

11. The negative voltage generating circuit according to claim 10, wherein The voltage clamping module includes a plurality of first diodes, wherein each first diode is connected in series between a reference ground and a negative voltage.

12. The negative voltage generating circuit according to claim 10, wherein The overvoltage monitoring module includes a 13th PMOS transistor, a 14th PMOS transistor, a 15th PMOS transistor, a 16th PMOS transistor, a 17th PMOS transistor, an 11th NMOS transistor, a 12th NMOS transistor, a 13th NMOS transistor, a 14th NMOS transistor, a 9th inverter, a 2nd diode, a 3rd diode, a 4th diode, and a resistor. The gate of the 13th PMOS transistor is connected to its drain and then to the gate of the 14th PMOS transistor. The source of the 13th PMOS transistor is connected to the power supply voltage. The drain of the 13th PMOS transistor is connected to the source of the 15th PMOS transistor. The source of the 14th PMOS transistor is connected to the power supply voltage. The drain of the 14th PMOS transistor is connected to a reference ground sequentially via the resistor, the 2nd diode, and the 3rd diode. The drain of the 14th PMOS transistor is also connected to the gate of the 16th PMOS transistor, the gate of the 12th NMOS transistor, and the 13th NMOS transistor. The gate of the fifteenth PMOS transistor receives a second enable signal. The drain of the fifteenth PMOS transistor is connected to the drain of the eleventh NMOS transistor. The source of the sixteenth PMOS transistor is connected to the power supply voltage. The drain of the sixteenth PMOS transistor is connected to the drain of the seventeenth PMOS transistor and the drain of the fourteenth NMOS transistor, and outputs the overvoltage signal through the ninth inverter. The gate of the seventeenth PMOS transistor is connected to the gate of the fourteenth NMOS transistor and receives the negative voltage completion signal. The source of the seventeenth PMOS transistor is connected to the power supply voltage. The gate of the eleventh NMOS transistor is connected to the reference ground. The source of the eleventh NMOS transistor receives the negative voltage through the fourth diode. The drain of the twelfth NMOS transistor is connected to the source of the fourteenth NMOS transistor. The source of the twelfth NMOS transistor is connected to the drain of the thirteenth NMOS transistor, and the source of the thirteenth NMOS transistor is connected to the reference ground.

13. The negative voltage generating circuit according to claim 10, wherein The discharge control module includes a discharge control unit and a fifteenth NMOS transistor; wherein, the discharge control unit is connected to the overvoltage monitoring module and generates the discharge signal based on the overvoltage signal; the gate of the fifteenth NMOS transistor receives the discharge signal, the source of the fifteenth NMOS transistor receives the negative voltage, and the drain of the fifteenth NMOS transistor is connected to reference ground.

14. A circuit system, characterized by The circuit system includes: a negative pressure generating circuit as described in any one of claims 1 to 13.

15. The circuitry of claim 14, wherein, The circuit system is a memory system.

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