Semiconductor structure and method of forming the same

Abstract

The method includes providing a structure. The structure includes: an active region having a channel region and a source / drain region adjacent to the channel region; a gate structure located above the channel region; source / drain components located above the source / drain regions; a contact etch stop layer (CESL) located above the source / drain components; and an interlayer dielectric (ILD) layer located above the CESL. The method further includes: forming trenches in the CESL and ILD layers to expose the source / drain components; providing a metal precursor and a phosphorus source in the trenches to form a metal phosphide layer above the source / drain components; forming a silicide layer on the metal phosphide layer; and forming a metal fill layer in the trenches. Embodiments of this application also relate to semiconductor structures and methods of forming them.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs.

[0003] Such miniaturization also increases the complexity of handling and manufacturing ICs, and similar developments in IC handling and manufacturing are needed to achieve these advancements. For example, stacked device structures have been introduced to enable further density reduction for advanced IC technology nodes. However, manufacturing such stacked device structures introduces further challenges. Therefore, existing implementations are not satisfactory in all respects. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor structure, including: providing a structure including: a bottom source / drain component; a bottom contact etch stop layer (CESL) disposed above the bottom source / drain component; a bottom interlayer dielectric (ILD) layer disposed above the bottom contact etch stop layer, wherein the thickness of the bottom contact etch stop layer is less than the thickness of the bottom interlayer dielectric layer; a top source / drain component disposed above the bottom interlayer dielectric layer; and a top contact etch stop layer disposed above the top source / drain component and the bottom interlayer dielectric layer; A top interlayer dielectric layer is disposed above the top source / drain component, wherein the thickness of the top contact etch stop layer is less than the thickness of the top interlayer dielectric layer; trenches are formed extending in the top interlayer dielectric layer and the bottom interlayer dielectric layer, wherein the trenches expose the top source / drain component and the bottom source / drain component; a metal precursor and a phosphorus-containing precursor are deposited in the trenches to form a metal phosphide layer above the top source / drain component and the bottom source / drain component; and a metal filler layer is formed in the trenches and above the metal phosphide layer.

[0005] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a structure including: an active region including a channel region and a source / drain region adjacent to the channel region; a gate structure located above the channel region; a source / drain component located above the source / drain region; a contact etch stop layer (CESL) located above the source / drain component; and an interlayer dielectric (ILD) layer located above the contact etch stop layer; forming a trench in the contact etch stop layer and the interlayer dielectric layer to expose the source / drain component; providing a metal precursor and a phosphorus source in the trench to form a metal phosphide layer above the source / drain component; forming a silicide layer on the metal phosphide layer; and forming a metal fill layer in the trench.

[0006] Some embodiments of this application provide a semiconductor structure including: a bottom transistor and a top transistor, the top transistor being disposed above the bottom transistor, wherein the bottom transistor includes a bottom source / drain component and a bottom dielectric layer disposed above the bottom source / drain component, and wherein the top transistor includes a top source / drain component and a top dielectric layer disposed above the top source / drain component; a contact component extending through the top dielectric layer and the bottom dielectric layer, wherein the conductivity of the contact component is greater than the conductivity of the top source / drain component and the bottom source / drain component; and a metal phosphide layer and a metal silicide layer disposed between the top source / drain component and the contact component and between the bottom source / drain component and the contact component, wherein the metal phosphide layer includes a first metal and phosphorus, and wherein the metal silicide layer includes a second metal different from the first metal. Attached Figure Description

[0007] The embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart of a method for forming a semiconductor structure according to one or more aspects of embodiments of the present disclosure is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 Exemplary semiconductor structures according to one or more aspects of embodiments of this disclosure are shown in Figure 1 Partial cross-sectional views during each manufacturing stage of the method.

[0010] Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 The optional semiconductor structure according to one or more aspects of embodiments of the present disclosure is shown in Figure 1 Partial cross-sectional views during each manufacturing stage of the method.

[0011] Figure 17A , Figure 17B and Figure 17C One or more aspects of embodiments according to this disclosure are shown in accordance with Figure 1 An exemplary structure of a metal precursor in an exemplary semiconductor structure is fabricated using a method described above.

[0012] Figure 18A and Figure 18B One or more aspects of embodiments according to this disclosure are shown in accordance with Figure 1 The method describes an exemplary reaction that forms a metal phosphide layer in an exemplary semiconductor structure.

[0013] Figure 19 One or more aspects of embodiments according to this disclosure are illustrated. Figure 1 A schematic diagram of the electric field at the interface of an exemplary semiconductor structure manufactured by the method. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact.

[0015] Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments disclosed herein. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, in the following embodiments of the present disclosure, forming a component connected to and / or coupled to another component on another component may include embodiments where the components are formed in direct contact, and may also include embodiments where an additional component is formed between the components, such that the components do not directly contact each other. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in the embodiments of the present disclosure. Spatially relative terms are intended to cover different orientations of the device including the component. Moreover, when numerical values ​​or ranges of values ​​are described using terms such as “about,” “approximately,” etc., as will be understood by those skilled in the art, the term is intended to cover numerical values ​​within a reasonable range that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing parts having numerically related characteristics, the numerical value or range of numerical values ​​encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" can include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is + / - 15%, as is known to those skilled in the art.

[0016] Stacked transistor structures can provide further density reduction for advanced integrated circuit (IC) technology nodes (especially as they evolve to 3nm (N3) and below), particularly when the stacked transistor structure includes multi-gate devices such as fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors comprising nanowires and / or nanosheets, and other types of multi-gate devices. Stacked transistor structures include vertically stacked transistors. For example, a stacked transistor structure may include a first transistor (i.e., an upper / top transistor) disposed above a second transistor (i.e., a lower / bottom transistor). When the first and second transistors have opposite conductivity types (i.e., an n-type transistor and a p-type transistor), the transistor stack can provide a complementary field-effect transistor (CFET).

[0017] Stacked transistor structures may include source / drain contacts. In some cases, stacked n-type and p-type transistors share a common source / drain contact. The common source / drain contact can be a local interconnect used to connect the n-type and p-type source / drain epitaxial components together. Because the n-type and p-type epitaxial components are stacked vertically one on top of the other, the local interconnect may need to penetrate the top epitaxial component until it lands on the bottom epitaxial component. However, forming source / drain contacts in stacked devices presents various challenges, such as higher resistance. Therefore, while existing stacked device structures (e.g., CFET structures) and their associated fabrication processes are generally sufficient to meet their intended purpose, they are not entirely satisfactory in every respect.

[0018] This disclosure generally relates to semiconductor structures (e.g., stacked transistor structures) having source / drain contacts. In an exemplary process, a structure (e.g., a CFET structure) is provided. The structure includes a bottom transistor disposed above a substrate and a top transistor disposed above the bottom transistor. The bottom transistor includes bottom source / drain components, and the top transistor includes a top source / drain component perpendicularly positioned above the bottom source / drain components. A trench is formed to expose the bottom source / drain components and the top source / drain components. A metal precursor and a phosphorus-containing precursor are deposited in the trench to form a metal phosphide layer comprising a first metal over the bottom source / drain components and the top source / drain components. Optionally, a silicide layer comprising a second metal may be formed on the metal phosphide layer. A metal fill layer is formed in the trench, and a planarization process is performed to remove excess material, thereby forming the source / drain contacts. By forming the metal phosphide layer using the methods described in this disclosure, the resistance of the source / drain contacts is reduced. By forming a silicide layer over a metal phosphide layer, an additional dipole layer is formed, which can further reduce the resistance of the source / drain contacts.

[0019] Various aspects of embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. The following is in conjunction with... Figures 2 to 9 Description method 100. Figures 2 to 9 It is based on Figure 1 Partial cross-sectional views of structure 200 at different manufacturing stages of an embodiment of method 100. Figures 10 to 16 They are based on Figure 1 Partial cross-sectional views of optional structures 300, 400, 500, 200', 300', 400' and 500' manufactured according to embodiments of method 100. Figures 17A to 17C It is shown in accordance with Figure 1 The method is used to manufacture the exemplary structure of the metal precursor in the exemplary structure. Figures 18A to 18B It is shown in accordance with Figure 1 The method describes an exemplary reaction that forms a metal phosphide layer in an exemplary semiconductor structure. Figure 19 It shows that according to Figure 1 This is a schematic diagram of the electric field at the interface of an exemplary semiconductor structure fabricated by the method. Method 100 is merely an example and is not intended to limit the embodiments of this disclosure to what is expressly shown in method 100. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, eliminated, or moved around for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. Because structure 200 (or 300, 400, 500, 200', 300', 400', 500') will be manufactured as a semiconductor structure, structure 200 (or 300, 400, 500, 200', 300', 400', 500') may be referred to herein as semiconductor structure 200 (or 300, 400, 500, 200', 300', 400', 500') or semiconductor device 200 (or 300, 400, 500, 200', 300', 400', 500'). To avoid ambiguity, Figures 2 to 16 The X, Y, and Z directions are perpendicular to each other and are used consistently throughout the embodiments of this disclosure. Throughout the embodiments of this disclosure, the same reference numerals denote the same parts unless otherwise stated. That is, the material properties and comparisons of the various numbered elements described in conjunction with the methods or drawings should be applied to the same numbered elements described in conjunction with different methods or different drawings.

[0020] refer to Figures 1 to 3 Method 100 includes a frame 102 in which a structure 200 is formed or provided. Figure 3 It shows the following: Figure 2 A partial cross-sectional view of structure 200 intercepted by line A-A'. Figure 2 In some embodiments illustrated, the precursor structure 200 includes a front-end process (FEOL) CFET structure fabricated on a substrate 202. In the depicted embodiments, the FEOL CFET structure includes a bottom device structure formed around a bottom channel member 2080B and a top device structure formed around a top channel member 2080T. Along the vertical direction (i.e., the Z-direction), the bottom channel member 2080B is spaced from the top channel member 2080T by an intermediate dielectric layer 210 sandwiched between two intermediate semiconductor layers 2080M. The bottom channel member 2080B is disposed above a base fin 202B, which is patterned by the substrate 202. Isolation member 212 ( Figure 3(As shown) is disposed above substrate 202 and surrounding base fin 202B. A bottom channel member 2080B forms a channel region extending horizontally between two bottom source / drain members 218B. Similarly, a top channel member 2080T forms a channel region extending horizontally between two top source / drain members 218T. Depending on the context, the bottom source / drain members 218B and the top source / drain members 218T may be collectively referred to as source / drain members 218 or individually. The bottom device structure includes a bottom gate structure 220B that encloses each of the vertically stacked members of the bottom channel member 2080B, and the top device structure includes a top gate structure 220T that encloses each of the vertically stacked members of the top channel member 2080T. Depending on the context, the bottom gate structure 220B and the top gate structure 220T may be collectively referred to as gate structure 220 or individually.

[0021] Each of the top source / drain components 218T is positioned directly above one of the bottom source / drain components 218B. The bottom source / drain components 218B may be positioned on the substrate epitaxial region 226. Figure 2 As shown, the bottom source / drain component 218B is spaced apart from the top source / drain component 218T above it by a bottom contact etch stop layer (BCESL) 232B and a bottom interlayer dielectric (BILD) layer 234B. The BILD layer 234B is spaced apart from the intermediate semiconductor layer 2080M and the intermediate dielectric layer 210 by the BCESL 232B. The top contact etch stop layer (TCESL) 232T and the top interlayer dielectric (TILD) layer 234T are disposed above each of the top source / drain components 218T. The bottom channel components 2080B are stacked one on top of the other along the Z-direction and are staggered with the inner spacer component 228. Similarly, the top channel components 2080T are stacked one on top of the other along the Z-direction and are staggered with the inner spacer component 228. The gate spacer 222 extends along the sidewall of the portion of the top gate structure 220T located above the top channel component 2080T. Due to the planarization process, the top surfaces of TCESL 232T, TILD layer 234T, gate spacer 222, and top gate structure 220T are coplanar. For example... Figure 2 As shown, the bottom channel member 2080B and the top channel member 2080T fall within the channel region 204C of the active region 204, and the bottom source / drain member 218B and the top source / drain member 218T fall within the source / drain region 204SD of the active region 204. The source / drain region 204SD is disposed between the two channel regions 204C, and the channel region 204C is disposed between the two source / drain regions 204SD.

[0022] In some embodiments, substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Base fin 202B is patterned by substrate 202 and may share the same composition as substrate 202. In some embodiments, bottom channel member 2080B, intermediate semiconductor layer 2080M, and top channel member 2080T may include silicon (Si). Gate spacer 222, intermediate dielectric layer 210, and internal spacer component 228 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, metal nitride, or suitable dielectric materials. BCESL 232B and TCESL 232T may include silicon nitride or aluminum nitride. BILD layer 234B and TILD layer 234T may include oxide-based dielectric materials such as silicon oxide, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. BCESL 232B and TCESL 232T may be thinner than BILD layer 234B and TILD layer 234T, respectively, along the X-direction. Isolation component 212 may include oxide-based dielectric materials such as silicon oxide, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0023] The epitaxial region 226 may include undoped semiconductor material. In the depicted embodiments, the epitaxial region 226 includes undoped silicon (Si), undoped silicon germanium (SiGe), or undoped germanium (Ge). The top surface of the epitaxial region 226 may be located at the same level as the top surface of the substrate fin 202B. The epitaxial region 226 may reduce leakage into the substrate 202. In some embodiments, fin spacers 222f are disposed along the sidewalls of the epitaxial region 226. The fin spacers 222f and the gate spacers 222 may be formed of the same material.

[0024] In the embodiments illustrated in the accompanying drawings, the bottom source / drain component 218B is p-type and may comprise silicon germanium (SiGe) doped with a p-type dopant (such as boron (B)); the top source / drain component 218T is n-type and may comprise silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). In these depicted embodiments, the bottom source / drain component 218B may comprise boron-doped silicon germanium (SiGe:B), and the top source / drain component 218T may comprise phosphorus-doped silicon (Si:P). As used herein, source / drain region, source / drain component, epitaxial source / drain, epitaxial source / drain component, etc., may refer to the source of a device, the drain of a device, or the source and / or drain of multiple devices.

[0025] In some embodiments, each of the bottom gate structure 220B and the top gate structure 220T includes an interface layer 236 connected to the bottom channel member 2080B, the top channel member 2080T, the intermediate semiconductor layer 2080M, and / or the base fin 202B, a gate dielectric layer 238 above the interface layer 236, and a gate electrode 240 above the gate dielectric layer 238. The gate electrode 240 in the bottom gate structure 220B includes a p-type work function layer. The gate electrode 240 in the top gate structure 220T includes an n-type work function layer. In some embodiments, the interface layer 236 includes silicon oxide. The gate dielectric layer 238 is formed of a high-k dielectric material. As used and described herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermally heated silicon oxide (~3.9). The gate dielectric layer 238 may include hafnium oxide. Optionally, the gate dielectric layer 238 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The dielectric constant of the gate dielectric layer 238 is greater than that of the isolation component 212, the internal spacer component 228, the intermediate dielectric layer 210, the gate spacer 222, BCESL 232B, the BILD layer 234B, the TCESL 232T, and the TILD layer 234T. In some instances, the dielectric constant of the gate dielectric layer 238 is more than twice that of the isolation component 212, the internal spacer component 228, the intermediate dielectric layer 210, the gate spacer 222, the BCESL 232B, the BILD layer 234B, the TCESL 232T, or the TILD layer 234T. Furthermore, along the X-direction, the thickness of the gate dielectric layer 238 is less than the thickness of the gate spacer 222.

[0026] For example, the p-type work function layer in the gate electrode 240 of the bottom gate structure 220B may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), other p-type work function materials, or combinations thereof. The n-type work function layer in the gate electrode 240 of the top gate structure 220T may include titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), other n-type work function materials, or combinations thereof. In one embodiment, the gate electrode 240 in the bottom gate structure 220B and the top gate structure 220T comprises a titanium-based material.

[0027] In some embodiments, reference Figure 3 Structure 200 includes a gate isolation structure 250. The gate isolation structure 250 may extend longitudinally along the X direction in a top view. In the depicted embodiment, the gate isolation structure 250 is disposed between two active regions 204. The gate isolation structure 250 may divide the gate structure 220 into two portions and electrically isolate the two portions. In some embodiments, the gate isolation structure 250 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbon oxynitride, or combinations thereof. In one embodiment, the gate isolation structure 250 includes a silicon nitride pad 252 and a dielectric filler 254 surrounded by the silicon nitride pad 252. The dielectric filler 254 may include silicon oxide.

[0028] Figures 4 to 9 The following is shown according to method 100 Figure 3 Partial cross-sectional views of section B of structure 200 at different manufacturing stages. (Reference) Figure 1 and Figure 4 Method 100 includes a frame 104 in which a trench 256 is formed to expose source / drain components 218.

[0029] Trench 256 may include a first type trench 256-1 and a second type trench 256-2. The first type trench 256-1 extends vertically through the TILD layer 234T, BILD layer 234B, TCESL 232T, and BCESL 232B to expose the top source / drain component 228T and the bottom source / drain component 218B. The top surface and sidewalls of the top source / drain component 218T and the top surface of the bottom source / drain component 218B are exposed in the first type trench 256-1. Therefore, the first type trench 256-1 has a first depth to the top surface of the top source / drain component 218T and a second depth to the top surface of the bottom source / drain component 218B. The second type trench 256-2 extends through the TILD layer 234T and TCESL 232T to expose only the top source / drain component 218T.

[0030] In some embodiments, a patterning process is performed on dielectric layers (e.g., TILD layer 234T, BILD layer 234B, TCESL 232T, and BCESL 232B) to form trenches 256. In some embodiments, a portion of the top source / drain component 218T is removed during the patterning process. First type trench 256-1 and second type trench 256-2 may be formed in different patterning processes. Forming the first type trench 256-1 may include more than one patterning process to extend the first type trench 256-1 to a first depth and a second depth. The patterning process may include multiple photolithography and etching processes. The photolithography process may include forming a patterned mask layer 262 over the TILD layer 234T. The patterned mask layer 262 may include multiple dielectric layers, such as etch stop layer (ESL) 258-1, ILD layer 260-1, ESL 258-2, and ILD layer 260-2, stacked one on top of the other as depicted. The patterned mask layer 262 has openings, each of which overlaps with a portion of the corresponding source / drain region 204SD in a top view. The etching process may include, for example, transferring the pattern in the patterned mask layer 262 to the underlying dielectric layer and / or source / drain components 218 by removing portions of the TILD layer 234T, BILD layer 234B, TCESL 232T and BCESL 232B and / or the source / drain components 218 exposed by the openings. The etching process may include dry etching, wet etching, other suitable etching processes, or combinations thereof.

[0031] Still referencing Figure 1 and Figure 4 Method 100 includes a frame 106, wherein a dielectric pad 264 is formed on the sidewall of a trench 256. Forming the dielectric pad 264 is optional. Figure 1 In the middle, the selectable box is a dashed rectangle with rounded corners.

[0032] The dielectric pad 264 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the dielectric pad 264 includes silicon nitride. For example, the dielectric pad 264 may be formed by conformally depositing a dielectric material layer over structure 200 using processes such as chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch-back (e.g., anisotropic) process to remove the dielectric material layer from the bottom portions of the horizontal surfaces and sidewalls of trench 256. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or combinations thereof. In some embodiments, the etch-back process includes a directional etching process (e.g., tilted plasma etching), wherein an ion beam may be oriented at a tilt angle relative to the Z-direction to the surface of structure 200. In an embodiment, the bottom portion of the sidewalls of trench 256 (e.g., starting from and below the top source / drain component 218T) is exposed after the etch-back process. A dielectric layer may be retained as a dielectric pad 264 on the exposed sidewalls of the TILD layer 234T, TCESL 232T, and gate isolation structure 250. The dielectric pad 264 prevents diffusion between the metal filler layer (described below) and the dielectric layer (e.g., TILD layer 234T, TCESL 232T). In some embodiments, the deposited dielectric pad 264 is first processed, thereby altering its composition. In some instances, the processed portion of the dielectric pad 264 is retained during the etch-back process, and the unprocessed portion is removed by the etch-back process. In a further embodiment, the dielectric pad 264 comprises silicon oxide, and the processing includes tilted ion implantation using appropriate ions (such as nitrogen ions) such that nitrogen is introduced into the bottom portion of the dielectric pad 264. Subsequently, the processed portions of the dielectric pad 264 are selectively removed by an etch-back process using a suitable etchant such as phosphorous acid. In some embodiments, the deposition of the dielectric material layer occurs before extending the first type trench 256-1 from a first depth to a second depth, followed by an etch-back (e.g., anisotropic) process to remove the dielectric material layer from a horizontal surface (e.g., the top surface of the top source / drain component 218T), thereby forming the dielectric pad 264.

[0033] Before proceeding to the next process step, a cleaning process can be performed to remove any debris from the surface of trench 256. In some embodiments, the cleaning process includes purging a carrier gas (e.g., an inert gas) to clean the surface of structure 200.

[0034] Still referencing Figure 1and Figure 4 Method 100 includes block 108, wherein a first silicide layer 266 is selectively formed on the bottom source / drain component 218B but not on the exposed surface (e.g., top surface) of the source / drain component 218T. Block 108 is optional.

[0035] The first silicide layer 266 may include silicides, germanides, and / or germanium silicides of suitable metals, such as ruthenium, nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. In some embodiments, the first silicide layer 266 includes titanium, silicon, and germanium, and may be referred to as titanium germanium silicide.

[0036] In some embodiments, the selective formation of the first silicide layer 266 on the bottom source / drain component 218B employs a selective deposition process, such as ALD, plasma-enhanced atomic layer deposition (PEALD), CVD, plasma-enhanced chemical vapor deposition (PECVD), or metal-organic chemical vapor deposition (MOCVD). In such embodiments, due to the selectivity of the deposition process, the first silicide layer 266 is formed on the exposed surface of the bottom source / drain component 218B more than on other surfaces of the structure 200 (e.g., the exposed surfaces of the top source / drain component 218T and the dielectric layer in the trench 256). In some other embodiments, the selective formation of the first silicide layer 266 on the bottom source / drain component 218B may include a deposition process and a patterning process. In the deposition process, silicide layers are formed on the top source / drain component 218T and the bottom source / drain component 218B. A mask layer (e.g., a bottom anti-reflective coating (BARC) layer) can be deposited and patterned to cover the silicide layer on the bottom source / drain component 218B. The silicide layer on the top source / drain component 218T can be removed by a suitable process (e.g., an etching process), and the patterned mask layer can be removed, leaving a first silicide layer 266 on the bottom source / drain component 218B. The first silicide layer 266 can reduce the resistance of the source / drain contacts (as will be described).

[0037] refer to Figure 1 and Figure 5 Method 100 includes a block 110, wherein a metal phosphide layer 268 is formed over a top source / drain component 218T and a bottom source / drain component 218B. For simplicity, in Figure 5 The dielectric pad 264 is not explicitly depicted in the following figures. It should be understood that structure 200 may include the dielectric pad 264 as described above.

[0038] The operation in box 110 may include depositing a metal precursor and a phosphorus-containing precursor into structure 200, including trench 256. The deposition of the metal precursor and phosphorus-containing precursor may be performed using processes such as CVD or ALD. The deposition may be performed at temperatures from about 100 degrees Celsius to about 600 degrees Celsius.

[0039] In some embodiments, the metal precursor comprises a first metal (M). The first metal may include an early transition metal. In some embodiments, the first metal comprises zirconium (Zr), hafnium (Hf), scandium (Sc), yttrium (Y), ytterbium (Yb), lanthanum (La), erbium (Er), dysprosium (Dy), cerium (Ce), or combinations thereof. In some embodiments, the metal precursor comprises a metal halide of the first metal (e.g., a fluoride, chloride, bromide, and iodide), a coordination complex of the first metal, or combinations thereof. The metal halide may have a boiling point, sublimation temperature, and / or decomposition temperature equal to or less than about 500 degrees Celsius. For example, metal halides include zirconium(III) chloride (ZrCl3), zirconium(IV) chloride (ZrCl4), hafnium tetrachloride (HfCl4), zirconium(IV) bromide (ZrBr4), hafnium tetrabromide (HfBr4), or combinations thereof. The range of boiling point, sublimation temperature, and / or decomposition temperature is not randomly selected but specifically configured to facilitate the following processes. In some embodiments, the coordination complex comprises a coordination center of a first metal and a ligand surrounding the coordination center. In some embodiments, the ligand is independently selected from trialkylcyclopentadienyl, dialkylcyclopentadienyl-alkylamidinyl, trialkylamidinyl, tris(alkylacetic acid), tris[N,N-bis(trimethylsilyl)amide], tetra(dialkylamide), and cyclopentadienyl metal chloride. Figures 17A to 17C Some examples of metallic precursors are shown. Figures 17A to 17C In this context, M is the first metal, Me is a methyl group, and X is a halogen atom (e.g., F, Cl, Br, I). Groups R and R... 1 R 2 R 3 , R', R" are specified under the corresponding structures, where "=" indicates independent selection. Each occurrence of a subscript variable (e.g., n, m) in any structure or group provided herein may be independently selected from the corresponding range provided herein. For example, in Figure 17C In the same structure 17C-1, the n in groups R, R', and R" can each be independently selected from the corresponding range of n provided below structure 17C-1. For example, in Figure 17C In the different structures 17C-1 and 17C-2, the n in group R of structure 17C-1 and the n in group R of structure 17C-2 can each be independently selected from the corresponding range of n provided below for the corresponding structure of group R. Figure 17C In the structure, in some instances, M is Y, Sc, or La.

[0040] In some embodiments, the phosphorus-containing precursor includes phosphorus (P), phosphine (PH3), diphosphine (P2H4), and P. n H n+2 (phosphine, phosphine, phosbenzene), P(SiH3)3, P(Si(C) n H 2n+1 )3)3、P(C n H 2n+1 3. P(C) n H 2n-1 3. Triphenylphosphine, tris(2-furanyl)phosphine, white phosphorus (P4), or combinations thereof. Each occurrence of a subscript variable (e.g., n) in any chemical formula provided in the embodiments of this disclosure may be independently selected from the corresponding range provided herein. For example, P... n H n+2 n, P(Si(C) n H 2n+1 )3)3 in n, P(C n H 2n+1 n and P(C) in )3 n H 2n-1 In P, n can be independently selected from the corresponding range of n provided below. n H n+2 In this context, n can be equal to or less than approximately 3. In P(Si(C) n H 2n+1 In )3)3, n can be equal to or less than approximately 8. In P(C n H 2n+1 In P(C)3, n can be equal to or less than approximately 8. n H 2n-1 In 3, n can be equal to or greater than about 5 and equal to or less than about 8. In some embodiments, n is an integer.

[0041] In some embodiments, the metal precursor and the phosphorus-containing precursor react to form a metal phosphide, as in reaction (1) below. The byproduct can be any product of reaction (1) other than the metal phosphide, such as hydrogen chloride (HCl), amidine, or compounds having a cyclopentadienyl group.

[0042] Metal precursor + phosphorus-containing precursor → metal phosphide + byproduct (1)

[0043] In some embodiments, the Gibbs free energy of reaction (1) is less than zero. In some embodiments, the Gibbs free energy of reaction (1) is less than about -1.0 eV. Therefore, reaction (1) is spontaneous. The metal phosphide layer 268 can be formed under operating conditions (e.g., temperature). Reaction (1) can include surface reactions at the exposed surfaces of the source / drain components 218 and / or the first silicide layer 266. Figure 18Aand Figure 18B Some examples of reaction (1) are shown. Cp can refer to cyclopentadienyl.

[0044] In addition to reaction (1), the composition of the source / drain component 218 (e.g., silicon) can react with a metal phosphide. Therefore, in some embodiments, the metal phosphide layer 268 comprises a metal phosphide (M) of a first metal. x P z ), first metal silicon phosphide (M x Si y P z () or combinations thereof. In some embodiments, x is equal to or greater than about 1, and equal to or less than about 15. y may be equal to or greater than zero, and equal to or less than about 30. z may be greater than zero, and equal to or less than about 12. In some embodiments, the ratio of y to x is equal to or less than about 2. In some embodiments, the ratio of z to x is equal to or less than about 1. x, y, and z may be integers. The metal phosphide layer 268 on the top source / drain component 218T may include M x P z and / or M x Si y P z The metal phosphide layer 268 above the bottom source / drain component 218B may include M x P z In some embodiments, the metal phosphide layer 268 includes impurities (e.g., carbon, nitrogen) detectable by X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). The impurities may have a concentration of about 0.001% to about 3.0%.

[0045] The material of metal phosphide layer 268 (e.g., M) x P z M x Si y P zThe lattice of the source / drain component 218 can be matched with the lattice of the material (e.g., silicon) of the source / drain component 218, thus reducing the resistance of the source / drain contact (as will be described). In some embodiments, the conduction band of the material of the metal phosphide layer 268 matches the conduction band of the material of the source / drain component 218 (e.g., silicon), which can reduce the resistance of the source / drain contact. The metal phosphide layer 268 can be conformally formed over the source / drain component 218. The term "conformal" is used herein for the convenience of describing a layer having a substantially uniform thickness over the respective regions. In some embodiments, the respective regions herein include the exposed surface of the top source / drain component 218T and the exposed surface of the first silicide layer 266 located over the bottom source / drain component 218B. The conformal formation of the metal phosphide layer 268 can increase the interface region between the metal phosphide layer 268 and the components below it (e.g., source / drain components 218 and / or the first silicide layer 266), thereby reducing the resistance of the source / drain contacts.

[0046] Various parameters of the process (e.g., ALD process, CVD process) can be adjusted to achieve the designed composition and thickness of the metal phosphide layer 268, such as gas composition, temperature, duration, pressure, gas flow rate, source power, bias power, bias voltage, other suitable parameters or combinations thereof.

[0047] A phosphorus-containing precursor provides a phosphorus source to form the metal phosphide layer 268, thus avoiding or mitigating phosphorus consumption from the source / drain components 218 (e.g., doped phosphorus in the top source / drain component 218T). In some embodiments, the top source / drain component 218T includes doped phosphorus formed from the top source / drain component 218T. The concentration of doped phosphorus at the surface of the top source / drain component 218T in contact with the metal phosphide layer 268 can be maintained or increased during the formation of the metal phosphide layer 268.

[0048] In the depicted embodiment, the deposition process also forms a metal phosphide residue layer 268' on the exposed surfaces (e.g., sidewalls, top surfaces) of the dielectric material (e.g., nitride layer 264, TCESL 232T, BCEL 232B, TILD layer 234T, BILD layer 234B, and / or gate isolation structure 250) in trench 256. The metal phosphide residue layer 268' may include a metal phosphide (M) of the first metal as described above. x P zIn some embodiments, the metal phosphide residual layer 268' is thinner than the metal phosphide layer 268. This may be due to the selectivity of the deposition process and / or the first pull-back process following the deposition process (e.g., sidewall pull-back process) (e.g., epitaxial to dielectric selectivity). In some embodiments, the metal precursor and phosphorus-containing precursor are selectively deposited more over the source / drain components 218 than over the dielectric material in the trench 256, thus forming more metal phosphide over the source / drain components 218 than over the dielectric material in the trench 256. In some embodiments, the first pull-back process includes an etching process. In some embodiments, the first pull-back process includes flowing a halide gas (e.g., chlorine, metal chloride, hydrogen chloride) over the structure 200 to reduce the thickness of the metal phosphide on the dielectric material in the trench 256, thereby forming the metal phosphide residual layer 268'. The first pull-back process may be performed after the deposition process.

[0049] refer to Figure 1 and Figure 6 Method 100 includes block 112, wherein a second silicide layer 270 is formed over a metal phosphide layer 268.

[0050] The operation in block 112 may include depositing a second metal (M') and an optional silicon-containing gas onto structure 200 (e.g., including trench 256) using a suitable deposition process (such as CVD or ALD). The deposition process may be performed at a temperature of about 100 degrees Celsius to about 600 degrees Celsius, optionally about 350 degrees Celsius to about 600 degrees Celsius. The second metal may include titanium (Ti), zirconium (Zr), vanadium (V), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), rhenium (Re), ruthenium (Ru), osmium (Os), nickel (Ni), platinum (Pt), palladium (Pd), zinc (Zn), or combinations thereof. In some embodiments, the second metal is different from the first metal. In some embodiments, the second metal has a greater electronegativity than the first metal. The silicon-containing gas may include silane (SiH4), disilane (Si2H6), other suitable gases, or combinations thereof. The second silicide layer 270 may include the second metal and silicon, and is referred to as a metal silicide of the second metal. In some embodiments, the second silicide layer 270 comprises TiSi, NiSi, CoSi, or a combination thereof. In some embodiments, a second metal and a silicon-containing gas form the second silicide layer 270. In some embodiments, a component of the source / drain component 218 (e.g., silicon) diffuses through the metal phosphide layer 268 and reacts with the second metal to form the second silicide layer 270. The second silicide layer 270 may include a metal silicide M'. x Si y In M' x Si yIn this context, x is equal to or greater than about 1 and equal to or less than about 15, and y is greater than 0 and equal to or less than about 30. In some embodiments, the ratio of y to x is equal to or less than about 2.

[0051] In such Figure 5 and Figure 6 In some embodiments depicted, the profile of the metal phosphide layer 268 may be altered after the formation of the second silicide layer 270. This may be due to diffusion at the temperatures (e.g., silicon, metal) of the deposition process described above. In such embodiments, the metal phosphide layer 268 occupies a portion of the original source / drain component 218T (e.g., as shown in the image). Figure 4 (in the middle). In some other embodiments, the metal phosphide layer 268 is disposed on the exposed surface of the original source / drain component 218T (e.g., as shown in the middle). Figure 4 (In some embodiments, the metal phosphide layer 268 above the source / drain component 218 has a first thickness of about 0.5 nm to about 8 nm. The second silicide layer 270 above the source / drain component 218 and the metal phosphide layer 268 may have a second thickness of about 3 nm to about 10 nm. In some embodiments, the ratio of the second thickness to the first thickness is about 0.5 to about 20. Various parameters of operation (e.g., ALD process, CVD process) can be adjusted to achieve the designed composition and thickness of the second silicide layer 270, such as gas composition, temperature, duration, pressure, gas flow rate, source power, bias power, bias voltage, other suitable parameters, or combinations thereof.

[0052] In the depicted embodiment, the deposition process also forms a metal silicide residue layer 270' on the metal phosphide residue layer 268' above the surface (e.g., sidewalls) of the dielectric material of trench 256. The metal silicide residue layer 270' may include a second metal and / or a metal silicide of the second metal, as described above. The first total thickness of the metal phosphide residue layer 268' and the metal silicide residue layer 270' may be equal to or less than about 2 nm. If the first total thickness is too large (e.g., greater than about 2 nm), it may reduce the integrity of the source / drain contacts and may affect the reliability of the subsequent planarization process and structure 200. In some embodiments, the first total thickness is less than the second total thickness of the metal phosphide layer 268 and the second silicide layer 270. This may be due to the selectivity (e.g., epitaxial to dielectric selectivity) of the deposition processes in blocks 110 and 112 as described above, the first pullback process in block 110, and / or the second pullback process in block 112. In some embodiments, the precursors (e.g., a second metal, a silicon-containing gas) and process parameters of the deposition process in block 112 are selected such that the second metal and / or the metal silicide of the second metal is formed over the source / drain components 218 in greater quantities than over the dielectric material in the trench 256. The second pull-back process can be similar to the first pull-back process. In some embodiments, the second pull-back process removes the portion of the second metal and / or metal silicide located over the dielectric material in the trench 256, thus reducing the thickness of the second metal and / or metal silicide, thereby forming a metal silicide residual layer 270'. The second pull-back process can be performed after the deposition process in block 112.

[0053] refer to Figure 1 and Figure 7 Method 100 includes frame 114, in which a metal liner 272 is formed in trench 256. The metal liner 272 is conformally deposited over structure 200, including over a second silicide layer 270 and a metal silicide residual layer 270'. The metal liner 272 may have a thickness equal to or less than about 2 nm. In some embodiments, the metal liner 272 comprises a nitride or silicon nitride of Ti, Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof. For example, the metal liner 272 comprises TiN, TiSiN, ScN, or ScSiN. The metal in the metal liner 272 may be the same as or different from the first metal in the metal phosphide layer 268. The metal liner 272 may prevent diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers. In some embodiments, the metal liner 272 reduces electromigration of the metal filler layer formed thereon and slows oxygen diffusion into the metal filler layer.

[0054] refer to Figure 1 and Figure 8Method 100 includes frame 116, wherein a metal filler layer 274 is formed over structure 200 to fill trench 256. The metal filler layer 274 may be deposited over patterned mask layer 262. The metal filler layer 274 may include aluminum (Al), W, Mo, Co, Ru, Re, rhodium (Rh), iridium (Ir), Pt, Ni, Pd, other metals, or alloys thereof (e.g., NiAl, NiRu). In some embodiments, the metal filler layer 274 includes W. The conductivity of the metal filler layer 274 is greater than the conductivity of the source / drain component 218. In some embodiments, the metal filler layer 274 is formed by CVD, PVD, metal-organic CVD (MOCVD), plating, or other suitable processes.

[0055] refer to Figure 1 and Figure 9 Method 100 includes a frame 118 in which a planarization process (e.g., CMP process) is performed to remove excess material. The planarization process may remove the top portion of the patterned mask layer 262. After planarization, the remaining metal filler layer 274 forms the source / drain contact plug 274'. The source / drain contact plug 274', metal pad 272, first silicide layer 266, metal phosphide layer 268, second silicide layer 270, metal phosphide residue layer 268', and metal silicide residue layer 270' in the first type trench 256-1 together form the first source / drain contact 276-1. The source / drain contact plug 274', metal gasket 272, metal phosphide layer 268, second silicide layer 270, metal phosphide residue layer 268', and metal silicide residue layer 270' in the second type trench 256-2 together form the second source / drain contact 276-2. Depending on the context, the first source / drain contact 276-1 and the second source / drain contact 276-2 can be collectively referred to as or individually referred to as the source / drain contact 276.

[0056] The metal phosphide layer 268 and the second silicide layer 270 can form an additional dipole layer above the source / drain component 218, thereby reducing the resistance of the source / drain contact 276. Figure 19 A schematic diagram is shown at the interface 280 between the n-type source / drain component 218 (e.g., top source / drain component 218T) and the source / drain contact 276. Vector E is the electric field formed by the first dipole. The first dipole is formed by the top source / drain component 218T and the second silicide layer 270, without the metal phosphide layer 268. Vector E local The electric field is formed by the second dipole. The second dipole is formed by a metal phosphide layer 268 and a second silicide layer 270. The first and second dipoles are stacked together. Vector E NET It is vector E and vector E localThe sum of the electric fields. Because the second dipole has a dipole moment opposite to that of the first dipole, the vector E local In the direction opposite to vector E, as depicted, therefore E NET The magnitude of is smaller than the magnitude of vector E. E C It is the edge of the conduction band, E F It is the energy of the Fermi level, and E V It is the price band. The real and dashed curves represent the price bands formed by vector E and vector E, respectively. local Before and after compensation (e.g., summation), the E near the interface 280 in the top source / drain component 218T C / E V In vector E, by vector E local After compensation, E at interface 280 C / E V The electric field at the interface is reduced, as described above, by having a metal phosphide layer 268 and a second silicide layer 270, the interface Schottky barrier height (SBH) is reduced, and the resistance of the source / drain contact 276 is further reduced.

[0057] Structure 200 may undergo further processes to form various components and regions known in the art. For example, subsequent processing may form additional interlayer dielectric (ILD) layers, contacts / vias / lines, and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) configured to connect the various components to form functional circuitry over substrate 202. The functional circuitry may include one or more devices comprising semiconductor device 200. In a further embodiment of the example, the multilayer interconnects may include vertical interconnects (such as vias or contacts) and horizontal interconnects (such as metal lines). The various interconnect components may employ a variety of conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form copper-associated multilayer interconnect structures.

[0058] Figures 10 to 16 Partial cross-sectional views of optional structures 300, 400, 500, 200', 300', 400', and 500' are shown respectively. Optional structures 300, 400, 500, 200', 300', 400', and 500' are based on the description above. Figure 1 The components, such as grooves 256 (including first type grooves 256-1 and second type grooves 256-2), can be manufactured using method 100.

[0059] refer to Figure 10 ,and Figures 2 to 9 The differences in manufacturing and structure compared to the illustrated embodiments include the following. For example... Figure 9 The metal gasket 272 in the middle does not form in Figure 10 In structure 300, the operations in block 114 are omitted in the fabrication of structure 300. In structure 300, source / drain contact plugs 274' are deposited directly on the metal silicide residue layer 270' and the second silicide layer 270. The first source / drain contact 276-1 includes the source / drain contact plug 274', the first silicide layer 266, the metal phosphide layer 268, the second silicide layer 270, the metal phosphide residue layer 268', and the metal silicide residue layer 270' in the first type trench 256-1. The second source / drain contact 276-2 includes the source / drain contact plug 274', the metal phosphide layer 268, the second silicide layer 270, the metal phosphide residue layer 268', and the metal silicide residue layer 270' in the second type trench 256-2.

[0060] refer to Figure 11 ,and Figure 9 The differences in manufacturing and structure compared to the illustrated embodiments include the following. For example... Figure 9 The metal phosphide residue 268' and metal silicide residue 270' are not included in Figure 11 In structure 400, metal pad 272 is deposited directly on the surface of the dielectric material in the second silicide layer 272 and trench 256. The lack of sidewall residues (e.g., metal phosphide residue layer 268' and metal silicide residue layer 270') may be a result of the selectivity of the deposition processes in frames 110 and 112 (e.g., epitaxial to dielectric selectivity) and / or the third pull-back process in frames 110 and / or 112 (e.g., sidewall pull-back process). The third pull-back process can replace the first and second pull-back processes described above with a method similar to the first and second pull-back processes and removes most (e.g., more than about 95%) to all of the metal phosphide, second metal, and / or metal silicide from the surface of the dielectric material in trench 256 of structure 400. After the third pull-back process, the metal phosphide, second metal, and / or metal silicide on the surface of the dielectric material in trench 256 is negligible. The third pull-back process can be performed after the deposition process in frames 110 and / or 112. Figure 11 In the first source / drain contact 276-1, a source / drain contact plug 274', a metal gasket 272, a first silicide layer 266, a metal phosphide layer 268, and a second silicide layer 270 are included in a first type trench 256-1. The second source / drain contact 276-2 includes a source / drain contact plug 274', a metal gasket 272, a metal phosphide layer 268, and a second silicide layer 270 in a second type trench 256-2.

[0061] refer to Figure 12 ,and Figure 11The differences in manufacturing and structure compared to the illustrated embodiments include the following. For example... Figure 11 The metal gasket 272 in the middle does not form in Figure 12 In structure 500, the operations in block 114 are omitted in the fabrication of structure 500. In structure 500, the source / drain contact plug 274' is deposited directly on the second silicide layer 270 and on the sidewalls of the dielectric material in trench 256. The first source / drain contact 276-1 includes the source / drain contact plug 274', the first silicide layer 266, the metal phosphide layer 268, and the second silicide layer 270 in the first type trench 256-1. The second source / drain contact 276-2 includes the source / drain contact plug 274', the metal phosphide layer 268, and the second silicide layer 270 in the second type trench 256-2.

[0062] Figures 13 to 16 The structures 200', 300', 400', and 500' in the text are typically similar to... Figures 9 to 12 Structures 200, 300, 400, and 500 in the diagram do not form a second silicide layer 270 and a metal silicide residue layer 270'. In other words, the operations in box 112 are omitted in the formation of structures 200', 300', 400', and 500'.

[0063] refer to Figure 13 ,and Figure 9 Compared to the illustrated embodiment, additional differences in manufacturing and structure include the following: The thickness of the metal phosphide layer 268 is from about 3 nm to about 10 nm. The ratio of the thickness of the metal phosphide layer 268 to the thickness of the first silicide layer 266 is from about 0.5 to about 3. The metal phosphide residue layer 268' may have a thickness equal to or less than about 2 nm. The metal pad 272 is deposited directly on the metal phosphide layer 268 and the metal phosphide residue layer 268'. The first source / drain contact 276-1 includes the source / drain contact plug 274', the metal pad 272, the first silicide layer 266, the metal phosphide layer 268, and the metal phosphide residue layer 268' in the first type trench 256-1. The second source / drain contact 276-2 includes a source / drain contact plug 274', a metal gasket 272, a metal phosphide layer 268, and a metal phosphide residue layer 268' in a second type trench 256-2.

[0064] refer to Figure 14 ,and Figure 13 The differences in manufacturing and structure compared to the illustrated embodiments include the following. For example... Figure 13 The metal gasket 272 in the middle does not form in Figure 14In structure 300', the operations in block 114 are omitted in the fabrication of structure 300'. In structure 300', the source / drain contact plug 274' is directly deposited on the metal phosphide layer 268 and the metal phosphide residue layer 268' in trench 256. The first source / drain contact 276-1 includes the source / drain contact plug 274', the first silicide layer 266, the metal phosphide layer 268, and the metal phosphide residue layer 268' in the first type trench 256-1. The second source / drain contact 276-2 includes the source / drain contact plug 274', the metal phosphide layer 268, and the metal phosphide residue layer 268' in the second type trench 256-2.

[0065] refer to Figure 15 ,and Figure 13 The differences in manufacturing and structure compared to the illustrated embodiments include the following. For example... Figure 13 The metal phosphide residue 268' in is not included Figure 15 In structure 400', metal pad 272 is deposited directly on the surface of the dielectric material in the metal phosphide layer 268 and the trench 256 of structure 400'. The lack of sidewall residue (e.g., metal phosphide residue layer 268') may be a result of the selectivity of the deposition process in frame 110 (e.g., epitaxial to dielectric selectivity) and / or the fourth pull-back process in frame 110 (e.g., sidewall pull-back process). The fourth pull-back process can replace the first pull-back process as described above by using a method similar to the first pull-back process and removing most (e.g., more than about 95%) to all of the metal phosphide from the surface of the dielectric material in the trench 256 of structure 400'. After the fourth pull-back process, the metal phosphide on the surface of the dielectric material in the trench 256 is negligible. The fourth pull-back process can be performed after the deposition process in frame 110. Figure 15 In the first source / drain contact 276-1, a source / drain contact plug 274', a metal gasket 272, a first silicide layer 266, and a metal phosphide layer 268 are included in a first type trench 256-1. The second source / drain contact 276-2 includes a source / drain contact plug 274', a metal gasket 272, and a metal phosphide layer 268 in a second type trench 256-2.

[0066] refer to Figure 16 ,and Figure 15 The differences in manufacturing and structure compared to the illustrated embodiments include the following. For example... Figure 15 The metal gasket 272 in the middle does not form in Figure 16In structure 500', the operations in block 114 are omitted in the fabrication of structure 500'. In structure 500', the source / drain contact plugs 274' are deposited directly on the surface of the dielectric material in the metal phosphide layer 268 and the trench 256. Figure 16 In the first source / drain contact 276-1, there are source / drain contact plugs 274', a first silicide layer 266, and a metal phosphide layer 268 in a first type trench 256-1. The second source / drain contact 276-2 includes source / drain contact plugs 274' and a metal phosphide layer 268 in a second type trench 256-2.

[0067] exist Figures 9 to 16 In this embodiment, the first silicide layer 266 can be omitted (i.e., not formed). In such an embodiment, the metal phosphide layer 268 is formed directly on the bottom source / drain component 218B. In such an embodiment, without the first silicide layer 266, the composition of the bottom source / drain component 218B (e.g., silicon, germanium) can react with the metal phosphide during the deposition process in block 110, so the composition of the metal phosphide layer 268 on the bottom source / drain component 218B can be different from the composition of the metal phosphide layer 268 on the top source / drain component 218B as described above. Without forming the first silicide layer 266, the metal phosphide layer 268 on the bottom source / drain component 218B can include the metal phosphide described above, and also includes a metal germanium silicide phosphide of the first metal (M... x Si y Ge g P z ). In M x Si y Ge g P z In this equation, g can be equal to or greater than zero, and equal to or less than approximately 30. The ratio of the sum of g and y to x can be equal to or less than approximately 2 (i.e., (g+y) / x≤2). The ratio of z to x can be equal to or less than approximately 1.

[0068] Although Figures 2 to 15 A stacked transistor structure with GAA transistors is shown, but other instances of semiconductor devices (e.g., multi-gate devices, stacked transistor structures with any combination of transistors, such as planar, FinFET, nanosheet, and nanowire transistors) can benefit from aspects of the embodiments of this disclosure.

[0069] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits to semiconductor structures. For example, by depositing a metal precursor and a phosphorus-containing precursor to form a metal phosphide layer, the resistance of the source / drain contact can be reduced. Furthermore, by forming a silicide layer over the metal phosphide layer, forming an additional dipole between the silicide and metal phosphide layers, the SBH at the interface between the source / drain components and the source / drain contact can be reduced, and the resistance of the source / drain contact can be reduced. Therefore, the overall performance of the semiconductor device can be improved.

[0070] In one exemplary aspect, embodiments of this disclosure relate to a method. The method includes providing a structure. The structure includes: a bottom source / drain component; a bottom contact etch stop layer (CESL) disposed over the bottom source / drain component; a bottom interlayer dielectric (ILD) layer disposed over the bottom CESL; a top source / drain component disposed over the bottom ILD layer; a top CESL disposed over the top source / drain component and the bottom ILD layer; and a top ILD layer disposed over the top source / drain component. The thickness of the bottom CESL is less than the thickness of the bottom ILD layer, and the thickness of the top CESL is less than the thickness of the top ILD layer. The method further includes forming trenches extending in the top ILD layer and the bottom ILD layer, the trenches exposing the top source / drain component and the bottom source / drain component. The method further includes: depositing a metal precursor and a phosphorus-containing precursor in the trenches to form a metal phosphide layer over the top source / drain component and the bottom source / drain component; and forming a metal filler layer in the trenches and over the metal phosphide layer.

[0071] In some embodiments, the method further includes forming a silicide layer over a metal phosphide layer. In some embodiments, the metal phosphide layer comprises a first metal having a first electronegativity, and the silicide layer comprises a second metal having a second electronegativity greater than that of the first metal. In some embodiments, prior to depositing the metal precursor and the phosphorus-containing precursor in the trench, the method further includes forming a silicide layer over a bottom source / drain component but not over a top source / drain component, the silicide layer being disposed between the metal phosphide layer and the bottom source / drain component. In some embodiments, the metal precursor comprises a metal halide, a coordination complex, or a combination thereof, and the ligand of the coordination complex comprises tri-alkylcyclopentadienyl, di-alkylcyclopentadienyl-alkylamidinyl, tri-alkylamidinyl, tri-(alkylacetic acid), tris[N,N-bis(trimethylsilyl)amide], tetra(dialkylamide), cyclopentadienyl metal chloride, or a combination thereof. In some embodiments, the phosphorus-containing precursor comprises P, PH3, P2H4, P n H n+2 Phosphorus, phosphine, phosphine, phosphonobenzene, P(SiH3)3, P(Si(C) m H 2m+1 )3)3、P(Cx H 2x+1 3. P(C) y H 2y-1 3. Triphenylphosphine, tri(2-furanyl)phosphine, white phosphorus, or combinations thereof, wherein n is equal to or less than about 3, m is equal to or less than about 8, x is equal to or less than about 8, and y is equal to or greater than about 5 and equal to or less than about 8. In some embodiments, the deposition of the metal precursor and the phosphorus-containing precursor is carried out at a temperature of about 100 degrees Celsius to about 600 degrees Celsius. In some embodiments, prior to forming the metal filler layer, the method further includes depositing a metal liner in the trench and over the metal phosphide layer, the metal filler layer being disposed over the metal liner. In some embodiments, the metal phosphide layer further includes silicon.

[0072] In another exemplary aspect, embodiments of this disclosure relate to a method. The method includes providing a structure. The structure includes: an active region including a channel region and a source / drain region adjacent to the channel region; a gate structure located above the channel region; source / drain components located above the source / drain regions; a contact etch stop layer (CESL) located above the source / drain components; and an interlayer dielectric (ILD) layer located above the CESL. The method further includes: forming a trench in the CESL and the ILD layer to expose the source / drain components; providing a metal precursor and a phosphorus source in the trench to form a metal phosphide layer above the source / drain components; forming a silicide layer on the metal phosphide layer; and forming a metal fill layer in the trench.

[0073] In some embodiments, the metal precursor and the metal phosphide layer comprise a first metal, and the silicide layer comprises a second metal different from the first metal. In some embodiments, the first metal is an early transition metal. In some embodiments, the metal precursor comprises a metal halide, a coordination complex, or a combination thereof. In some embodiments, the metal phosphide layer comprises M m P n M x Si y P z Or a combination thereof, where m is equal to or greater than about 1 and equal to or less than about 15, n is greater than 0 and equal to or less than about 12, x is equal to or greater than about 1 and equal to or less than about 15, y is equal to or greater than 0 and equal to or less than about 30, and z is greater than 0 and equal to or less than about 12. In some embodiments, the ratio of y to x is equal to or less than about 2, and the ratio of n to m and the ratio of z to x are equal to or less than about 1. In some embodiments, a metal phosphide layer is also formed on the sidewalls of the trench.

[0074] In another exemplary aspect, embodiments of this disclosure relate to a semiconductor structure. The semiconductor structure includes a bottom transistor and a top transistor disposed above the bottom transistor. The bottom transistor includes a bottom source / drain component and a bottom dielectric layer disposed above the bottom source / drain component, and the top transistor includes a top source / drain component and a top dielectric layer disposed above the top source / drain component. The semiconductor structure further includes: contact components extending through the top and bottom dielectric layers; and a metal phosphide layer and a metal silicide layer disposed between the top source / drain component and the contact component, and between the bottom source / drain component and the contact component. The conductivity of the contact component is greater than the conductivity of the top and bottom source / drain components. The metal phosphide layer includes a first metal and phosphorus, and the metal silicide layer includes a second metal different from the first metal.

[0075] In some embodiments, a metal silicide layer is disposed between the metal phosphide layer and the contact component. In some embodiments, the first metal includes Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof, and the second metal includes Ti, Zr, V, Nb, Ta, Mo, W, Re, Ru, Os, Ni, Pd, Pt, or Zn, or combinations thereof. In some embodiments, the electronegativity of the second metal is greater than that of the first metal.

[0076] Some embodiments of this application provide a method for forming a semiconductor structure, including: providing a structure including: a bottom source / drain component; a bottom contact etch stop layer (CESL) disposed above the bottom source / drain component; a bottom interlayer dielectric (ILD) layer disposed above the bottom contact etch stop layer, wherein the thickness of the bottom contact etch stop layer is less than the thickness of the bottom interlayer dielectric layer; a top source / drain component disposed above the bottom interlayer dielectric layer; and a top contact etch stop layer disposed above the top source / drain component and the bottom interlayer dielectric layer; A top interlayer dielectric layer is disposed above the top source / drain component, wherein the thickness of the top contact etch stop layer is less than the thickness of the top interlayer dielectric layer; trenches are formed extending in the top interlayer dielectric layer and the bottom interlayer dielectric layer, wherein the trenches expose the top source / drain component and the bottom source / drain component; a metal precursor and a phosphorus-containing precursor are deposited in the trenches to form a metal phosphide layer above the top source / drain component and the bottom source / drain component; and a metal filler layer is formed in the trenches and above the metal phosphide layer.

[0077] In some embodiments, the method further includes forming a silicide layer over the metal phosphide layer. In some embodiments, the metal phosphide layer comprises a first metal having a first electronegativity, wherein the silicide layer comprises a second metal having a second electronegativity greater than that of the first metal. In some embodiments, prior to depositing the metal precursor and the phosphorus-containing precursor in the trench, a silicide layer is further formed over the bottom source / drain component, but not over the top source / drain component, wherein the silicide layer is disposed between the metal phosphide layer and the bottom source / drain component. In some embodiments, the metal precursor comprises a metal halide, a coordination complex, or a combination thereof, and wherein the ligand of the coordination complex comprises tri-alkylcyclopentadienyl, bis-alkylcyclopentadienyl-alkylamidinyl, tri-alkylamidinyl, tri-(alkylacetic acid), tris[N,N-bis(trimethylsilyl)amide], tetra(dialkylamide), cyclopentadienyl metal chloride, or a combination thereof. In some embodiments, the phosphorus-containing precursor includes P, PH3, P2H4, and P. n H n+2 Phosphorus, phosphine, phosphine, phosphonobenzene, P(SiH3)3, P(Si(C) m H 2m+1 )3)3、P(C x H 2x+1 3. P(C) y H 2y-1 3. Triphenylphosphine, tri(2-furanyl)phosphine, white phosphorus, or combinations thereof, wherein n is equal to or less than about 3, m is equal to or less than about 8, x is equal to or less than about 8, and y is equal to or greater than about 5 and equal to or less than about 8. In some embodiments, the deposition of the metal precursor and the phosphorus-containing precursor is performed at a temperature of about 100 degrees Celsius to about 600 degrees Celsius. In some embodiments, prior to forming the metal filler layer, a metal liner is further deposited in the trench and over the metal phosphide layer, wherein the metal filler layer is disposed over the metal liner. In some embodiments, the metal phosphide layer further includes silicon.

[0078] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a structure including: an active region including a channel region and a source / drain region adjacent to the channel region; a gate structure located above the channel region; a source / drain component located above the source / drain region; a contact etch stop layer (CESL) located above the source / drain component; and an interlayer dielectric (ILD) layer located above the contact etch stop layer; forming a trench in the contact etch stop layer and the interlayer dielectric layer to expose the source / drain component; providing a metal precursor and a phosphorus source in the trench to form a metal phosphide layer above the source / drain component; forming a silicide layer on the metal phosphide layer; and forming a metal fill layer in the trench.

[0079] In some embodiments, the metal precursor and the metal phosphide layer comprise a first metal, and wherein the silicide layer comprises a second metal different from the first metal. In some embodiments, the first metal is an early transition metal. In some embodiments, the metal precursor comprises a metal halide, a coordination complex, or a combination thereof. In some embodiments, the metal phosphide layer comprises M m P n M x Si y P z Or a combination thereof, wherein m is equal to or greater than about 1 and equal to or less than about 15, n is greater than 0 and equal to or less than about 12, x is equal to or greater than about 1 and equal to or less than about 15, y is equal to or greater than 0 and equal to or less than about 30, and z is greater than 0 and equal to or less than about 12. In some embodiments, the ratio of y to x is equal to or less than about 2, and wherein the ratio of n to m and the ratio of z to x are equal to or less than about 1. In some embodiments, the metal phosphide layer is also formed on the sidewalls of the trench.

[0080] Some embodiments of this application provide a semiconductor structure including: a bottom transistor and a top transistor, the top transistor being disposed above the bottom transistor, wherein the bottom transistor includes a bottom source / drain component and a bottom dielectric layer disposed above the bottom source / drain component, and wherein the top transistor includes a top source / drain component and a top dielectric layer disposed above the top source / drain component; a contact component extending through the top dielectric layer and the bottom dielectric layer, wherein the conductivity of the contact component is greater than the conductivity of the top source / drain component and the bottom source / drain component; and a metal phosphide layer and a metal silicide layer disposed between the top source / drain component and the contact component and between the bottom source / drain component and the contact component, wherein the metal phosphide layer includes a first metal and phosphorus, and wherein the metal silicide layer includes a second metal different from the first metal.

[0081] In some embodiments, the metal silicide layer is disposed between the metal phosphide layer and the contact member. In some embodiments, the first metal comprises Zr, Hf, Sc, Y, Yb, La, Er, Dy, Ce, or combinations thereof, and the second metal comprises Ti, Zr, V, Nb, Ta, Mo, W, Re, Ru, Os, Ni, Pd, Pt, or Zn, or combinations thereof. In some embodiments, the electronegativity of the second metal is greater than that of the first metal.

[0082] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Provides a structure, including: Bottom source / drain components; A bottom contact etch stop layer is disposed above the bottom source / drain components; A bottom interlayer dielectric layer is disposed above the bottom contact etch stop layer, wherein the thickness of the bottom contact etch stop layer is less than the thickness of the bottom interlayer dielectric layer; The top source / drain component is disposed above the bottom interlayer dielectric layer; A top contact etch stop layer is disposed above the top source / drain components and the bottom interlayer dielectric layer; and A top interlayer dielectric layer is disposed above the top source / drain component, wherein the thickness of the top contact etch stop layer is less than the thickness of the top interlayer dielectric layer; Trenches are formed extending in the top interlayer dielectric layer and the bottom interlayer dielectric layer, wherein the trenches expose the top source / drain components and the bottom source / drain components; Metal precursors and phosphorus-containing precursors are deposited in the trench to form a metal phosphide layer over the top source / drain components and the bottom source / drain components; and A metal filler layer is formed in the trench and above the metal phosphide layer.

2. The method according to claim 1, further comprising forming a silicide layer over the metal phosphide layer.

3. The method of claim 2, wherein, The metal phosphide layer comprises a first metal having a first electronegativity. The silicide layer includes a second metal having a second electronegativity greater than that of the first metal.

4. The method of claim 1, further comprising, before depositing the metal precursor and the phosphorus-containing precursor in the trench, forming a silicide layer above the bottom source / drain component, but not above the top source / drain component. wherein The silicide layer is disposed between the metal phosphide layer and the bottom source / drain component.

5. The method of claim 1, wherein, The metal precursor includes metal halides, coordination complexes, or combinations thereof, and The ligands of the coordination complex include tri-alkylcyclopentadienyl, bis-alkylcyclopentadienyl-alkylamidinyl, tri-alkylamidinyl, tri-(alkylacetic acid), tris[N,N-bis(trimethylsilyl)amide], tetra(dialkylamide), cyclopentadienyl metal chloride, or combinations thereof.

6. The method of claim 1, wherein, The phosphorus-containing precursor includes P, PH3, P2H4, P n H n+2 , phosphorus, phosphine, phosphane, phosphabenzene, P(SiH3)3, P(Si(C m H 2m+1 )3)3, P(C x H 2x+1 )3, P(C y H 2y-1 )3, triphenylphosphine, tris(2-furyl)phosphine, white phosphorus, or a combination thereof, Where n is equal to or less than about 3, m is equal to or less than about 8, x is equal to or less than about 8, and y is equal to or greater than about 5 and equal to or less than about 8.

7. The method of claim 1, wherein, The deposition of the metal precursor and the phosphorus-containing precursor is carried out at a temperature of about 100 degrees Celsius to about 600 degrees Celsius.

8. The method of claim 1, wherein, Prior to forming the metal filler layer, a metal liner is also deposited in the trench and over the metal phosphide layer. The metal filler layer is disposed above the metal liner.

9. A method for forming a semiconductor structure, comprising: Provides a structure, including: The active region includes a channel region and a source / drain region adjacent to the channel region; A gate structure is located above the channel region; The source / drain component is located above the source / drain region; A contact etch stop layer is located above the source / drain components; and An interlayer dielectric layer is located above the contact etch stop layer; Trenches are formed in the contact etch stop layer and the interlayer dielectric layer to expose the source / drain components; A metal precursor and a phosphorus source are provided in the trench, thereby forming a metal phosphide layer above the source / drain components; A silicide layer is formed on the metal phosphide layer; and A metal filling layer is formed in the trench.

10. A semiconductor structure comprising: A bottom transistor and a top transistor, the top transistor being disposed above the bottom transistor, wherein the bottom transistor includes a bottom source / drain component and a bottom dielectric layer disposed above the bottom source / drain component, and wherein the top transistor includes a top source / drain component and a top dielectric layer disposed above the top source / drain component; A contact component extending through the top dielectric layer and the bottom dielectric layer, wherein the conductivity of the contact component is greater than the conductivity of the top source / drain component and the bottom source / drain component; and A metal phosphide layer and a metal silicide layer are disposed between the top source / drain component and the contact component, and between the bottom source / drain component and the contact component. The metal phosphide layer comprises a first metal and phosphorus. The metal silicide layer includes a second metal that is different from the first metal.

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