Chip packaging structure and chip packaging method
By forming a vertical interconnect structure with conductive lower and upper pillars on the substrate, the problems of long interconnect paths and high complexity in multi-chip stacked packaging are solved, achieving efficient vertical conductive interconnect and improved yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JCET SEMICON (SHAOXING) CO LTD
- Filing Date
- 2026-04-13
- Publication Date
- 2026-06-30
Smart Images
Figure CN122318890A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip packaging, and in particular to a chip packaging structure and a chip packaging method. Background Technology
[0002] In the current chip packaging field, to meet the ever-increasing demand for storage density in memory chips, multi-chip stacking packaging technology is commonly used. In related technologies, for memory chips with only side pads (such as Low Power Double Data Rate SDRAM, or LPDDR), wire bonding is primarily used to achieve electrical connections between stacked chips layer by layer, or integration is achieved through package-on-package (PoP) stacking.
[0003] However, while the above methods can meet the requirements of stacked packaging to a certain extent, when the number of stacked layers increases, there are often problems such as longer interconnect paths, larger space occupation, more complex wiring, increased package thickness and process complexity, which in turn have an adverse impact on packaging efficiency, interconnect reliability and product yield. Summary of the Invention
[0004] Based on this, the embodiments of this application provide a chip packaging structure and a chip packaging method, which can efficiently realize vertical conductive interconnection of chip stacking structure, which is beneficial to simplify process steps and improve packaging yield.
[0005] To achieve the above objectives, some embodiments of this application provide a chip packaging method. This chip packaging method includes the following steps.
[0006] Before performing the dicing process, conductive lower pillars that are electrically connected to the first pads are formed on the surface of the first pads of each chip body on the substrate.
[0007] The dicing process is performed so that the chip body after the formation of conductive lower pillars constitutes the chip to be packaged.
[0008] Multiple chips to be packaged are stacked from bottom to top on one side of a temporary carrier board, with each chip body staggered and the top surface of each conductive lower pillar exposed away from the chip body. The area above each conductive lower pillar away from the chip body is a clear area, thus obtaining a chip stacking structure.
[0009] A molding compound is formed to encapsulate the stacked chip structure.
[0010] A conductive column receiving groove is formed within the molding layer to expose the corresponding conductive lower column.
[0011] A conductive upper column is formed within the conductive column receiving groove, electrically connected to the conductive lower column. The conductive upper column and the conductive lower column are integrated to form a vertical conductive column.
[0012] In some embodiments, the chip stacking structure includes a first step structure and a second step structure; multiple chips to be packaged are stacked from bottom to top on one side of a temporary carrier board, such that the chip bodies are staggered and the top surface of each conductive lower post is exposed away from the chip body, and the area above each conductive lower post away from the chip body is a clear area, thereby obtaining the chip stacking structure, including the following steps.
[0013] On one side of the temporary carrier, the first target number of chip bodies are stacked from bottom to top as steps and extend along a first direction parallel to the temporary carrier to form a first stepped structure, such that the conductive lower pillars on each chip body in the first stepped structure are exposed on the exposed surface of the corresponding step.
[0014] On a portion of the surface of the top step in the first step structure, a second target number of chip bodies are stacked from bottom to top as steps and extend along a second direction parallel to the temporary carrier to form a second step structure, such that the conductive lower pillars on each chip body in the second step structure are exposed on the exposed surface of the corresponding step.
[0015] The first direction and the second direction are opposite.
[0016] In some embodiments, the number of the first target and the number of the second target are the same.
[0017] In some embodiments, forming a conductive post receiving groove within the molding layer for exposing a corresponding conductive lower post includes the following steps.
[0018] Using laser drilling technology, reference holes of the target depth are formed in the encapsulation layer on the side of each conductive lower post away from the first pad, so that the reference holes are located directly above the corresponding conductive lower post, and there is a gap between the bottom surface of the reference hole and the top surface of the corresponding conductive lower post.
[0019] The molding layer is vertically etched based on the reference hole until the conductive lower post is exposed, forming a conductive post receiving groove.
[0020] In some embodiments, the depth of each reference hole is the same; the distance from the top surface of the conductive lower pillar on different chip bodies to the bottom surface of the corresponding reference hole is different.
[0021] In some embodiments, forming a conductive upper column electrically connected to a conductive lower column within a conductive column receiving groove includes the following steps.
[0022] A conductive material layer is formed on the surface of the conductive pillar receiving groove and the encapsulation layer.
[0023] Grinding removes the conductive material layer from the surface of the plastic sealant, leaving the conductive material layer remaining in the conductive post receiving groove to form the conductive upper post.
[0024] In some embodiments, after forming an electrically connected conductive upper post within a conductive post receiving groove, the chip packaging method further includes the following steps.
[0025] A redistribution layer electrically connected to the vertical conductive pillar is formed on the side of the molding layer away from the temporary carrier.
[0026] Multiple second pads electrically connected to the redistribution layer are formed on the side of the redistribution layer opposite to the molding layer.
[0027] Multiple bump structures electrically connected to the second pad are formed on the side of the second pad away from the redistribution layer.
[0028] On the other hand, this application also provides a chip packaging structure according to some embodiments; the chip packaging structure can be manufactured by the chip packaging method as described in the preceding aspect of this application.
[0029] In some embodiments, the chip packaging structure includes a chip stack structure, a molding compound, and conductive upper pillars. The chip stack structure includes multiple chips to be packaged stacked from bottom to top; each chip to be packaged includes: a chip body, a first pad located on the chip body, and a conductive lower pillar located on the surface of the first pad and electrically connected to the first pad; wherein the chip bodies are staggered, and the conductive lower pillars are staggered. The molding compound covers the chip stack structure and has multiple conductive pillar receiving grooves for exposing corresponding conductive lower pillars. The conductive upper pillars are located within the conductive pillar receiving grooves, electrically connected to the conductive lower pillars, and integrally form vertical conductive pillars.
[0030] In some embodiments, the orthographic projection of the conductive upper pillar onto the chip body coincides with the orthographic projection of the conductive lower pillar onto the chip body; and / or, the heights of the conductive lower pillars are equal; the heights of different conductive upper pillars are negatively correlated with the stacking height of the corresponding chip body in the chip stacking structure.
[0031] In some embodiments, the chip stacking structure includes a first step structure and a second step structure; the first step structure includes a first target number of chip bodies and vertical conductive pillars located on the first target number of chip bodies; the second step structure includes a second target number of chip bodies and vertical conductive pillars located on the second target number of chip bodies. The first target number of chip bodies are stacked from bottom to top as steps and extend along a first direction to form the first step structure, and each vertical conductive pillar in the first step structure is located on the surface of the corresponding step that is not covered by an adjacent step; the second step structure is located on a portion of the surface of the top step in the first step structure; the second target number of chip bodies are stacked from bottom to top as steps and extend along a second direction to form the second step structure, and each vertical conductive pillar in the second step structure is located on the surface of the corresponding step that is not covered by an adjacent step; the first direction and the second direction are parallel to and opposite to the surface of the first pad.
[0032] The embodiments of this application may have, or at least have, the following advantages:
[0033] In this embodiment, conductive lower pillars are formed on the surface of the first pads of each chip body on the substrate before the dicing process. This prefabrication of the conductive lower pillars is completed while the chip body is still at the wafer level, converting pads unsuitable for vertical interconnects into pillar structures suitable for vertical interconnects. Afterward, the substrate is diced to obtain multiple chips suitable for vertical interconnects in batches. These chips are then stacked from bottom to top to obtain a chip stack structure, where multiple chip bodies are staggered, the top surfaces of the conductive lower pillars are exposed, and the upper region is a clear area. This not only enables high-density stacking integration of multiple chip bodies but also reserves space for vertical interconnects in the chip stack structure. After encapsulating the chip stack structure into a single unit using a molding compound, multiple conductive pillar receiving grooves are formed in one step using the molding compound, and these grooves are directly filled to form conductive upper pillars. This allows the conductive upper pillars and conductive lower pillars to form a vertical conductive pillar as a single unit. In this way, vertical electrical interconnection of multiple layers of chips to be packaged is achieved in one step. This eliminates the need for wire bonding, which has a high area footprint, and also omits multiple alignment, electroplating, and polishing steps in the layer-by-layer interconnection process. This improves packaging efficiency and achieves reliable interconnection of the chip stack structure, thereby increasing yield. Through the combined effect of these technical features, this application can efficiently achieve vertical conductive interconnection of the chip stack structure, which helps simplify process steps and improve packaging yield.
[0034] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a flowchart illustrating a chip packaging method provided in some embodiments;
[0037] Figure 2 This is a flowchart illustrating step S300 provided in some embodiments;
[0038] Figure 3 This is a flowchart illustrating step S500 provided in some embodiments;
[0039] Figure 4 This is a flowchart illustrating step S600 provided in some embodiments;
[0040] Figure 5 This is a flowchart illustrating another chip packaging method provided in some embodiments;
[0041] Figure 6 This is a schematic diagram of the structure of a substrate provided in some embodiments;
[0042] Figure 7 This is a schematic diagram of a structure obtained after forming a conductive lower column, as provided in some embodiments;
[0043] Figure 8 This is a schematic diagram of the structure of a chip to be packaged provided in some embodiments;
[0044] Figure 9 This is a schematic diagram of a structure obtained after forming a chip stacking structure, provided in some embodiments;
[0045] Figure 10 This is a schematic diagram of a structure obtained after forming a molding layer, provided in some embodiments;
[0046] Figure 11 This is a schematic diagram of a structure obtained after forming a reference hole, as provided in some embodiments;
[0047] Figure 12 This is a schematic diagram of a structure obtained after forming a conductive pillar receiving groove, as provided in some embodiments;
[0048] Figure 13 This is a schematic diagram of a structure obtained after forming a conductive material layer, provided in some embodiments;
[0049] Figure 14 This is a schematic diagram of a structure obtained after forming a conductive upper pillar, as provided in some embodiments;
[0050] Figure 15 This is a schematic diagram of a structure obtained after forming a redistribution layer and a second pad, provided in some embodiments;
[0051] Figure 16 This is a schematic diagram of a structure obtained after forming a bump structure, provided in some embodiments;
[0052] Figure 17 This is a schematic diagram of a chip packaging structure provided in some embodiments.
[0053] Explanation of reference numerals in the attached figures:
[0054] 1-Chip to be packaged, C-Chip body, P1-First pad, H1-Conductive lower pillar, H2-Conductive upper pillar, H-Vertical conductive pillar, 2-Temporary carrier board, 3-Chip stacking structure, S1-First step structure, S2-Second step structure, 4-Bonding layer, 5-Protective layer, 6-Molding layer, 7-Chip bonding film, G1-Reference hole, G2-Conductive pillar receiving groove, 8-Conductive material layer, 9-Redistribution layer, 91-Dielectric layer, 92-Metallic trace layer, P2-Second pad, 10-Bump structure. Detailed Implementation
[0055] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0057] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0058] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0059] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.
[0060] Based on this, the embodiments of this application provide a chip packaging structure and a chip packaging method, which can efficiently realize vertical conductive interconnection of chip stacking structure, which is beneficial to simplify process steps and improve packaging yield.
[0061] In some embodiments, please refer to Figure 1 The chip packaging method includes the following steps S100~S600.
[0062] S100, before performing the dicing process, conductive lower pillars that are electrically connected to the first pads are formed on the surface of the first pads of each chip body on the substrate.
[0063] S200 performs a dicing process, which transforms the chip body after the formation of conductive lower pillars into a chip to be packaged.
[0064] S300: Multiple chips to be packaged are stacked from bottom to top on one side of a temporary carrier board, with each chip body stacked in a staggered manner. The top surface of each conductive lower pillar is exposed away from the chip body, and the area above each conductive lower pillar away from the chip body is a clear area, thus obtaining a chip stacking structure.
[0065] S400 forms a molding compound that encapsulates the stacked chip structure.
[0066] S500, a conductive post receiving groove is formed within the molding layer to expose the corresponding conductive lower post.
[0067] S600, an upper conductive column electrically connected to the lower conductive column is formed in the conductive column receiving groove, and the upper conductive column and the lower conductive column are integrated to form a vertical conductive column.
[0068] In this embodiment, conductive lower pillars are formed on the surface of the first pads of each chip body on the substrate before the dicing process. This prefabrication of the conductive lower pillars is completed while the chip body is still at the wafer level, converting pads unsuitable for vertical interconnects into pillar structures suitable for vertical interconnects. Afterward, the substrate is diced to obtain multiple chips suitable for vertical interconnects in batches. These chips are then stacked from bottom to top to obtain a chip stack structure, where multiple chip bodies are staggered, the top surfaces of the conductive lower pillars are exposed, and the upper region is a clear area. This not only enables high-density stacking integration of multiple chip bodies but also reserves space for vertical interconnects in the chip stack structure. After encapsulating the chip stack structure into a single unit using a molding compound, multiple conductive pillar receiving grooves are formed in one step using the molding compound, and these grooves are directly filled to form conductive upper pillars. This allows the conductive upper pillars and conductive lower pillars to form a vertical conductive pillar as a single unit. In this way, vertical electrical interconnection of multiple layers of chips to be packaged is achieved in one step. This eliminates the need for wire bonding, which has a high area footprint, and also omits multiple alignment, electroplating, and polishing steps in the layer-by-layer interconnection process. This improves packaging efficiency and achieves reliable interconnection of the chip stack structure, thereby increasing yield. Through the combined effect of these technical features, this application can efficiently achieve vertical conductive interconnection of the chip stack structure, which helps simplify process steps and improve packaging yield.
[0069] In some embodiments, before step S300, the chip packaging method further includes the following steps S301 to S302.
[0070] S301, a bonding layer is formed on one side of the temporary carrier.
[0071] S302, a protective layer is formed on the side of the bonding layer opposite to the temporary carrier in the direction perpendicular to the temporary carrier.
[0072] Accordingly, the chip stacking structure in step S300 is formed on the side of the protective layer that is away from the bonding layer in the direction perpendicular to the temporary carrier.
[0073] In some embodiments, the chip stacking structure includes a first-step structure and a second-step structure; see also Figure 2 Step S300 includes the following steps S310~S320.
[0074] S310, on one side of the temporary carrier, the first target number of chip bodies are stacked from bottom to top as steps and extended along a first direction parallel to the temporary carrier to form a first stepped structure, and the conductive lower pillars on each chip body in the first stepped structure are exposed on the exposed surface of the corresponding step.
[0075] S320, on a portion of the surface of the top step in the first stepped structure, a second target number of chip bodies are stacked from bottom to top as steps and extend along a second direction parallel to the temporary carrier to form a second stepped structure, such that the conductive lower pillars on each chip body in the second stepped structure are exposed on the exposed surface of the corresponding step; wherein, the first direction and the second direction are opposite.
[0076] In some embodiments, the number of the first target and the number of the second target are the same.
[0077] In some embodiments, please refer to Figure 3 Step S500 includes the following steps S510~S520.
[0078] S510 uses laser drilling technology to form reference holes of target depth in the encapsulation layer on the side of each conductive lower post away from the first pad, so that the reference holes are located directly above the corresponding conductive lower post, and there is a gap between the bottom surface of the reference hole and the top surface of the corresponding conductive lower post.
[0079] S520 uses vertical etching of the encapsulation layer based on the reference hole until the conductive lower post is exposed, forming a conductive post receiving groove.
[0080] In this embodiment, a laser-drilled hole is used to precisely position the reference hole directly above each conductive lower post, quickly forming a reference hole. Furthermore, a gap is created between the bottom surface of the reference hole and the top surface of the corresponding conductive lower post, preventing the laser from directly impacting the conductive lower post and causing thermal damage to its surface. Subsequently, the molding compound is etched vertically based on the reference hole, using the sidewall of the reference hole as a reference for the etching direction. This helps ensure the verticality of the conductive post receiving groove and accurately exposes each conductive lower post.
[0081] In some embodiments, the depth of each reference hole is the same; the distance from the top surface of the conductive lower pillar on different chip bodies to the bottom surface of the corresponding reference hole is different.
[0082] In some embodiments, please refer to Figure 4 Step S600 includes the following steps S610~S620.
[0083] S610, a conductive material layer is formed on the surface of the conductive post receiving groove and the encapsulation layer.
[0084] S620, grinding removes the conductive material layer from the surface of the plastic sealant, so that the conductive material layer remaining in the conductive post receiving groove constitutes the conductive upper post.
[0085] In this embodiment, a conductive material layer filling multiple conductive pillar receiving grooves is formed in one step, and conductive upper pillars filling each conductive pillar receiving groove are formed through a one-step grinding process; thus, vertical electrical interconnection of multiple layers of chips to be packaged is achieved in one step, effectively improving process efficiency.
[0086] In some embodiments, please refer to Figure 5 After step S600, the chip packaging method further includes the following steps S700~S900.
[0087] S700, a redistribution layer electrically connected to the vertical conductive pillar is formed on the side of the molding layer away from the temporary carrier.
[0088] S800 forms multiple second pads electrically connected to the redistribution layer on the side of the redistribution layer opposite to the molding compound.
[0089] S900 forms multiple bump structures electrically connected to the second pad on the side of the second pad away from the redistribution layer.
[0090] In some embodiments, please continue reading Figure 5 After step S900, the chip packaging method further includes the following step S1000.
[0091] S1000, removes the bonding layer and temporary carrier.
[0092] It should be understood that, although Figures 1-5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0093] To more clearly illustrate the chip packaging methods in the above embodiments, please refer to the following embodiments. Figures 6-17 I understand.
[0094] In some embodiments, the chip packaging method includes the following steps S100~S600.
[0095] In step S100, please refer to Figures 6-7 Before performing the dicing process, conductive lower pillars H1 are formed on the surface of the first pad P1 of each chip body C on the substrate, which are electrically connected to the first pad P1.
[0096] For example, the substrate can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be such as a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of protection of this application.
[0097] For example, the chip body C includes, but is not limited to, memory chips; for example, it may be Low Power Double Data Rate SDRAM (LPDDR).
[0098] In some embodiments, please refer to Figure 6 The first pad P1 is located on one edge of the front side of the chip body C.
[0099] For example, the material of the first pad P1 includes, but is not limited to, conductive metals; for example, it can be aluminum (Al) or the like.
[0100] For example, the material of the conductive lower pillar H1 includes, but is not limited to, conductive metals; for example, it can be copper (Cu).
[0101] In some examples, please refer to Figure 6 The first pad P1 is embedded in the chip body C. The first pad P1 is flush with the surface of the chip body C in a direction perpendicular to the chip body C, away from the top surface of the chip body C.
[0102] In step S200, please refer to Figure 8 The dicing process is performed so that the chip body C after forming the conductive lower pillar H1 constitutes the chip to be packaged 1.
[0103] It should be noted that the chip to be packaged 1 includes the chip body C, the first pad P1, and the conductive lower post H1.
[0104] In step S300, please refer to Figure 9 Multiple chips 1 to be packaged are stacked from bottom to top on one side of the temporary carrier board 2, so that the chip bodies C are staggered and the top surface of each conductive lower pillar H1 is exposed away from the chip body C. The area above each conductive lower pillar H1 away from the chip body C is a clear area, thus obtaining the chip stacking structure 3.
[0105] In some embodiments, before step S300, the chip packaging method further includes the following steps S301 to S302.
[0106] In step S301, please refer to Figure 9 A bonding layer 4 is formed on one side of the temporary carrier plate 2.
[0107] For example, the bonding layer 4 includes, but is not limited to, a photolysis layer formed using a photoresponsive material.
[0108] In step S302, please continue reading. Figure 9 A protective layer 5 is formed on the side of the bonding layer 4 that is away from the temporary carrier plate 2 in the direction perpendicular to the temporary carrier plate 2.
[0109] For example, the material of protective layer 5 includes, but is not limited to, insulating materials.
[0110] Accordingly, the chip stack structure 3 in step S300 is formed on the side of the protective layer 5 facing away from the bonding layer 4 in the direction perpendicular to the temporary carrier 2.
[0111] In some examples, the back side of the chip body C is covered with a chip adhesive film 7. Each layer of chip body C is bonded to a portion of the front side of the adjacent layer of chip body C below via the chip adhesive film 7. It should be noted that the bottom chip body C in the chip stack structure 3 is bonded to the protective layer 5 via the chip adhesive film 7.
[0112] In some embodiments, the chip stacking structure 3 includes a first step structure S1 and a second step structure S2; step S300 includes the following steps S310~S320.
[0113] In step S310, please refer to Figure 9 On one side of the temporary carrier board 2, the first target number of chip bodies C are stacked from bottom to top as steps and extended along a first direction (e.g., the X direction) parallel to the temporary carrier board 2 to form a first stepped structure S1, such that the conductive lower pillars H1 on each chip body C in the first stepped structure S1 are exposed on the exposed surface of the corresponding step.
[0114] For example, the number of the first target is greater than or equal to 2.
[0115] For example, in the first stepped structure S1, the width of each step is equal.
[0116] In step S320, please continue reading. Figure 9 On a portion of the surface of the top step in the first stepped structure S1, a second target number of chip bodies C are stacked from bottom to top as steps and extended along a second direction (e.g., the Z direction) parallel to the temporary carrier 2 to form a second stepped structure S2, such that the conductive lower pillars H1 on each chip body C in the second stepped structure S2 are exposed on the exposed surface of the corresponding step; wherein the first direction (e.g., the X direction) and the second direction (e.g., the Z direction) are opposite.
[0117] For example, the number of the second objective is greater than or equal to 2.
[0118] For example, in the second-step structure S2, the step widths of each step are equal.
[0119] It should be noted that the step width of each step in the first step structure S1 may or may not be equal to the step width of each step in the second step structure S2, and this application does not impose any restrictions on this.
[0120] In some embodiments, the number of the first target and the number of the second target are the same.
[0121] In step S400, please refer to Figure 10 This forms a molding layer 6 that covers the chip stack structure 3.
[0122] For example, the molding layer 6 includes, but is not limited to, epoxy resin, etc.
[0123] It should be noted that the molding layer 6 covers the surface of the protective layer 5 and encapsulates the chip bonding film 7, the chip body C, the first pad P1, and the conductive lower post H1.
[0124] In step S500, a conductive post receiving groove G2 for exposing the corresponding conductive lower post H1 is formed in the molding layer 6.
[0125] In some embodiments, step S500 includes the following steps S510 to S520.
[0126] In step S510, please refer to Figure 11 Using laser drilling technology, reference holes G1 of the target depth are formed in the plastic encapsulation layer 6 on the side of each conductive lower post H1 away from the first pad P1, so that the reference holes G1 are located directly above the corresponding conductive lower post H1, and there is a gap between the bottom surface of the reference hole G1 and the top surface of the corresponding conductive lower post H1.
[0127] In some examples, the top surface of the encapsulation layer 6 before laser aperture opening is separated from the top surface of the temporary carrier 2 and the top surface of the conductive lower pillar H1 on the top chip body C, with a target spacing.
[0128] For example, the target depth is less than the target spacing.
[0129] In some embodiments, the reference holes G1 corresponding to the multiple conductive lower pillars H1 are formed based on the same laser drilling process.
[0130] In some embodiments, the depth of each reference hole G1 is the same; the distance between the top surface of the conductive lower pillar H1 on different chip bodies C and the bottom surface of the corresponding reference hole G1 is different.
[0131] For example, the distance between the top surface of the conductive lower pillar H1 on different chip bodies C and the bottom surface of the corresponding reference hole G1 is negatively correlated with the stacking height of the corresponding chip body C in the chip stacking structure 3.
[0132] In step S520, please refer to Figure 12 Based on the reference hole G1, the plastic sealing layer 6 is vertically etched until the conductive lower post H1 is exposed, forming the conductive post receiving groove G2.
[0133] For example, the etching process used in step S520 includes anisotropic etching; for example, it may be a dry etching process.
[0134] In some embodiments, the conductive post receiving grooves G2 corresponding to the multiple conductive lower posts H1 are formed based on the same etching process.
[0135] It should be noted that the etching process in step S520 is not only used to vertically etch the molding layer 6 so that the reference hole G1 extends downward to form the conductive pillar receiving groove G2, but also used to refine the bottom and wall of the groove to improve the flatness of the inner wall of the conductive pillar receiving groove G2, so as to accurately expose the top surface of the conductive lower pillar H1.
[0136] In step S600, a conductive upper column H2 electrically connected to the conductive lower column H1 is formed in the conductive column receiving groove G2. The conductive upper column H2 and the conductive lower column H1 are integrally formed to constitute a vertical conductive column H.
[0137] In some examples, the orthographic projection of the conductive upper pillar H2 onto the chip body C coincides with the orthographic projection of the conductive lower pillar H1 onto the chip body C.
[0138] In some embodiments, the conductive upper column H2 and the conductive lower column H1 are made of the same material.
[0139] In some embodiments, step S600 includes the following steps S610 to S620.
[0140] In step S610, please refer to Figure 13 A conductive material layer 8 is formed on the surface of the conductive pillar receiving groove G2 and the encapsulation layer 6.
[0141] For example, the material of the conductive material layer 8 includes, but is not limited to, conductive metals, such as copper (Cu).
[0142] For example, the formation process of the conductive material layer 8 includes, but is not limited to, electrochemical deposition processes, such as electroplating processes.
[0143] It should be added that, before step S610, step S600 also includes the following step S601.
[0144] In step S601, a seed layer is formed on at least the surface of the exposed conductive lower column H1 on the wall of the conductive column receiving groove G2, the bottom of the conductive column receiving groove G2, and the surface of the plastic sealing layer 6.
[0145] For example, the seed layer can be a single-layer structure or a multi-layer structure; for instance, in an embodiment where the seed layer is a multi-layer structure, the seed layer may include an adhesion layer and a conductive seed layer.
[0146] For example, the materials of the adhesion layer include, but are not limited to, titanium (Ti), tantalum (Ta), or their nitrides, and the materials of the conductive seed layer include, but are not limited to, copper (Cu).
[0147] For example, the formation process of the seed layer includes, but is not limited to, physical vapor deposition processes, such as sputtering.
[0148] It should be noted that the seed layer is continuously distributed along the wall and bottom of the conductive pillar receiving groove G2 and is electrically connected to the conductive lower pillar H1, so as to serve as the conductive base layer for forming the conductive material layer 8 in the subsequent step S610.
[0149] In step S620, please refer to Figure 14 The conductive material layer 8 on the surface of the plastic sealant layer 6 is removed by grinding, so that the conductive material layer 8 remaining in the conductive post receiving groove G2 constitutes the conductive upper post H2.
[0150] For example, grinding processes include, but are not limited to, mechanical grinding and chemical-mechanical polishing (CMP).
[0151] For example, step S620 includes the following steps: using a mechanical grinding process to coarsely grind the surface of the conductive material layer 8 away from the molding layer 6 to remove most of the conductive material layer; using a chemical-mechanical polishing (CMP) process to finely polish the conductive material layer 8 until the conductive material layer 8 is flush with the molding layer 6 and the surface is flattened to obtain the conductive upper pillar H2.
[0152] For example, after the grinding process is performed, the top surface of each conductive upper post H2 is flush with the surface of the plastic sealant layer 6 in the direction perpendicular to the temporary carrier plate 2, away from the top surface of the conductive lower post H1.
[0153] For example, such as Figure 14 In the example, the heights of the lower conductive pillars H1 are equal; the heights of the upper conductive pillars H2 are negatively correlated with the stacking height of the corresponding chip body C in the chip stacking structure 3.
[0154] For example, the height of the conductive upper pillar H2 is greater than the height of the conductive lower pillar H1.
[0155] It should be noted that the "height" mentioned here and below refers to the dimension in the direction perpendicular to the first pad P1.
[0156] In some embodiments, after step S600, the chip packaging method further includes the following steps S700 to S900.
[0157] In step S700, please refer to Figure 15 A redistribution layer 9, electrically connected to the vertical conductive post H, is formed on the side of the molding layer 6 opposite to the temporary carrier plate 2.
[0158] For example, the redistribution layer 9 includes multiple sub-routing layers stacked from bottom to top; each sub-routing layer includes a dielectric layer 91 and a metal trace layer 92 embedded within the dielectric layer 91. The metal trace layers 92 of adjacent sub-routing layers are electrically connected.
[0159] For example, the vertical conductive post H is electrically connected to the metal trace layer 92 of the underlying sub-wiring layer.
[0160] For example, the material of the dielectric layer 91 includes, but is not limited to, insulating materials, such as polyimide (PI).
[0161] For example, the material of the metal trace layer 92 includes, but is not limited to, conductive metals, such as copper (Cu).
[0162] In step S800, please continue reading. Figure 15Multiple second pads P2 are formed on the side of the redistribution layer 9 opposite to the molding layer 6 and are electrically connected to the redistribution layer 9.
[0163] For example, the formation process of the second pad P2 includes, but is not limited to, an electroplating process.
[0164] For example, the material of the second pad P2 includes, but is not limited to, conductive metals, such as copper (Cu).
[0165] For example, the second pad P2 is electrically connected to the metal trace layer 92 of the top sub-wiring layer.
[0166] In step S900, please refer to Figure 16 Multiple bump structures 10 electrically connected to the second pad P2 are formed on the side of the second pad P2 away from the redistribution layer 9.
[0167] In some embodiments, after step S900, the chip packaging method further includes step S1000.
[0168] In step S1000, please refer to Figure 17 Remove bonding layer 4 and temporary carrier plate 2.
[0169] For example, the removal process of the bonding layer 4 and the temporary carrier 2 includes, but is not limited to, the debonding process.
[0170] For example, the bonding layer 4 includes a photodebonding layer; step S1000 can dissociate the bonding layer 4 by photonic debonding, thereby separating the temporary carrier 2 from the protective layer 5.
[0171] This application also provides a chip packaging structure according to some embodiments, which can be prepared by the chip packaging methods in the above embodiments. The chip packaging structure also possesses all the technical advantages of the aforementioned chip packaging methods. It should be noted that the parts that are the same as or corresponding to the above embodiments can be referred to the corresponding descriptions of the above embodiments, and will not be described in detail below.
[0172] In some embodiments, please refer to Figure 17The chip packaging structure includes a chip stack structure 3, a molding compound 6, and conductive upper pillars H2. The chip stack structure 3 includes multiple chips 1 to be packaged, stacked from bottom to top. Each chip 1 includes a chip body C, a first pad P1 on the chip body C, and a conductive lower pillar H1 located on the surface of the first pad P1 and electrically connected to the first pad P1. The chip bodies C are staggered, and the conductive lower pillars H1 are staggered. The molding compound 6 covers the chip stack structure 3 and has multiple conductive pillar receiving grooves G2 for exposing the corresponding conductive lower pillars H1. The conductive upper pillars H2 are located within the conductive pillar receiving grooves G2, electrically connected to the conductive lower pillars H1, and integrally form a vertical conductive pillar H.
[0173] For example, the chip body C includes, but is not limited to, memory chips; for example, it may be Low Power Double Data Rate SDRAM (LPDDR).
[0174] For example, the first pad P1 is located on one edge of the front side of the chip body C.
[0175] For example, the first pad P1 is embedded in the chip body C. The first pad P1 is flush with the surface of the chip body C in a direction perpendicular to the chip body C, away from the top surface of the chip body C.
[0176] For example, the back side of the chip body C is covered with a chip adhesive film 7. Each layer of the chip body C is bonded to a portion of the front side of the adjacent layer of the chip body C below via the chip adhesive film 7.
[0177] For example, the top surface of each conductive upper post H2 is flush with the surface of the plastic sealant layer 6 in the direction perpendicular to the temporary carrier plate 2, away from the top surface of the conductive lower post H1.
[0178] In some embodiments, please refer to Figure 17 The orthographic projection of the conductive upper pillar H2 onto the chip body C coincides with the orthographic projection of the conductive lower pillar H1 onto the chip body C; and / or, the heights of the conductive lower pillars H1 are equal; the heights of different conductive upper pillars H2 are negatively correlated with the stacking height of the corresponding chip body C in the chip stacking structure 3.
[0179] In some embodiments, the conductive upper column H2 and the conductive lower column H1 are made of the same material.
[0180] For example, the height of the conductive upper pillar H2 is greater than the height of the conductive lower pillar H1.
[0181] In some embodiments, please refer to Figure 17The chip stacking structure 3 includes a first step structure S1 and a second step structure S2. The first step structure S1 includes a first target number of chip bodies C and vertical conductive pillars H located on the first target number of chip bodies C. The second step structure S2 includes a second target number of chip bodies C and vertical conductive pillars H located on the second target number of chip bodies C. The first target number of chip bodies C are stacked from bottom to top as steps and extend along a first direction (e.g., the X direction) to form the first step structure S1. Each vertical conductive pillar H in the first step structure S1 is located on the surface of the corresponding step that is not covered by an adjacent step. The second step structure S2 is located on a portion of the surface of the top step in the first step structure S1. The second target number of chip bodies C are stacked from bottom to top as steps and extend along a second direction (e.g., the Z direction) to form the second step structure S2. Each vertical conductive pillar H in the second step structure S2 is located on the surface of the corresponding step that is not covered by an adjacent step. The first direction (e.g., the X direction) and the second direction (e.g., the Z direction) are parallel to and opposite to the surface of the first pad P1.
[0182] For example, the number of the first target is greater than or equal to 2.
[0183] For example, in the first stepped structure S1, the width of each step is equal.
[0184] For example, the number of the second objective is greater than or equal to 2.
[0185] For example, in the second-step structure S2, the step widths of each step are equal.
[0186] It should be noted that the step width of each step in the first step structure S1 may or may not be equal to the step width of each step in the second step structure S2, and this application does not impose any restrictions on this.
[0187] In some embodiments, please refer to Figure 17 The chip packaging structure also includes a redistribution layer 9, multiple second pads P2, and a bump structure 10.
[0188] The redistribution layer 9 is located on the side of the vertical conductive post H facing away from the first pad P1, covering the vertical conductive post H and the molding compound layer 6. The redistribution layer 9 includes multiple sub-wiring layers stacked from bottom to top. Each sub-wiring layer includes a dielectric layer 91 and a metal trace layer 92 embedded within the dielectric layer 91. The metal trace layers 92 of adjacent sub-wiring layers are electrically connected, and the vertical conductive post H is electrically connected to the metal trace layer 92 of the bottom sub-wiring layer. The second pad P2 is located on the side of the redistribution layer 9 facing away from the molding compound layer 6; the second pad P2 is electrically connected to the metal trace layer 92 of the top sub-wiring layer. The bump structure 10 is located on the side of the second pad P2 facing away from the redistribution layer 9 and is electrically connected to the second pad P2.
[0189] In some embodiments, please refer to Figure 17 The chip packaging structure also includes a protective layer 5. The protective layer 5 is located on the side of the molding layer 6 opposite to the redistribution layer 9, and covers the surface of the molding layer 6 opposite to the redistribution layer 9.
[0190] For example, the bottom chip body C in the chip stack structure 3 is bonded to the protective layer 5 through the chip bonding film 7.
[0191] In the description of this specification, references to terms such as "some embodiments," "some examples," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0192] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0193] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.
Claims
1. A chip packaging method, characterized in that, include: Before performing the dicing process, conductive lower pillars that are electrically connected to the first pads are formed on the surface of the first pads of each chip body on the substrate. Perform a dicing process so that the chip body after forming the conductive lower pillar constitutes a chip to be packaged; Multiple chips to be packaged are stacked from bottom to top on one side of a temporary carrier board, with each chip body stacked in a staggered manner, and each conductive lower post is exposed away from the top surface of the chip body. The area above each conductive lower post away from the chip body is a clear area, thus obtaining a chip stacking structure. A molding compound layer is formed to cover the chip stack structure; A conductive column receiving groove is formed within the encapsulation layer to expose the corresponding conductive lower column; A conductive upper column is formed within the conductive column receiving groove, electrically connected to the conductive lower column, and the conductive upper column and the conductive lower column are integrally formed to constitute a vertical conductive column.
2. The chip packaging method according to claim 1, characterized in that, The chip stacking structure includes a first-step structure and a second-step structure; multiple chips to be packaged are stacked from bottom to top on one side of a temporary carrier, with each chip body staggered and the top surface of each conductive lower post exposed away from the chip body, and the area above each conductive lower post away from the chip body is a clear area, thus obtaining the chip stacking structure, including: On one side of the temporary carrier, a first target number of chip bodies are stacked from bottom to top as steps and extended along a first direction parallel to the temporary carrier to form the first stepped structure, such that the conductive lower pillars on each chip body in the first stepped structure are exposed on the exposed surface of the corresponding step. On a portion of the surface of the top step in the first stepped structure, the second target number of chip bodies are stacked from bottom to top as steps and extended along a second direction parallel to the temporary carrier to form the second stepped structure, such that the conductive lower pillars on each chip body in the second stepped structure are exposed on the exposed surface of the corresponding step. The first direction and the second direction are opposite.
3. The chip packaging method according to claim 2, characterized in that, The number of the first target and the number of the second target are the same.
4. The chip packaging method according to claim 1, characterized in that, The step of forming a conductive post receiving groove within the molding layer for exposing the corresponding conductive lower post includes: Using laser drilling technology, reference holes of a target depth are formed in the molding layer on the side of each conductive lower post away from the first pad, such that the reference holes are located directly above the corresponding conductive lower post, and there is a gap between the bottom surface of the reference holes and the top surface of the corresponding conductive lower post. The molding layer is vertically etched based on the reference hole until the conductive lower post is exposed, forming the conductive post receiving groove.
5. The chip packaging method according to claim 4, characterized in that, The depth of each reference hole is the same; the distance from the top surface of the conductive lower pillar on each chip body to the bottom surface of the corresponding reference hole is different.
6. The chip packaging method according to claim 1, characterized in that, The conductive upper post, which is electrically connected to the conductive lower post and formed within the conductive post receiving groove, includes: A conductive material layer is formed on the surface of the conductive pillar receiving groove and the encapsulation layer; The conductive material layer on the surface of the plastic sealant is removed by grinding, so that the conductive material layer remaining in the conductive post receiving groove constitutes the conductive upper post.
7. The chip packaging method according to any one of claims 1 to 6, characterized in that, After forming a conductive upper post electrically connected to the conductive lower post within the conductive post receiving groove, the chip packaging method further includes: A redistribution layer electrically connected to the vertical conductive pillar is formed on the side of the molding layer opposite to the temporary carrier plate. A plurality of second pads electrically connected to the redistribution layer are formed on the side of the redistribution layer opposite to the molding compound layer; Multiple bump structures electrically connected to the second pad are formed on the side of the second pad away from the redistribution layer.
8. A chip packaging structure, characterized in that, include: A chip stacking structure, comprising multiple chips to be packaged stacked from bottom to top; The chip to be packaged includes: a chip body, a first pad located on the chip body, and a conductive lower post located on the surface of the first pad and electrically connected to the first pad; wherein the chip bodies are stacked in a staggered manner, and the conductive lower posts are distributed in a staggered manner. A molding layer, covering the chip stack structure, has multiple conductive pillar receiving grooves for exposing the corresponding conductive lower pillars; The conductive upper column is located within the conductive column receiving groove and is electrically connected to the conductive lower column, forming a vertical conductive column integrally.
9. The chip packaging structure according to claim 8, characterized in that, The orthographic projection of the upper conductive post on the chip body coincides with the orthographic projection of the lower conductive post on the chip body. And / or, the height of each of the conductive lower pillars is equal; the height of different conductive upper pillars is negatively correlated with the stacking height of the corresponding chip body in the chip stacking structure.
10. The chip packaging structure according to claim 8 or 9, characterized in that, The chip stacking structure includes a first step structure and a second step structure; the first step structure includes a first target number of chip bodies and vertical conductive pillars located on the first target number of chip bodies; the second step structure includes a second target number of chip bodies and vertical conductive pillars located on the second target number of chip bodies. Wherein, the first target number of chip bodies are stacked from bottom to top as steps and extend along the first direction to form the first stepped structure, and each of the vertical conductive pillars in the first stepped structure is located on the surface of the corresponding step that is not covered by the adjacent step. The second step structure is located on a portion of the surface of the top step in the first step structure; the second target number of chip bodies are stacked from bottom to top as steps and extend along the second direction to form the second step structure, and each of the vertical conductive pillars in the second step structure is located on the surface of the corresponding step that is not covered by the adjacent step. The first direction and the second direction are parallel to and opposite to the surface of the first pad.