Through structure

Abstract

A chip includes a first transistor, the first transistor including a first source / drain, a second source / drain, a gate located between the first source / drain and the second source / drain, and a first back-side contact connected to the bottom surface of the first source / drain. The chip also includes a through-structure including a first diffusion region extending in a first direction, a second back-side contact connected to the bottom surface of the first diffusion region, and a top-side contact connected to the top surface of the first diffusion region. The chip also includes back-side metal wiring connecting the first back-side contact and the second back-side contact.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to non-provisional patent application serial number 18 / 391,137, filed on December 20, 2023, with the United States Patent and Trademark Office, the entire contents of which are as fully set forth herein and incorporated herein for all applicable purposes. background Technical Field

[0003] This disclosure relates in general to chip layout, and more specifically to a through structure that provides signal routing between a back metal layer and a top metal layer. Background Technology

[0004] A chip may include many cells (e.g., thousands to millions of cells) disposed on the chip. Each cell may include one or more transistors arranged to provide circuitry (e.g., drivers, logic gates, combinational logic components, latches, or other types of circuitry). The chip may also include multiple metal layers that may be patterned (e.g., using photolithography and etching) to provide signal wiring for the cells. Summary of the Invention

[0005] The following is a simplified overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] A first aspect relates to a chip. The chip includes a first transistor, the first transistor including a first source / drain, a second source / drain, a gate located between the first source / drain and the second source / drain, and a first back-side contact connected to a bottom surface of the first source / drain. The chip also includes a through-structure including a first diffusion region extending in a first direction, a second back-side contact connected to the bottom surface of the first diffusion region, and a top-side contact connected to the top surface of the first diffusion region. The chip also includes back-side metal wiring connecting the first back-side contact and the second back-side contact.

[0007] The second aspect relates to a chip. The chip includes a first transistor comprising a first source / drain, a second source / drain, a gate located between the first and second source / drains, and a back-side contact coupled to the bottom surface of the first source / drain. The chip also includes a through-structure, a back-side metal wiring coupled to the back-side contact and extending below the first transistor into the through-structure, and a top-side metal line extending above the through-structure. The through-structures are connected in parallel between the back-side metal wiring and the top-side metal line, and each through-structure provides a corresponding signal path between the back-side metal wiring and the top-side metal line.

[0008] The third aspect relates to a chip. The chip includes a first transistor comprising a first source / drain, a second source / drain, a gate located between the first and second source / drains, and a back-side contact connected to the bottom surface of the first source / drain. The chip also includes a through-structure comprising a first diffusion region extending in a first direction, a second back-side contact connected to the bottom surface of the first diffusion region, a first top-side contact connected to the top surface of the first diffusion region, a third back-side contact connected to the bottom surface of the first diffusion region, and a second top-side contact connected to the top surface of the first diffusion region. The chip also includes back-side metal wiring connected to the first, second, and third back-side contacts, wherein the back-side metal wiring extends below the first transistor into the through-structure. The chip also includes a top-side metal line extending in the first direction, wherein the top-side metal line is connected to the first and second top-side contacts.

[0009] The fourth aspect relates to a chip. The chip includes a first unit comprising: a first diffusion region extending in a first direction; gates formed over the first diffusion region, wherein each gate is elongated and extends in a second direction perpendicular to the first direction; and a first back-side contact coupled to a bottom surface of the first diffusion region. The chip also includes a through-fill unit comprising a second diffusion region, a second back-side contact coupled to a bottom surface of the second diffusion region, and a top-side contact coupled to a top surface of the second diffusion region. The chip further includes back-side metal wiring connecting the first back-side contact and the second back-side contact.

[0010] The fifth aspect relates to a chip. The chip includes a first unit comprising: a first diffusion region extending in a first direction; gates formed over the first diffusion region, wherein each gate is elongated and extends in a second direction perpendicular to the first direction; and a first back-side contact coupled to a bottom surface of the first diffusion region. The chip also includes a through-fill unit comprising a second diffusion region, a second back-side contact coupled to a bottom surface of the second diffusion region, a first top-side contact coupled to a top surface of the second diffusion region, a third back-side contact coupled to a bottom surface of the second diffusion region, and a second top-side contact coupled to a top surface of the second diffusion region. The chip further includes back-side metal wiring coupled to the first, second, and third back-side contacts, wherein the back-side metal wiring extends below the first unit to the through-fill unit. The chip also includes a top-side metal line extending in the first direction, wherein the top-side metal line is coupled to the first and second top-side contacts. Attached Figure Description

[0011] Figure 1A A side view of an example chip comprising transistors, multiple top-side layers, and multiple back-side layers according to certain aspects of this disclosure is shown.

[0012] Figure 1B Some aspects of this disclosure are shown. Figure 1A A side view of the chip, which also includes a via disposed between a back-side contact and a back-side metal layer.

[0013] Figure 1C This illustrates implementations using a fully all-around gate field-effect transistor according to certain aspects of this disclosure. Figure 1A A side view of a transistor.

[0014] Figure 1D Some aspects of this disclosure are shown. Figure 1C A side view of the chip, which also includes a via disposed between a back-side contact and a back-side metal layer.

[0015] Figure 2 An example of a cell formed by a first top-side metal layer and a second top-side metal layer according to certain aspects of this disclosure is shown, along with exemplary signal wiring for the cell.

[0016] Figure 3 An example of a cell line according to certain aspects of this disclosure is shown, which illustrates examples of blockages within a cell and blockages in adjacent cells.

[0017] Figure 4A An example of a through-filled cell in a cell row according to certain aspects of this disclosure is shown.

[0018] Figure 4B Links to certain aspects of this disclosure are shown. Figure 4A An example of the top side metal wire of the through-fill unit shown.

[0019] Figure 5A An example of a through-fill cell at another location in a cell row is shown, according to certain aspects of this disclosure.

[0020] Figure 5B Links to certain aspects of this disclosure are shown. Figure 5A An example of the top side metal wire of the through-fill unit shown.

[0021] Figure 6 A top view shows an exemplary layout of the diffusion region and gate for the first cell, the through-fill cell, and the second cell, according to certain aspects of this disclosure.

[0022] Figure 7A A top view shows an example of a back-side metal wiring of a through structure extending from the first cell into the through-fill cell, according to certain aspects of this disclosure.

[0023] Figure 7B An example of a through structure, including a back-side metal wiring connected to a back-side contact of the through structure, is shown according to certain aspects of this disclosure.

[0024] Figure 7C An example of a through structure including a top-side contact element is shown according to certain aspects of this disclosure.

[0025] Figure 7D An example of a top-side metal wire extending over and connected to a top-side contact of a through-structure, according to certain aspects of this disclosure, is shown.

[0026] Figure 7E Some aspects of this disclosure are shown. Figure 7D A cross-sectional view of the through structure.

[0027] Figure 8A Another example of a through structure, including a back-side metal wiring connected to a back-side contact of the through structure, is shown according to certain aspects of this disclosure.

[0028] Figure 8B Another example of a through structure including a top-side contact element is shown according to certain aspects of this disclosure.

[0029] Figure 8C Another example is shown of a top-side metal wire extending over and connected to a top-side contact of the through-structure, according to certain aspects of this disclosure.

[0030] Figure 8D Some aspects of this disclosure are shown. Figure 8C A cross-sectional view of the through structure.

[0031] Figure 9A Another example of a through structure, including connecting back-side metal wiring to a back-side contact of the through structure, is shown according to certain aspects of this disclosure.

[0032] Figure 9B Another example of a through structure including a top-side contact element is shown according to certain aspects of this disclosure.

[0033] Figure 9C Another example is shown of a top-side metal wire extending over and connected to a top-side contact of a through-structure, according to certain aspects of this disclosure.

[0034] Figure 9D Some aspects of this disclosure are shown. Figure 9C A cross-sectional view of the through structure.

[0035] Figure 10A Examples of a first through-structure including a first back-side contact and a second through-structure including a second back-side contact are shown according to certain aspects of this disclosure.

[0036] Figure 10B Examples of a first through structure including a first top-side contact member and a second through structure including a second top-side contact member are shown according to certain aspects of this disclosure.

[0037] Figure 10C An example of a top-side metal wire extending over a first through structure and a second through structure, according to certain aspects of this disclosure, is shown.

[0038] Figure 11 This is a block diagram illustrating a computer system according to certain aspects of this disclosure. Detailed Implementation

[0039] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0040] Figure 1AA side view of an example of a chip 100 (e.g., a die) including transistor 110, multiple top-side layers 105, and multiple back-side layers 108 according to certain aspects is shown. Although for simplicity... Figure 1A A transistor 110 is shown, but it should be understood that chip 100 includes a number of transistors and other devices. As discussed further below, transistor 110 can be implemented using a FinFET process, a gate-all-around FET process, or another type of process. Top-side layer 105 includes a layer located above transistor 110, and back-side layer 108 includes a layer located below transistor 110. Top-side layer may also be referred to as front-side layer or another term.

[0041] exist Figure 1A In the example shown, transistor 110 includes a diffusion region 112 and a gate 126 located on the diffusion region 112. The diffusion region 112 may also be referred to as an oxide diffusion region, an active region, an active diffusion portion, an active portion (RX), or another term. The gate 126 may comprise polysilicon, a gate metal, and / or another gate material. Figure 1A In the example shown, a portion of the diffusion region 112 to the left of the gate 126 provides a first source / drain 114 for transistor 110, and a portion of the diffusion region 112 to the right of the gate 126 provides a second source / drain 116 for transistor 110. As used herein, the term "source / drain" means source, drain, or both. In this example, the gate 126 controls the conductivity between the first source / drain 114 and the second source / drain 116 based on the voltage applied to the gate 126. Transistor 110 may be a p-type transistor in which the diffusion region 112 is a p-type diffusion region, or transistor 110 may be an n-type transistor in which the diffusion region 112 is an n-type diffusion region.

[0042] In this example, chip 100 includes a top-side contact 124 formed on the top surface of the second source / drain 116. The top surface may also be referred to as the front-side surface. The contact 124 can be formed (i.e., patterned) from the top-side contact layer using, for example, photolithography and etching processes. The contact 124 may be referred to as a metal-diffused (MD) contact, a contact active (CA), or another term. Chip 100 may also include a gate contact 128 formed on the gate 126. The gate contact 128 may be referred to as a metal-polysilicon (MP) contact or another term. In some embodiments, the gate contact 128 may be omitted.

[0043] In this example, the top-side layer 105 includes a top-side metal layer 140. The top-side metal layer may also be referred to as a front-side metal layer, a metal interconnect, or another term. The top-side metal layer 140 can be patterned (e.g., using photolithography and etching) to accommodate transistors 110 and other transistors integrated on chip 100. Figure 1A (Not shown) provides signal routing. In some embodiments, the top-side metal layer 140 may also be patterned to form a power distribution network including power rails for distributing power to transistors 110 and other transistors integrated on chip 100. In other embodiments, a back-side layer 108 is used to provide the power distribution network (e.g., to reduce wiring congestion in the top-side layer 105), as discussed further below.

[0044] exist Figure 1A In the example shown, the bottommost top metal layer among the top metal layers 140 is called metal layer M0. The top metal layer directly above metal layer M0 is called metal layer M1, the top metal layer directly above metal layer M1 is called metal layer M2, the top metal layer directly above metal layer M2 is called metal layer M3, and so on. Although for ease of illustration... Figure 1A Four top-side metal layers 140 (i.e., M0 to M3) are shown, but it should be understood that top-side layer 105 may include an additional top-side metal layer located above metal layer M3. It should be understood that this disclosure is not limited to the nomenclature in which the bottommost metal layer is referred to as metal layer M0. For example, in another example, the bottommost top-side metal layer may be referred to as metal layer M1 instead of metal layer M0.

[0045] The top-side layer 105 also includes vias 150 providing connections between the top-side metal layers 140. In this example, via V0 provides a connection between metal layers M0 and M1, via V1 provides a connection between metal layers M1 and M2, and via V2 provides a connection between metal layers M2 and M3. Figure 1A In one example, the chip further includes a via 136 disposed between the gate contact 128 and the metal layer M0, wherein the via 136 connects the gate contact 128 (and therefore the gate 126) to the metal layer M0. In implementations where the gate contact 128 is omitted, the via 136 may be disposed between the gate 126 and the metal layer M0, without an intermediate gate contact. Alternatively, in this example, the chip 100 includes a via 134 disposed between the contact 124 and the metal layer M0, wherein the via 134 connects the contact 124 to the metal layer M0. In some implementations, the via 134 may be omitted, wherein the contact 124 directly contacts the metal layer M0.

[0046] In some respects, the top-side layer 105, as well as the diffusion region 112 and gate 126 of the transistor 110, can be formed on the silicon substrate during manufacturing. A carrier wafer (not shown) can then be bonded to the top of the chip 100 for structural support, and most or all of the silicon substrate can be ground and / or polished. A back-side layer 108 can then be formed on any remaining portion of the silicon substrate and / or beneath the transistor 110.

[0047] In this example, the back-side layer 108 includes a back-side metal layer 160. The back-side metal layer 160 can be patterned (e.g., using photolithography and etching) to form a power distribution network including power rails for distributing power to transistors 110 and other transistors on chip 100.

[0048] exist Figure 1A In the example shown, the topmost back metal layer among the back metal layers 160 is called back metal layer BM0. The back metal layer directly below back metal layer BM0 is called back metal layer BM1, the back metal layer directly below back metal layer BM1 is called back metal layer BM2, and so on. Although for ease of illustration... Figure 1A Three back-side metal layers 160 (i.e., BM0 to BM2) are shown, but it should be understood that back-side layer 108 may include an additional metal layer located below back-side metal layer BM2.

[0049] exist Figure 1A In one example, chip 100 includes a back-side contact 122 formed on the bottom surface (i.e., the back-side surface) of the first source / drain 114. The back-side contact 122 can be formed (i.e., patterned) from a back-side contact layer (labeled "BSC") using, for example, photolithography and etching processes. The back-side contact 122 is used to connect the first source / drain 114 to the back-side metal layer BMO. In some specific implementations, the back-side contact 122 can directly contact the back-side metal layer BMO, such as... Figure 1A As shown in the example. In other embodiments, the back contact 122 can be coupled to the back metal layer BMO via an intermediate via. In this respect, Figure 1B An example is shown in which chip 100 includes a back-side via 168 (labeled "BVD") disposed between a back-side contact 122 and a back-side metal layer BMO. In this example, via 168 is in the vertical direction (i.e., Figure 1B A space is provided between the back contact 122 and the back metal layer BMO in the z direction.

[0050] exist Figure 1A and Figure 1BIn one example, the backside layer 108 includes a via 165 providing a connection between the backside metal layers 160. In this example, the via 165 includes a via BSV0 providing a connection between the backside metal layers BM0 and BM1, and a via BSV1 providing a connection between the backside metal layers BM1 and BM2.

[0051] In some respects, (e.g., using photolithography and etching) the top-side metal layer 140 is patterned for transistors 110 and other transistors integrated on chip 100. Figure 1A (Not shown) provides signal routing, and the back-side metal layer 160 is patterned to form a power distribution network including power rails for distributing power to transistors 110 and other transistors integrated on chip 100. Moving the power distribution network to the back-side layer 108 significantly reduces routing congestion compared to using the top-side layer 105 for both signal routing and power distribution. This reduced congestion allows for better optimization of the signal routing layout (e.g., to reduce parasitic capacitance for higher performance) and also allows for better optimization of the power distribution network layout (e.g., to reduce resistance in the power distribution network for lower current-resistance (IR) voltage drop).

[0052] As discussed above, transistor 110 can be implemented using a FinFET process, a gate-all-around FET process, or another type of process. For an example of a FinFET process, the diffusion region 112 includes areas in the horizontal direction (i.e., Figure 1A and Figure 1B A fin extending in the x-direction, wherein a gate 126 may surround each fin on three sides. Figure 1C An example is shown in which transistor 110 is implemented using a gate-all-around FET process. In this example, diffusion region 112 includes vertically stacked channels 170 (e.g., nanosheets), wherein gate 126 may surround each of the channels 170 on four sides. First source / drain 114 and second source / drain 116 may each comprise epitaxially grown or deposited silicon, silicon-based materials (e.g., silicon-germanium), or any combination thereof. In this example, first source / drain 114 is coupled to a first side 170a of channel 170, and second source / drain 116 is coupled to a second side 170b of channel 170. However, it should be understood that this disclosure is not limited to this example. Figure 1D It shows Figure 1C An exemplary transistor 110, wherein chip 100 includes a via 168 (labeled “BVD”) located between back-side contact 122 and back-side metal layer BMO. As discussed above, via 168 provides space between back-side contact 122 and back-side metal layer BMO.

[0053] Despite Figure 1A , Figure 1B , Figure 1C and Figure 1D A gate 126 is shown, but it should be understood that transistor 110 may include multiple gates arranged in parallel and interconnected with each other (e.g., via metal layer M0). A transistor with multiple gates may be referred to as a multi-finger transistor or another term.

[0054] The transistors on chip 100 can be organized into cells. Each cell may include one or more transistors arranged to provide circuitry (e.g., a driver, logic gate, combinational logic unit, latch, flip-flop, or another type of circuitry). The cells may be arranged in rows on chip 100, wherein each row of cells may be located between a power rail and a ground rail to deliver power to the cells in the row.

[0055] The layout of each cell can be specified (i.e., defined) in a standard cell library, which can be stored in memory. The standard cell library can specify (i.e. define) the layout of each cell among various cells that can be placed (i.e., laid out) on chip 100 for a specific process. Chip 100 can include multiple instances of a specific cell defined in the standard cell library. The layout of each cell defined in the standard cell library can include the layout of the gate (e.g., a polysilicon gate), diffusion region, and contacts within the cell. The standard cell library can also specify the layout of fill cells, decap cells, endcap cells, etc.

[0056] Figure 2 A top view of a cell 210 that can be placed on chip 100 is shown. Although for simplicity... Figure 2 A unit 210 is shown, but it should be understood that chip 100 may include (e.g., arranged in rows and / or columns) many units. Figure 2 An example of signal wiring using the top-side metal layers M0 and M1 for unit 210 is shown.

[0057] More specifically, Figure 2 An example is shown of metal lines 215, 225, and 235 formed (i.e., patterned) by a metal layer M0 to provide signal routing for cells 210 in the metal layer M0. Metal lines 215, 225, and 235 extend in the x-direction and thus provide signal routing in the x-direction. Each metal line 215, 225, and 235 can be routed via a via (e.g., Figures 1A to 1D The vias (VG or VD) in the cell are connected to the gate or source / drain contacts in cell 210.

[0058] Figure 2Examples of metal lines 220, 230, and 240 formed (i.e., patterned) by a metal layer M1 to provide signal routing for cells 210 in the metal layer M1 are also shown. The metal lines 220, 230, and 240 extend in the y-direction and thus provide signal routing in the y-direction.

[0059] In this example, metal lines 230 and 240 provide signal routing for cell 210 within the same column where cell 210 resides. Metal line 230 is routed through vias (e.g., Figures 1A to 1D The via V0 in the middle is connected to the metal wire 235, and the metal wire 240 is connected through the via (e.g., V0 in the middle). Figures 1A to 1D The via (V0) is connected to the metal line 225. However, in some cases, the signal routing for cell 210 in the metal layer M1 within the same column as cell 210 may create a bottleneck for the routing resources in the metal layer M1. For example, the signal routing for cell 210 in the metal layer M1 may form a blockage for the signal routing of another cell (not shown) residing in the same column as cell 210 in the metal layer M1.

[0060] To provide greater flexibility in signal routing for cells 210 in metal layer M1 and to alleviate routing congestion in metal layer M1, layout techniques have been developed to allow metal lines in metal layer M1 to access cells 210 from different columns. In this regard, Figure 2 An example is shown in which metal lines 220 access cells 210 from different columns. This is achieved by extending metal lines 215 in the x-direction to adjacent cells and connecting metal lines 220 to metal lines 215 above adjacent cells.

[0061] However, a challenge with the above technique is that, due to obstructions in the metal layer M0, it is not always possible to extend the metal lines in the metal layer M0 to adjacent cells. Examples of obstructions in the metal layer M0 are shown in... Figure 3 The example is illustrated below and will be discussed further.

[0062] Figure 3 An example of a cell row 305 is shown, comprising a first cell 310, a second cell 312, a third cell 314, and a fourth cell 316. Each cell in 310, 312, 314, and 316 may provide a logic gate, a driver, a latch, a combinational logic component, or another type of circuit. In this example, cell row 305 also includes a first filler cell 320 located between the first cell 310 and the second cell 312, and a second filler cell 322 located between the third cell 314 and the fourth cell 316. In this example, each filler cell in filler cells 320 and 322 may be a non-functional cell that provides space between cells in the x-direction.

[0063] Figure 3 An example of metal lines formed (i.e., patterned) by metal layer M0 to provide signal routing for cells 310, 312, 314, and 316 in metal layer M0 is also shown. The metal lines in metal layer M0 include metal lines 330, 335, 340, and 342 for providing signal routing for first cell 310. In this example, metal line 330 extends to a first fill cell 320, which provides access to the metal line 330 (not shown) in metal layer M1 outside the same column as first cell 310. Also in this example, metal line 335 extends to an adjacent cell (i.e., a third cell 314), which provides access to the metal line 335 (not shown) in metal layer M1 outside the same column as first cell 310.

[0064] However, metal line 340 is prevented from extending into the first fill cell 320 and also prevented from extending into the adjacent cell (i.e., the third cell 314). More specifically, metal line 340 is prevented from extending into the first fill cell 320 by metal line 342. In this example, metal line 342 can be referred to as an intra-cell blockage because metal line 342 corresponds to the same cell as metal line 340. Metal line 340 is prevented from extending into the adjacent cell (i.e., the third cell 314) by metal line 344, which provides signal wiring for the adjacent cell. In this example, metal line 344 can be referred to as an adjacent cell blockage because metal line 344 corresponds to the adjacent cell. Therefore, in this example, metal line 340 is prevented from extending into the first fill cell 320 by an intra-cell blockage and also prevented from extending into the adjacent cell by an adjacent cell blockage.

[0065] To address the aforementioned issues, aspects of this disclosure provide a through-fill cell configured to transmit signals between a back-side metal layer (e.g., back-side metal layer BMO) and a top-side metal layer (e.g., top-side metal layer M0). This allows the use of the back-side metal layer to route signals for cells (e.g., first cell 310) beneath the cells to the through-fill cell, avoiding obstructions in the top-side metal layer. The above-described and other features of this disclosure are further discussed below.

[0066] Figure 4A An example of a through-fill unit 410 according to certain aspects of this disclosure is shown. The through-fill unit 410 includes a through structure 415 configured to transmit signals between a back-side metal layer BMO and a top-side metal layer M0. The through structure 415 may include (e.g., by...) Figures 1A to 1D The back-side contact layer (BSC) shown in the diagram forms a back-side contact element, one or more diffusion regions, and (e.g., formed by...) Figures 1A to 1DThe top-side contact element is formed by the top-side contact layer MD shown. An exemplary specific implementation of the through structure 415 is discussed below. The top-side contact element may also be referred to as the front-side contact element or another term.

[0067] Figure 4A An example is shown in which the through-fill unit 410 is located between the first unit 310 and the second unit 312. Figure 4A An example of a backside metal wiring 420 extending from the first cell 310 to the through structure 415 and passing beneath the first cell 310 is also shown. The backside metal wiring 420 may include backside metal lines extending in the x-direction and formed (i.e., patterned) by the backside metal layer MMO. Because the backside metal wiring 420 passes beneath the first cell 310, it avoids obstructions (e.g., intra-cell obstructions) in the metal layer MMO. It should be noted that... Figure 4A Not shown in the middle Figure 3 The top side metal wire is shown to more clearly illustrate the back side metal wiring 420.

[0068] The back-side metal wiring 420 (e.g., a back-side metal line) can be connected to the bottom surface of the gate or source / drain (e.g., by means of...). Figures 1A to 1D The back-side contacts (formed by the back-side contact layer BSC) shown are connected to the gate or source / drain in the first cell 310. In this example, the back-side metal wiring 420 connects the through-structure 415 between the gate and / or source / drain in the first cell 310.

[0069] Figure 4B An example of a metal line 425 extending in the x-direction and connected to a through structure 415 in metal layer M0 is shown. In this example, through structure 415 provides a signal path between backside metal wiring 420 and metal line 425. Figure 4B An example of a metal line 430 located in metal layer M1 and extending in the y-direction is also shown. Metal line 430 can be connected to metal line 425 via a via (e.g., via V0). In this example, the through-structure 415 and the back-side metal wiring 420 allow metal line 430 to access the first cell 310 outside the same column as the first cell 310, while avoiding obstructions in metal layer M0 (e.g., avoiding intra-cell obstructions in metal layer M0, e.g., ...). Figure 3 Metal wire 342 in the example).

[0070] Figure 5A An example is shown in which the through-fill unit 410 is located between the third unit 314 and the fourth unit 316. Figure 5AIn this structure, the back-side metal wiring 420 extends from the first unit 310 to the through structure 415 and passes under the first unit 310 and the adjacent unit (i.e., the third unit 314). Since the back-side metal wiring 420 passes under the first unit 310 and the adjacent unit, the back-side metal wiring 420 avoids obstructions (e.g., adjacent unit obstructions) in the metal layer M0. Figure 5B Examples are shown of metal wire 425 in metal layer M0 connected to through structure 415 and metal wire 430 in metal layer M1 connected to metal wire 425. Figure 5B An example is also shown in which the back-side metal wiring passes beneath transistor 450 in the third unit 314. Transistor 450 can utilize Figures 1A to 1D The exemplary transistor 110 shown is used to implement this.

[0071] Figure 6 A top view is shown of an exemplary layout for the diffusion regions and gates of a first cell 310, a through-fill cell 410, and a second cell 312, according to certain aspects of this disclosure. In this example, the first cell 310 includes a first diffusion region 630 and a second diffusion region 635. Each of the diffusion regions 630 and 635 extends in the x-direction, and the diffusion regions 630 and 635 are spaced apart from each other in the y-direction. The first diffusion region 630 may be an n-type diffusion, and the second diffusion region 635 may be a p-type diffusion region, or vice versa.

[0072] The second unit 312 includes a first diffusion region 610 and a second diffusion region 615. Each of the diffusion regions 610 and 615 extends in the x-direction, and the diffusion regions 610 and 615 are spaced apart from each other in the y-direction. The first diffusion region 610 can be an n-type diffusion region, and the second diffusion region 615 can be a p-type diffusion region, or vice versa.

[0073] The through-fill unit 410 includes a first diffusion region 620 and a second diffusion region 625. Each of the diffusion regions 620 and 625 extends in the x-direction, and the diffusion regions 620 and 625 are spaced apart from each other in the y-direction. The first diffusion region 620 may be an n-type diffusion region, and the second diffusion region 625 may be a p-type diffusion region, or vice versa.

[0074] Figure 6Examples of gates 650, 652, 654, 656, 658, 660, 662, 664, 666, and 668 are shown, wherein each of the gates 650, 652, 654, 656, 658, 660, 662, 664, 666, and 668 is elongated and extends in the y-direction. Gates 650, 652, 654, 656, 658, 660, 662, 664, 666, and 668 are spaced apart from each other in the x-direction. For example, 650, 652, 654, 656, 658, 660, 662, 664, 666, and 668 may be spaced apart from each other with a uniform pitch. Each of the gates 650, 652, 654, 656, 658, 660, 662, 664, 666, and 668 may contain polysilicon, gate metal, another gate material, or any combination thereof.

[0075] exist Figure 6 In the example, gates 662, 664, and 666 extend across a first diffusion region 630 and a second diffusion region 635 of the first cell 310. Gates 662, 664, and 666 in the first cell 310 and the first diffusion region 630 may form one or more transistors in the first cell 310, wherein a portion of the first diffusion region 630 located between gates 662, 664, and 666 provides the source / drain of one or more transistors. For example, the first transistor 670 may include at least a portion of gate 666 to form gate 676 of the first transistor 670. The first transistor 670 may also include at least a portion of the first diffusion region 630 to form a first source / drain 672 and a second source / drain 674, wherein gate 676 is located between the first source / drain 672 and the second source / drain 674. It should be understood that in some embodiments, the first transistor 670 may also include at least a portion of one or more of gates 664 and 662 for a multi-finger embodiment of the first transistor 670.

[0076] The gates 662, 664, and 666 in the first unit 310 and the second diffusion region 635 may also form one or more transistors in the first unit 310, wherein the portion of the second diffusion region 635 located between the gates 662, 664, and 666 provides the source / drain of one or more transistors. In some aspects, the first diffusion region 630 may be an n-type diffusion region to provide one or more n-type field-effect transistors (NFETs), and the second diffusion region 635 may be a p-type diffusion region to provide one or more p-type field-effect transistors (PFETs), or vice versa.

[0077] exist Figure 6In the example, gates 652, 654, and 656 extend across a first diffusion region 610 and a second diffusion region 615 of the second cell 312. Gates 652, 654, and 656 in the second cell 322, and the first diffusion region 610, can form one or more transistors in the second cell 312, wherein a portion of the first diffusion region 610 located between gates 652, 654, and 656 provides the source / drain of one or more transistors. For example, the second transistor 680 may include at least a portion of gate 652 to form gate 686 of the second transistor 680. The first transistor 680 may also include at least a portion of the first diffusion region 610 to form a first source / drain 682 and a second source / drain 684, wherein gate 686 is located between the first source / drain 682 and the second source / drain 684. It should be understood that in some embodiments, the second transistor 680 may also include at least a portion of one or more of gates 654 and 656 for a multi-finger embodiment of the first transistor 680.

[0078] The gates 652, 654, and 656 in the second unit 312 and the second diffusion region 615 may also form one or more transistors in the second unit 312, wherein the portion of the second diffusion region 615 located between the gates 652, 654, and 656 provides the source / drain of one or more transistors. In some aspects, the first diffusion region 610 may be an n-type diffusion region to provide one or more n-type field-effect transistors (NFETs), and the second diffusion region 615 may be a p-type diffusion region to provide one or more p-type field-effect transistors (PFETs), or vice versa.

[0079] Gate 650 is located on the left boundary of the second cell 312, gate 658 is located on the boundary between the through-fill cell 410 and the second cell 312, gate 660 is located on the boundary between the through-fill cell 410 and the first cell 310, and gate 668 is located on the right boundary of the first cell 310. However, it should be understood that this disclosure is not limited to this example. In some aspects, gates 650, 658, 660, and 668 on the cell boundaries may be dummy gates. Chip 100 may include a single diffusion interruption (SDB) or a double diffusion interruption (DDB) located at each cell boundary to separate the diffusion regions 610, 615, 620, 625, 630, and 635 of cells 310, 312, and 410.

[0080] Now, based on certain aspects, Figures 7A to 7E Let's discuss an exemplary implementation of the through structure 415.

[0081] Figure 7AA top view shows an example of a back-side metal wiring 420 extending from the first unit 310 to the through structure 415 and passing beneath the first unit 310. Diffusion regions 610, 615, 620, 625, 630, and 635 are... Figure 7A The back metal wiring 420 is shown in dashed lines to make it clearer. Figure 7A An example is also shown of a first back-side via 705 (e.g., BVD) disposed at one end of the back-side metal wiring 420 and a second back-side via 708 (e.g., BVD) disposed at the other end of the back-side metal wiring 420 below the through structure 415.

[0082] Figure 7B An example is shown of a first back-side contact 710 (e.g., BSC) extending in the y-direction below the first diffusion region 630 and the second diffusion region 635. In this example, the first back-side contact 710 is positioned at ( Figure 7A (As shown) Between the first back-side via 705 and the bottom surface of the first diffusion region 630. A first back-side contact 710 is also disposed between the first back-side via 705 and the bottom surface of the second diffusion region 635. Therefore, in this example, the first diffusion region 630 and the second diffusion region 635 are connected to the back-side metal wiring 420 via the first back-side via 705 and the first back-side contact 710. However, it should be understood that this disclosure is not limited to this example.

[0083] In another example, the first back-side contact 710 may extend below only one of the first diffusion region 630 and the second diffusion region 635. In this example, one of the first diffusion region 630 and the second diffusion region 635 is connected to the back-side metal wiring 420 via the first back-side via 705 and the first back-side contact 710. In another example, the back-side contact 710 may be connected to the bottom surface of one of the gates 622, 624, and 666 to connect the gate to the back-side metal wiring 420.

[0084] The first back-side contact 710 may be connected to a portion of the first diffusion region 630 that provides the source or drain of the first transistor (e.g., the portion of the first diffusion region 630 located between gate 666 and gate 668). The first back-side contact 710 may also be connected to a portion of the second diffusion region 635 that provides the source or drain of the second transistor (e.g., the portion of the second diffusion region 635 located between gate 666 and gate 668).

[0085] Figure 7B The bottom surface of the second diffusion region 625 disposed in the through-fill unit 410 is also shown. Figure 7AAn example of a second back-side contact 715 between back-side vias 708 is shown. In this example, the second back-side contact 715 and the second diffusion region 625 are part of a through-structure 415, wherein the second back-side contact 715 provides a back-side contact for connecting the through-structure 415 to a back-side metal wiring 420.

[0086] Figure 7C An example of a top-side contact 730 (e.g., MD) disposed on the top surface of the second diffusion region 625 is shown. As discussed further below, the top-side contact 730 is part of the through structure 415 and provides a contact for connecting the through structure 415 to the metal layer M0. Figure 7C An example of a via 735 (e.g., VD) provided on the top side contact 730 is also shown.

[0087] Figure 7D This shows the metal layer M0 in the x-direction at ( Figure 7C An example of a metal line 425 extending above a via 735 is shown. In this example, the via 735 is disposed between the top contact 730 and the metal line 425, and connects the top contact 730 to the metal line 425. Figure 7D An example is also shown in which the first back-side contact 710 is coupled to the bottom surface of the first source / drain 672 of the first transistor 670. In this example, the back-side metal wiring 420 and the through-structure 415 provide signal wiring for the first source / drain 672. However, it should be understood that this disclosure is not limited to this example.

[0088] Figure 7E The through structure 415 is shown along Figure 7D The sectional view taken from line 765 in the figure. (See figure) Figure 7E As shown, the through structure 415 provides a signal path 770 between the back-side metal wiring 420 in the back-side metal layer M0 and the metal line 425 in the metal layer M0. In this example, the signal path 770 passes through the second diffusion region 625.

[0089] Figures 8A to 8D Another exemplary embodiment of the through-structure 415 is shown, wherein the signal path 770 passes through the first diffusion region 620 of the through-fill unit 410. More specifically, Figure 8A The second back-side contact 715 is shown to be disposed on the bottom surface of the first diffusion region 620 of the through-filling unit 410 and ( Figure 7A Example between the back-side vias 708 shown. In this example, the second back-side contact 715 and the first diffusion region 620 are part of the through structure 415, wherein the second back-side contact 715 provides a back-side contact for connecting the through structure 415 to the back-side metal wiring 420.

[0090] Figure 8B An example is shown in which a top-side contact 730 (e.g., MD) is disposed on the top surface of the first diffusion region 620. As discussed above, the top-side contact 730 is part of the through structure 415 and provides a contact for connecting the through structure 415 to the metal layer M0. Figure 8B An example of a via 735 (e.g., VD) provided on the top side contact 730 is also shown.

[0091] Figure 8C This shows the metal layer M0 in the x-direction at ( Figure 8B An example of a metal line 425 extending above a via 735 is shown. In this example, the via 735 is disposed between the top contact 730 and the metal line 425, and connects the top contact 730 to the metal line 425. Figure 8C An example is also shown in which the first back-side contact 710 is coupled to the bottom surface of the first source / drain 672 of the first transistor 670. In this example, the back-side metal wiring 420 and the through-structure 415 provide signal wiring for the first source / drain 672. However, it should be understood that this disclosure is not limited to this example.

[0092] Figure 8D The through structure 415 is shown along Figure 8C The sectional view taken from line 765 in the figure. (See figure) Figure 8D As shown, the through structure 415 provides a signal path 770 between the back-side metal wiring 420 in the back-side metal layer M0 and the metal line 425 in the metal layer M0. In this example, the signal path 770 passes through the first diffusion region 620.

[0093] Figures 9A to 9D Another exemplary embodiment of a through structure 415 including a first diffusion region 620 and a second diffusion region 625 is shown. More specifically, Figure 9A An example is shown in which a second back-side contact 715 extends in the y-direction below the first diffusion region 620 and the second diffusion region 625 of the through-fill unit 410. The second back-side contact 715 is disposed between the bottom surface of the first diffusion region 620 and the back-side via 708. The second back-side contact 715 is also disposed between the bottom surface of the second diffusion region 625 and the back-side via 708. In this example, the second back-side contact 715, the first diffusion region 620, and the second diffusion region 625 are part of the through-structure 415, wherein the second back-side contact 715 provides a back-side contact for connecting the through-structure 415 to the back-side metal wiring 420.

[0094] Figure 9BAn example is shown in which a top-side contact 730 (e.g., MD) extends in the y-direction over the first diffusion region 620 and the second diffusion region 625 and is disposed on the top surface of the first diffusion region 620 and the top surface of the second diffusion region 625. As discussed above, the top-side contact 730 is part of the through structure 415 and provides a contact for connecting the through structure 415 to the metal layer M0. Figure 9B An example of a via 735 (e.g., VD) provided on the top side contact 730 is also shown.

[0095] Figure 9C This shows the metal layer M0 in the x-direction at ( Figure 9B An example of a metal line 425 extending above a via 735 is shown. In this example, the via 735 is disposed between the top contact 730 and the metal line 425, and connects the top contact 730 to the metal line 425. Figure 9C An example is also shown in which the first back-side contact 710 is coupled to the bottom surface of the first source / drain 672 of the first transistor 670. In this example, the back-side metal wiring 420 and the through-structure 415 provide signal wiring for the first source / drain 672. However, it should be understood that this disclosure is not limited to this example.

[0096] Figure 9D The through structure 415 is shown along Figure 9C The sectional view taken from line 765 in the figure. (See figure) Figure 9D As shown, the through-structure 415 provides a first signal path 770a and a second signal path 770b between the back-side metal wiring 420 in the back-side metal layer BMO and the metal line 425 in the metal layer M0. In this example, the first signal path 770a passes through the first diffusion region 620, and the second signal path 770b passes through the second diffusion region 625. The first signal path 770a and the second signal path 770b provide two parallel signal paths, which help reduce the resistance between the back-side metal wiring 420 in the back-side metal layer BMO and the metal line 425 in the metal layer M0 (and thus reduce the IR voltage drop).

[0097] In some respects, the through-fill unit 410 may include multiple instances of through structures 415 connected in parallel to reduce the resistance between the back-side metal wiring 420 in the back-side metal layer MMO and the metal line 425 in the metal layer M0. In this respect, Figure 10A An example is shown in which the through-fill unit 410 includes a first through structure 415-1 and a second through structure 415-2. Each through structure in through structures 415-1 and 415-2 is a separate instance of through structure 415, and each through structure in through structures 415-1 and 415-2 can be used Figures 7A to 7E , Figures 8A to 8D and Figures 9A to 9D This can be implemented in any of the exemplary embodiments of the through-structure 415 shown. In this example, the back-side metal wiring 420 extends below the first through-structure 415-1 and the second through-structure 415-2, and connects to both the first through-structure 415-1 and the second through-structure 415-2. The first through-structure 415-1 and the second through-structure 415-2 can be considered as part of a single through-structure including the first through-structure 415-1 and the second through-structure 415-2.

[0098] Figure 10A An example is shown in which the first through structure 415-1 includes a second back contact 715-1 extending in the y-direction below the first diffusion region 620 and the second diffusion region 625 of the through filling unit 410. The second back contact 715-1 (e.g., via a corresponding back via BVD) is coupled to the bottom surface of the first diffusion region 620, the bottom surface of the second diffusion region 625, and the back metal wiring 420.

[0099] The second through structure 415-2 includes a third back-side contact 715-2 extending in the y-direction below the first diffusion region 620 and the second diffusion region 625 of the through-fill unit 410. The third back-side contact 715-2 (e.g., via a corresponding back-side via BVD) is coupled to the bottom surface of the first diffusion region 620, the bottom surface of the second diffusion region 625, and the back-side metal wiring 420.

[0100] In this example, the through-fill cell 410 includes a gate 1010 located between the first through structure 415-1 and the second through structure 415-2. The gate 1010 may be a non-functional gate placed in the through-fill cell 410 to maintain a uniform spacing between gates on the chip 100. In this example, the length of the through-fill cell 410 in the x-direction may be... Figures 7A to 7E , Figures 8A to 8D and Figures 9A to 9D The example of the through-fill cell 410 shown is approximately twice the length. Since the gate 1010 is located within the through-fill cell, the gate 1010 can also be referred to as a filled gate. The gate 1010 may comprise polysilicon, gate metal, or another gate material.

[0101] Figure 10B An example is shown in which the first through structure 415-1 includes a first top-side contact 730-1 (e.g., MD) extending in the y-direction over the first diffusion region 620 and the second diffusion region 625. The first top-side contact 730-1 is disposed on the top surface of the first diffusion region 620 and the top surface of the second diffusion 625. Figure 10BA first top-side via 735-1 (e.g., VD) is also shown provided on the first top-side contact 730-1.

[0102] Figure 10B An example is also shown in which the second through structure 415-2 includes a second top-side contact 730-2 (e.g., MD) extending in the y-direction over the first diffusion region 620 and the second diffusion region 625. The second top-side contact 730-2 is disposed on the top surface of the first diffusion region 620 and the top surface of the second diffusion 625. Figure 10B A second top-side via 735-2 (e.g., VD) is also shown disposed on the second top-side contact 730-2. In this example, the second top-side via 735-2 is aligned with the first top-side via 735-1 in the y-direction.

[0103] Figure 10C This shows the metal layer M0 in the x-direction at ( Figure 10B The example shown is a metal line 425 extending over vias 735-1 and 735-2. In this example, a first top-side via 735-1 is disposed between a first top-side contact 730-1 and the metal line 425, and connects the first top-side contact 730-1 to the metal line 425. A second top-side via 735-2 is disposed between a second top-side contact 730-2 and the metal line 425, and connects the second top-side contact 730-2 to the metal line 425. Figure 10C An example is also shown in which the first back-side contact 710 is coupled to the bottom surface of the first source / drain 672 of the first transistor 670. In this example, the back-side metal wiring 420 and the through structures 415-1 and 415-2 provide signal wiring for the first source / drain 672. However, it should be understood that this disclosure is not limited to this example.

[0104] Therefore, the metal line 425 extends over the first through structure 415-1 and the second through structure 415-2, and connects to both the first through structure 415-1 and the second through structure 415-2. Thus, the first through structure 415-1 and the second through structure 415-2 provide parallel signal paths between the back metal wiring 420 in the back metal layer MMO and the metal line 425 in the metal layer M0.

[0105] Despite Figures 10A to 10C In the example shown, each of the through structures 415-1 to 415-2 passes through both diffusion regions 620 and 625. However, it should be understood that in other specific embodiments, each of the through structures 415-1 to 415-2 may pass through only one of the diffusion regions 620 and 625. For example, each of the through structures 415-1 to 415-2 may utilize... Figures 7A to 7EThe exemplary specific implementation shown or Figures 8A to 8D The exemplary specific implementation shown is used to achieve this.

[0106] It should be understood that the through-fill unit 410 is not limited to the example of two through structures, and may include an additional through structure that connects in parallel between the back metal wiring 420 in the back metal layer M0 and the metal line 425 in the metal layer M0.

[0107] Despite Figures 7A to 7D , Figures 8A to 8D , Figures 9A to 9D and Figures 10A to 10C In the example shown, the through-fill unit 410 is located between the first unit 310 and the second unit 312, but it should be understood that this disclosure is not limited to this example. For example, the through-fill unit 410 could be located between the third unit 314 and the fourth unit 316 (e.g., Figure 5A and Figure 5B (As shown in the diagram). In this example, the back-side metal wiring 420 also extends below the third cell 314 to reach the through-fill cell 410. For example, the back-side metal wiring 420 may be... Figure 5B The transistor 450 in the third unit 314 shown extends below.

[0108] In some respects, computer systems can be used to determine the exemplary layout discussed above. In this respect, Figure 11 An example of a computer system 1100 is illustrated, which, according to certain aspects, can be used to determine the layout for chip 100. The computer system 1100 may include a processor 1120, a memory 1110, a network interface 1130, and a user interface 1140. These components may communicate electronically via one or more buses 1145.

[0109] Memory 1110 may store instructions 1115 that can be executed by processor 1120 to cause computer system 1100 to perform one or more of the operations described herein. Processor 1120 may include a general-purpose processor, a digital signal processor (DSP), a central processing unit (CPU), a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof.

[0110] By way of example, memory 1110 may include random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, disks, optical disks, hard disks, or any other suitable storage media or any combination thereof. Memory 1110 may also store a cell library comprising a file specifying the layouts of various cells that can be placed on chip 100, including layouts of through-fill cells (e.g., through-fill cell 410).

[0111] Network interface 1130 is configured to interface computer system 1100 with one or more other devices. User interface 1140 may be configured (e.g., via keypad, mouse, etc.) to receive data from a user and provide data to processor 1120. User interface 1140 may also be configured (e.g., via display, speakers, etc.) to output data from processor 1120 to a user.

[0112] Specific implementation examples are described in the following numbered clauses: 1. A chip, the chip comprising: A first transistor, the first transistor comprising: First source / drain; Second source / drain; Gate, the gate being located between the first source / drain and the second source / drain; and The first back-side contact is connected to the bottom surface of the first source / drain. Through structure, the through structure includes: A first diffusion region extends in a first direction; A second back-side contact member is attached to the bottom surface of the first diffusion region; and Top-side contact member, the top-side contact member being coupled to the top surface of the first diffusion region; and A back-side metal wiring is connected between the first back-side contact and the second back-side contact.

[0113] 2. The chip according to Clause 1, the chip further comprising a second transistor located between the first transistor and the through structure, wherein the backside metal wiring extends below the second transistor.

[0114] 3. The chip according to clause 1 or 2, wherein the back-side metal wiring includes a back-side metal line extending in the first direction.

[0115] 4. The chip according to any one of clauses 1 to 3, the chip further comprising a first top-side metal line extending in the first direction, wherein the top-side contact is coupled to the first top-side metal line.

[0116] 5. The chip according to Clause 4, the chip further comprising a second top-side metal line extending in a second direction perpendicular to the first direction, wherein the second top-side metal line is coupled to the first top-side metal line.

[0117] 6. The chip according to Clause 5, wherein the first top-side metal line is formed by a first metal layer, and the second top-side metal line is formed by a second metal layer above the first metal layer.

[0118] 7. The chip according to any one of clauses 1 to 6, wherein the chip further comprises: A first back-side via is disposed between the first back-side contact and the back-side metal wiring; and The second back-side via is disposed between the second back-side contact and the back-side metal wiring.

[0119] 8. The chip according to any one of clauses 1 to 7, wherein the through-structure further comprises a second diffusion region, the second back-side contact being coupled to the bottom surface of the second diffusion region, and the top-side contact being coupled to the top surface of the second diffusion region.

[0120] 9. The chip according to Clause 8, wherein the first diffusion region and the second diffusion region are spaced apart in a second direction perpendicular to the first direction.

[0121] 10. The chip according to Clause 9, wherein the first diffusion region is a p-type diffusion region and the second diffusion region is an n-type diffusion region.

[0122] 11. The chip according to Clause 9, wherein the first diffusion region is an n-type diffusion region and the second diffusion region is a p-type diffusion region.

[0123] 12. A chip, the chip comprising: A first transistor, the first transistor comprising: First source / drain; Second source / drain; Gate, the gate being located between the first source / drain and the second source / drain; and A back-side contact, which is connected to the bottom surface of the first source / drain electrode; Through structure; A back-side metal wiring connection, the back-side metal wiring being coupled to the back-side contact and extending below the first transistor to the through-structure; and A top-side metal line extends above the through-structure, wherein the through-structure is connected in parallel between the back-side metal wiring and the top-side metal line, and each through-structure provides a corresponding signal path between the back-side metal wiring and the top-side metal line.

[0124] 13. The chip according to Clause 12, the chip further comprising a second transistor located between the first transistor and the through structure, wherein the backside metal wiring extends below the second transistor.

[0125] 14. The chip according to Clause 12 or 13, wherein the back-side metal wiring includes back-side metal lines.

[0126] 15. A chip, the chip comprising: A first transistor, the first transistor comprising: First source / drain; Second source / drain; A first gate, the first gate being located between the first source / drain and the second source / drain; and A first back-side contact is connected to the bottom surface of the first source / drain electrode; and Through structure, the through structure includes: A first diffusion region extends in a first direction; The second back-side contact is connected to the bottom surface of the first diffusion region; A first top-side contact member is connected to the top surface of the first diffusion region; A third back-side contact member, the third back-side contact member being coupled to the bottom surface of the first diffusion region; and A second top-side contact is attached to the top surface of the first diffusion region; A back-side metal wiring connection to a first back-side contact, a second back-side contact, and a third back-side contact, wherein the back-side metal wiring extends below the first transistor into the through-structure; and A top-side metal wire extending in the first direction, wherein the top-side metal wire is connected to the first top-side contact and the second top-side contact.

[0127] 16. The chip according to Clause 15, the chip further comprising a second transistor located between the first transistor and the through structure, wherein the backside metal wiring extends below the second transistor.

[0128] 17. The chip according to Clause 15 or 16, wherein the back-side metal wiring includes back-side metal lines.

[0129] 18. The chip according to any one of clauses 15 to 17, wherein the through-structure further comprises a second gate located between the first top-side contact and the second top-side contact.

[0130] 19. The chip according to any one of Clauses 15 to 18, wherein the through-structure further comprises a second diffusion region extending in the first direction, a second back-side contact coupled to a bottom surface of the second diffusion region, a third back-side contact coupled to the bottom surface of the second diffusion region, a first top-side contact coupled to a top surface of the second diffusion region, and a second top-side contact coupled to the top surface of the second diffusion region.

[0131] 20. The chip according to Clause 19, wherein the first diffusion region and the second diffusion region are spaced apart in a second direction perpendicular to the first direction.

[0132] 21. The chip according to Clause 20, wherein the first diffusion region is a p-type diffusion region and the second diffusion region is an n-type diffusion region.

[0133] 22. The chip according to Clause 20, wherein the first diffusion region is an n-type diffusion region and the second diffusion region is a p-type diffusion region.

[0134] 23. A chip, the chip comprising: The first unit includes: A first diffusion region extends in a first direction; Gates, the gates being formed over the first diffusion region, wherein each of the gates is elongated and extends in a second direction perpendicular to the first direction; and A first back-side contact is attached to the bottom surface of the first diffusion region; Through-fill unit, the through-fill unit comprising: Second diffusion zone; A second back-side contact member is attached to the bottom surface of the second diffusion region; and Top-side contact member, the top-side contact member being coupled to the top surface of the second diffusion region; and A back-side metal wiring is connected between the first back-side contact and the second back-side contact.

[0135] 24. The chip according to Clause 23, the chip further comprising a second unit located between the first unit and the through-fill unit, wherein the back-side metal wiring extends below the second unit.

[0136] 25. The chip according to clause 23 or 24, the chip further comprising a first top-side metal line extending in the first direction, wherein the top-side contact is coupled to the first top-side metal line.

[0137] 26. The chip according to Clause 25, the chip further comprising a second top-side metal line extending in the second direction, wherein the second top-side metal line is coupled to the first top-side metal line.

[0138] 27. The chip according to any one of clauses 23 to 26, wherein the chip further comprises: A first back-side via is disposed between the first back-side contact and the back-side metal wiring; and The second back-side via is disposed between the second back-side contact and the back-side metal wiring.

[0139] 28. The chip according to any one of clauses 23 to 27, wherein the through-fill unit further comprises a third diffusion region, the second back-side contact is coupled to the bottom surface of the third diffusion region, and the top-side contact is coupled to the top surface of the third diffusion region.

[0140] 29. The chip according to Clause 28, wherein the second diffusion region and the third diffusion region are spaced apart in the second direction.

[0141] 30. A chip, the chip comprising: The first unit includes: A first diffusion region extends in a first direction; Gates, the gates being formed over the first diffusion region, wherein each of the gates is elongated and extends in a second direction perpendicular to the first direction; and A first back-side contact is attached to the bottom surface of the first diffusion region; Through-fill unit, the through-fill unit comprising: Second diffusion zone; The second back-side contact is connected to the bottom surface of the second diffusion region; A first top-side contact member is connected to the top surface of the second diffusion region; A third back-side contact member, the third back-side contact member being coupled to the bottom surface of the second diffusion region; and A second top-side contact member is attached to the top surface of the second diffusion region; A back-side metal wiring connection to a first back-side contact, a second back-side contact, and a third back-side contact, wherein the back-side metal wiring extends below the first unit to the through-fill unit; and A top-side metal wire extending in the first direction, wherein the top-side metal wire is connected to the first top-side contact and the second top-side contact.

[0142] 31. The chip according to Clause 30, the chip further comprising a second unit located between the first unit and the through-fill unit, wherein the back-side metal wiring extends below the second unit.

[0143] 32. The chip according to clause 30 or 31, wherein the backside metal wiring includes a backside metal line extending in the first direction.

[0144] 33. The chip according to any one of clauses 30 to 32, wherein the through-fill unit further includes a fill gate extending in the second direction, wherein the fill gate is located between the first top-side contact and the second top-side contact.

[0145] 34. The chip according to any one of clauses 30 to 33, wherein the through-fill unit further comprises a third diffusion region extending in the first direction, the second back-side contact being coupled to the bottom surface of the third diffusion region, the third back-side contact being coupled to the bottom surface of the third diffusion region, the first top-side contact being coupled to the top surface of the third diffusion region, and the second top-side contact being coupled to the top surface of the third diffusion region.

[0146] 35. The chip according to Clause 34, wherein the second diffusion region and the third diffusion region are spaced apart in the second direction.

[0147] 36. The chip according to Clause 35, wherein the second diffusion region is a p-type diffusion region and the third diffusion region is an n-type diffusion region.

[0148] 37. The chip according to Clause 35, wherein the second diffusion region is an n-type diffusion region and the third diffusion region is a p-type diffusion region.

[0149] In this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "connection" is used herein to refer to a direct or indirect electrical connection between two structures. As used herein, the term "about" means within 90% to 110% of the stated value. The x-direction may also be referred to as a first direction, and the y-direction may also be referred to as a second direction perpendicular to the first direction.

[0150] The use of designations such as "first" and "second" to refer to elements in this document generally does not restrict the number or order of those elements. Rather, these designations are used here as a convenient way to distinguish two or more elements or instances of elements. Therefore, a reference to the first element and the second element does not imply that only two elements can be used, or that the first element must precede the second element.

[0151] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Thus, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip, the chip comprising: A first transistor, the first transistor comprising: First source / drain; Second source / drain; Gate, the gate being located between the first source / drain and the second source / drain; and The first back-side contact is connected to the bottom surface of the first source / drain. Through structure, the through structure includes: A first diffusion region extends in a first direction; A second back-side contact member is attached to the bottom surface of the first diffusion region; and Top-side contact member, the top-side contact member being coupled to the top surface of the first diffusion region; and A back-side metal wiring is connected between the first back-side contact and the second back-side contact.

2. The chip of claim 1, further comprising a second transistor located between the first transistor and the through structure, wherein the backside metal wiring extends below the second transistor.

3. The chip of claim 1, wherein the back-side metal wiring includes a back-side metal line extending in the first direction.

4. The chip of claim 1, further comprising a first top-side metal line extending in the first direction, wherein the top-side contact is coupled to the first top-side metal line.

5. The chip of claim 4, further comprising a second top-side metal line extending in a second direction perpendicular to the first direction, wherein the second top-side metal line is connected to the first top-side metal line.

6. The chip of claim 5, wherein the first top-side metal line is formed by a first metal layer, and the second top-side metal line is formed by a second metal layer above the first metal layer.

7. The chip according to claim 1, further comprising: A first back-side via is disposed between the first back-side contact and the back-side metal wiring. and The second back-side via is disposed between the second back-side contact and the back-side metal wiring.

8. The chip of claim 1, wherein the through-structure further comprises a second diffusion region, the second back-side contact being coupled to the bottom surface of the second diffusion region, and the top-side contact being coupled to the top surface of the second diffusion region.

9. The chip according to claim 8, wherein the first diffusion region and the second diffusion region are spaced apart in a second direction perpendicular to the first direction.

10. The chip according to claim 9, wherein the first diffusion region is a p-type diffusion region and the second diffusion region is an n-type diffusion region.

11. The chip according to claim 9, wherein the first diffusion region is an n-type diffusion region and the second diffusion region is a p-type diffusion region.

12. A chip, the chip comprising: A first transistor, the first transistor comprising: First source / drain; Second source / drain; Gate, the gate being located between the first source / drain and the second source / drain; and A back-side contact, which is connected to the bottom surface of the first source / drain electrode; Through structure; A back-side metal wiring connection, the back-side metal wiring being coupled to the back-side contact and extending below the first transistor to the through-structure; and A top-side metal line extends above the through-structure, wherein the through-structure is connected in parallel between the back-side metal wiring and the top-side metal line, and each through-structure provides a corresponding signal path between the back-side metal wiring and the top-side metal line.

13. The chip of claim 12, further comprising a second transistor located between the first transistor and the through-structure, wherein the backside metal wiring extends below the second transistor.

14. The chip of claim 12, wherein the back-side metal wiring comprises back-side metal lines.

15. A chip, the chip comprising: A first transistor, the first transistor comprising: First source / drain; Second source / drain; A first gate, the first gate being located between the first source / drain and the second source / drain; and A first back-side contact is connected to the bottom surface of the first source / drain electrode; and Through structure, the through structure includes: A first diffusion region extends in a first direction; The second back-side contact is connected to the bottom surface of the first diffusion region; A first top-side contact member is connected to the top surface of the first diffusion region; A third back-side contact member, the third back-side contact member being coupled to the bottom surface of the first diffusion region; and A second top-side contact is attached to the top surface of the first diffusion region; A back-side metal wiring connection to a first back-side contact, a second back-side contact, and a third back-side contact, wherein the back-side metal wiring extends below the first transistor into the through-structure; and A top-side metal wire extending in the first direction, wherein the top-side metal wire is connected to the first top-side contact and the second top-side contact.

16. The chip of claim 15, further comprising a second transistor located between the first transistor and the through-structure, wherein the backside metal wiring extends below the second transistor.

17. The chip of claim 15, wherein the back-side metal wiring comprises a back-side metal line.

18. The chip of claim 15, wherein the through-structure further comprises a second gate located between the first top-side contact and the second top-side contact.

19. The chip of claim 15, wherein the through-structure further comprises a second diffusion region extending in the first direction, the second back-side contact being coupled to the bottom surface of the second diffusion region, the third back-side contact being coupled to the bottom surface of the second diffusion region, the first top-side contact being coupled to the top surface of the second diffusion region, and the second top-side contact being coupled to the top surface of the second diffusion region.

20. The chip of claim 19, wherein the first diffusion region and the second diffusion region are spaced apart in a second direction perpendicular to the first direction.

21. The chip of claim 20, wherein the first diffusion region is a p-type diffusion region and the second diffusion region is an n-type diffusion region.

22. The chip of claim 20, wherein the first diffusion region is an n-type diffusion region and the second diffusion region is a p-type diffusion region.

23. A chip, the chip comprising: The first unit includes: A first diffusion region extends in a first direction; Gates, the gates being formed over the first diffusion region, wherein each of the gates is elongated and extends in a second direction perpendicular to the first direction; and A first back-side contact is attached to the bottom surface of the first diffusion region; Through-fill unit, the through-fill unit comprising: Second diffusion zone; A second back-side contact member is attached to the bottom surface of the second diffusion region; and Top-side contact member, the top-side contact member being coupled to the top surface of the second diffusion region; and A back-side metal wiring is connected between the first back-side contact and the second back-side contact.

24. The chip of claim 23, further comprising a second unit located between the first unit and the through-fill unit, wherein the back-side metal wiring extends below the second unit.

25. The chip of claim 23, further comprising a first top-side metal line extending in the first direction, wherein the top-side contact is coupled to the first top-side metal line.

26. The chip of claim 25, further comprising a second top-side metal line extending in the second direction, wherein the second top-side metal line is coupled to the first top-side metal line.

27. The chip according to claim 23, further comprising: A first back-side via is disposed between the first back-side contact and the back-side metal wiring. and The second back-side via is disposed between the second back-side contact and the back-side metal wiring.

28. The chip of claim 23, wherein the through-fill unit further comprises a third diffusion region, the second back-side contact is coupled to the bottom surface of the third diffusion region, and the top-side contact is coupled to the top surface of the third diffusion region.

29. The chip of claim 28, wherein the second diffusion region and the third diffusion region are spaced apart in the second direction.

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